Sequential Circuits
NAND latch(RS Latch)
NOR Latch (RS Latch)
Comparison between NAND and NOR Latches
Bouncing due to mechanical switch
The “Clock”
Clocked RS Latch
JK- Flip flop
D Flip-Flop
T Flip-Flop
• The T flip-flop is a single input version of the JK flip-flop. The T flip-flop is
obtained from the JK type if both inputs are tied together.
• The toggle, or T, flip-flop is a bistable device, where the output of the T flip-flop
"toggles" with each clock pulse.
• When CP=1, for T=0, previous output is memorized by the circuit. When T=1
along with the clock pulse, the output toggles from the previous value as given in
the characteristic table below.
• Characteristic Table:
Excitation Table of Flip-Flops
• It indicates the input required to be applied to the flip flop to take it
from present state to the next state.
S-R Flip-Flop:
Conversion of Flip-Flops
S-R Flip-Flop to J-K Flip-Flop
J-K Flip-Flop to S-R Flip-Flop
S-R Flip-Flop to D Flip-Flop
D Flip-Flop to S-R Flip-Flop
J-K Flip-Flop to T Flip-Flop
J-K Flip-Flop to D Flip-Flop
D to J-K Flip-Flop
Applications of Flip-Flops
• Parallel and Serial Data storage
• Transfer of Data
• Serial to parallel and Parallel to serial conversion
• Counting
• Frequency Division
Registers
• A register is a group of binary cells suitable for holding binary
information. A group of flip-flops constitutes a register, since each
flip-flop is a binary cell capable of storing one bit of information.
• In addition to the flip-flops, a register may have combinational gates
that perform certain data-processing tasks.
Shift Register
Serial In Serial Out(SISO)
Parallel In Parallel Out
Serial In Parallel Out(SIPO)
Parallel In Serial Out
Bidirectional Shift Register
Universal Shift Register
Application of Shift Registers
• Time Delays
• Serial/Parallel Conversion
• Ring Counters
• UART(Universal asynchronous receiver transmitter)
Counters
Binary Ripple counter(Asynchronous Counter)
Asynchronous 2-bit down counter using Negative edge triggered
Flip-Flops
2-bit Ripple Up-Counter Using Positive Edge
triggered Flip-Flops
2-bit Ripple Down-Counter Using Positive Edge
triggered Flip-Flops
3-bit Up-Down binary ripple counter
Design of a Mod-6 Asynchronous Counter using T- FFs
Effects of Propagation Delay in Ripple counters
Synchronous Counters
Design of Synchronous Counters
• Determine the number of Flip-Flops
• Draw the State diagram
• Select the type of Flip-Flops and draw the Excitation table
• Obtain the Minimal expressions for excitations
• Draw the Logic Diagram.
Excitation Table of Flip-Flops
• It indicates the input required to be applied to the flip flop to take it
from present state to the next state.
S-R Flip-Flop:
Design of Synchronous 3-bit counter
• Logic Diagram of 3-bit Synchronous Counter
Design of 3-bit Synchronous down counter
•
Design of 3-bit Synchronous Up/Down Counter
Design a Modulo -9 Synchronous counter
• Step 1: The Counter has 9 states. Number of Flip-Flops: 4.
Remaining 7 states are invalid and are treated as don’t cares.
• Step 2: State Diagram
• Step 3: Type of Flip-Flops and Excitation Table
T Flip-Flops are used and writing of excitation table for the counter using the
Excitation table of T Flip-Flops.
• Step 4 : Minimal Expressions:
• Step 5. Logic Diagram:
Design of a Synchronous BCD Counter using J-K Flip-Flop
• Step 1: The Counter has 10 states. Number of Flip-Flops: 4.
Remaining 6 states are invalid and are treated as don’t cares.
• Step 2: State Diagram
• Step 3: Type of Flip-Flops and Excitation Table
J-K Flip-Flops are used and writing of excitation table for the counter using the
Excitation table of J-K Flip-Flops.
• Step 4 : Minimal Expressions:
• Step 5. Logic Diagram:
• To check for Lock-out condition
Design a Synchronous Counter that goes through
0,3,5,6,0…. Using T-Flip-Flop. Is the counter self
starting?
• No of Flip-Flops: 3
• State Diagram and Excitation Table
• Logic Diagram
• Check for lock-out
• Elimination of lock-out
• Method 1:
• Method 2:
Design a type D counter that goes through 0,1,2,4,0…. states
Shift Register Counter
• Ring Counter
Twisted Ring Counter
