BIRLA INSTITUTE OF TECHNOLOGY & SCIENCE, PILANI
WORK INTEGRATED LEARNING PROGRAMMES
COURSE HANDOUT
Part A: Content Design
Course Title Computer Organization & Architecture
Course No(s) SE* ZC353 / IS ZC353 / CSI* ZC353
Credit Units 4
1-1-2, (total 4 units or credits) ie 1 unit for class room hours, 1 unit
for lab hours, 2 units for student preparation.
Typically 1 unit translates to 32 hours
Course Author Dr. Lucy J Gudino/ Chandra Shekar RK
Version No 1.0
Date
Course Objectives
No Course Objective
CO1 To understand the structure, function, organization and architecture of modern day
computing systems.
CO2 To learn the major components of a computer and their interconnections, both with each
other and the outside world with detailed discussion of internal and external memory and of
input–output (I/O) devices.
CO3 To examine the internal architecture and organization of the processor with an extended
discussion of computer arithmetic and the instruction set architecture.
CO4 To give an introduction of parallel organization, including symmetric multiprocessing,
clusters, and multicore architecture.
CO5 To learn the Hardware Description Language and simulator to design and verify the basic
components of a computing system.
Text Book(s)
T1 Stallings William, Computer Organization & Architecture, Pearson Education, 8th Ed.,
2010
Reference Book(s) & other resources
R1 Computer Organization by C Hamacher, Z Vranesic and S Zaky, McGrawHill 5th Ed.
2002
R2 Computer Organization & Design, Hennenssy & D.A. Patterson, Morgan Kaufmann 4th
Ed.2009
R3 The Essentials of Computer Organization and Architecture, Linda Null and Julia Lobur,
Jones and Bartlett publisher, 2003 [24x7 online]
Modular Content Structure
1. Computer System Components and Interconnections
1.1. Introduction
1.1.1. Organization and Architecture
1.1.2. Structure and Function
1.2. Computer Evolution and Performance
1.2.1. A Brief History of Computers
1.2.2. Designing for Performance
1.2.3. The Evolution of the Intel x86 Architecture
1.2.4. Performance Assessment
1.3. Top-Level View of Computer Function and Interconnection
1.3.1. Computer Components
1.3.2. Computer Function
1.3.3. Interconnection Structures
1.3.4. Bus Interconnection
1.3.5. PCI
2. Central Processing Unit - Computer Arithmetic
2.1. The Arithmetic and Logic Unit (ALU)
2.2. Integer Representation
2.3. Integer Arithmetic
2.4. Floating-Point Representation
2.5. Floating-Point Arithmetic
3. Instruction Set Architecture (8086 ARM as an example)
3.1. Instruction Sets: Characteristics and Functions
3.1.1. Machine Instruction Characteristics
3.1.2. Types of Operands
3.1.3. Intel x86 and ARM Data Types
3.1.4. Types of Operations
3.1.5. Intel x86 and ARM Operation Types
3.2. Instruction Sets: Addressing Modes and Formats
3.2.1. Addressing
3.2.2. x86 and ARM Addressing Modes
3.2.3. Instruction Formats
3.2.4. x86 and ARM Instruction Formats
3.2.5. Assembly Language
4. Cache Memory Organization
4.1. Computer Memory System Overview
4.2. Cache Memory Principles
4.3. Elements of Cache Design
5. Internal and External memory
5.1. Internal Memory Technology
5.1.1. Semiconductor Main Memory
5.1.2. Error Correction
5.1.3. Advanced DRAM Organization
5.2. External Memory
5.2.1. Magnetic Disk
5.2.2. RAID
6. Input/Output Organization
6.1. I/O Modules
6.2. Programmed I/O
6.3. Interrupt-Driven I/O
6.4. Direct Memory Access
6.5. I/O Channels and Processors
7. Scalar and Super Scalar Instruction Pipeline
7.1. Processor Structure and Function
7.1.1. The Instruction Cycle
7.1.2. Instruction Pipelining
7.1.3. The ARM Processor
7.2. Reduced Instruction Set Computers
7.2.1. Instruction Execution Characteristics
7.2.2. The Use of a Large Register File
7.2.3. Reduced Instruction Set Architecture
7.2.4. RISC Pipelining
7.2.5. SPARC / ARM7TDMI
8. Micro-operations and Control Unit
8.1. Control Unit Operation - Micro-operations
8.2. Control of the Processor
8.3. Hardwired Implementation
8.4. Micro programmed Control - Basic Concepts
8.5. Microinstruction Sequencing
8.6. Microinstruction Execution
9. Multiprocessor Organizations
9.1. The Use of Multiple Processors
9.2. Symmetric Multiprocessors
9.3. Cache Coherence and the MESI Protocol
9.4. Multithreading and Chip Multiprocessors
9.5. Clusters
9.6. Non uniform Memory Access Computers
Learning Outcomes:
No Learning Outcomes
LO1 To apply the knowledge of performance metrics to find the performance of systems.
LO2 To Build an assembly language program to program a microprocessor system.
LO3 To Investigate high performance architecture design for X86 system
LO4 To Examine different computer architectures and hardware
LO5 To design a hardware component for an embedded system
Part B: Contact Session Plan
Academic Term
Course Title Computer Organization & Architecture
Course No
Lead Instructor
Course Contents
Contact List of Topic Title Topic # Text/Ref
Hour (from content structure in Part A) (from content Book/external
structure in resource
Part A)
1 Introduction 1.1 - 1.2.1 T1:
●
Ch1: 1.1-1.2
Organization and Architecture Ch2: 2.1
●
Structure and Function
●
Computer Evolution and Performance
●
A Brief History of Computers
●
2 Designing for Performance 1.2.2 - T1:
●
1.2.4 Ch2: 2.2 - 2.5
The Evolution of the Intel x86 Architecture (excluding 2.4)
●
Performance Assessment
●
3 Top-Level View of Computer Function and 1.3 - 1.3.2 T1:
●
Ch3:3.1 - 3.2
Interconnection
Computer Components
●
Computer Function
●
4 Interconnection Structures 1.3.3 - T1:
●
1.3.5 Ch3: 3.3 - 3.5
Bus Interconnection
●
PCI
●
5 The Arithmetic and Logic Unit (ALU) 2.1 - 2.2 T1:
●
Ch9:9.1 - 9.2
Integer Representation
●
6 Integer Arithmetic 2.3 T1:
●
Ch9: 9.3
7 Integer Arithmetic 2.3 T1:
●
Ch9: 9.3
8 Floating-Point Representation 2.4 - 2.5 T1:
●
Ch9: 9.4 - 9.5
Floating-Point Arithmetic
●
9 Instruction Sets: Characteristics and Functions 3.1 - 3.1.5 T1:
●
Ch10: 10.1 - 10.5
Machine Instruction Characteristics
●
Types of Operands
●
Intel x86 and ARM Data Types
●
Types of Operations
●
Intel x86 and ARM Operation Types
●
10 Addressing 3.2 - 3.2.4 T1:
●
Ch11: 11.1 - 11.4
x86 and ARM Addressing Modes
●
Instruction Formats
●
x86 and ARM Instruction Formats
●
11 Computer Memory System Overview 4.1 T1:
●
Ch4: 4.1
12 Cache Memory Principles 4.2 T1:
●
Ch4: 4.2
13 Elements of Cache Design 4.3 T1:
●
Ch4: 4.3
14 Internal Memory Technology 5.1 - 5.1.2 T1:
●
Ch5: 5.1 - 5.2
Semiconductor Main Memory
●
Error Correction
●
15 Advanced DRAM Organization 5.1.3 T1:
●
Ch5: 5.3
16 External Memory 5.2 - 5.2.2 T1:
●
Ch6: 6.1 - 6.2
Magnetic Disk
●
RAID
●
17 I/O Modules 6.1 - 6.2 T1:
●
Ch7: 7.2 - 7.3
Programmed I/O
●
18 Interrupt-Driven I/O 6.3 T1:
●
Ch7: 7.4
19 Direct Memory Access 6.4 T1:
●
Ch7: 7.5
20 I/O Channels and Processors 6.5 T1:
●
Ch7: 7.6
21 Processor Structure and Function 7.1 - 7.1.1 T1:
●
Ch12: 12.1 - 12.3
The Instruction Cycle
●
22 Instruction Pipelining 7.1.2 - T1:
●
7.1.3 Ch12: 12.4 - 12.6
The ARM Processor (Excluding 12.5)
●
23 Reduced Instruction Set Computers 7.2 - 7.2.2 T1:
●
Ch13: 13.1 - 13.2
Instruction Execution Characteristics
●
The Use of a Large Register File
●
24 Reduced Instruction Set Architecture 7.2.3 - T1:
●
7.2.5 Ch13: 13.4 - 13.7
RISC Pipelining (Excluding 13.6)
●
SPARC / ARM7TDMI
●
25 Control Unit Operation - Micro-operations 8.1 T1:
●
Ch15: 15.1
26 Control of the Processor 8.2 T1:
●
Ch15: 15.2
27 Hardwired Implementation 8.3 - 8.4 T1:
●
Ch15: 15.3
Micro programmed Control - Basic Concepts Ch16: 16.1
●
28 Microinstruction Sequencing 8.5 - 8.6 T1:
●
Ch16: 16.2 - 16.3
Microinstruction Execution
●
29 The Use of Multiple Processors 9.1 - 9.2 T1:
●
Ch17: 17.1 - 17.2
Symmetric Multiprocessors
●
30 Cache Coherence and the MESI Protocol 9.3 T1:
●
Ch17: 17.3
31 Multithreading and Chip Multiprocessors 9.4 - 9.5 T1:
●
Ch17: 17.4 - 17.5
Clusters
●
32 Non-uniform Memory Access Computers 9.6 T1:
●
Ch17: 17.6
Detailed Plan for Lab work/Design work:
Ref: CPU-OS simulator (http://www.teach-sim.com)
Lab Lab Objective Lab Sheet Content
No Access URL Reference
1 Introduction to CPU-OS Simulator Unit 1
2 Lab to investigate CPU instructions Unit: 3
3 Lab to investigate Instruction Pipelines Unit: 7
4 Lab to investigate Cache Technology Unit: 4
5 ARM based assembly language programming using Unit: 3
ARM-SIM
Evaluation Scheme
Evaluation Name Type Weight Duration Day, Date,
Component (Quiz, Lab, Project, Mid (Open book, Session, Time
term exam, End Closed book,
semester exam, etc) Online, etc.)
EC - 1 Paper Presentation Contact 20% 25m To be announced
EC - 2 Mid Term exam Closed book 30% 90m To be announced
EC - 3 End Semester exam Open book 50% 150m To be announced
Note - Evaluation components can be tailored depending on the proposed model.
Important Information
Syllabus for Mid-Semester Test (Closed Book): Topics in Weeks 1-7
Syllabus for Comprehensive Exam (Open Book): All topics given in plan of study
Evaluation Guidelines:
1. EC-1 consists of either two Assignments or three Quizzes. Announcements regarding the
same will be made in a timely manner.
2. For Closed Book tests: No books or reference material of any kind will be permitted.
Laptops/Mobiles of any kind are not allowed. Exchange of any material is not allowed.
3. For Open Book exams: Use of prescribed and reference text books, in original (not
photocopies) is permitted. Class notes/slides as reference material in filed or bound form is
permitted. However, loose sheets of paper will not be allowed. Use of calculators is permitted
in all exams. Laptops/Mobiles of any kind are not allowed. Exchange of any material is not
allowed.
4. If a student is unable to appear for the Regular Test/Exam due to genuine exigencies, the
student should follow the procedure to apply for the Make-Up Test/Exam. The genuineness of
the reason for absence in the Regular Exam shall be assessed prior to giving permission to
appear for the Make-up Exam. Make-Up Test/Exam will be conducted only at selected exam
centres on the dates to be announced later.
It shall be the responsibility of the individual student to be regular in maintaining the self-study
schedule as given in the course handout, attend the lectures, and take all the prescribed evaluation
components such as Assignment/Quiz, Mid-Semester Test and Comprehensive Exam according to the
evaluation scheme provided in the handout.
