ER1731 – Digital Electronics and Programmable Systems.

Digital Logic Systems 5 – Introduction to TTL & CMOS

Carl Berry
[email protected]
CM024

Where opportunity creates success

 ER1731 - Digital Electronics and
Programmable Systems

For the Degree Apprenticeship Programme

Knowledge, Skills and Behaviours underpinned during this

session

Apprentice Standard Knowledge, Skills and Behaviour

Electrical/Electronic Technical Support K6, K8
Engineer
Simplifying a Logic Expression
• One to try for yourselves for next week:
• Z = !A.C.!(!A.B.D) + !A.B.!C.!D + A.!B.C
• Hint : Start with DeMorgan’s theorem on the first term.
• Apply DeMorgans
• !AC(!!A+!B+!D) + !AB!C!D+A!BC - !!A = A
• !AC(A+!B+!D)+!AB!C!D+A!BC - Distribution
• !ACA + !AC!B + !AC!D + !AB!C!D + A!BC - A!A = 0
• 0C + !AC!B + !AC!D + !AB!C!D + A!BC - Distributive Law (AB+AC = A(B+C)), term 2 & 5
• C!B(!A+A) + !AC!D + !AB!C!D - !A+A = 1
• C!B + !AC!D + !AB!C!D - Distributive Law (AB+AC = A(B+C)) , term 2 & 3
• C!B + !A!D(C + B!C) - Absorption Law (!AB+A = B+A)
• C!B + !A!D(B+C) - Distribution
• C!B + !A!DB + !A!DC - The final result.
In This Material
In this section we are going to look at:-
• Logic Families (TTL and CMOS)
• TTL Inverter
• TTL NAND Gate
• TTL Totem Poles
• Temperature
• CMOS Inverter
Logic Families

• There are two main designs of logic integrated circuits.

• TTL (Transistor – Transistor Logic)
• CMOS (Complementary Metal-Oxide Semi-conductor Logic)
• TTL is the older series (commercially) and is known high speed.
• CMOS is simpler and cheaper to fabricate, takes up less space and generally uses less
power (some variation across factors).
• CMOS has less power dissipation (energy lost through heat).
• However TTL is more rugged, CMOS can be suspectable to electrostatic and
overvoltage damage although they are better at dealing with noise.
A Simple, One-Input, TTL Inverter

VCC • The inverter circuit uses transistors and a

resistor to create a “steering” circuit.
• If the input is “low” the circuit routes the
current through to ground (0V go to
output)
output • If the input is “high” all the current flows
to output.
input • In the case of TTL the voltage at output
will be 5V
• It’s a circuit that allows control of voltage
to be either 0V or 5V and nothing else.

gnd
 TTL NAND Gate

VCC • The inverter forms the basis of a TTL NAND gate

circuit.
R1 R2 R3
4 kΩ 1.6 kΩ 130 Ω • The circuit consists of three parts:
• Input (the inverter, Q1)
• A splitter or switching part (Q2)
Q3
• A Totem Pole (Q3 & Q4)
Q1
X (output)
A
Q2
B D3

D1
D2 Q4

R4
1 kΩ

gnd
 TTL NAND Gate (Low State)
VCC

R1 R2 R3 • Q1 can be redrawn as 2 diodes.

4 kΩ 1.6 kΩ 130 Ω • This helps see where the current will flow in the
circuit.
0.8V • The circuit operates in two modes depending
Q3 on the inputs.
Q1 • If both of the inputs are 1 current flows through
X (output)
Q1 into the base of Q2 causing Q2 to go into
A Q2 0.1V saturation.
B D3
• Q2 in saturation causes Q3 to dissipate it’s
charge through Q2 and therefore Q3 goes into
cut-off.
Q4 • Current flows into the base of Q4 causing it to
saturate and current goes to ground.
D1
• No current goes from Vcc to output so we get a
D2 R4 0.7V
logic 0.
1 kΩ

gnd
 TTL NAND Gate (High State)
VCC

R1 R2 R3 • If either of the inputs are set to 0, this will cause

4 kΩ 1.6 kΩ 130 Ω Q1 to flow away from Q2, this causes Q2 base
to discharge through Q1 sending Q2 into cut-
0.8V off.
Q3 • With Q2 in cut-off current from Vcc will go
Q1 through the base of Q3.
X (output)
• Q3 will saturate and current will flow to output.
A Q2 0.1V • Q4 will not receive current, so Q2 and Q3 will
B D3
be in cut-out and Q3 will be saturated so a logic
1 will be received at output.
• In order to turn this circuit into an AND we
Q4 would place another inverter circuit after this.

D1 D2 R4 0.7V
1 kΩ

gnd
Totem Pole
5V • The circuit in the final layer of the NAND (Q3 5V

R4 & Q4) is called a Totem Pole (see left). R4

130 Ω 130 Ω
• It is responsible for determining the output
of the circuit.
Q3

• Sometimes you may come across is slightly

simpler version of the NAND that doesn’t use
D3
a Totem Pole and instead uses a passive
resistor (see right).
Q4 Q4
• Why do we use a Totem Pole rather than the
passive resistor?
Why use Totem Poles?
• Advantages : 5V
• With Q3 in the circuit, no current flows through R4 in the output LOW state,
reducing power dissipation.
R4
• In the HIGH output state, Q3 acts as an emitter follower with low output
130 Ω
impedance (typically 10 Ω).
Q3
• This provides a short time constant in charging up any capacitive load when the
output goes from LOW to HIGH. This action (called active pull-up) provides fast
rise time at the output.
D3
• Disadvantages :
• During transition from LOW to HIGH, Q4 turns OFF more slowly than Q3 turns ON,
so that there is a few nano-seconds during which both transistors are conducting. Q4
During this period a relatively large current (30-50 mA) will be drawn from the
supply.
• Thus whenever a totem-pole output goes from LOW to HIGH, a high amplitude
current spike is drawn from the +5 V supply.
• The advantages generally outweigh the disadvantages.
Temperature
• Of course life is never quite a simple as it first appears.
• Temperature has a large effect on TTL circuits.
• In particular is has an effect on the activation energy of transistors, the minimum energy required for
the transistor to react (cut-off to saturation etc.).
• As the temperature increases the transistor requires less energy to react.
• This leads to faster circuits and improved performance (to a point).
• It can lead to thermal instability and unpredictable behaviour of circuits.
• Gate characteristics must remain constant over operating temperatures.
• Most commercial TTL logic gates are specified to operate between 0-70 oC.
• Outside of this range the gates may not behave as expected.
CMOS
• CMOS gates are Field-effect transistors called MOSFETs (Metal Oxide Semiconductor Field Effect Transistor).
• There are two kinds of MOSFET; NMOS and PMOS.
• NMOS turns on when voltage is high and off when low.
• PMOS turns off when voltage is high and on when low.
• Using them together creates CMOS (Complimentary Metal Oxide Semiconductor).
CMOS Inverter
VDD
• The circuit on the left is a CMOS inverter.
• The input gate is connected to two transistors
source and the output is connected to the drain
terminals of both transistors.
• The transistors are a PMOS and an NMOS.
• When the input is high (1) the PMOS is off (cut-
drain off) and the NMOS is on (saturated).
P
in out • The current flows to Vss (usually ground) and
the output is 0.
N • When input is low (0) the PMOS is on (saturated)
drain
and the NMOS is off (cut-off).
• The current flows to output and we get a logical
1.
source

VSS