IRFL014, SiHFL014

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Power MOSFET
D FEATURES
• Surface-mount
• Available in tape and reel
SOT-223 • Dynamic dV/dt rating
D G • Fast switching
• Ease of paralleling Available

S • Simple drive requirements

D
G • Material categorization: for definitions of compliance
S
please see www.vishay.com/doc?99912
N-Channel MOSFET
DESCRIPTION
Marking code: FA Third generation power MOSFETs from Vishay provide the
designer with the best combination of fast switching,
ruggedized device design, low on-resistance and
PRODUCT SUMMARY cost-effectiveness.
VDS (V) 60 The SOT-223 package is designed for surface-mounting
RDS(on) () VGS = 10 V 0.20 using vapor phase, infrared, or wave soldering techniques.
Its unique package design allows for easy automatic
Qg max. (nC) 11
pick-and-place as with other SOT or SOIC packages but
Qgs (nC) 3.1 has the added advantage of improved thermal performance
Qgd (nC) 5.8 due to an enlarged tab for heatsinking. Power dissipation of
Configuration Single greater than 1.25 W is possible in a typical surface mount
application.

ORDERING INFORMATION
Package SOT-223
SiHFL014TR-GE3 a
Lead (Pb)-free and halogen-free
IRFL014TRPbF-BE3 a, b
Lead (Pb)-free IRFL014TRPbF a
Notes
a. See device orientation
b. “-BE3” denotes alternate manufacturing location

ABSOLUTE MAXIMUM RATINGS (TC = 25 °C, unless otherwise noted)

PARAMETER SYMBOL LIMIT UNIT
Drain-source voltage VDS 60
V
Gate-source voltage VGS ± 20
TC = 25 °C 2.7
Continuous drain current VGS at 10 V ID
TC = 100 °C 1.7 A
Pulsed drain current a IDM 22
Linear derating factor 0.025
W/°C
Linear derating factor (PCB mount) e 0.017
Single pulse avalanche energy b EAS 100 mJ
Maximum power dissipation TC = 25 °C 3.1
PD W
Maximum power dissipation (PCB mount) e TA = 25 °C 2.0
Peak diode recovery dv/dt c dV/dt 4.5 V/ns
Operating junction and storage temperature range TJ, Tstg -55 to +150
°C
Soldering recommendations (peak temperature) d For 10 s 300
Notes
a. Repetitive rating; pulse width limited by maximum junction temperature (see fig. 11)
b. VDD = 25 V, starting TJ = 25 °C, L = 16 mH, Rg = 25 , IAS = 2.7 A (see fig. 12)
c. ISD  10 A, dI/dt  90 A/μs, VDD  VDS, TJ  150 °C
d. 1.6 mm from case
e. When mounted on 1" square PCB (FR-4 or G-10 material)

S21-0322-Rev. G, 05-Apr-2021 1 Document Number: 91191

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THERMAL RESISTANCE RATINGS

PARAMETER SYMBOL MIN. TYP. MAX. UNIT
Maximum junction-to-ambient 
RthJA - - 60
(PCB mount) a °C/W
Maximum junction-to-case (drain) RthJC - - 40
Note
a. When mounted on 1" square PCB (FR-4 or G-10 material)

SPECIFICATIONS (TJ = 25 °C, unless otherwise noted)

PARAMETER SYMBOL TEST CONDITIONS MIN. TYP. MAX. UNIT
Static
Drain-source breakdown voltage VDS VGS = 0 V, ID = 250 μA 60 - - V
VDS temperature coefficient VDS/TJ Reference to 25 °C, ID = 1 mA - 0.068 - V/°C
Gate-source threshold voltage VGS(th) VDS = VGS, ID = 250 μA 2.0 - 4.0 V
Gate-source leakage IGSS VGS = ± 20 V - - ± 100 nA
VDS = 60 V, VGS = 0 V - - 25
Zero gate voltage drain current IDSS μA
VDS = 48 V, VGS = 0 V, TJ = 125 °C - - 250
Drain-source on-state resistance RDS(on) VGS = 10 V ID = 1.6 A b - - 0.20 
Forward transconductance gfs VDS = 25 V, ID = 1.6 A 1.9 - - S
Dynamic
Input capacitance Ciss VGS = 0 V, - 300 -
Output capacitance Coss VDS = 25 V, - 160 - pF
Reverse transfer capacitance Crss f = 1.0 MHz, see fig. 5 - 29 -
Total gate charge Qg - - 11
ID = 10 A, VDS = 48 V,
Gate-source charge Qgs VGS = 10 V - - 3.1 nC
see fig. 6 and 13 b
Gate-drain charge Qgd - - 5.8
Turn-on delay time td(on) - 10 -
Rise time tr VDD = 30 V, ID = 10 A, - 50 -
ns
Turn-off delay time td(off) Rg = 24 , RD = 2.7 , see fig. 10 b - 13 -
Fall time tf - 19 -
Between lead, D

Internal drain inductance LD - 4.0 -

6 mm (0.25") from
package and center of G
nH
Internal source inductance LS die contact - 6.0 -
S

Drain-Source Body Diode Characteristics

MOSFET symbol
Continuous source-drain diode current IS D
- - 2.7
showing the 
integral reverse G
A
Pulsed diode forward current a ISM p - n junction diode S
- - 22

Body diode voltage VSD TJ = 25 °C, IS = 2.7 A, VGS = 0 V b - - 1.6 V

Body diode reverse recovery time trr - 70 140 ns
TJ = 25 °C, IF = 10 A, dI/dt = 100 A/μs b
Body diode reverse recovery charge Qrr - 0.20 0.40 μC
Forward turn-on time ton Intrinsic turn-on time is negligible (turn-on is dominated by LS and LD)
Notes
a. Repetitive rating; pulse width limited by maximum junction temperature (see fig. 11)
b. Pulse width  300 μs; duty cycle  2 %

S21-0322-Rev. G, 05-Apr-2021 2 Document Number: 91191

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ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000
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TYPICAL CHARACTERISTICS (25 °C, unless otherwise noted)

Fig. 1 - Typical Output Characteristics, TC = 25 °C Fig. 3 - Typical Transfer Characteristics

Fig. 2 - Typical Output Characteristics, TC = 150 °C Fig. 4 - Normalized On-Resistance vs. Temperature

S21-0322-Rev. G, 05-Apr-2021 3 Document Number: 91191

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THIS DOCUMENT IS SUBJECT TO CHANGE WITHOUT NOTICE. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT
ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000
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Fig. 5 - Typical Capacitance vs. Drain-to-Source Voltage Fig. 7 - Typical Source-Drain Diode Forward Voltage

Fig. 6 - Typical Gate Charge vs. Gate-to-Source Voltage Fig. 8 - Maximum Safe Operating Area

S21-0322-Rev. G, 05-Apr-2021 4 Document Number: 91191

For technical questions, contact: [email protected]
THIS DOCUMENT IS SUBJECT TO CHANGE WITHOUT NOTICE. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT
ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000
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RD
VDS

VGS
D.U.T.
Rg
+
- VDD

10 V
Pulse width ≤ 1 µs
Duty factor ≤ 0.1 %

Fig. 10a -Switching Time Test Circuit

VDS
90 %

10 %
VGS
td(on) tr td(off) tf
Fig. 9 - Maximum Drain Current vs. Case Temperature
Fig. 10b -Switching Time Waveforms

Fig. 11 - Maximum Effective Transient Thermal Impedance, Junction-to-Case

S21-0322-Rev. G, 05-Apr-2021 5 Document Number: 91191

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L
VDS VDS
Vary tp to obtain tp
required IAS VDD
Rg D.U.T. +
V DD
- VDS
I AS
10 V
tp 0.01 Ω
IAS

Fig. 12a - Unclamped Inductive Test Circuit Fig. 12b - Unclamped Inductive Waveforms

Fig. 12c - Maximum Avalanche Energy vs. Drain Current

Current regulator
Same type as D.U.T.

QG 50 kΩ

VGS 12 V 0.2 µF
0.3 µF

QGS QGD +
VDS
D.U.T. -

VG
VGS

3 mA

Charge
IG ID
Current sampling resistors

Fig. 13a - Basic Gate Charge Waveform Fig. 13b - Gate Charge Test Circuit

S21-0322-Rev. G, 05-Apr-2021 6 Document Number: 91191

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THIS DOCUMENT IS SUBJECT TO CHANGE WITHOUT NOTICE. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT
ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000
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Vishay Siliconix

Peak Diode Recovery dV/dt Test Circuit

+ Circuit layout considerations

D.U.T.
• Low stray inductance
• Ground plane
• Low leakage inductance
current transformer
-

- +
-

Rg • dV/dt controlled by Rg +
• Driver same type as D.U.T. VDD
-
• ISD controlled by duty factor “D”
• D.U.T. - device under test

Driver gate drive

Period P.W.
D=
P.W. Period

VGS = 10 Va

D.U.T. lSD waveform

Reverse
recovery Body diode forward
current current
dI/dt
D.U.T. VDS waveform
Diode recovery
dV/dt
VDD

Re-applied
voltage
Body diode forward drop
Inductor current

Ripple ≤ 5 % ISD

Note
a. VGS = 5 V for logic level devices

Fig. 12 - For N-Channel

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Vishay Siliconix maintains worldwide manufacturing capability. Products may be manufactured at one of several qualified locations. Reliability data for Silicon
Technology and Package Reliability represent a composite of all qualified locations. For related documents such as package/tape drawings, part marking, and
reliability data, see www.vishay.com/ppg?91191.

S21-0322-Rev. G, 05-Apr-2021 7 Document Number: 91191

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THIS DOCUMENT IS SUBJECT TO CHANGE WITHOUT NOTICE. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT
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 Package Information
Vishay Siliconix

SOT-223 (HIGH VOLTAGE)

D B A
3
0.08 (0.003)
B1
C
0.10 (0.004) M C B M
A
4

3 H
E
0.20 (0.008) M C A M
L1
1 2 3
4xL
3xB
e θ
0.10 (0.004) M C B M
e1
4xC

MILLIMETERS INCHES
DIM. MIN. MAX. MIN. MAX.
A 1.55 1.80 0.061 0.071
B 0.65 0.85 0.026 0.033
B1 2.95 3.15 0.116 0.124
C 0.25 0.35 0.010 0.014
D 6.30 6.70 0.248 0.264
E 3.30 3.70 0.130 0.146
e 2.30 BSC 0.0905 BSC
e1 4.60 BSC 0.181 BSC
H 6.71 7.29 0.264 0.287
L 0.91 - 0.036 -
L1 0.061 BSC 0.0024 BSC
θ - 10' - 10'
ECN: S-82109-Rev. A, 15-Sep-08
DWG: 5969
Notes
1. Dimensioning and tolerancing per ASME Y14.5M-1994.
2. Dimensions are shown in millimeters (inches).
3. Dimension do not include mold flash.
4. Outline conforms to JEDEC outline TO-261AA.

Document Number: 91363 www.vishay.com

Revision: 15-Sep-08 1
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Revision: 01-Jan-2024 1 Document Number: 91000

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THIS DOCUMENT IS SUBJECT TO CHANGE WITHOUT NOTICE. THE PRODUCTS DESCRIBED HEREIN AND THIS DOCUMENT
ARE SUBJECT TO SPECIFIC DISCLAIMERS, SET FORTH AT www.vishay.com/doc?91000