LTC2208-14

14-Bit, 130Msps ADC

FEATURES DESCRIPTION
n Sample Rate: 130Msps The LTC®2208-14 is a 130Msps, sampling 14-bit A/D
n 77.1dBFS Noise Floor converter designed for digitizing high frequency, wide
n 98dB SFDR dynamic range signals with input frequencies up to
n SFDR >81dB at 250MHz (1.5VP-P Input Range) 700MHz. The input range of the ADC can be optimized
n PGA Front End (2.25VP-P or 1.5VP-P Input Range) with the PGA front end.
n 700MHz Full Power Bandwidth S/H
n
The LTC2208-14 is perfect for demanding communications
Optional Internal Dither
n
applications, with AC performance that includes 77.1dBFS
Optional Data Output Randomizer
n
Noise Floor and 98dB spurious free dynamic range (SFDR).
LVDS or CMOS Outputs
n
Ultralow jitter of 70fsRMS allows undersampling of high
Single 3.3V Supply
n
input frequencies with excellent noise performance.
Power Dissipation: 1.32W
n
Maximum DC specs include ±1.5LSB INL, ±0.5LSB DNL
Clock Duty Cycle Stabilizer
n
(no missing codes).
Pin Compatible 16-Bit Version
130Msps: LTC2208 (16-Bit) The digital output can be either differential LVDS or
n 64-Pin (9mm × 9mm) QFN Package single-ended CMOS. There are two format options for the
CMOS outputs: a single bus running at the full data rate or
APPLICATIONS demultiplexed buses running at half data rate. A separate
n Telecommunications output power supply allows the CMOS output swing to
n Receivers range from 0.5V to 3.6V.
n Cellular Base Stations The ENC+ and ENC– inputs may be driven differentially
n Spectrum Analysis or single-ended with a sine wave, PECL, LVDS, TTL or
n Imaging Systems CMOS inputs. An optional clock duty cycle stabilizer al-
n ATE lows high performance at full speed with a wide range of
L, LT, LTC, LTM, Linear Technology and the Linear logo are registered trademarks of Linear clock duty cycles.
Technology Corporation. All other trademarks are the property of their respective owners.

TYPICAL APPLICATION
3.3V
32k Point FFT, fIN = 15.11MHz,
SENSE
–1dB, PGA = 0, RAND “On”,
VCM 1.25V INTERNAL ADC
OVDD
0.5V TO 3.6V
Dither “OFF”
COMMON MODE REFERENCE 0
2.2μF BIAS VOLTAGE GENERATOR 0.1μF
–10
–20
OF
AIN+ CLKOUT –30
+
AMPLITUDE (dBFS)

14-BIT CORRECTION OUTPUT D13 CMOS –40

ANALOG S/H PIPELINED DRIVERS
LOGIC AND • OR –50
INPUT AMP ADC CORE SHIFT REGISTER • LVDS
AIN–
– •
–60
D0 –70
–80
OGND
–90
CLOCK/DUTY –100
CYCLE VDD 3.3V
CONTROL –110
0.1μF 0.1μF
GND 0.1μF –120
0 10 20 30 40 50 60
220814 TA01 FREQUENCY (MHz)
ENC + ENC – PGA SHDN DITH MODE LVDS RAND
220814 G05

ADC CONTROL INPUTS

220814fb

1
LTC2208-14
ABSOLUTE MAXIMUM RATINGS PIN CONFIGURATION
OVDD = VDD (Notes 1 and 2)
TOP VIEW
Supply Voltage (VDD) ................................... –0.3V to 4V

58 D13+/DA12
57 D13–/DA11
56 D12+/DA10
55 D12–/DA9
54 D11+/DA8
53 D11–/DA7
52 D10+/DA6
51 D10–/DA5
59 OF–/DA13
60 OF+/0FA
62 MODE

50 OGND
63 RAND
Digital Output Ground Voltage (OGND) ........ –0.3V to 1V

61 LVDS

49 OVDD
64 PGA
Analog Input Voltage (Note 3) ..... –0.3V to (VDD + 0.3V)
Digital Input Voltage .................... –0.3V to (VDD + 0.3V) SENSE 1 48 D9+/DA4
GND 2 47 D9–/DA3
Digital Output Voltage................ –0.3V to (OVDD + 0.3V) VCM 3 46 D8+/DA2
GND 4 45 D8–/DA1
Power Dissipation ............................................ 2000mW VDD 5 44 D7+/DA0
VDD 6 43 D7–/DNC
Operating Temperature Range GND 7 42 D6+/DNC
AIN+ 8 41 D6–/CLKOUTA
LTC2208C-14 ........................................... 0°C to 70°C AIN– 9
65
40 CLKOUT+/CLKOUTB
GND 10 39 CLKOUT–/OFB
LTC2208I-14 ........................................–40°C to 85°C GND 11 38 D5+_ /DB13
ENC+ 12 37 D5 /DB12
Storage Temperature Range ..................–65°C to 150°C ENC– 13 36 D4+/DB11
GND 14 35 D4–/DB10
Digital Output Supply Voltage (OVDD) .......... –0.3V to 4V VDD 15 34 D3+/DB9
VDD 16 33 D3–/DB8

VDD 17
GND 18
SHDN 19
DITH 20
NC 21
NC 22
DNC/DB0 23
DNC/DB1 24
D0–/DB2 25
D0+/DB3 26
D1–/DB4 27
D1+/DB5 28
D2–/DB6 29
D2+/DB7 30
OGND 31
OVDD 32
UP PACKAGE
64-LEAD (9mm s 9mm) PLASTIC QFN
EXPOSED PAD (PIN 65) IS GND, MUST BE SOLDERED TO PCB BOARD
TJMAX = 150°C, θJA = 20°C/W

ORDER INFORMATION
LEAD FREE FINISH TAPE AND REEL PART MARKING* PACKAGE DESCRIPTION TEMPERATURE RANGE
LTC2208CUP-14#PBF LTC2208CUP-14#TRPBF LTC2208UP-14 64-Lead (9mm × 9mm) Plastic Plastic QFN 0°C to 70°C
LTC2208IUP-14#PBF LTC2208IUP-14#TRPBF LTC2208UP-14 64-Lead (9mm × 9mm) Plastic Plastic QFN –40°C to 85°C
Consult LTC Marketing for parts specified with wider operating temperature ranges. *The temperature grade is identified by a label on the shipping container.
Consult LTC Marketing for information on non-standard lead based finish parts.
For more information on lead free part marking, go to: http://www.linear.com/leadfree/
For more information on tape and reel specifications, go to: http://www.linear.com/tapeandreel/

CONVERTER CHARACTERISTICS The l denotes the specifications which apply over the full operating
temperature range, otherwise specifications are at TA = 25°C. (Note 4)
PARAMETER CONDITIONS MIN TYP MAX UNITS
Integral Linearity Error Differential Analog Input (Note 5) l ±1 ±1.5 LSB
Differential Linearity Error Differential Analog Input l ±0.2 ±0.5 LSB
Offset Error (Note 6) l ±2 ±10.8 mV
Offset Drift ±10 μV/°C
Gain Error External Reference l ±0.2 ±2.3 %FS
Full-Scale Drift Internal Reference ±30 ppm/°C
External Reference ±15 ppm/°C
Transition Noise External Reference 0.8 LSBRMS

220814fb

2
 LTC2208-14
ANALOG INPUT The l denotes the specifications which apply over the full operating temperature range, otherwise
specifications are at TA = 25°C. (Note 4)
SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS
VIN Analog Input Range (AIN+ – AIN–) 3.135V ≤ VDD ≤ 3.465V 1.5 to 2.25 VP-P
VIN, CM Analog Input Common Mode Differential Input (Note 7) l 1 1.25 1.5 V
IIN Analog Input Leakage Current 0V ≤ AIN+, AIN– ≤ VDD l –1 1 μA
ISENSE SENSE Input Leakage Current 0V ≤ SENSE ≤ VDD l –3 3 μA
IMODE MODE Pin Pull-Down Current to GND 10 μA
ILVDS LVDS Pin Pull-Down Current to GND 10 μA
CIN Analog Input Capacitance Sample Mode ENC+ < ENC– 6.5 pF
Hold Mode ENC+ > ENC– 1.8 pF
tAP Sample-and-Hold 1 ns
Acquisition Delay Time
tJITTER Sample-and-Hold 70 fsRMS
Acquisition Delay Time Jitter
CMRR Analog Input 1V < (AIN+ = AIN–) <1.5V 80 dB
Common Mode Rejection Ratio
BW-3dB Full Power Bandwidth RS ≤ 25Ω 700 MHz

DYNAMIC ACCURACY The l denotes the specifications which apply over the full operating temperature range,
otherwise specifications are at TA = 25°C. AIN = –1dBFS. (Note 4)
SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS
SNR Signal-to-Noise Ratio 5MHz Input (2.25V Range, PGA = 0) 77.1 dBFS
5MHz Input (1.5V Range, PGA = 1) 74.9 dBFS
30MHz Input (2.25V Range, PGA = 0), TA = 25ºC 75.7 77 dBFS
30MHz Input (2.25V Range, PGA = 0) l 75.4 77 dBFS
30MHz Input (1.5V Range, PGA = 1) 74.9 dBFS
70MHz Input (2.25V Range, PGA = 0) 76.9 dBFS
70MHz Input (1.5V Range, PGA = 1) 74.8 dBFS
140MHz Input (2.25V Range, PGA = 0) 76.4 dBFS
140MHz Input (1.5V Range, PGA = 1), TA = 25ºC 73.5 74.6 dBFS
140MHz Input (1.5V Range, PGA = 1) l 73.3 74.6 dBFS
250MHz Input (2.25V Range, PGA = 0) 75 dBFS
250MHz Input (1.5V Range, PGA = 1) 73.6 dBFS
SFDR Spurious Free 5MHz Input (2.25V Range, PGA = 0) 98 dBc
Dynamic Range 5MHz Input (1.5V Range, PGA = 1) 98 dBc
2nd or 3rd 30MHz Input (2.25V Range, PGA = 0) l 84 96 dBc
Harmonic 30MHz Input (1.5V Range, PGA = 1) 98 dBc
70MHz Input (2.25V Range, PGA = 0) 90 dBc
70MHz Input (1.5V Range, PGA = 1) 93 dBc
140MHz Input (2.25V Range, PGA = 0) 85 dBc
140MHz Input (1.5V Range, PGA = 1) l 81.5 95 dBc
250MHz Input (2.25V Range, PGA = 0) 76 dBc
250MHz Input (1.5V Range, PGA = 1) 81 dBc

220814fb

3
LTC2208-14
DYNAMIC ACCURACY The l denotes the specifications which apply over the full operating temperature range,
otherwise specifications are at TA = 25°C. AIN = –1dBFS. (Note 4)
SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS
SFDR Spurious Free 5MHz Input (2.25V Range, PGA = 0) 100 dBc
Dynamic Range 5MHz Input (1.5V Range, PGA = 1) 100 dBc
4th Harmonic 30MHz Input (2.25V Range, PGA = 0) l 87 100 dBc
or Higher 30MHz Input (1.5V Range, PGA = 1) 100 dBc
70MHz Input (2.25V Range, PGA = 0) 100 dBc
70MHz Input (1.5V Range, PGA = 1) 100 dBc
140MHz Input (2.25V Range, PGA = 0) 95 dBc
140MHz Input (1.5V Range, PGA = 1) l 85 95 dBc
250MHz Input (2.25V Range, PGA = 0) 90 dBc
250MHz Input (1.5V Range, PGA = 1) 90 dBc
S/(N+D) Signal-to-Noise 5MHz Input (2.25V Range, PGA = 0) 77 dBFS
Plus Distortion Ratio 5MHz Input (1.5V Range, PGA = 1) 74.8 dBFS
30MHz Input (2.25V Range, PGA = 0), TA = 25ºC 75.4 76.9 dBFS
30MHz Input (2.25V Range, PGA = 0 l 75.1 76.9 dBFS
30MHz Input (1.5V Range, PGA = 1) 74.7 dBFS
70MHz Input (2.25V Range, PGA = 0) 76.6 dBFS
70MHz Input (1.5V Range, PGA = 1) 74.6 dBFS
140MHz Input (2.25V Range, PGA = 0) 76.3 dBFS
140MHz Input (1.5V Range, PGA = 1), TA = 25ºC 73.4 74.5 dBFS
140MHz Input (1.5V Range, PGA = 1) l 73 74.5 dBFS
250MHz Input (2.25V Range, PGA = 0) 73.6 dBFS
250MHz Input (1.5V Range, PGA = 1) 72.9 dBFS
SFDR Spurious Free Dynamic Range 5MHz Input (2.25V Range, PGA = 0) 105 dBFS
at –25dBFS 5MHz Input (1.5V Range, PGA = 1) 105 dBFS
Dither “OFF” 30MHz Input (2.25V Range, PGA = 0) 105 dBFS
30MHz Input (1.5V Range, PGA = 1) 105 dBFS
70MHz Input (2.25V Range, PGA = 0) 105 dBFS
70MHz Input (1.5V Range, PGA = 1) 105 dBFS
140MHz Input (2.25V Range, PGA = 0) 100 dBFS
140MHz Input (1.5V Range, PGA = 1) 100 dBFS
250MHz Input (2.25V Range, PGA = 0) 100 dBFS
250MHz Input (1.5V Range, PGA = 1) 100 dBFS
SFDR Spurious Free Dynamic Range 5MHz Input (2.25V Range, PGA = 0) 115 dBFS
at –25dBFS 5MHz Input (1.5V Range, PGA = 1) 115 dBFS
Dither “ON” 30MHz Input (2.25V Range, PGA = 0) l 95 110 dBFS
30MHz Input (1.5V Range, PGA = 1) 110 dBFS
70MHz Input (2.25V Range, PGA = 0) 110 dBFS
70MHz Input (1.5V Range, PGA = 1) 110 dBFS
140MHz Input (2.25V Range, PGA = 0) 107 dBFS
140MHz Input (1.5V Range, PGA = 1) 107 dBFS
250MHz Input (2.25V Range, PGA = 0) 105 dBFS
250MHz Input (1.5V Range, PGA = 1) 105 dBFS

220814fb

4
 LTC2208-14
COMMON MODE BIAS CHARACTERISTICS The l denotes the specifications which apply over
the full operating temperature range, otherwise specifications are at TA = 25°C. (Note 4)
PARAMETER CONDITIONS MIN TYP MAX UNITS
VCM Output Voltage IOUT = 0 1.15 1.25 1.35 V
VCM Output Tempco IOUT = 0 40 ppm/°C
VCM Line Regulation 3.135V ≤ VDD ≤ 3.465V 1 mV/ V
VCM Output Resistance | IOUT | ≤ 1mA 2 Ω

DIGITAL INPUTS AND DIGITAL OUTPUTS The l denotes the specifications which apply over the
full operating temperature range, otherwise specifications are at TA = 25°C. (Note 4)
SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS
ENCODE INPUTS (ENC+, ENC–)
VID Differential Input Voltage (Note 7) l 0.2 V
VICM Common Mode Input Voltage Internally Set 1.6 V
Externally Set (Note 7) 1.2 3
RIN Input Resistance (See Figure 2) 6 kΩ
CIN Input Capacitance (Note 7) 3 pF
LOGIC INPUTS (DITH, PGA, SHDN, RAND)
VIH High Level Input Voltage VDD = 3.3V l 2 V
VIL Low Level Input Voltage VDD = 3.3V l 0.8 V
IIN Digital Input Current VIN = 0V to VDD l ±10 μA
CIN Digital Input Capacitance (Note 7) 1.5 pF
LOGIC OUTPUTS (CMOS MODE)
OVDD = 3.3V
VOH High Level Output Voltage VDD = 3.3V IO = –10μA 3.299 V
IO = –200μA l 3.1 3.29 V
VOL Low Level Output Voltage VDD = 3.3V IO = 160μA 0.01 V
IO = 1.60mA l 0.1 0.4 V
ISOURCE Output Source Current VOUT = 0V –50 mA
ISINK Output Sink Current VOUT = 3.3V 50 mA
OVDD = 2.5V
VOH High Level Output Voltage VDD = 3.3V IO = –200μA 2.49 V
VOL Low Level Output Voltage VDD = 3.3V IO = 1.6mA 0.1 V
OVDD = 1.8V
VOH High Level Output Voltage VDD = 3.3V IO = –200μA 1.79 V
VOL Low Level Output Voltage VDD = 3.3V IO = 1.6mA 0.1 V
LOGIC OUTPUTS (LVDS MODE)
STANDARD LVDS
VDD Differential Output Voltage 100Ω Differential Load l 247 350 454 mV
VOS Output Common Mode Voltage 100Ω Differential Load l 1.125 1.2 1.375 V
LOW POWER LVDS
VDD Differential Output Voltage 100Ω Differential Load l 125 175 250 mV
VOS Output Common Mode Voltage 100Ω Differential Load l 1.125 1.2 1.375 V
220814fb

5
LTC2208-14
POWER REQUIREMENTS The l denotes the specifications which apply over the full operating temperature
range, otherwise specifications are at TA = 25°C. AIN = –1dBFS. (Note 4)
SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS
VDD Analog Supply Voltage (Note 8) l 3.135 3.3 3.465 V
PSHDN Shutdown Power SHDN = VDD 0.2 mW
STANDARD LVDS OUTPUT MODE
OVDD Output Supply Voltage (Note 8) l 3 3.3 3.6 V
IVDD Analog Supply Current l 401 470 mA
IOVDD Output Supply Voltage l 71 90 mA
PDIS Power Dissipation l 1498 1782 mW
LOW POWER LVDS OUTPUT MODE
OVDD Output Supply Voltage (Note 8) l 3 3.3 3.6 V
IVDD Analog Supply Current l 401 470 mA
IOVDD Output Supply Voltage l 40 50 mA
PDIS Power Dissipation l 1356 1650 mW
CMOS OUTPUT MODE
OVDD Output Supply Voltage (Note 8) l 0.5 3.6 V
IVDD Analog Supply Current l 401 470 mA
PDIS Power Dissipation l 1320 1551 mW

TIMING CHARACTERISTICS The l denotes the specifications which apply over the full operating temperature
range, otherwise specifications are at TA = 25°C. (Note 4)
SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS
fS Sampling Frequency (Note 8) l 1 130 MHz
tL ENC Low Time Duty Cycle Stabilizer Off (Note 7) l 3.65 3.846 1000 ns
Duty Cycle Stabilizer On (Note 7) l 2.6 3.846 1000 ns
tH ENC High Time Duty Cycle Stabilizer Off (Note 7) l 3.65 3.846 1000 ns
Duty Cycle Stabilizer On (Note 7) l 2.6 3.846 1000 ns
tAP Sample-and-Hold Aperture Delay –1 ns
LVDS OUTPUT MODE (STANDARD AND LOW POWER)
tD ENC to DATA Delay (Note 7) l 1.3 2.5 3.8 ns
tC ENC to CLKOUT Delay (Note 7) l 1.3 2.5 3.8 ns
tSKEW DATA to CLKOUT Skew (tC-tD) (Note 7) l –0.6 0 0.6 ns
tRISE Output Rise Time 0.5 ns
tFALL Output Fall Time 0.5 ns
Data Latency Data Latency 7 Cycles
CMOS OUTPUT MODE
tD ENC to DATA Delay (Note 7) l 1.3 2.7 4 ns
tC ENC to CLKOUT Delay (Note 7) l 1.3 2.7 4 ns
tSKEW DATA to CLKOUT Skew (tC-tD) (Note 7) l –0.6 0 0.6 ns
Data Latency Data Latency Full Rate CMOS 7 Cycles
Demuxed 7 Cycles

220814fb

6
 LTC2208-14
ELECTRICAL CHARACTERISTICS
Note 1: Stresses beyond those listed under Absolute Maximum Ratings Note 5: Integral nonlinearity is defined as the deviation of a code from a “best
may cause permanent damage to the device. Exposure to any Absolute fit straight line” to the transfer curve. The deviation is measured from the
Maximum Rating condition for extended periods may affect device center of the quantization band.
reliability and lifetime. Note 6: Offset error is the offset voltage measured from –1/2LSB when the
Note 2: All voltage values are with respect to GND, with GND and OGND output code flickers between 00 0000 0000 0000 and 11 1111 1111 1111 in
shorted (unless otherwise noted). 2’s complement output mode.
Note 3: When these pin voltages are taken below GND or above VDD, they Note 7: Guaranteed by design, not subject to test.
will be clamped by internal diodes. This product can handle input currents Note 8: Recommended operating conditions.
of greater than 100mA below GND or above VDD without latchup.
Note 4: VDD = 3.3V, fSAMPLE = 130MHz, LVDS outputs, differential ENC+/
ENC– = 2VP-P sine wave with 1.6V common mode, input range = 2.25VP-P
with differential drive (PGA = 0), unless otherwise specified.

TIMING DIAGRAM
LVDS Output Mode Timing
All Outputs are Differential and Have LVDS Levels

tAP
N+1 N+4
ANALOG
INPUT N N+3
N+2
tH
tL

ENC–

ENC+
tD

D0-D13, OF N–7 N–6 N–5 N–4 N–3

tC
CLKOUT+

CLKOUT – 220814 TD01

220814fb

7
LTC2208-14
TIMING DIAGRAM
Full-Rate CMOS Output Mode Timing
All Outputs are Single-Ended and Have CMOS Levels

tAP
N+1 N+4
ANALOG
INPUT N N+3
N+2
tH
tL
–
ENC

ENC+
tD

DA0-DA13, OFA N–7 N–6 N–5 N–4 N–3

tC
CLKOUTA

CLKOUTB

DB0-DB13, OFB HIGH IMPEDANCE

220814 TD02

Demultiplexed CMOS Output Mode Timing

All Outputs are Single-Ended and Have CMOS Levels

tAP
N+1 N+4
ANALOG
INPUT N N+3
N+2
tH
tL
–
ENC

ENC+
tD

DA0-DA13, OFA N–8 N–6 N–4

tD

DB0-DB13, OFB N–7 N–5 N–3

tC
CLKOUTA

CLKOUTB 220814 TD03

220814fb

8
 LTC2208-14
TYPICAL PERFORMANCE CHARACTERISTICS
Integral Nonlinearity (INL) Differential Nonlinearity (DNL)
vs Output Code vs Output Code AC Grounded Input Histogram
1.0 0.5 250000
0.8 0.4
0.6 0.3 200000
0.4 0.2

DNL ERROR (LSB)

INL ERROR (LSB)

0.2 0.1 150000

COUNT
0 0
–0.2 –0.1 100000
–0.4 –0.2
–0.6 –0.3 50000
–0.8 –0.4
–1.0 –0.5 0
0 4096 8192 12288 16384 0 4096 8192 12288 16384 8176 8178 8180 8182 8184 8186
OUTPUT CODE OUTPUT CODE OUTPUT CODE
220814 G01 220814 G02 220814 G03

32k Point FFT, fIN = 5.21MHz, 32k Point FFT, fIN = 15.11MHz, 128k Point FFT, fIN = 15.11MHz,
–1dBFS, PGA = 0, RAND = “On”, –1dBFS, PGA = 0, RAND = “On”, –40dBFS, PGA = 0, RAND = “On”,
Dither “Off” Dither “Off” Dither “Off”
0 0 0
–10 –10 –10
–20 –20 –20
–30 –30 –30

AMPLITUDE (dBFS)
AMPLITUDE (dBFS)

AMPLITUDE (dBFS)

–40 –40 –40

–50 –50 –50
–60 –60 –60
–70 –70 –70
–80 –80 –80
–90 –90 –90
–100 –100 –100
–110 –110 –110
–120 –120 –120
0 10 20 30 40 50 60 0 10 20 30 40 50 60 0 10 20 30 40 50 60
FREQUENCY (MHz) FREQUENCY (MHz) FREQUENCY (MHz)
220814 G04 220814 G05 220814 G06

128k Point FFT, fIN = 15.11MHz, 32k Point 2-Tone FFT, fIN = 20.14MHz 32k Point 2-Tone FFT, fIN = 20.14MHz
–40dBFS, PGA = 0, RAND = “On”, and 14.25MHz, –7dBFS, PGA = 0, and 14.25MHz, –25dBFS, PGA = 0,
Dither “On” RAND = “On”, Dither “Off” RAND = “On”, Dither “Off”
0 0 0
–10 –10 –10
–20 –20 –20
–30 –30 –30
AMPLITUDE (dBFS)

AMPLITUDE (dBFS)
AMPLITUDE (dBFS)

–40 –40 –40

–50 –50 –50
–60 –60 –60
–70 –70 –70
–80 –80 –80
–90 –90 –90
–100 –100 –100
–110 –110 –110
–120 –120 –120
0 10 20 30 40 50 60 0 10 20 30 40 50 60 0 10 20 30 40 50 60
FREQUENCY (MHz) FREQUENCY (MHz) FREQUENCY (MHz)
220814 G07 220814 G08 220814 G09

220814fb

9
LTC2208-14
TYPICAL PERFORMANCE CHARACTERISTICS
32k Point FFT, fIN = 30.11MHz,
SFDR vs Input Level, fIN = 15.1MHz, SFDR vs Input Level, fIN = 15.1MHz, –1dBFS, PGA = 0, RAND = “On”,
PGA = 0, RAND = “On”, Dither “Off” PGA = 0, RAND = “On”, Dither “On” Dither “Off”
120 120 0
–10
100 100 –20
–30
SFDR (dBc AND dBFS)

SFDR (dBc AND dBFS)

AMPLITUDE (dBFS)
80 80 –40
–50
60 60 –60
–70
40 40 –80
–90
20 20 –100
–110
0 0 –120
–80 –70 –60 –50 –40 –30 –20 –10 0 –80 –70 –60 –50 –40 –30 –20 –10 0 0 10 20 30 40 50 60
INPUT LEVEL (dBFS) INPUT LEVEL (dBFS) FREQUENCY (MHz)
220814 G10 220814 G11 220814 G12

32k Point FFT, fIN = 30.11MHz, 32k Point FFT, fIN = 70.11MHz, 32k Point FFT, fIN = 70.11MHz,
–25dBFS, PGA = 0, RAND = “On”, –1dBFS, PGA = 0, RAND = “On”, –10dBFS, PGA = 0, RAND = “On”,
Dither “On” Dither “Off” Dither “Off”
0 0 0
–10 –10 –10
–20 –20 –20
–30 –30 –30
AMPLITUDE (dBFS)

AMPLITUDE (dBFS)

AMPLITUDE (dBFS)
–40 –40 –40
–50 –50 –50
–60 –60 –60
–70 –70 –70
–80 –80 –80
–90 –90 –90
–100 –100 –100
–110 –110 –110
–120 –120 –120
0 10 20 30 40 50 60 0 10 20 30 40 50 60 0 10 20 30 40 50 60
FREQUENCY (MHz) FREQUENCY (MHz) FREQUENCY (MHz)
220814 G13 220814 G14 220814 G15

128k Point FFT, fIN = 70.11MHz, 128k Point FFT, fIN = 70.11MHz, 32k Point FFT, fIN = 70.11MHz,
–40dBFS, PGA = 0, RAND = “On”, –40dBFS, PGA = 0, RAND = “On”, –1dBFS, PGA = 1, RAND = “On”,
Dither “Off” Dither “On” Dither “Off”
0 0 0
–10 –10 –10
–20 –20 –20
–30 –30 –30
AMPLITUDE (dBFS)

AMPLITUDE (dBFS)
AMPLITUDE (dBFS)

–40 –40 –40

–50 –50 –50
–60 –60 –60
–70 –70 –70
–80 –80 –80
–90 –90 –90
–100 –100 –100
–110 –110 –110
–120 –120 –120
0 10 20 30 40 50 60 0 10 20 30 40 50 60 0 10 20 30 40 50 60
FREQUENCY (MHz) FREQUENCY (MHz) FREQUENCY (MHz)
220814 G16 220814 G17 220814 G18

220814fb

10
 LTC2208-14
TYPICAL PERFORMANCE CHARACTERISTICS
32k Point 2-Tone FFT, fIN = 67.2MHz
SFDR vs Input Level, fIN = 70.2MHz, SFDR vs Input Level, fIN = 70.2MHz, and 74.4MHz, –7dBFS, PGA = 0,
PGA = 0, RAND = “On”, Dither “Off” PGA = 0, RAND = “On”, Dither “On” RAND = “On”, Dither “Off”
120 120 0
–10
100 100 –20
–30
SFDR (dBc AND dBFS)

SFDR (dBc AND dBFS)

AMPLITUDE (dBFS)
80 80 –40
–50
60 60 –60
–70
40 40 –80
–90
20 20 –100
–110
0 0 –120
–80 –70 –60 –50 –40 –30 –20 –10 0 –80 –70 –60 –50 –40 –30 –20 –10 0 0 10 20 30 40 50 60
INPUT LEVEL (dBFS) INPUT LEVEL (dBFS) FREQUENCY (MHz)
220814 G19 220814 G20 220814 G21

32k Point 2-Tone FFT, fIN = 67.2MHz 32k Point FFT, fIN = 140.11MHz, 32k Point FFT, fIN = 140.11MHz,
and 74.4MHz, –15dBFS, PGA = 0, –1dBFS, PGA = 0, RAND = “On”, –1dBFS, PGA = 1, RAND = “On”,
RAND = “On”, Dither “Off” Dither “Off” Dither “Off”
0 0 0
–10 –10 –10
–20 –20 –20
–30 –30 –30
AMPLITUDE (dBFS)

AMPLITUDE (dBFS)

AMPLITUDE (dBFS)
–40 –40 –40
–50 –50 –50
–60 –60 –60
–70 –70 –70
–80 –80 –80
–90 –90 –90
–100 –100 –100
–110 –110 –110
–120 –120 –120
0 10 20 30 40 50 60 0 10 20 30 40 50 60 0 10 20 30 40 50 60
FREQUENCY (MHz) FREQUENCY (MHz) FREQUENCY (MHz)
220814 G22 220814 G23 220814 G24

32k Point FFT, fIN = 170.1MHz,

SFDR vs Input Level, fIN = 140.1MHz, SFDR vs Input Level, fIN = 140.1MHz, –1dBFS, PGA = 1, RAND = “On”,
PGA = 1, RAND = “On”, Dither “Off” PGA = 1, RAND = “On”, Dither “On” Dither “Off”
120 120 0
–10
100 100 –20
–30
SFDR (dBc AND dBFS)
SFDR (dBc AND dBFS)

AMPLITUDE (dBFS)

80 80 –40
–50
60 60 –60
–70
40 40 –80
–90
20 20 –100
–110
0 0 –120
–80 –70 –60 –50 –40 –30 –20 –10 0 –80 –70 –60 –50 –40 –30 –20 –10 0 0 10 20 30 40 50 60
INPUT LEVEL (dBFS) INPUT LEVEL (dBFS) FREQUENCY (MHz)
220814 G25 220814 G26 220814 G27

220814fb

11
LTC2208-14
TYPICAL PERFORMANCE CHARACTERISTICS
32k Point FFT, fIN = 250.11MHz, 32k Point FFT, fIN = 250.11MHz, 32k Point FFT, fIN = 380.11MHz,
–1dBFS, PGA = 1, RAND = “On”, –10dBFS, PGA = 1, RAND = “On”, –1dBFS, PGA = 1, RAND = “On”,
Dither “Off” Dither “Off” Dither “Off”
0 0 0
–10 –10 –10
–20 –20 –20
–30 –30 –30

AMPLITUDE (dBFS)

AMPLITUDE (dBFS)
AMPLITUDE (dBFS)

–40 –40 –40

–50 –50 –50
–60 –60 –60
–70 –70 –70
–80 –80 –80
–90 –90 –90
–100 –100 –100
–110 –110 –110
–120 –120 –120
0 10 20 30 40 50 60 0 10 20 30 40 50 60 0 10 20 30 40 50 60
FREQUENCY (MHz) FREQUENCY (MHz) FREQUENCY (MHz)
220814 G28 220814 G29 220814 G30

32k Point FFT, fIN = 380.11MHz,

–10dBFS, PGA = 1, RAND = “On”, SFDR (HD2 and HD3)
Dither “Off” vs Input Frequency SNR vs Input Frequency
0 110 78
–10
105
–20 77
–30 100
76
AMPLITUDE (dBFS)

–40 95 PGA = 0
PGA = 1 SNR (dBFS)
SFDR (dBc)

–50 75
90
–60
–70 85 74
PGA = 0
–80 80 PGA = 1
73
–90
75
–100
72
–110 70
–120 65 71
0 10 20 30 40 50 60 0 50 100 150 200 250 300 0 100 200 300
FREQUENCY (MHz) INPUT FREQUENCY (MHz) INPUT FREQUENCY (MHz)
220814 G31 220814 G32 220814 G33

SNR and SFDR vs Sample Rate SNR and SFDR vs Supply Voltage IVDD vs Sample Rate,
fIN = 5.1MHz, –1dBFS (VDD), fIN = 5.1MHz, –1dBFS fIN = 5.1MHz, –1dBfs
110 110 470

105 105
450
SFDR
100 100 VDD = 3.47V
SNR AND SFDR (dBFS)

SNR AND SFDR (dBFS)

SFDR 430
95 95 VDD = 3.3V
IVDD (mA)

90 90 410
VDD = 3.13V
85 85
390
80 SNR 80
SNR
370
75 75

70 70 350
0 25 50 75 100 125 150 175 200 2.8 3.0 3.2 3.4 3.6 0 20 40 60 80 100 120 140 160
SAMPLE RATE (Msps) SUPPLY VOLTAGE (V) SAMPLE RATE (Msps)
220814 G34 220814 G35 220814 G36

220814fb

12
 LTC2208-14
TYPICAL PERFORMANCE CHARACTERISTICS
Gain Error Drift vs Temperature, Gain Error Drift vs Temperature,
SNR and SFDR vs Duty Cycle Internal Reference, Drift from 25°C External Reference, Drift from 25°C
110 0.2 0.08
0.06
SFDR DCS ON 0.1
100 0.04

GAIN ERROR DRIFT (%)

GAIN ERROR DRIFT (%)

SFDR AND SNR (dBFS)

0 0.02
SFDR DCS OFF
90 0
–0.1
–0.02
–0.2
80 –0.04
SNR DCS ON
–0.3 –0.06

70 –0.08
–0.4
SNR DCS OFF –0.10

60 –0.5 –0.12
30 40 50 60 70 –50 –30 –10 10 30 50 70 90 –50 –30 –10 10 30 50 70 90
DUTY CYCLE (%) TEMPERATURE (°C) TEMPERATURE (°C)
220814 G37 220814 G38 220814 G39

Input Offset Voltage Drift SNR and SFDR vs Input Common

vs Temperature, Drift from 25°C Mode Voltage
0.24 100

SFDR
0.20
INPUT OFFSET VOLTAGE (mV)

SNR (dBFS) AND SFDR (dBc)

90
0.15

0.10 80

SNR
0.05
70
0

–0.05 60
–50 –30 –10 10 30 50 70 90 0.50 0.75 1.00 1.25 1.50 1.75 2.00
TEMPERATURE (°C) INPUT COMMON MODE VOLTAGE (V)
220814 G40 220814 G41

Mid-Scale Settling After Wake Full-Scale Settling After Wake

Up from Shutdown or Starting Up from Shutdown or Starting
Encode Clock Encode Clock
1.0 5
0.8 4
0.6 3
FULL-SCALE ERROR (%)
FULL-SCALE ERROR (%)

0.4 2
0.2 1
0 0
–0.2 –1
–0.4 –2
–0.6 –3
–0.8 –4
–1.0 –5
0 50 100 150 200 250 300 350 400 450 500 0 100 200 300 400 500 600 700 800 900 1000
TIME AFTER WAKE-UP OR CLOCK START (μs) TIME FROM WAKE-UP OR CLOCK START (μs)
2208 G42 2208 G43

220814fb

13
LTC2208-14
PIN FUNCTIONS
For CMOS Mode. Full Rate or Demultiplexed OFB (Pin 39): Overflow/Underflow Digital Output for the B
SENSE (Pin 1): Reference Mode Select and External Bus. OFB is high when an over or under flow has occurred
Reference Input. Tie SENSE to VDD to select the internal on the B bus. This pin goes to high impedance state in
2.5V bandgap reference. An external reference of 2.5V or full rate CMOS mode.
1.25V may be used; both reference values will set a full CLKOUTB (Pin 40): Data Valid Output. CLKOUTB will toggle
scale ADC range of 2.25V (PGA = 0). at the sample rate in full rate CMOS mode or at 1/2 the
GND (Pins 2, 4, 7, 10, 11, 14, 18): ADC Power Ground. sample rate in demultiplexed mode. Latch the data on the
falling edge of CLKOUTB.
VCM (Pin 3): 1.25V Output. Optimum voltage for input com-
mon mode. Must be bypassed to ground with a minimum CLKOUTA (Pin 41): Inverted Data Valid Output. CLKOUTA
of 2.2μF. Ceramic chip capacitors are recommended. will toggle at the sample rate in full rate CMOS mode or
at 1/2 the sample rate in demultiplexed mode. Latch the
VDD (Pins 5, 6, 15, 16, 17): 3.3V Analog Supply Pin. data on the rising edge of CLKOUTA.
Bypass to GND with 0.1μF ceramic chip capacitors.
DNC (Pins 42, 43): Do Not Connect in CMOS Mode.
AIN+ (Pin 8): Positive Differential Analog Input.
DA0-DA13 (Pins 44-48 and 51-59): Digital Outputs, A Bus.
AIN– (Pin 9): Negative Differential Analog Input. DA13 is the MSB. Output bus for full rate CMOS mode
ENC+ (Pin 12): Positive Differential Encode Input. The and demultiplexed mode.
sampled analog input is held on the rising edge of ENC+. OFA (Pin 60): Overflow/Underflow Digital Output for the
Internally biased to 1.6V through a 6.2kΩ resistor. Output A Bus. OFA is high when an over or under flow has oc-
data can be latched on the rising edge of ENC+. curred on the A bus.
ENC– (Pin 13): Negative Differential Encode Input. The LVDS (Pin 61): Data Output Mode Select Pin. Connecting
sampled analog input is held on the falling edge of ENC –. LVDS to 0V selects full rate CMOS mode. Connecting LVDS
Internally biased to 1.6V through a 6.2kΩ resistor. By- to 1/3VDD selects demultiplexed CMOS mode. Connecting
pass to ground with a 0.1μF capacitor for a single-ended LVDS to 2/3VDD selects Low Power LVDS mode. Connect-
Encode signal. ing LVDS to VDD selects Standard LVDS mode.
SHDN (Pin 19): Power Shutdown Pin. SHDN = low results MODE (Pin 62): Output Format and Clock Duty Cycle
in normal operation. SHDN = high results in powered Stabilizer Selection Pin. Connecting MODE to 0V selects
down analog circuitry and the digital outputs are placed offset binary output format and disables the clock duty
in a high impedance state. cycle stabilizer. Connecting MODE to 1/3VDD selects offset
DITH (Pin 20): Internal Dither Enable Pin. DITH = low binary output format and enables the clock duty cycle sta-
disables internal dither. DITH = high enables internal dither. bilizer. Connecting MODE to 2/3VDD selects 2’s complement
Refer to Internal Dither section of this data sheet for details output format and enables the clock duty cycle stabilizer.
on dither operation. Connecting MODE to VDD selects 2’s complement output
format and disables the clock duty cycle stabilizer.
NC (Pins 21, 22): No Connect.
RAND (Pin 63): Digital Output Randomization Selection
DB0-DB13 (Pins 23-30 and 33-38): Digital Outputs, B Bus.
Pin. RAND low results in normal operation. RAND high
DB13 is the MSB. Active in demultiplexed mode. The B bus
selects D1-D13 to be EXCLUSIVE-ORed with D0 (the
is in high impedance state in full rate CMOS mode.
LSB). The output can be decoded by again applying an
OGND (Pins 31 and 50): Output Driver Ground. XOR operation between the LSB and all other bits. This
OVDD (Pins 32 and 49): Positive Supply for the Output mode of operation reduces the effects of digital output
Drivers. Bypass to ground with O.1μF capacitor. interference.

220814fb

14
 LTC2208-14
PIN FUNCTIONS
PGA (Pin 64): Programmable Gain Amplifier Control Pin. NC (Pins 21, 22): No Connect.
Low selects a front-end gain of 1, input range of 2.25VP-P.
NC (Pins 23, 24): Do Not Connect in LVDS Mode.
High selects a front-end gain of 1.5, input range of
1.5VP-P. D0–/D0+ to D13–/D13+ (Pins 25-30, 33-38, 41-48 and
51-58): LVDS Digital Outputs. All LVDS outputs require
GND (Exposed Pad): ADC Power Ground. The exposed
pad on the bottom of the package must be soldered to differential 100Ω termination resistors at the LVDS receiver.
ground. D13+/D13– is the MSB.
OGND (Pins 31 and 50): Output Driver Ground.

For LVDS Mode. Standard or Low Power OVDD (Pins 32 and 49): Positive Supply for the Output
Drivers. Bypass to ground with 0.1μF capacitor.
SENSE (Pin 1): Reference Mode Select and External
Reference Input. Tie SENSE to VDD to select the internal CLKOUT–/CLKOUT + (Pins 39 and 40): LVDS Data Valid
2.5V bandgap reference. An external reference of 2.5V or 0utput. Latch data on the rising edge of CLKOUT +, falling
1.25V may be used; both reference values will set a full edge of CLKOUT –.
scale ADC range of 2.25V (PGA = 0). OF–/OF+ (Pins 59 and 60): Overflow/Underflow Digital Out-
GND (Pins 2, 4, 7, 10, 11, 14, 18): ADC Power Ground. put OF is high when an over or under flow has occurred.

VCM (Pin 3): 1.25V Output. Optimum voltage for input com- LVDS (Pin 61): Data Output Mode Select Pin. Connecting
mon mode. Must be bypassed to ground with a minimum LVDS to 0V selects full rate CMOS mode. Connecting LVDS
of 2.2μF. Ceramic chip capacitors are recommended. to 1/3VDD selects demultiplexed CMOS mode. Connecting
LVDS to 2/3VDD selects Low Power LVDS mode. Connect-
VDD (Pins 5, 6, 15, 16, 17): 3.3V Analog Supply Pin. ing LVDS to VDD selects Standard LVDS mode.
Bypass to GND with 0.1μF ceramic chip capacitors.
MODE (Pin 62): Output Format and Clock Duty Cycle
AIN + (Pin 8): Positive Differential Analog Input. Stabilizer Selection Pin. Connecting MODE to 0V selects
AIN – (Pin 9): Negative Differential Analog Input. offset binary output format and disables the clock duty
cycle stabilizer. Connecting MODE to 1/3VDD selects offset
ENC + (Pin 12): Positive Differential Encode Input. The binary output format and enables the clock duty cycle sta-
sampled analog input is held on the rising edge of ENC+. bilizer. Connecting MODE to 2/3VDD selects 2’s complement
Internally biased to 1.6V through a 6.2kΩ resistor. Output output format and enables the clock duty cycle stabilizer.
data can be latched on the rising edge of ENC+. Connecting MODE to VDD selects 2’s complement output
ENC – (Pin 13): Negative Differential Encode Input. The format and disables the clock duty cycle stabilizer.
sampled analog input is held on the falling edge of ENC –. RAND (Pin 63): Digital Output Randomization Selection Pin.
Internally biased to 1.6V through a 6.2kΩ resistor. By- RAND low results in normal operation. RAND high selects
pass to ground with a 0.1μF capacitor for a single-ended D1-D13 to be EXCLUSIVE-ORed with D0 (the LSB). The
Encode signal. output can be decoded by again applying an XOR operation
SHDN (Pin 19): Power Shutdown Pin. SHDN = low results between the LSB and all other bits. The mode of operation
in normal operation. SHDN = high results in powered reduces the effects of digital output interference.
down analog circuitry and the digital outputs are set in PGA (Pin 64): Programmable Gain Amplifier Control Pin. Low
high impedance state. selects a front-end gain of 1, input range of 2.25VP-P. High
DITH (Pin 20): Internal Dither Enable Pin. DITH = low selects a front-end gain of 1.5, input range of 1.5VP-P.
disables internal dither. DITH = high enables internal dither. GND (Exposed Pad Pin 65): ADC Power Ground. The
Refer to Internal Dither section of the data sheet for details exposed pad on the bottom of the package must be sol-
on dither operation. dered to ground.
220814fb

15
LTC2208-14
BLOCK DIAGRAM
AIN+
VDD
INPUT FIRST PIPELINED SECOND PIPELINED THIRD PIPELINED FOURTH PIPELINED FIFTH PIPELINED
S/H ADC STAGE ADC STAGE ADC STAGE ADC STAGE ADC STAGE
AIN–
GND

DITHER
SIGNAL
GENERATOR
CORRECTION LOGIC
AND
SHIFT REGISTER

RANGE ADC CLOCKS

SELECT OVDD
CLKOUT+
CLKOUT–
SENSE OF+
DIFFERENTIAL
ADC OF–
INPUT
PGA
REFERENCE CONTROL OUTPUT D13+
LOW JITTER LOGIC DRIVERS • D13–
CLOCK
VCM DRIVER •
BUFFER •
D0+
D0–
VOLTAGE
REFERENCE

OGND 220814 F01

ENC+ ENC– SHDN PGA RAND M0DE LVDS DITH

Figure 1. Functional Block Diagram

220814fb

16
 LTC2208-14
OPERATION
DYNAMIC PERFORMANCE If two pure sine waves of frequencies fa and fb are applied
to the ADC input, nonlinearities in the ADC transfer function
Signal-to-Noise Plus Distortion Ratio can create distortion products at the sum and difference
The signal-to-noise plus distortion ratio [S/(N+D)] is the frequencies of mfa ± nfb, where m and n = 0, 1, 2, 3, etc.
ratio between the RMS amplitude of the fundamental input For example, the 3rd order IMD terms include (2fa + fb),
frequency and the RMS amplitude of all other frequency (fa + 2fb), (2fa - fb) and (fa - 2fb). The 3rd order IMD is
components at the ADC output. The output is band lim- defined as the ratio of the RMS value of either input tone
ited to frequencies above DC to below half the sampling to the RMS value of the largest 3rd order IMD product.
frequency.
Spurious Free Dynamic Range (SFDR)
Signal-to-Noise Ratio The ratio of the RMS input signal amplitude to the RMS
The signal-to-noise (SNR) is the ratio between the RMS value of the peak spurious spectral component expressed
amplitude of the fundamental input frequency and the RMS in dBc. SFDR may also be calculated relative to full scale
amplitude of all other frequency components, except the and expressed in dBFS.
first five harmonics.
Full Power Bandwidth
Total Harmonic Distortion The Full Power bandwidth is that input frequency at which
Total harmonic distortion is the ratio of the RMS sum the amplitude of the reconstructed fundamental is reduced
of all harmonics of the input signal to the fundamental by 3dB for a full scale input signal.
itself. The out-of-band harmonics alias into the frequency
band between DC and half the sampling frequency. THD Aperture Delay Time
is expressed as: The time from when a rising ENC + equals the ENC– voltage
THD = –20Log (√(V22 + V32 + V42 + ... VN2)/V1) to the instant that the input signal is held by the sample-
and-hold circuit.
where V1 is the RMS amplitude of the fundamental fre-
quency and V2 through VN are the amplitudes of the second Aperture Delay Jitter
through nth harmonics.
The variation in the aperture delay time from convertion
Intermodulation Distortion to conversion. This random variation will result in noise
when sampling an AC input. The signal to noise ratio due
If the ADC input signal consists of more than one spectral to the jitter alone will be:
component, the ADC transfer function nonlinearity can
produce intermodulation distortion (IMD) in addition to SNRJITTER = –20log (2π • fIN • tJITTER)
THD. IMD is the change in one sinusoidal input caused
by the presence of another sinusoidal input at a different
frequency.

220814fb

17
LTC2208-14
APPLICATIONS INFORMATION
CONVERTER OPERATION SAMPLE/HOLD OPERATION AND INPUT DRIVE
The LTC2208-14 is a CMOS pipelined multistep converter
with a front-end PGA. As shown in Figure 1, the converter Sample/Hold Operation
has five pipelined ADC stages; a sampled analog input Figure 2 shows an equivalent circuit for the LTC2208-14
will result in a digitized value seven cycles later (see the CMOS differential sample and hold. The differential ana-
Timing Diagram). The analog input is differential for im- log inputs are sampled directly onto sampling capacitors
proved common mode noise immunity and to maximize (CSAMPLE) through NMOS transitors. The capacitors shown
the input range. Additionally, the differential input drive attached to each input (CPARASITIC) are the summation of
will reduce even order harmonics of the sample and hold all other capacitance associated with each input.
circuit. The encode input is also differential for improved
common mode noise immunity. During the sample phase when ENC is low, the NMOS
transistors connect the analog inputs to the sampling
The LTC2208-14 has two phases of operation, determined capacitors and they charge to, and track the differential
by the state of the differential ENC+/ENC – input pins. For input voltage. When ENC transitions from low to high, the
brevity, the text will refer to ENC+ greater than ENC – as sampled input voltage is held on the sampling capacitors.
ENC high and ENC+ less than ENC – as ENC low. During the hold phase when ENC is high, the sampling
Each pipelined stage shown in Figure 1 contains an ADC, capacitors are disconnected from the input and the held
a reconstruction DAC and an interstage amplifier. In voltage is passed to the ADC core for processing. As ENC
operation, the ADC quantizes the input to the stage and transitions from high to low, the inputs are reconnected to
the quantized value is subtracted from the input by the the sampling capacitors to acquire a new sample. Since
DAC to produce a residue. The residue is amplified and the sampling capacitors still hold the previous sample,
output by the residue amplifier. Successive stages oper- a charging glitch proportional to the change in voltage
ate out of phase so that when odd stages are outputting between samples will be seen at this time. If the change
their residue, the even stages are acquiring that residue between the last sample and the new sample is small,
and vice versa. the charging glitch seen at the input will be small. If the
When ENC is low, the analog input is sampled differentially
LTC2208-14
directly onto the input sample-and-hold capacitors, inside VDD
the “input S/H” shown in the block diagram. At the instant RPARASITIC RON
CSAMPLE
4.9pF
that ENC transitions from low to high, the voltage on the 3Ω 20Ω
AIN+
sample capacitors is held. While ENC is high, the held CPARASITIC
1.8pF
input voltage is buffered by the S/H amplifier which drives VDD
CSAMPLE
the first pipelined ADC stage. The first stage acquires RPARASITIC RON 4.9pF
3Ω 20Ω
the output of the S/H amplifier during the high phase of AIN–
ENC. When ENC goes back low, the first stage produces CPARASITIC
1.8pF
its residue which is acquired by the second stage. At VDD
the same time, the input S/H goes back to acquiring the
analog input. When ENC goes high, the second stage
produces its residue which is acquired by the third stage. 1.6V
An identical process is repeated for the third and fourth 6k
stages, resulting in a fourth stage residue that is sent to ENC+
the fifth stage for final evaluation.
ENC–
Each ADC stage following the first has additional range to 6k
accommodate flash and amplifier offset errors. Results
1.6V
from all of the ADC stages are digitally delayed such that
220814 F02
the results can be properly combined in the correction
logic before being sent to the output buffer. Figure 2. Equivalent Input Circuit
220814fb

18
 LTC2208-14
APPLICATIONS INFORMATION
input change is large, such as the change seen with input provide isolation from ADC S/H switching. The LTC2208-14
frequencies near Nyquist, then a larger charging glitch has a very broadband S/H circuit, DC to 700MHz; it can
will be seen. be used in a wide range of applications; therefore, it is not
possible to provide a single recommended RC filter.
Common Mode Bias
Figures 3, 4a and 4b show three examples of input RC
The ADC sample-and-hold circuit requires differential filtering at three ranges of input frequencies. In general
drive to achieve specified performance. Each input should it is desirable to make the capacitors as large as can be
swing ±0.5625V for the 2.25V range (PGA = 0) or ±0.375V
tolerated—this will help suppress random noise as well
for the 1.5V range (PGA = 1), around a common mode
as noise coupled from the digital circuitry. The LTC2208-
voltage of 1.25V. The VCM output pin (Pin 3) is designed
14 does not require any input filter to achieve data sheet
to provide the common mode bias level. VCM can be tied
directly to the center tap of a transformer to set the DC specifications; however, no filtering will put more stringent
input level or as a reference level to an op amp differential noise requirements on the input drive circuitry.
driver circuit. The VCM pin must be bypassed to ground
Transformer Coupled Circuits
close to the ADC with 2.2μF or greater.
Figure 3 shows the LTC2208-14 being driven by an RF
Input Drive Impedance transformer with a center-tapped secondary. The secondary
As with all high performance, high speed ADCs the dy- center tap is DC biased with VCM, setting the ADC input
namic performance of the LTC2208-14 can be influenced signal at its optimum DC level. Figure 3 shows a 1:1 turns
by the input drive circuitry, particularly the second and ratio transformer. Other turns ratios can be used; however,
third harmonics. Source impedance and input reactance as the turns ratio increases so does the impedance seen by
can influence SFDR. At the falling edge of ENC the the ADC. Source impedance greater than 50Ω can reduce
sample and hold circuit will connect the 4.9pF sampling the input bandwidth and increase high frequency distor-
capacitor to the input pin and start the sampling period. tion. A disadvantage of using a transformer is the loss of
The sampling period ends when ENC rises, holding the low frequency response. Most small RF transformers have
sampled input on the sampling capacitor. Ideally, the poor performance at frequencies below 1MHz.
input circuitry should be fast enough to fully charge Center-tapped transformers provide a convenient means
the sampling capacitor during the sampling period of DC biasing the secondary; however, they often show
1/(2F encode); however, this is not always possible and the poor balance at high input frequencies, resulting in large
incomplete settling may degrade the SFDR. The sampling 2nd order harmonics.
glitch has been designed to be as linear as possible to
VCM
minimize the effects of incomplete settling.
2.2μF
For the best performance it is recommended to have a 5Ω
10Ω 5Ω AIN+
source impedance of 100Ω or less for each input. The
T1
source impedance should be matched for the differential 8.2pF LTC2208-14
35Ω
inputs. Poor matching will result in higher even order
8.2pF
harmonics, especially the second. 0.1μF
35Ω
10Ω 5Ω AIN–

INPUT DRIVE CIRCUITS T1 = MA/COM ETC1-1T 8.2pF

220814 F03
RESISTORS, CAPACITORS
ARE 0402 PACKAGE SIZE
Input Filtering EXCEPT 2.2μF

A first order RC low pass filter at the input of the ADC can Figure 3. Single-Ended to Differential Conversion
serve two functions: limit the noise from input circuitry and Using a Transformer. Recommended for Input
Frequencies from 5MHz to 100MHz
220814fb

19
LTC2208-14
APPLICATIONS INFORMATION
Figure 4a shows transformer coupling using a transmis- Reference Operation
sion line balun transformer. This type of transformer has Figure 6 shows the LTC2208-14 reference circuitry con-
much better high frequency response and balance than sisting of a 2.5V bandgap reference, a programmable gain
flux coupled center tap transformers. Coupling capaci- amplifier and control circuit. The LTC2208-14 has three
tors are added at the ground and input primary terminals modes of reference operation: Internal Reference, 1.25V
to allow the secondary terminals to be biased at 1.25V. external reference or 2.5V external reference. To use the
Figure 4b shows the same circuit with components suit- internal reference, tie the SENSE pin to VDD. To use an
able for higher input frequencies. external reference, simply apply either a 1.25V or 2.5V
VCM
reference voltage to the SENSE input pin. Both 1.25V
and 2.5V applied to SENSE will result in a full scale range
2.2μF
0.1μF
of 2.25VP-P (PGA = 0). A 1.25V output, VCM is provided
10Ω 5Ω AIN+
ANALOG
LTC2208-14
for a common mode bias for input drive circuitry. An
INPUT
25Ω 0.1μF 4.7pF external bypass capacitor is required for the VCM output.
T1 This provides a high frequency low impedance path to
1:1 4.7pF
0.1μF 25Ω 10Ω 5Ω AIN– ground for internal and external circuitry. This is also the
compensation capacitor for the reference; it will not be
4.7pF
T1 = MA/COM ETC1-1-13
RESISTORS, CAPACITORS
220814 F04a
stable without this capacitor. The minimum value required
ARE 0402 PACKAGE SIZE for stability is 2.2μF.
EXCEPT 2.2μF
Figure 4a. Using a Transmission Line Balun Transformer. VCM
Recommended for Input Frequencies from 100MHz to 250MHz
HIGH SPEED 2.2μF
DIFFERENTIAL
VCM AMPLIFIER 25Ω AIN+
LTC2208-14
ANALOG +
2.2μF 12pF
INPUT +
0.1μF CM
5Ω AIN+
ANALOG
LTC2208-14 – –
INPUT 25Ω AIN–
25Ω 0.1μF 2.2pF
T1 AMPLIFIER = LTC6600-20, 12pF
220814 F05
1:1 LT1993, ETC.
0.1μF 25Ω
5Ω AIN–

2.2pF
Figure 5. DC Coupled Input with Differential Amplifier
T1 = MA/COM ETC1-1-13 220814 F04b
RESISTORS, CAPACITORS
ARE 0402 PACKAGE SIZE
EXCEPT 2.2μF RANGE
SELECT
Figure 4b. Using a Transmission Line Balun Transformer. AND GAIN
Recommended for Input Frequencies from 250MHz to 500MHz TIE TO VDD TO USE INTERNAL
CONTROL
INTERNAL 2.5V ADC
REFERENCE REFERENCE
OR INPUT FOR SENSE
Direct Coupled Circuits EXTERNAL 2.5V
REFERENCE PGA
Figure 5 demonstrates the use of a differential amplifier to OR INPUT FOR
EXTERNAL 1.25V
convert a single ended input signal into a differential input REFERENCE
2.5V
signal. The advantage of this method is that it provides BANDGAP
REFERENCE
low frequency input response; however, the limited gain
VCM
bandwidth of any op amp or closed-loop amplifier will de- BUFFER 1.25V
2.2μF
grade the ADC SFDR at high input frequencies. Additionally,
wideband op amps or differential amplifiers tend to have
high noise. As a result, the SNR will be degraded unless 220814 F06

the noise bandwidth is limited prior to the ADC input. Figure 6. Reference Circuit
220814fb

20
 LTC2208-14
APPLICATIONS INFORMATION
The internal programmable gain amplifier provides the In applications where jitter is critical (high input frequen-
internal reference voltage for the ADC. This amplifier has cies), take the following into consideration:
very stringent settling requirements and is not accessible 1. Differential drive should be used.
for external use.
2. Use as large an amplitude possible. If using trans-
The SENSE pin can be driven ±5% around the nominal 2.5V former coupling, use a higher turns ratio to increase the
or 1.25V external reference inputs. This adjustment range amplitude.
can be used to trim the ADC gain error or other system
gain errors. When selecting the internal reference, the 3. If the ADC is clocked with a fixed frequency sinusoidal
SENSE pin should be tied to VDD as close to the converter signal, filter the encode signal to reduce wideband
as possible. If the sense pin is driven externally it should noise.
be bypassed to ground as close to the device as possible 4. Balance the capacitance and series resistance at both
with 1μF ceramic capacitor. encode inputs such that any coupled noise will appear
VCM at both inputs as common mode noise.
1.25V
2.2μF The encode inputs have a common mode range of 1.2V
LTC2208-14 to 3V. Each input may be driven from ground to VDD for
2 6 SENSE
3.3V LT1461-2.5 single-ended drive.
1μF 4 2.2μF

LTC2208-14 VDD
220814 F07

TO INTERNAL
Figure 7. A 2.25V Range ADC with an External 2.5V Reference ADC CLOCK
DRIVERS
PGA Pin VDD 1.6V

6k
The PGA pin selects between two gain settings for the ADC
+
front-end. PGA = 0 selects an input range of 2.25VP-P; ENC

PGA = 1 selects an input range of 1.5VP-P. The 2.25V input VDD 1.6V
range has the best SNR; however, the distortion will be 6k
higher for input frequencies above 100MHz. For applica- ENC–
tions with high input frequencies, the low input range
will have improved distortion; however, the SNR will be
approximately 1.8dB worse. See the Typical Performance 220814 F08a

Characteristics section. Figure 8a. Equivalent Encode Input Circuit

Driving the Encode Inputs
The noise performance of the LTC2208-14 can depend on 0.1μF
T1 ENC+
the encode signal quality as much as on the analog input.
The encode inputs are intended to be driven differentially, 50Ω
primarily for noise immunity from common mode noise 100Ω
LTC2208-14
sources. Each input is biased through a 6k resistor to a 0.1μF 50Ω
8.2pF

1.6V bias. The bias resistors set the DC operating point

for transformer coupled drive circuits and can set the logic 0.1μF ENC–
threshold for single-ended drive circuits. T1 = MA/COM ETC1-1-13 220814 F08b
RESISTORS AND CAPACITORS
Any noise present on the encode signal will result in ad- ARE 0402 PACKAGE SIZE
ditional aperture jitter that will be RMS summed with the
Figure 8b. Transformer Driven Encode
inherent ADC aperture jitter.
220814fb

21
LTC2208-14
APPLICATIONS INFORMATION
ENC+
The lower limit of the LTC2208-14 sample rate is determined
VTHRESHOLD = 1.6V
by droop of the sample and hold circuits. The pipelined
1.6V ENC– LTC2208-14 architecture of this ADC relies on storing analog signals on
0.1μF small valued capacitors. Junction leakage will discharge
the capacitors. The specified minimum operating frequency
220814 F09
for the LTC2208-14 is 1Msps.
Figure 9. Single-Ended ENC Drive,
Not Recommended for Low Jitter
DIGITAL OUTPUTS

3.3V Digital Output Modes

MC100LVELT22
3.3V
130Ω 130Ω
The LTC2208-14 can operate in four digital output modes:
Q0 ENC+ standard LVDS, low power LVDS, full rate CMOS, and
D0 demultiplexed CMOS. The LVDS pin selects the mode of
ENC–
LTC2208-14 operation. This pin has a four level logic input, centered at
Q0 0, 1/3VDD, 2/3VDD and VDD. An external resistor divider can
83Ω 83Ω
220814 F10
be used to set the 1/3VDD and 2/3VDD logic levels. Table 1
shows the logic states for the LVDS pin.

Figure 10. ENC Drive Using a CMOS to PECL Translator Table 1. LVDS Pin Function
LVDS DIGITAL OUTPUT MODE
Maximum and Minimum Encode Rates 0V(GND) Full-Rate CMOS
The maximum encode rate for the LTC2208-14 is 130Msps. 1/3VDD Demultiplexed CMOS
For the ADC to operate properly the encode signal should 2/3VDD Low Power LVDS
have a 50% (±5%) duty cycle. Each half cycle must have at VDD LVDS
least 3.65ns for the ADC internal circuitry to have enough
settling time for proper operation. Achieving a precise 50% Digital Output Buffers (CMOS Modes)
duty cycle is easy with differential sinusoidal drive using
Figure 11 shows an equivalent circuit for a single output
a transformer or using symmetric differential logic such
buffer in CMOS Mode, Full-Rate or Demultiplexed. Each
as PECL or LVDS. When using a single-ended ENCODE
buffer is powered by OVDD and OGND, isolated from the
signal asymmetric rise and fall times can result in duty
ADC power and ground. The additional N-channel transistor
cycles that are far from 50%.
in the output driver allows operation down to low voltages.
An optional clock duty cycle stabilizer can be used if the The internal resistor in series with the output makes the
input clock does not have a 50% duty cycle. This circuit output appear as 50Ω to external circuitry and eliminates
uses the rising edge of ENC pin to sample the analog input. the need for external damping resistors.
The falling edge of ENC is ignored and an internal falling
As with all high speed/high resolution converters, the
edge is generated by a phase-locked loop. The input clock
digital output loading can affect the performance. The
duty cycle can vary from 30% to 70% and the clock duty
digital outputs of the LTC2208-14 should drive a minimum
cycle stabilizer will maintain a constant 50% internal duty
capacitive load to avoid possible interaction between the
cycle. If the clock is turned off for a long period of time,
digital outputs and sensitive input circuitry. The output
the duty cycle stabilizer circuit will require one hundred
should be buffered with a device such as a ALVCH16373
clock cycles for the PLL to lock onto the input clock. To
CMOS latch. For full speed operation the capacitive load
use the clock duty cycle stabilizer, the MODE pin must be
should be kept under 10pF. A resistor in series with the
connected to 1/3VDD or 2/3VDD using external resistors.
220814fb

22
 LTC2208-14
APPLICATIONS INFORMATION
output may be used but is not required since the ADC has resistor, even if the signal is not used (such as OF+/OF– or
a series resistor of 43Ω on-chip. CLKOUT+/CLKOUT–). To minimize noise the PC board
traces for each LVDS output pair should be routed close
Lower OVDD voltages will also help reduce interference
from the digital outputs. together. To minimize clock skew, all LVDS PC board traces
should have about the same length.
LTC2208-14
OVDD In Low Power LVDS Mode 1.75mA is steered between
0.5V
VDD VDD TO 3.6V the differential outputs, resulting in ±175mV at the LVDS
0.1μF receiver’s 100Ω termination resistor. The output com-
OVDD
mon mode voltage is 1.20V, the same as standard LVDS
Mode.
DATA PREDRIVER 43Ω TYPICAL
FROM LOGIC DATA
LATCH
OUTPUT Data Format

OGND
The LTC2208-14 parallel digital output can be selected
for offset binary or 2’s complement format. The format
220814 F11
is selected with the MODE pin. This pin has a four level
logic input, centered at 0, 1/3VDD, 2/3VDD and VDD. An
Figure 11. Equivalent Circuit for a Digital Output Buffer
external resistor divider can be used to set the 1/3VDD
and 2/3VDD logic levels. Table 2 shows the logic states
Digital Output Buffers (LVDS Modes) for the MODE pin.
Figure 12 shows an equivalent circuit for an LVDS output Table 2. MODE Pin Function
pair. A 3.5mA current is steered from OUT+ to OUT– or MODE OUTPUT FORMAT CLOCK DUTY CYCLE STABILIZER
vice versa, which creates a ±350mV differential voltage 0(GND) Offset Binary Off
across the 100Ω termination resistor at the LVDS receiver. 1/3VDD Offset Binary On
A feedback loop regulates the common mode output volt- 2/3VDD 2’s Complement On
age to 1.20V. For proper operation each LVDS output pair VDD 2’s Complement Off
must be terminated with an external 100Ω termination

LTC2208-14 OVDD
3.3V
3.5mA 0.1μF

VDD
VDD
OVDD

43Ω
DATA PREDRIVER 10k 10k
FROM LOGIC
LATCH OVDD LVDS
100Ω RECEIVER

43Ω

+
1.20V – OGND

220814 F12

Figure 12. Equivalent Output Buffer in LVDS Mode

220814fb

23
LTC2208-14
APPLICATIONS INFORMATION
Overflow Bit LSB and all other bits. The LSB, OF and CLKOUT outputs
are not affected. The output Randomizer function is active
An overflow output bit (OF) indicates when the converter is
when the RAND pin is high.
overranged or underranged. In CMOS mode, a logic high
on the OFA pin indicates an overflow or underflow on the
A data bus, while a logic high on the OFB pin indicates
an overflow on the B data bus. In LVDS mode, a differen- CLKOUT CLKOUT

tial logic high on OF+/OF– pins indicates an overflow or

underflow.
OF OF

Output Clock
D13
The ADC has a delayed version of the encode input avail- D13/D0

able as a digital output, CLKOUT. The CLKOUT pin can

be used to synchronize the converter data to the digital D12
D12/D0
system. This is necessary when using a sinusoidal en- •
code. In both CMOS modes, A bus data will be updated •
as CLKOUTA falls and CLKOUTB rises. In demultiplexed •
D2
CMOS mode the B bus data will be updated as CLKOUTA D2/D0

falls and CLKOUTB rises.

D1
In Full Rate CMOS Mode, only the A data bus is active; D1/D0

data may be latched on the rising edge of CLKOUTA or

RAND = HIGH,
the falling edge of CLKOUTB. RANDOMIZER
RAND
ENABLED
In demultiplexed CMOS mode CLKOUTA and CLKOUTB
will toggle at 1/2 the frequency of the encode signal. Both D0 D0

the A bus and the B bus may be latched on the rising edge 220814 F13

of CLKOUTA or the falling edge of CLKOUTB.

Figure 13. Functional Equivalent of Digital Output Randomizer
Digital Output Randomizer
Interference from the ADC digital outputs is sometimes Output Driver Power
unavoidable. Interference from the digital outputs may be Separate output power and ground pins allow the output
from capacitive or inductive coupling or coupling through drivers to be isolated from the analog circuitry. The power
the ground plane. Even a tiny coupling factor can result in supply for the digital output buffers, OVDD, should be tied
discernible unwanted tones in the ADC output spectrum. to the same power supply as for the logic being driven.
By randomizing the digital output before it is transmitted For example, if the converter is driving a DSP powered
off chip, these unwanted tones can be randomized, trading by a 1.8V supply, then OVDD should be tied to that same
a slight increase in the noise floor for a large reduction in 1.8V supply. In CMOS mode OVDD can be powered with
unwanted tone amplitude. any logic voltage up to the 3.6V. OGND can be powered
The digital output is “Randomized” by applying an exclu- with any voltage from ground up to 1V and must be less
sive-OR logic operation between the LSB and all other data than OVDD. The logic outputs will swing between OGND
output bits. To decode, the reverse operation is applied; and OVDD. In LVDS Mode, OVDD should be connected to
that is, an exclusive-OR operation is applied between the a 3.3V supply and OGND should be connected to GND.

220814fb

24
 LTC2208-14
APPLICATIONS INFORMATION
PC BOARD Internal Dither
FPGA
CLKOUT
The LTC2208-14 is a 14-bit ADC with a very linear transfer
function; however, at low input levels even slight imperfec-
tions in the transfer function will result in unwanted tones.
OF Small errors in the transfer function are usually a result
of ADC element mismatches. An optional internal dither
D13/D0 mode can be enabled to randomize the input location on
D13 the ADC transfer curve, resulting in improved SFDR for
low signal levels.
D12/D0
D12 As shown in Figure 15, the output of the sample-and-hold
• amplifier is summed with the output of a dither DAC. The
LTC2208-14
• dither DAC is driven by a long sequence pseudo-random
D2/D0 • number generator; the random number fed to the dither
D2
DAC is also subtracted from the ADC result. If the dither
D1/D0
DAC is precisely calibrated to the ADC, very little of the
D1 dither signal will be seen at the output. The dither signal
that does leak through will appear as white noise. The dither
DAC is calibrated to result in less than 0.5dB elevation in
D0
D0 the noise floor of the ADC, as compared to the noise floor
with dither off.

220814 F14

Figure 14. Derandomizing a Randomized Digital Output

LTC2208-14
CLKOUT
OF
AIN+ D13
14-BIT •
ANALOG S/H DIGITAL OUTPUT
PIPELINED •
INPUT AMP SUMMATION DRIVERS
ADC CORE
AIN– •
D0

CLOCK/DUTY MULTIBIT DEEP

CYCLE PRECISION PSEUDO-RANDOM
CONTROL DAC NUMBER
GENERATOR

220814 F15

+ –
ENC ENC DITH
DITHER ENABLE
HIGH = DITHER ON
LOW = DITHER OFF

Figure 15. Functional Equivalent Block Diagram of Internal Dither Circuit

220814fb

25
LTC2208-14
APPLICATIONS INFORMATION
Grounding and Bypassing connecting the pins and bypass capacitors must be kept
short and should be made as wide as possible.
The LTC2208-14 requires a printed circuit board with a
clean unbroken ground plane; a multilayer board with an The LTC2208-14 differential inputs should run parallel and
internal ground plane is recommended. The pinout of the close to each other. The input traces should be as short as
LTC2208-14 has been optimized for a flowthrough layout possible to minimize capacitance and to minimize noise
so that the interaction between inputs and digital outputs pickup.
is minimized. Layout for the printed circuit board should
ensure that digital and analog signal lines are separated Heat Transfer
as much as possible. In particular, care should be taken Most of the heat generated by the LTC2208-14 is trans-
not to run any digital track alongside an analog signal ferred from the die through the bottom-side exposed pad.
track or underneath the ADC. For good electrical and thermal performance, the exposed
High quality ceramic bypass capacitors should be used pad must be soldered to a large grounded pad on the PC
at the VDD, VCM, and OVDD pins. Bypass capacitors must board. It is critical that the exposed pad and all ground
be located as close to the pins as possible. The traces pins are connected to a ground plane of sufficient area
with as many vias as possible.

220814fb

26
 LTC2208-14
PACKAGE DESCRIPTION
UP Package
64-Lead Plastic QFN (9mm × 9mm)
(Reference LTC DWG # 05-08-1705 Rev C)

0.70 p 0.05

7.15 p 0.05
7.50 REF
8.10 p 0.05 9.50 p 0.05
(4 SIDES)

7.15 p 0.05

PACKAGE OUTLINE

0.25 p 0.05
0.50 BSC

RECOMMENDED SOLDER PAD PITCH AND DIMENSIONS

APPLY SOLDER MASK TO AREAS THAT ARE NOT SOLDERED

9 .00 p 0.10 0.75 p 0.05 R = 0.115

(4 SIDES) R = 0.10 TYP
TYP 63 64

0.40 p 0.10
PIN 1 TOP MARK
(SEE NOTE 5) 1
2

PIN 1
CHAMFER
C = 0.35

7.15 p 0.10
7.50 REF
(4-SIDES)

7.15 p 0.10

(UP64) QFN 0406 REV C

0.200 REF 0.25 p 0.05
0.00 – 0.05 0.50 BSC
NOTE:
1. DRAWING CONFORMS TO JEDEC PACKAGE OUTLINE MO-220 VARIATION WNJR-5 BOTTOM VIEW—EXPOSED PAD
2. ALL DIMENSIONS ARE IN MILLIMETERS
3. DIMENSIONS OF EXPOSED PAD ON BOTTOM OF PACKAGE DO NOT INCLUDE
MOLD FLASH. MOLD FLASH, IF PRESENT, SHALL NOT EXCEED 0.20mm ON ANY SIDE, IF PRESENT
4. EXPOSED PAD SHALL BE SOLDER PLATED
5. SHADED AREA IS ONLY A REFERENCE FOR PIN 1 LOCATION ON THE TOP AND BOTTOM OF PACKAGE
6. DRAWING NOT TO SCALE

220814fb

27
Information furnished by Linear Technology Corporation is believed to be accurate and reliable.
However, no responsibility is assumed for its use. Linear Technology Corporation makes no representa-
tion that the interconnection of its circuits as described herein will not infringe on existing patent rights.
LTC2208-14
RELATED PARTS
PART NUMBER DESCRIPTION COMMENTS
LTC1747 12-Bit, 80MSPS ADC 72dB SNR, 87dB SFDR, 48-Pin TSSOP Package
LTC1748 14-Bit, 80Msps ADC 76.3dB SNR, 90dB SFDR, 48-Pin TSSOP Package
LTC1749 12-Bit, 80Msps Wideband ADC Up to 500MHz IF Undersampling, 87dB SFDR
LTC1750 14-Bit, 80Msps Wideband ADC Up to 500MHz IF Undersampling, 90dB SFDR
LT1993-2 High Speed Differential Op Amp 800MHz BW, 70dBc Distortion at 70MHz, 6dB Gain
LTC2202 16-Bit, 10MSPS ADC 140mW, 81.6dB SNR, 100dB SFDR
LTC2203 16-Bit, 25MSPS ADC 220mW, 81.6dB SNR, 100dB SFDR
LTC2204 16-Bit, 40Msps ADC 480mW, 79.1dB SNR, 100dB SFDR
LTC2205 16-Bit, 65Msps ADC 610mW, 79dB SNR, 100dB SFDR
LTC2206 16-Bit, 80Msps ADC 725mW, 77.9dB SNR, 100dB SFDR
LTC2207 16-Bit, 105Msps ADC 900mW, 77.9dB SNR, 100dB SFDR
LTC2208 16-Bit, 130Msps ADC 1250mW, 77.7dB SNR, 100dB SFDR
LTC2220 12-Bit, 170Msps ADC 890mW, 67.5dB SNR, 9mm × 9mm QFN Package
LTC2220-1 12-Bit, 185Msps ADC 910mW, 67.5dB SNR, 9mm × 9mm QFN Package
LTC2249 14-Bit, 65Msps ADC 230mW, 73dB SNR, 5mm × 5mm QFN Package
LTC2250 10-Bit, 105Msps ADC 320mW, 61.6dB SNR, 5mm × 5mm QFN Package
LTC2251 10-Bit, 125Msps ADC 395mW, 61.6dB SNR, 5mm × 5mm QFN Package
LTC2252 12-Bit, 105Msps ADC 320mW, 70.2dB SNR, 5mm × 5mm QFN Package
LTC2253 12-Bit, 125Msps ADC 395mW, 70.2dB SNR, 5mm × 5mm QFN Package
LTC2254 14-Bit, 105Msps ADC 320mW, 72.5dB SNR, 5mm × 5mm QFN Package
LTC2255 14-Bit, 125Msps ADC 395mW, 72.4dB SNR, 5mm × 5mm QFN Package
LTC2299 Dual 14-Bit, 80Msps ADC 445mW, 73dB SNR, 9mm × 9mm QFN Package
LT5512 DC-3GHz High Signal Level Downconverting Mixer DC to 3GHz, 21dBm IIP3, Integrated LO Buffer
LT5514 Ultralow Distortion IF Amplifier/ADC Driver with 450MHz 1dB BW, 47dB OIP3, Digital Gain Control 10.5dB to 33dB in 1.5dB/Step
Digitally Controlled Gain
LT5522 600MHz to 2.7GHz High Linearity 4.5V to 5.25V Supply, 25dBm IIP3 at 900MHz, NF = 12.5dB,
Downconverting Mixer 50Ω Single-Ended RF and LO Ports

220814fb

28 Linear Technology Corporation

LT 0909 REV B • PRINTED IN USA

1630 McCarthy Blvd., Milpitas, CA 95035-7417

(408) 432-1900 ● FAX: (408) 434-0507 ● www.linear.com © LINEAR TECHNOLOGY CORPORATION 2006