UNIT

Low VOLTA GE LOWE R PowE R

4 MULTI PLIER S

Syllabus
LOW-VOLT AGE LOW-POWER MULTIPLIERS
Introduction , Overview of Mul~icatio n, Types of Multiplier Architecture s, Braun Multiplier, Baugh-Woo ley
M ultiplier, Booth lvlultiplier, Introduction to Wallace Tree Multiplier. -

(LEAR NING □ BJECTIVESJ

\ Cr
Concept of multi plication

Different types of multiplier architectures

Cr Operation of Braun 'multiplier and its modified ve~sion

Operation of. Baugh-Woo ley multiplier and its modified version

Concept of Booth's algorithm

Operation of Booth multipliers and its modified version

Cr. Function of Booth encoder

Cr Working of Wallace multiplier

Cr Introduction to wallace tree multiplier

Cr Wallace three construction

( I NTR □ DUCTl □ N
J
like Multiply and
In arithmetic operations, multiplicatio n is a fundamenta l function. Multiplicatio n-based operations
arithmetic f unctions in
Accumulate (MAC) and inner product are among the most commonly utilized computation -intensive
flltering, and other s. In thi s
many Digital Signal Processing (DSP) applications like convolution, Fast Fourier Transform (FFT),
unit, multiplicatio n operation and different types of multiplies are discussed.

~
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50
LOW POWER VLSI DESIGN (JNTU--HYDERA.e

PART-A SHORT QUESTIONS WITH SOLUTIONS

01 · What are tho variables to bo consldotod wh1I d sfgn ng a mu UpUe.r

Ans:
l"hc three ~1gnihcru1t v 11ahJc<1 10 con 1dered whiled
lhtp nron.
2. ( olcu1nt1on ,peed
3. Per d1,qpat10n.
Q2. What are the different type..s of m•tltiplier architectures.
Ans: Mcdlll Paper.•

The different t)pe' of multiplier architecture; are,

I. S.:rial multtphcr
2. Parallel multtplier
3. Serial-parallel multiplier.
Q3. Mention the various muttiplier architectures followed for VLSI design.
Ans:
The different types of multiplier architecture followed in VLSI design are as follows.
I. Serial parallel multiplier
2. Braun multiplier
,3. Baugh-Wooley multiplier
4. Array multiplier
5. Wallace tree multiplier.
Q4. What is serial parallel multiplier?
A ns:
Serial-parallel Multiplier is one of the simplest available multiplier. The operation of this multiplier is explained De m
Let, A = (an, an-1......, ac)
s· = (bn, bn-1......, b 0)
Then the multiplication of A and Bis given by,

Q5.
Ans:
A.B = (A.2n.bn.+ A.2n-l b n-1 + ....... + A.2°.b()I\

What is Braun multiplier? l

Braun Multiplier this type of multiplier, all the partial products are computed in parallel and coJected using a c:isc:11..,
array of carry save adders.
Q6.
Ans:
What is Baugh-Wooley multiplier?
J
llodel Paper-t, o•

Baugh-Wooley Multiplier is used for two's complement multiplication. It is explamed belo\\.

n 2
Let, A (an 1
..... aJ - a,, 1 2" 1 + La,.2 1

0
n 2
b11-I 2" 1 t ~
~hd
0

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,r-4 (Low Voltage Low Power Multiplie rs)
uN · 1· ·
'fhen. the mu1tip 1catton of f and B is gi\ en h,.

AB
• • n-1 b r. 1
=a i-: ti•
0 0
1 b1 2 1 a 'L "',,
0
1
~,,
._
11 h,, '-¾ 2"
I ~ a,
0
nte s1mphfic att0n
In order to aYotd subtracti on. th: ncgatiH· 11.'rms nrc mtcrch 111g(·d hy u!.1ng nppropn
~ a t is Pipeline d multipli er and wallace Tree Multipli er?
Q1• M!>del Papot•2. 01(l)
J\.,s:
pipelined ~lultipli er
r. lhese type ofmultip lters are u~cd
❖ Pipclmcd \,lultiplic r is th e multipltc r using latches. ,vc can obtain a pipelined multiplie
111 case \\ here no-storag e clements
arc present

Let the multiplie r be } . multiplic and he \ ' and the product be P.

partial product (,\ 1 x } ;) 1s r,ormcd as.
k of each
Then. the !<'h bit

pk = L
,=0
Xk-i X };

"allace Tree l\lultipli er

ted from adder cells.
❖
These multiplie rs are named after their inventor. These multiplie rs can be construc
complet ion time grows as the logarith m
❖ The main concept of this multiplie rs revolves around designin g multiplie rs, whose
of the number of bits that are to be multiplie d.
QB. Explain the signific ance of Booth's algorith m.
Model Paper-3, Q1(i)
Ans:
complem ent multipli cation. It produce s
Booth's algorithm is the stronges t and effective algorithm for solving signed 2's
algorithm adopts a techniqu e in which mul-
2 n-bit product and gives equal priority to both positive and negative numbers . This
of operatio ns required for multipli cation.
tiplication is represen ted as differenc e between numbers , thereby reducing the number
In this algorithm, O's in the multiplie r require just shifting and l 's in the multiplie ., m can be
r from bit position n to bit position
treated as 2n + 1 - 2m.
Q9. State radix-2 booth· encodin g table.
Model Paper-2. Q1 (d)
Ans:
Radix-2 booth encoding table is shown below.

Y.I Vi - I
Partial Product
'

0 0 0 x Multipli cand
0 1 1 x Multipli cand

1 0 - 1 x Multipli.c and

l 1 0 x-Multip licand .
-1
Q 0. What are the steps involve d m a Wallace tree?
Ans:

The Wallace tree has the followin g three steps.

I. Partial Product Generati on Stage
2.
Partial Product Reductio n Stage
~ Partial Product Addition Stage
11
Q - What is a 4:2 compre ssor?
-ns: Modal Paper-3, Q1(d)

full adders. It has four input bhs In 1• In2• In and In and two tp t b'
A 4:2 compres sor is a combina tion of two
. J 4 Ou u its sum
and ca
rry (Sand C) along with an input carry bit , C,n and output carry bit c .
""' '
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52 LOW POWER Vt.SI DESIGN rJNTU HYOl:RAe

PART-B ESSAY QUESTION S WITH SOLUTION S

4,1 INTRODUCTION, OVERVIEW OF MULTIPLICATION

Q12. Give an Introduction to multlpllcation In brief. 0

Ans: X 0 0
In 11nthnwtir operations, multtpltcatl(ln ts a titndamcntal 0 0 0 0 Partial prod
5

l
fot\l'lll,n, M11lt1phcatton-hnscd operations like Multiply and
0
\.·cumulate (M \ (') and inner product arc among the most (D
,x,mmlmh utili ·cd computation-intensive arithmetic functions 1 0
(i)
111 man) Digital Signal Processing (DSP) applications like 0 0 0 0
.:onnilution. Fast Fourier Transfonn (FFT), filtering, and others.
(78)10 = 1 0 0 I 0 Products
The) frequent\) generate a large amount of time delay
and consun1e a significant amount of silicon area in the DSP
system. Because multiplication takes up the majority of the
Q14. Give an overview of multiplication.
execution time in most DSP algorithms, a high-speed multiplier
1s essential. Multiplication time is still the most important Ans: Model Paper-2,
component in detennining a DSP chip's instruction cycle time. Multiplication can be viewed as a series of repea:
With the growing demand for more computational power additions that are repeated. The multiplicand is th.e numbe;
on battery-powered mobile devices, the focus has changed from be multiplied, the multiplier is the number of times it is a
optimizing traditional delay times and area sizes to minimizing and the result is the product.
po,\erwaste while maintaining good performance. A low-power Multiplication involves the basic actions of producr
design, in comparison to prior designs, allows portable devices and accumulating or adding partial products. As a result, ti:
tG wort-- for longer periods of time with the same amount of two primary phases must be streamlined to speed up the en -
battery charge. multiplication process.
~- Discuss the concept of multiplication with an 1. Unsigned multiplication
example.
2. Signed multiplication
Ans: Model Paper-1, QS(a) 1. Unsigned Multiplication
Multiplier is an arithmetic operator which perfonns
. Unsigned multiplication can be performed on a pr]
multiplication between two binary numbers and generates the
using AND gates and full adders. c
result. For M x N bit multiplication, N partial products are
formed for each Mbit and then the shifted partial products are This multiplication uwolves the following two steps.
added to generate M x N bit result. The operation of binary ❖ Each digit of multiplier is multiplied by the multiplicar.
multiplication is similar to logical AND operation, So, each for partial result
partial product includes, ANDing of multiplicand and multiplier ❖ The partial results are added to obtain final result
bits.
For instance, consider two n-bit unsigned numbers
Consider B = (bM_1, bM_2, bM_3, .... b1, b0) as multiplicand and B defined by,
and A = (aN 1
, aN_2, aN_ 3,.... al' a ) as multiplier. Then, the
0
n- 1

product of multiplicand and multiplier bits is given,

A = I:A,i
i=O

A= [f
;zO
bj21 ][Ia i]
, =O
1
n- 1
B = I:B;21
JnO
N-1 M-1
B= L L a;b12; +j Where,
•
A - Multiplicand
Binary multiplication is illustrated in the following B - Multiplier
example.
Then, the product P of A and Bis given by,
Multiplicand, 13 10 = 1 1 0 1 n In I

Multiplier, 610 = 0 1 1 0
p = I: I:Alii+j) c,
i • O j= O

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 uNff-4 (Low Voltage Low Power Multipliers)
53
~ h e y can be expanded as.
A Multiplicand A,. 1 A" Ao
4.2 TYPl!S OF MULTIPLII R ARCHITliCTURl!S
2 A"_ ·' ..... A,
Q15. What a r e tho d lfforon t t y pos of mul tlpllor
BMulttplier B,. 1 B,. 2 B" , ..... B,Bo architectu res? Explain t hem.
p Product (A*B) P:z,,_, P:z,,_ 2 p 2,,_ 3 ..... P, po Ans:
T he different types or multiplier architectures urc,
Each of the partial product terms p = A A · II d h
i J IS ca C t C
"
I. Serial multiphc1
summand.
2. Parnllel multiplier
Each partial product is then stored in ,he Arithmetic 3. Scria l-para llcl mullipltcr.
Logic Unit register, where it takes up memory until the fina l 1. Serial Multiplier
partial product is cal~ulated. The final result is obtained by A successive addition algorithm is used by the serial
;1dding all of the partial products. . multiplier.
Signed Multiplication They have a s imple structure because both operands are
2. entered sequentially. As a result, the physical circuit uses
Multiplication of signed numbers is performed in 2's less hardware and takes up less chip area.
complements form., Here, the negative number is in'itially . The serial multiplier, on the other hand, has a slow speed
converted to its 2's complements form to ensure that all partial due to the opetands be ing entered sequentially.
. 2. Parallel Multiplier
products are positive.
To perform high-speed mathematical calculations, most
one positive and one negative numbers advanced digital computers include a parallel multiplier. In
its arithmetic logic unit, a microprocessor needs multipliers,
Consider two n-bit numbers A .and - B .- The negative
and a digital signal processing system needs multipliers to
number B is converted into represented by (2" - B). imp lement techniques like convolution and filtering.
')
The pr~duct on direct multiplication is then giveh by, ln Reduced· Instruction Set Computers (R ISC), Digital
Signal Processing (.g.s_E), and graphics accelerators,
P' = A(- B) = A(2" - B) = 2° A - AB high-speed parallel multip liers with substantially bigger
This product differs from the expected result, areas and more com plexity are widely used.
The examples of p arallel multipliers are,
P =- AB = 2 21'- AB
Array mu ltipliers such as the Braun and Baugh-Wooley
where, 2"(2" - A) is the correction factor to be added. multipliers ,
This is done by shifting the 2's complement of A to the left by Tree multip liers like the Wallace multiplier
n places. The pre-calculated product of P' is then added to this Di!ladvantages ·
correction factor. ❖ The main disadvantage of these multipliers s that they
need a lot of chip space. ·
Two negative numbers
It has .a fast processing speed, but it is costly in terms of
If both the mu ltiplicand and multiplier are neg~tive, their silicon area and power consumption. This is because both
2's complements will be multiplied. operands are 's ent into the multiplier in parallel for parallel
multipliers. As a result, compared to serial multipliers, the
Consider two n-bit negative numbers -A and - B in which hardware takes up a lot more area and is m ore complicated.
-A is to be multiplied with - B. Serial-Parallel M ultiplier
The product P' is given by, A seri~l-parallel multiplier is one of the easiest and
m inutest m ethods to carry out the fundamental multiplication
P' = (2" - A) (2" - B) = 2211 - 22n A - 2"B + AB algorithm. It is a better trade-off b etween the time-consuming
seria l mu ltiplier and the area-consuming parallel multipliers,
It differs from the expect result,
~ which take up a lot of time and space. This type of multiplier
P = AB is used when there is a need for both speed and a small area.
The difference One operand is entered sequentially while the other
operand is stored them in paralle l wi\h a fixed number of bits.
P - P =-22n + 2"A + 2"B A combinational fyll adder and a register are incorporated by
The term 22 " denotes a carry-out b it from the Most the sum units in the multiplier that holds the carry. The shift
and add operations are performed by the chain of summation
Significant Bit (MSB) that can be ignored. Correction factors
units and registers. The partial product wh ich is obtained from
for both multiplier and multiplicand must be included to get the the above operation is held in the sh ift. register chain, wh ile the
correct result. multiplicand is su ccessively added into the partial product.

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54 LOW rowr;R VLSI DESIGN fJNT'U-HYDf;RAe

lii.3 BRAUN MULTIPLIER

Q16. What Is Broun multlpllor? E11plnln its oporatlon.
An&: MOdtl P,1,1, ,

B .-111111 multl1,lir1
Jt ,~ 11 h11srl' J',1111llt·I n1111lipli<'r. lt ,s 11lso kllnwn .,~the< ,,rty 'i ,v \rr ,y M11l11pltcr I hr inul11pl1 r c in only
nmht1'lil·,1ti1,11 h.-t,,l'~ n two 11ns1gnnl velul'~. It ,s mndc up of ,1n lH'r,,y ol J\N D g,11 ~ ,111<I 1dd, rq th 11 nrc pl wed m nn
~1niclm~ "i1l11,111 tlw nn·d of log1r rcgi!>ll'tS. Bcc,111~c it does 1101 add in ndd111on,1l op ·rand to the mult1pl1 at1on tesulr 11
l-lll1W11 t\i- the ll()tl ,1dd11ivc mnltiphrr
\ rrhi(cruu ,.
In Rraun multiplkr, ;1l\ 1hc partial p10d11cts ~re comp111cd 111 parallel find collected 11~mg a cas•..adcd army of c.ar,,
Dddrn-. Ann"· 11-bil Rraun mult1plicr requires 11(11 i) adders and n 1\NIJ gates.
1

The cfficknt arclutcctun' of 4 x 4 Braun mult,phcr with fin itcr;itive layout of adders is .is shown in figure 11,
X3 ~ X1 ~

Po
___.,.___-'----'-..,__-'-__..j....-._,__ --1-_---1----Y,

P,
- -l----4.---4--<---+--+---+--- +--+--+-----t----y2

p1
...--~+-H--+--+--lf-.---t- + -t--..----t---Y3

A B C; A B C; A B Ci
FA7 FA8 FA9
co so co so co so
pl

A B c, A a C.I A B c, X: 4-bit multiplicand

FA10 FAJ, FA 12 Y: 4-bit multiplier
Co So co so co so
P: 8-bit product ofX and Y

p
PIt : XY is a product bit
) I J
j S
P, p6 4

Figure (1): Schematic Diagram of a 4 x 4-Bit Braun Multiplier

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,....,r-4
~
(Low Voltage Low Power Mutt· 1.
1p 1ers) 65
c,ptranon
-1 ,me taken for the Ct.trry-out (C:...,) or Sum
fhc \ ~f) gates generate cad\ of'th, ~· } (S_) 10 he generated al the output after the
·I
-II t:.
p,,... c • 1 1 pro<iuct hits 111
input are supplied to a RCA
l ,ingaro\\ ofaddcrs,cachp:mi· I d 'Avn - Delay of nn AND gate
• • ' .i pro net l'Hn he oddcd
w the pre, 10us sum ot p,nll,,l products. Q17. Glvo the schematic tor a 4:.<4 cerry-save
111e carry-out signals arc shillcd Olll' hi"t t 11 1 n multlptior and oxplaln Its operation.
0 lC C 1lCforc
bctnf ,1dded to thc first adi.kr's· nnd th c new partial . Ans:
,
products slmls. Figure shows a 4 ,.. 4 carry'-save mult,phcr
i\ l"arn ".i"e ·
~ ,·s rcspons1hlc
\dd••r for rclocatin the ~] 1...
,:~1m. ~lllt pans lo the left (CSA) g
l
~here is no hori~ontal carr) propagation for the ....
fin-t four rows because the carry bits. arc trans1crrc,. d
diag.onall) do,~TI\\ ard to the ne:\.t adder stage. Instead,
the correspondmg carr) bit 1s saved for the adder stage
that follows.

~ To output the fin al result, ripple carry adders (RCA) are

utilized at the end stage of the array. figure: A 4x 4 Carry-Save Multiplier (The Critica(Path is Hith•
lighted in Gray)
Speed Consideration
In a 4 x 4 carry-save multiplier. the output carry brts
The Braun mu ltip lier's delay is determined by the entire move downwards diagonally. This critical path can be observed
adder cell's dela) as well as the final adder in the last row. as highlighted in figure. The final result is generated by an
Because the sum and carry signals are both in the critical path, additional adder introduced known as vector-merging-adder.
The carry-bits in this multiplier are not added instantly but are
a complete adder with balanced carry and sum delays is ideal
"saved" for the next adder stage and hence it is termed as the
in the multiplier array. For large arrays, the complete adder's " Carry Save Multiplier''.
speed and power are critical.
The final stage of the multiplier combines both the carries
The worst-case multiplication time of a Braun multiplier and swns in a fast carry-propagate adder stage.
can be expressed as, As the carry-save multiplier requires an additional adder.
t Broun =(n - l ) tcarry-save + tAND + (n - l )tRipple-Corry its area cost is increased a little. Because ofthis. the wOf'St- case
critical path is made short and is represented usmg the following
Where, expression.
t=""""' - Time required to generate Carry-out /mull = f,d;J + (N - 1) fan,+,_
( C0 ) or Sum (S ,,,) at the output after Where,
0

the inputs are supplied to a CSA. ,_ is considered to be equal totcan, i.e.• '~= t
- ...,.

018. Explain modified o r enhanced Braun multiplier.

Ans: Model Paper-1, QS{bl

In enhanced Braun multiplier, the full adders FA 1, F~, F~, and FA 12 of Braun multiplier are rep laced with haJf-adders.
Each replacement will result in a savings of three logic gates thus enhancing the performance. Ho~ever, the structure's regularity
is deformed.

Optimization Measures

The Braun multiplier's performance can be improved by optimizing the interconnections between the adders. so that the
delay across each adder's path is nearly equal.

The connections are made on the basis that the previou~ adder's long delay path should be connected to the oext adder's
short delay path.
Using two optimally interconnecting full adders with fast input and fast output, an enhanced Braun multiplier 1s shown in
figure.

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LOW POWER VLSI DESIGN [JNTU-HYDERf\Q

"o- -~[ >7.

I\
l' ,~--1--+
tl'.,st "Input)
Sum I
- - .~ S , m 2
3 XOR Delay
2 XOR

c"" 2
(Fast Output)
3 XOR Delay
Cout 1
I XOR Delay

Figure· Two Optimally Interconnected Full Adders

~ Fitlwr input .I, or B,can he connected to the long delay path from the previous adder.
,, run adders can he used to connect the partial product array. Due to their logical similarity, any and all partial prodlle
in the same hit ll)Cali\)n can be used alternately. 1

B AUGH•WOOLEY MULTIPLIER
. What is Baugh-Wooley multiplier? Draw its structure.
:
nus multipiier is used for both unsigned and signed numbers with two's complement multiplica
tion to ensure
re~ult:; are positi\c.
The architecture of the Baugh-Wooley multiplier is based on the carry-save algorithm. It has a regular
and iterative str..,
of the ma) multiplier. Figure (1) shows the structure of a 4 x 4-bit 2's complement multiplier,
with the cell number indi
the type of basic cell.
A3 ~ Al Ao

Cell 3 Cell 1 Cell 1 Cell 1

Bo

Po

Cell 3 Cell 2 Cell 2 Cell 2 Bl

0 0 0 0
pl

Cell 3 Cell 2 Cell 2 Cell 2 B2

p2
•
Cell 5 Cell 4 Cell 4
B3
Cell 4

AJ Bi
"l"

FA FA FA FA FA

nc P, p
6
p p4
5

figure (1): Schematic Circuit of a 4 x 4-Bit Baugh-Wooley Multiplier

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 (LOW Voltage Low Power Multiplie rs) 57
11'~e five basic building blocks of the Baugh-W ooley In order lo avoid subtracti on, 1hc ncgntivc lcrms arc
illustrate d in figure (2).
· r are
·plte intcrchnn gcd hy using appiopri atc ,; 1mplift~•1111on.
~111 A, Sum in
A1 Cell] Therdore,
Cell 1
,, 2
---r-B , ' An I
I
L n ,2"
0
I I

The product is then grvcn hy,

Carry Carry
out m I' 11B
XI Sum out
A, 22n I• (An I+ fin I~ An /J,. 1)21" 2 +-
x, Sum in
A, Cell 3 Cell 4
n 2n 2

B,
BI BI L LA .a,21+1+(An 0
,+8,, 1)2" I+
I () /

n 2
An l "" B f 2" .. J I+ B n l ""
~
4 I 2" • I I
~
J O 0
Cany .._I-+- --< . r - - - i r - Carry
out '-t----1 f-----1 in Each AND gate of a multiplie r generate s partial product
A.I Sum out bit. The computa tion steps of a 4 x 4-bit array multipli er is
shown in table below. It produces an 8-bit output.
Cell 5
B, 7 6 5 4 3 2 I 0

aJ a, a, a.,

0 Denotes· a full
-
bl b, bl bo
adder
. a, b0
Cany..+ --+---<. a 3bo 3ib• aobo
out
Sum out a, b, a 1 b1 a 0 b,
A1 a3b1
al b2 a, b 2 a 0 bl
a3b2
fitlrt (2): Basic Building blocks of Baugh-Wooley Multiplier
a3b3 a2b3 a1b3 aob3
020. Explain Baugh- Wooley algorith m.
Model Paper-2, QB(b)
Table
Batp.Wootey Multipli er ' A single AND gate is used to generate each of the
product term. Prior inversion s are denoted by bars abo, e the
This multipli er is used for two's comple ment
variables . Prior to tl1e complete adder or AND gates, in\'erters
rnllhiplication. It is explaine d below.
are connecte d to their respectiv e inputs. Product terms are added
n-2
let, ~ a;,2 to each column in accordan ce with their appropri ate ""eighL.
A = (an- 1··•·• a 0) = -an-1 2n-l + L.J 1

•
0 n(n - 1) + 3 complete adders are needed in this S) stem. ~o. a
n-2 4 x 4-bit array multiplie r requires 15 adders.
B = (br>-l ••. • . b) = -bn-1 2n-1 ~ b;.2;
+ L..J
Q21. Draw the Baugh. Wooley wlth 2's comple ment
0
0

Then, the multiplic ation of A and B is given by, generat or..

Ans: Model Paper-3 QS(b)
n-2 n-2
LJ .L..J I.b.2.-
A.B=a,,._1 b n--1 2n- +""""a 2
I I
In Baugh-W oolo) multiplie r, the signed multiplu. :ands
0 0
arc initially converte d into their 7's complem ent tiJm1s. F1gu.rc-
n-2 n-2
a "" b. 2n+i- l_ bn-1 ""a.
~
2n+i-l below depicts a Baugh-W oole) multiplic-r "ith 2's complem ent
-I ~ I ~
0 0 generato r.

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58
LOW POWER VLSI DESIGN (JNTU-HYDERAe~
A
'
A
Comp s1
~

P, p~
Figure: Baugh-Wooley Multiplier with 2's Complement Generator

It is a combinational circuit that either pass the direct input or in its2's

complement form based on control signal.
❖ If Complementary Signal (Comp-Sig) is high, it converts input to it's
2's complement of form. The XOR gates inverts ...
input bits and adds 1 to the result. is the output result.
❖ When the Comp-Sig value is low, input remains same and bit O is added
to the multiplicand inputs
❖ After the signed multiplicands are processed, the MSB of the result
would reflect the sign of the result ( l for neg.itiw.
for positive).
022. Explain the perfonnance consideration of Baugh
-Wooley multip lier.
Ans:
In Baugh-Wooley multiplier, the number of bit operands and the layout
techniques aftect the afc'a and po,,er ct,nsumpti,,n
of a number of multiplier structures. In a standard-cell-based design
flow, increas ing regularit) and localit) at the silil'.t'n 1.:iel i
reduces power consumption.
S.ince, the Baugh-Wooley multiplier is an ex.tension of the Braun multipl
ier, it can use the same optimiz:ition in\ercoiuiec~
1
technique used in Braun multiplier.
The modified Baugh-Wooley mulhplier with optimized interconnects
1s depicted in figure bclo,,,
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~(LOW Voltage Low Power Multipliers) 59
A.~,-----/\:-----A~----------------- 1 ,\

·r -

r
0

----P ,
B

£ _____ J.... , ~-----,: ... , I

~-----,L -, £ _____ .. BJAl
t I
.. - _ .. t I I

: ' ~~~~ ~-~~ I I

Figure: Modified Baugh-Wooley Multiplier with Optimized Interconnects (Dotted Lines)

)

Points to Remebe r
partial products by evaluati ng two
The Booth multiplier uses the Booth encoding algorithm to minimize the number of
r architect ures .
bits o_f the multiplie r at a time, resulting in a performa nce gain over conventi onal multiplie
.algorithm is val.id for both signed and unsigned operands .

in compar ison of conven tional

Q2J. Explain how Booth's algorith m is suitable for signed number multipli cation
Shift and add method .
Ans: \1odel Paper-1, Q9(a)

two's complcm t:nt form. It i:s

The Booth's algorithm is an approach that performs multiplic ation of signed numbers in
number or both negati-.c numbers Unh!,e
functional for cases such as, two positive number, one negative number and one positive
onal unsigned multiplic -ation m~th'-lds
lhe current multiplic ation methods the Booth 's method is more or less s imilar to convc-nti
but With ti0 I .
lowmg differenc es.
courses must o~cur next Therefore,
,L Basically, here two bits of multiplie rs are multip lied ino rder to find out which of three-
"
1
taJg ·
O{llhm can be specified as,
(iJ
1s set to ·o·, th<'n p~rfonn sub.,tru.: twn
When the value of the current multiplie r bit is set to ' I ' and the next lower order bit
of multiplic and from the partial prod uct.
Oi)
-r bit i:s st>t 1,, · 1• then 1x·rfQnn
When the value o f the current m ultiplier bit is set to 'O' and the next lowl·t ord~r multiplit
· of multiplic and and partial product.
the add·1t1on

SPECTRUM ALL-IN-ONE JOURNAL FOR ENGINEERING STUDENTS

~
Q24. Explain the operati on of Booth's Algorithm. Montlon the standard rncf1x•2
LOW POWER VLSI OESIGII (JIITU-H
Booth mu1tlpUcatfon ~
/DEijAJlr
Ans:
Booth's \IJ?,m ithm
rn 2'• comp ~ form ~
for mulliplka1ion, till' Bmlth nlr,mithm. llasrd on rucli,c-2 computation. take numhcl"!l
is also called 1;1d1\.-2 algot ithm. In this, ;1 2\ complement tcprcscntat,on of signed bmary
multrpl,cat,on I med A5 at
\\ a) l1l't'mn,I ~igns ,m· kept in ,11r-:iliary circuits tn.:comc~ more comphtated.
Pror,•,iurl'
ln1t1ally an imagirrnry 0 is appended to the right of the multtplicr.
In 1,nkr to obtam the ;1h bit of_v, (J•. 1y, 2
.... J', y0) ot the recoded multiplter, the current brt x and the prevJOUS bit l
❖

multiplier (r_ 1
" , .... \ ' 1 , 0) arc l!valuatcJ ,

In this case, the previous bit x, , 1s used only as a reference bit.

Snnilarl) x, , will be recoded to yield Y, " with x1 2 as the reference bit.

for ; = 0, its corresponding reference bit, x, 1
is defined to be zero.
❖

TI1e recoding method used in Booth algorithm is summarized in table below.

x.I Operation on multiplicand A Y,

Xi - I

One bit shift to the right only 0

0 0
0 l
. ---
Add A to the existing sum of partial products and then shift 1

l 0
the result one bit to the right
Subtract A from the current sum of partial products and then
shift the result one bit to the right
I T

l l One bit shift to the right only 1 0 I

Table: Recoding Method in Boot~ Algorithm

Standard Radix-2 Booth Multiplication Rules

❖ Add a zero to the right of the multiplier's Least Significant Bit (LSB).
multiplier bits.
❖ Starting with the low-order bit (LSB) and the added zero, examine groups of two adjacent
❖ Shift the partial product I bit to the right, if the pair is 00 or 11 .
one bit, if the pair is 01.
❖ Multiply the partial product by the multi~licand and shift the partial product to the right
to the right b} one bit if the·
❖ Subtract the multiplicand from the partial product and shift the resultant partial product
is 10.
of the next.
❖ Continue with overlapping pairs of bits, with the MSB of one pair becoming the LSB
manner.
❖ Each iteration thrqugh the algorithm eliminates I bit of the multiplier number in this
the last pair of bits is e,aJu31;,!
❖ The partial pr~duct is updated according to the rules, except that no shift is made when
of I's is the s3Itle as a (k -J)-1'
The 2's complement multiplier is recoded considering the fact that a k-long sequence
. An) binary number can be rec~
sequence of O's. This change of a string of J's to O's helps to minimize the partial products
high end, and between O's replacing~...
in this way, with a minus l (denoted by Tat the low end, a positive 1 to the left of the
order. lt can even be done at the SJ!'.'
group of J or more adjacent l 's. This recoding method doesn't have to be done in a specific
time for all bits.
Drawback
Booth's approach becomes inefficient in the presence of isolated Is.
s.
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 61
ir-4 (Lbw Voltage Low Power Multipli ers)
th algorit hm. Mentio n tho sot of rules used fo~ tho radix-A modifi ed Booth algorit hm.
~pla in modifi ed Boo
~.,s: . .
h th
In modifie d Bool a~gon m. the multtph er is recodl•d in th1. higher
radix. Less number of cycles nrc needed tc'l prnd ur_c
tJJC product because more bits can be inspecte d and clunina tcd m every cycle.
procedure .
~ A ,cro 1s append ed to the nght of the LSB in the modified Booth's techniq ue.
~ With ., , as a referen ce bit, the multipli er bits' '"ond , I I arc recoded into ;, and y I I'
<
,~
In the next step, x, 2 and .', ., are recoded into Y, , and Y, ,, respecti vely,
with -c, serving as the referen ce bit.
❖ 2
multipl ier is subdivi ded into three-bi t substrin gs. with adjacen t groups sharing a same bit.
.:, As a result, each
On the right side of the multipl ier,. the term x, 1 with a zero value is
added.
~
) •:-c5x4 (x3) and so on •
0:,
The bit structur e of M SB become s x 1 x 0 (x - 1) ' followe d by x 1x2 (x 1•
used for the radix-4 modifie d Booth algorith m to
Set of rules used for the radix~4 m~difie d Booth Algorit hm: T he set of rules
,, odd number of values 1.e., 1 = l , 3, 5 .. . is shown in table below .
,n,"r' "or
'lI • .
,. - 1 x .- 2 Y, y 1 - l Comme nts Recode d Digit Operat ion on multipl icand A before shiftin g
2 bits to the right

0 0 0 0 0 String of zeros 0 Nothing

0 I 0 1 End of ones +l Add A to the existing sum of partial produc ts

0
1 0 0 1 Isolated one +l Add A to the existing sum of partial produc ts
0
1 1 1 0 End of ones =+2 Add 2A to the existing sum of partial produc ts
0
0 0 1 0 Beginni ng of ones -2 • Add -2A to the existing sum of partial produc ts
1
0 I 0 1 Isolated zero -1 Add - A to the existing sum of partial produc ts
1
l 0 0 I Beginni ng of ones -1 A dd - A to the existing sum of partial produc ts
I
~

1 l 1 0 0 String of ones 0 Nothing

Table: Modified Booth Recoding for Radix-4 Booth Algorithm
It is possibl e to generat e each of the recode d
In Booth's recodin g method, the carry is not propaga ted on to the next stage.
digits separate ly.
lier in brief.
Q26. . With a neat block diagra m, <explai n modifi ed Booth multip
Model Paper-3, Q9(a)
Ans:
The block diagram of a modified Booth multipli er is depicted in figure below.
X <n - 1 : O>
n
Booth Carry
Encode r

Y <n - 1 : 0>
n
and Sign
Bits
Partial Produc t
Generat or +
A dders' A rray
n-bit
A dder
P:-1,0~ /
. Extensi on
Carry \
P < n - 1 : n>
Figure: An n x n Modified Booth Multipli er
d Booth multipl ier arc,
For concate nating bits, a colon is used. The main compon ents of modifie
I.
The Sooth encode r and sign extensio n bits
2. adders
An array of multipliers, which consists of partial product gene rators and I-bit
3.
A final stage adder for 2n-bit addition .
o f the mu ltiplier's three unique 3-bit segments:
As a result, the Booth encoder generat es the followi ng five signals for eoch
O, + IA, +2A, - IA, and - 2A.

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62
Q27. Explai th LOW POWE:n VLSI DC:SIGN (JN HJ HYDER
n e concept of modlflod Booth multlplior with o sulU,blo uamplo ABAr,
A~ . -
th numb r ol 1111!J, r
1
A radix multiplit•r of higher 111di, lik,· ,mli, I 11111lt1pli~, / 111111th ,c, ord1111' 1111 111,plJ, r 111101111110
11111l11pl11.:r hit ,r div,,
~cnce the dd1n '.1ct·dcd to gcm•1,1h' tlw pnttiul s11111•) h, ,111111)/mt 1111 pl11111l11 y 1111 ,11 , 11mc IlcrL 1h
1 111d th lhlld hJI I I,
mto pairs of, .hits l'ilrh and ,1t II tmw l hits nn· ". 111m·d <>111 ol 1111 1 111I ""• 2 1,1, ... ' di c 1f!JI II pr II pu ll

order bit 11f ,1dJlll'l'llt lo'\\ ct or1k1 p1111 I he g1·m•1 al plllrnhn ,. ol 1111111 rplu .,11fi11 1 Aliowrr 111 liv.nri:; ( I I

Mull rp lwr <, 1'1(111111 1111100010110101

M11ll1plrt,lltd (M) 1011 1101 I ()(II 1100 IO I IO I I I

10011100101101 11 .. M I.sh
()
0 00 0 0 0 0 ()()() 0 0 0 000..,
I M
10011I00I01I011I~ ()
() II
oooooooooooooooo-
' M I
1001110010II011 ,,.,
M I
I 0011 I 00 IO I IO I I I-<- -- ()
0 I
0000000000000000-<i- - - M I p
1001110010110111 ◄ ---
0000000000000000 - - - - - ~10~> 0
() l
oooaoooooooooooo - - - - - ~~
()
0000000000000000-- -- - 0 I
100111ooio110111-- - - -- M .l C
1001110010110111-+-- - - - -- M r
1001110010110111......,.-- - - - - - ~
1001110010110111<<-------_JM~
+ 100lll0010ll0lll _ _ __ _ _ _ __:.M.!.!.-_ I Msb

100110000lOOOOOO·OOO1010 IO 11000 I 1=·2554336611 10 - Product

Figure (1)
The Booth multiplier has an array of adder cells arranged in rows and the input circuitry is also provided which reduce lhc

multiplier power consumption.

For the generation of all booth recoded control signals, Each recoding cell consists of balanced logic circuitry :,pht b111
present in the input circuitry provides first number to the array. The generation of partial products usmg Booths recodmg rs ~ho\lt

in figure (2).
Multiplier 63669'° II I 110001 01101~;11
Multiplisand(M) 4011910 1001110010110I~

I OOOI OOI I I OOI OI I OI I I-+- IM_ { I.sh ~

0 IM { O
11010011 IOOIOIIOl 11- - {: M

!0::::::::::::::::::7' ~ {{;) I iM I
l
I 101001 I 100101 l011I~ ----- 0
tOOllOOOIIOIOOlOOOI O ZM{ ~ I:
101]]]]1111111]]11]) ,:.__ _ _ _ () {: C

I O{ :
011111111111111111 ~
I IM { b Mb
+ 1001110010110111 O s

100110000 10 00000000101010110 0011

Figure (2)

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 (LOW Voltage Low Power Multipliers) • 63
1f ttf1 . -----------------
a neat block diagram, explain the function of Booth e_n_c_o_d_e_r_
ModCII Papor•1, Q!l(b)

: following are the main functions of Booth encoder

file . •
plcments Booth encodmg of the three multiplier bits.
101
dies the sign extension logic.
uan
;. basic strUcture of Booth encoder is illustrated in figure ( 1).

r----. D - - ~
Xi

bi - 1 - - - t - - + - - - - - - - 1
b; ---,--,~ ----....J
MUX

j+l ______ ______ ______ _l.__ _ _ _ _ _Mi

_.2._,
b

Figure (1 ): Logic Diagram of a Booth Encoder

The array's encoders are allocated between its various partial products, each of which is assigned to a certain encoder.
Only one of the five possible generated partial product signals is high during the steady state operation since there is a circuit for
each ofthe signals. The carry propagation circuits do not have common inputs and do not depend on partial product circuits.
As seen in the block diagram, the signals three signa.ls ~; 2 JS and~. are generated from three adjacent bits, b, _ 1 , bp and
b for selecting a partial product that is 0, +A, -A, +2A, or :_2A. Here, A is an n-bit multiplicand.
J• I
1be signals X1 ,2 XJ indicate whether the partial product is doubled or not and the signal M.J indicate whether negative partial
product must be used or not.
t An active ~ indicates that negative partial product must be used.
The conventional partial product generator for this implementation is as shown in figure (2).

a.-l
I
-----1
2x.-----
J
f
M.------ ------- ------'
J

Figure (21: Conventional Partial Product Generator

Using figures (1) and (2), the operations A* B and - A*B cannot be directly computed. These can be implemented using a
sign-select Booth encoder as shown in figure (3).

bj ~ : - - - - - ' D - -......
b - J----\
r~~~r>o-_ -~~::~~~~=== :~J
J

b. ----1
J
b;+ i- - - - - - - - - - - ~ SEL

Sgn---==----------~
b - 1----c
J
b; - - - - t_ __,,
bj+l _______ SELi----M i

Figure (3): Sign-Select Booth Encoder

SPECTRUM ALL-IN-ONE JOURNAL FOR ENGINEERING STUDEIVTS

 y ,.
\Jsmu s1.g11 sl'll•, I H1•llth rn1·c,dl'r, hy h;lll u mg the log,c
tilrry IIIV
01\ ml~ 111th l\1l l:X 1 !:, the p1111111I p111d11 11 gcncrntor Glln he ,dilet
mod1hcd n~ ,h,m11 m hg111i' ( 1).

8t_,rT _ l\1lJX
'i
Jl-
x, 2X 1
•
A,--- -
I I Pat(tlll
Pmduc.;t
MUX

'l /
MUX carry save
a,,---.____ _, adder

Figure (31: Modified Partial Product Generator

4.6 INTRODUCTION TO WALLACE TREE MULTIPLIER y ✓

carry save carry ,~ve

Q29. Draw the schematic and explain the working of adder adder
Wallace multiplier.

Ans: Figure: A Wallace Tree Structure

Q30. Give an Introduction to Wallace tree multipfi
The Wallace tree assembly is the finest approach for
and summarize the multiplication process.
,pecding up addition. It is an adder tree constructed from carry-
Ans:
save adders. The Wallace tree is an array of full adders whose
[n 1964, C.S. Wallace invented the Wallace T:
carry signals are not linked. Three· n-bit numbers a, b, c are
multiplier, which can handle the multiplication proce:!S for lar~
given by a carry save adder that calculates two new numbers.
operands i.e., more than 16-bit wide numbers. The Wall~.
Lety and z be two new numbers then y + z = a ➔ b + c tree multiplier uses Wallace tree algorithm The Wallace
decreases tho number of partial products that must be added Ill!:
The Wallace tree accomplishes 3 to 2 deductions at two intermediate results usmg multiple input compressors :m:
every single level of the tree, i numbers arc united to form r2i/3] full-adders. Generally, the Wallace tree multiplie:s tv.o wisigDI'
!)Urns. In this case a high speed adder is employed for addition, numbers. It is a hardware version of a digital multiplier th,;
when only two values are left. An assembly of Wallace tree inultiplics two numbers efficiently.
is illustrated in figure. The partial products arc initiated at the This algorithm adds three inputs using pseudo add,r,
bol1om of the tree. Each of the z outputs is shifted left by one then creates two output~ whose sum equals the sum of the thrtt
bit because it-signifies the carry out. h1puts. Using these pseudo udders, the multiplication speed ~
·,
because they don't have Ill propagate the carry forward. Usin.
The greatest advc1ntage of Wallace tree multiplier is il is muny pseudo adders al the same time cun improve multiplicali~
I
faster than a simple array multiplier. Jt requires less power lor speed t•von more. Fo1 n number ofrows, the Wallace tree meth():
bit widths between 8 and 32, with the advantage orthe Wallace can minimize the number of purtial products in parallel, will
tree growing as word length increased. on ovcrnll delay proportional to log 312 n .

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 p 8 rt1nl Product (,1,;n

u t \\ IS h,tkd { ll:

nd hit mult1phL Hmn lhl: 1•n t 11 1

I ft 111 1 ncd mult1phc tmn
p rt1 I Product Reduction Stage
tcm of cowllcrs reduces l 1L partial pre dud
d s not propa te the rrtC!-. Th 1\ t m d 1 a 1 4
ts of the counter:<-' Mllll'- ndc rr, In n t 1
ccd ,\,th another set of counters ,md the proc du c It
pcatcd until a l\\O-nrn matrn,. 1i,, p1odnccd
Partial Product Addition Stage
fnc um
nal adder, generall) a caIT) propagate adder 1s used
dd up the t" o ro\\ s. To avoid car1; propagation
5 I,

ul the last adder. this technil)uc uses the carry sa, e J!ere.
re utec:turc "T"l-."' ult1plic1 's speed is dctennincd by the ❖ Th input c rr
bcr of Jc,"' s . this system. lesser c;1gmfican b t
B, using 3:2 cmnpicssors. the traditional Wallace tree on to the next high
gonthm <fecreases the propagation stages. of each other thu
The Carry. r IS n
Q11 Why 4:2 c o mpressors are used in Wallace tree?
first full ndd.:r
Explain in detail.
The carry-out, C
Model Paper-2, Q9(b)
and In
4 2 compressors were invented by A. Weinberger from
Equnllon ( l) c;nn b ... "1 \\ >R
198 1. He proposed replacing the 3:2 compressors in
dda}., whtch is cqul\ alcnt to r
1onal Wallace tree method with 4:2 comprt:ssdrs t
output tram the \V<1ll,1cc tn:c tru ...
lldace 1he number of propagation stages in tree multipliers. · addcr:,,(C'SAs).
advantage of tree multipliers is that their speed scale<;
So, t·qu<111on (I) cm be n: 1
1oga.rdmucally with the length of the operand. Because it can
S [(In In)
our inputs of the same weight to two, the 4:2 compressor
v1dc a far more regular structure than the 3 :2 counter. Wllh this nrran • m nt, th

G32 Explain Wallace t ree construction. Mention the tree complexities.

In general, the Wa llace tree multiplies two u1!1;iµm d number~. J he proposed~ alla c tree muluphc •
A D array for comput111g partial products an uddc1 fo1 li<ld111g thl' p,1rual produd-. -.o "C ,crated I d
end of the addition process

By reducing the numhcr of adders iu the paniul produc ts 1cdtrct11m st,ltc, the \\ ,11lacc tr1.:c mult1plic1 s I n..:, 1 h"

lo~ercd Multi bn compressors arc employed in the pwposc<l t1rd11tccturc to 1cdm·c the numbc1 ofpani 11 produ1.:t dd1ti,, sh.:p

The Wallace tr ee is constructed by tak111g ,ill of the bits i11 cc1ch four rlnv 1l I l11m: ,111d L'o111pn:,s111 tht n in the most
cfticacnt way posi;ihlc as shown in l 1gwc (I) ·

SPECTRUM ALL-IN-ONE J OURNAL FOR ENGINt::ERING STUDENTS

 f1gu1 e 11). Traditional \'Jallace Tree Constructior:i
Con\trurtion r·om1•lc~itics

I. In trad1ttonal Wallace tree, as the pan ial products ~re being added m one direct on. from to bottom the
compn.-.s,or:. or adders and v,ircs incrca..cs with addtng stages. It result mer mg the ta,out widt!J.
.
figure (2) 11l~tratcs the increasing width of the adding stages. Each horr,ontal hne m the Wallace tree represenu a
of compressors.

111111

1 ::: :: : ::: 111::::::11111 1111

.Figure (2): layout of Wallace Tree Multiplier before Arrangement
2. The compression metho? varies depending on the number of partial products to be compr~ at each position. It's neat;
impossible to lay down a Wallace tree multiplier in a rectangular shape ¥.ithout wasting a lot of chtp area becaus.: of
non-regularity.

Figure (3) illustrates that when the tree is laid out in a rectangle shape, 38 percent of the o,erall rectangular area IS "~-
The wasted area is called the dead area.

I I I I I I I I I I I I I I I I 11 I !!! !!I> 3
~. to,, """

Figure (3): Layout of Conventional Wallace Tree Multiplier after Arrangement

------------------
Q33. Explain the modified Wallace tree construction

Ans:

The drawbacks of a traditional Wallace tree can be ove11;0111e u,ing thl• ll1lldifo,•d \\ 11IL1,e tre,•. Here. around the cen~
of the tree, the pan1al products arc divided int<, two groups, with p;ntinl pwduc t~ in one gr,lltp being addeJ from the top IO tll<
bottom and partial products in the other group being added fiom thl· bo\111111 Hl th,· t,lp.

Figure (1) illustrates the proccs~ of splitting" Wallacl' lll'C into two p.111,.

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 (LOW Voltage Low Power Multiplier s) 67
4
~ I I
I I - ►-
.._ .__
- ·- --·-._ ·-__ ,_
1-- '-
I I .' I 1 I ,-,
·-
X X X X X X X 'X ) I:x 'll' X I): IY
~
/\ddmg dircclio11 '!I 'l{

X X X "( X X '\{ X xx i'!IIY 1 ... \I IX

xx X X X X X X X X X xx D<X xx
xx xx X }
iX X X lX X X X xx xx
xx xx xx XX X X X XX XX xx
I, IX !X XIX xx xx X XX IA X X X X X
IX IX X IX IX JI. XIX X X X XIX l\ A l\ }\ .~
X X X X xx xx
xx X X X X xx xx XX XX XX xx xx
XX
XX Adding direction
xx X xx xx I} X xx xx xx X
XX xx X xx xx xx xx xx X

Figure (1): Splitting a Wallace Tree into Two Trees

lbe steps followed in this process are,

t bits are in the
The partial product bits are first separated into two trees: the left tree and the right tree. The least significan
right tree, whereas the most significan t bits are in the left tree.
ed in a downwar d
2 The right tree is compresse d in a Wallace tree in an upward pattern, whereas the left tree is compress
pattern. This reduces the amount of wasted area.
up)upwar ds. A
3. Then. one of the two sub-trees is accumulat es (adds up) downward s, while the other is accumulat es (adds
lot of area can be saved as a result.

A comparison of the traditional Wallace tree and jts modified version is illustrated in figure (2).
..... _ ....
I : •- . . .
I - ••

..........
-

I
I l l :·· ..--
(a) Traditional Wallace Tree (bl Modified Wallace Tree
Figure (2): Layout Diagram

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 1

68
LOW POWER VLSI DESIGN [JNTU-HYOERABAc
---.....;
IMPORTANT QUESTIONS •• •
•
Q1. Give an overview of multiplication .
Ans: Refer Q l4
~~
-

Q2. What is Braun multiplier? E,tplain Its operation.

Ans: Refer Q 16

Explain modified or enhanced Braun multlplior.

llr,JIOftlnt Q,"
--......
Q3.

Ans: RcferQIS.
lmpol'tlrl ~
Explain Baugh-Woole y algorithm. ---..
04.

Ans: Refer Q20.

lmpc;rtant~
~

QS. Draw the Baugh-Woole y with 2's complement generator.

Ans: Refer Ql I. . L~,t~

Q6. Explain how Booth's algorithm is suitable for signed number multiplication in comparison of conventior_a.
shift and add method.

Ans: Refer Q23.

lmpcmant~

Q7. Explain the operation of Booth's algorithm. Mention the standard radix-2 Booth multiplication rules

Ans: Refer Q2-t Important~

08. Explain modified Booth algorithm. Mention the set of rules used for the radix-4 modified Booth algolithn.
Ans: Refer Q25. lr.:oortant ~
Q9. Wrth a neat block diagram, explain modified Booth multiplier in brief.
Ans: Refer Q26. 1moo11an1Ques::DI

Q10. Wrth a neat block diagram, explain the function of Booth encoder.

Ans: Refer Q28. lmportant elues:»:

Q11. Why 4:2 compressors are used in Wallace tree? Explain in detail.

Ans: Refer Q3 l. lmportant QUIIStC'I

012. Explain Wallace tree construction. Mention the tree complexities.

.
Ans: Refer Q32. bnportant auesac:
Q13. Explain the mooified Wallace tree construction.

Ans: Refer Q33. lmpo!W\t Questie!'

.
. '

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