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36 views15 pagesEncoder Decoder
decoder encoder details
Uploaded by
mridusasikumarCopyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
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/ 15
hose
120 ENCODERS ‘ante haracise td eh
‘encoder is i inputs are decimal digits and/or apes aavice hici Converts
Samco pt elt li ius facnder tng be oad 0 OSE
tai une syle ats coded format. In other words,
ite of
he opposite of
. ion of the decoder. The f
bit ircui evens, opera ing familiar number:
S tenng Ee Cult that performs the edditig ie a proces OF Soliverting
M8 Process is called encoding, i.e. enc: number of input lines, only one of wh
or symbols into a coded format. An encoder has a number of inp whi
tcivste at gen me an prodics en Vi ouput eae depending on vhich inp sci
Figure 7.6 shows the block diagram of an encoder with M inputs and outputs, Here thet
are active HIGH, which means they are normally LOW.
xa
sh,
st
umber} X>¥
X=Y P Outputs
Xe¥
son
‘umber ¥
>—Not used
Figure 7.60 Example 7.9: Use of 7485 as a S-bit comparator,
Aa em
Ay boo,
AW) Nn boo,
Minos $ oe
eniyore J) | — a
HIGH at 4 D Out
atime 8 ‘ode
A
Aus 20x,
us| oon.
Figure 7.61 Block diagram of encoder
7.20.4 Octal-to-Binary Encoder
t. Figure 7.62 shows the truth table and the a
Gicuit for an octa-o-binary encode with active HIGH input,
From the truth table, we see that Ais a1 if any of the digits D, or D, or D, of D, 88
‘Therefore, amt
A, =D,+D,+D,+D,
Similarly,
,+D,+D,+D,
Wesee that D i ot reset in any of he expressions, So, Dy
1 don’t care. ‘COMBINATIONAL LOGIC DESIGN 377
Octal inputs
uae Binary 2 0, Dd, 0b,
AAA
wt
am aoe
uckiritind a8 =D-*
Le ame -
Pes gicanta gi =D-* a3,
ne
eee “
mar
(©) Loge saga
Figure 7.62 Octal-to-binary encoder.
1202. Decimal-to-BCD Encoder
Tistype of encoder has 10 inputs—one for each deci
imal digit, and 4 outputs corresponding to
{BCD code as shown in Figure 7.63a. This isa basic
10-line to 4-Line encoder. The BCD code is
>|
|e]
Be
a
ono he nan ely
PEL er I
3 2,
Pir @ Tah able
Decimal inputs
——a_or
Dy Dy Dy Dy Ds Dy Dy Dy Ds
eco
e > Pe
(6) Logi dlagram
Figure 7.63 Decimalto-BCD encoder. ‘378 FUNDAMENTALS OF DIGITAL CIRCUTTS
Tisted inthe truth table (Figure 7.63) and from this we can determine the relationships
cach BOD it and the aca igi, Tees no exptinput fra decimal 0. The BCD on
0000 when the decimal inputs 1~9 are all 0.
‘The logic circuit of the encoder is shown in Figure 7.63c. From. the table, we get
Ay=D,+D,
Aj=D,+D,+D,+D,
A\=D,+D,+D,+D,
Aj=D,+D,+D,+D,+D,
7.21 KEYBOARD ENCODERS
Figure 7.64 shows atypical keyboard encoder consisting ofa diode matrix, used to encode te
decimal digits in 842-1 BCD.
Figure 7.64 A keyboard encoder employing a diode matix.
‘The S-R flip-flops ate used to store the BCD output,
decimal digits is pressed, a positive voltage forward
SET(S) and RESET(R) inputs ofthe flip-flops. The,
7
. When akey corresponding 100%,
biases the selected diodes connect
diodes are so arranged that each fip-®°? COMBINATIONAL LOGIC DESIGN 379
en Oris that connected to the R in the S inputs of Q, Q,, and Q, are forward
A eta ine poe a tint Na tr te dade
‘ tiode ;
jon printed ict ards of many devices having a keybou sthe meme dec acye
122 PRIORITY ENCODERS
ecules discussed so far will operate correctly, provided that.
a omen ele ney ini
jae HIGH a the same time. For example, a person operating a keyboard might press a second
iy before releasing the first. Let us ay he presses key 3 before releasing key 4, In such a case the
fat willbe 7,9 (O111) instead of being 4, or 3,
‘Apsiority encoder isa logic circuit that responds to just one input in accordance with some
sity system, among all those that may be simultaneously HIGH. The most common priority
spe sbased on the relative magnitudes ofthe inputs; whichever decimal input isthe largest is
‘ene thats encoded, Thus, inthe above example, a priory encoder would encode decimal 4if
toh and 4 are simultaneously HIGH.
Insome practical applications, priority encoders may have several inpus that are routinely
{ll atthe same time, andthe principal function of the encoder in those cases is to select the
iat ith the highest priority. This function is called arbitration. A common example is found in
computer systems, where there are numerous input devices and several of which may attempt to
‘pty data tothe computer atthe same time; A priority encoder is used to enable that input device
‘ch us the highest priority among those competing fr acces tothe computer athe same ime.
1224. A-nput Priority Encoder
Tet able ofa 4input priority encoder is given in Figure 7.65 In adition othe outpats A
‘WB, the circuit has a third output designated by V. This is a valid bit tor that is set to 1
‘“hen one or more inputs are equal to 1. If all inputs are 0, there ‘no valid input and Vis equal to
(Tieoter vo outpts are not inspected when V equals Oand are speifed as don’ tear conditions
Acuring tothe truth table, the higher the subscript number, the higher the priority ofthe input.
has the highest priority. So regardless of the values of other inputs, when this input is L
cutpt for AB is 11 (binary 3). D, has the next prionity level. The output is 10 if Ds =
Pied that D, = 0 regardless ofthe values ofthe other two lower priority inputs, The ouput or
vs generated only if higher priority inputs are 0, and so on down the priority levels.
From the truth table we observe that
"A=Dy+ DyD,=D3+Ds_
by B=D, +D,D,D,=D,+,D,
VeD,+D,+D,+Dp
‘The condition for output V is an OR function ofall the input oo
Fpl ADs fr simplifying outputs A and B and he coreszondig lagi diagram are shown
es 7.65b, ¢ and d. Although the table has only five rows,
ye input variables. ‘eplaced by 0 and then by 1, we obtain all 16 possible input combinations. The minteng, 7
‘wo functions A and B are derived from the table as te
A=Em(1, 2, 3,5,6,7, 9, 10, 11, 13, 14, 15)
B=Em(1,3,4,5,7,9, 11, 12, 13, 15)
‘The same values of A and B mentioned above are obtained from the K-map,
2,0,
2.0, er
10 oo
OPN Oot HOD) 1
. co] x) [TT] 00} x
Tapa Outs 4 Bt
RD FeV 4 atl Ta ol
eye oe Fr] art Fa %
Hero's ORO! Beal Rot nog vial aff
x 100 014 7 a
= Mily tame O once 40pm ts Yeug| tay 10]
Sra Kod woe
‘R=D3+D, B=D,+5p,
(@) Tran tble (©) Kap for A (Kap rs
Dy B=0,+5,0,
abe D>
cy
A=D,+D,
v
Dy.
(@) Loge diagram
Figure 7.65. 4bit priority encoder.
7.22.2 Decimal-to-BCD Priority Encoder
ing to the truth table and logic diagram a
is HIGH when D,, Ds, D,, D,, or Dy is 6
In the priority encoder, input digit 1 will be
'si,_D, 0,70,
1 x x TWited
fs O00 shored
oo4 toad
oto 1404
Ds Ont t te d4o-ta duc
(@ Loge dagram © Tosh ab
Figure 7.70 2 lneto- line decoder with NANO gates.
tha, meee With enable input can function as a demure. A dermailenee is set
“ion erga fom a single line and recs ito oof th 2 pos ut
7. Specific output is controlled by the bit combination ofn selection lines.
inte of Figure 7.70 can function asa I-o-4 line demuliplexer when Eis taken asa
"Pine and A and Bare taken asthe selection np The single inpt variable has path
a 386 FUNDAMENTALS OF DIGITAL CIRCUITS:
‘toall 4 outputs, but the: st information is directed to only one of the output lines, as speci
Moe ea eP ice seleon ines AandBTisean be verified fom the mg
the circu. For example, ifthe selection lines AB = 10, the output D, will be same q
input value, while all eher outpts are maintained at a 1. Because decoder and demu
operations are obtained from the same circuit, a decoder with an enable input is refered,
decoder#demuliplexer.
7.23.5 Combinational Logic Implementation
‘A decoder provides 2* minterms of n input variables. Since any Boolean function can be ex
in sum of minterms, one can use a decoder to generate the minterms and an external OR gay
form the logic sum. In this way any combinational circuit with n inputs and m outputs can
implemented with an n-to-2* decoder and m OR gates.
“The procedure for implementing a combinational circuit by means of a decoder and 0g
‘gates requires that the Boolean function for the circuit is expressed in sum of minterms. A dcodg
that generates all the minterms ofthe input variables is then chosen. The inputs to each OR ae
are selected from the decoder outputs according to the list of minterms of each function. Tis
procedure will be illustrated by an example that implements a full adder.
From the truth table ofthe full adder, we obtain the functions forthe combinational cicitin.
‘sum of minterms.
@B@C,=Em(1,2,4,7)
and Cy, = ABC, + ABC,, + ABG,, + ABC,,= AB +(A @B)C, = EmG,5,6.7)
Since there are 3 inputs and a total of 8 minterms, we need a 3-t-8 line decode. Th
implementation is shown in Figure 7.71 The decoder generates the 8 minterms for A, B.C, TE
OR gate for output S forms the logical sum of minterms 1, 2, 4 and 7. The OR gate for Cy,
the logical sum of the minterms 4,5, 6 and .
Cua
Figure 7.71 Logic diagram ofa full adder using a decoder.
A function witha long li
A
of minterms requires an OR gate with a large numberof
function having a list of K minterms can be expressed in its complemented form F wit!”
terms. Ifthe number of mints in a function i greater than 272, then Fcan be exP 7
fewer minterms. In such a case, i is advantageous to use a NOR gate to sum the miners
_ NOR gate complements this sum and
tpt ofthe F {eneraes the normal output F. If NAND.
or Se rarer BE 1 ecm ah NAN
OR: became a te circuit implements a sum of minterms
manele oa vel AND On ANE ene
1238 10-16 Decoder from Two 3-t0-8 Decoders
with enabeipots canbe connected togeth
ibe rangement for wing two 741 38s,
in Gimtinali heen.
1 t form a larger decoder ciruit. Figure 7.72.
oes cuit. Figure
sepper decoders enabled andthe lover decoder isdsabled Toe "
sip oupus generate minterms. When Ayis HIGH ws
tap dzver is disabled. The botiom dec
lower decoder is enabled and the
"oder outputs generate minterms 1000 101111 while the
capat ofthe top decoder are all Os.
Forte
Upper decoder
‘Decimal outputs
Ay
3x8
1% decoder
Lower decoder
(Loge dag Fane
Faure 7.72. Connecting wo 74138 240-8 decoders oobain a 41616 decode,
r
a7 Decoder Applications
ed only onthe occurrence
(a speratt Used whenever an output or a group: oe soe See ded by the outputs of
mea! combination of input levels Tes input levels are often pr ;
ete orgie, Wh ts come from a counter that is being continually pulsed,
te en the decoder input be used as timing or sequencing
“eas g jg willbe activated sequentially, and they can be us
"9 tm devices on or off at specific times.
hh 388 FUNDAMENTALS OF DIGITAL CiRCUTTS
Decoders ae widely used in memory systems of computers, where they TespOnd tothe a
code input from the central processor to activate the memory storage location specife yy
address code,
7.23.8 BCD-to-Seven Segment Decoders
“This type of decoder accepts the BCD code and provides outputs to energize seven segment dia
devices in order to produce a decimal read out. Sometimes, the hex characters A through Fnayfy
produced, Each segment is made up of a material that emits light when current is passed through
"The most commonly used materials include LEDs, incandescent filaments and LCDs. The Lzp,
‘generally provide greater illumination levels but require more power than that by LCDs,
Figure 7.73a shows a seven-segment display consisting of seven light emitting segments, The
segments are designated by letters ag as shown inthe figure. By illuminating various combination,
of segments as shown in Figure 7.73b, the numbers 0-9 can be displayed. Figures 7.73¢ and dstoy
two types of LED display—the common-anode and the common-cathode types.
(@) Leters used o designate the segments
: 7 : 7
¢
eh fey =
é @
6 $ ‘ ¢
2
5
(©) By causing siterent combinatons othe segment ituminat (shown with soi aE).
‘the numerals 0-9 ean be deplayed,
Neo
: a beedie rg
re a ee) reyeyyy
(6) Acommon-anode LED depiay (@)A common-eathade LED spay
Figure 7.73 The seven segment display, COMBINATIONAL LOGIC DESIGN 369
table for such a decoder is shown in
‘Sates tha ine, we assume thatthe disp
split the logic expression for driving segment b is shown in Figure 7:74. Enea 10-15 are