Sir.
M Visvesvaraya Institute of Technology
DEPARTMENT OF ELECTRONICS & TELECOMMUNICATION ENGINEERING
ASSIGNMENT – 1
Academic Year (2022 – 23)
Semester 5th
Subj. Subj. Verilog Date of
Date of 18EC56 06/12/22
28/11/22 Code Name HDL Submission
Assignment
COURSE OUTCOMES:
CO1: Design and Verify the functionality of the digital circuit/system using test bench.
CO2: Write the program more effectively using Verilog task and directives.
SYLLABUS: Module–1, Module–2 (till Compiler Directives)
Q. No. CO PO
QUESTIONS
1. Explain a typical design flow for designing VLSI IC circuit
CO1 1, 2
using the block diagram.
2. Explain top down design methodology and bottom up design
CO1 1, 2
methodology.
3. Explain different levels of abstraction used for programming in
CO1 1, 2
verilog.
4. Explain the trends in Hardware Description Languages (HDLs). CO1 1, 2
5. What do you mean by Instantiation and Instances? Write a
verilog code for 4bit ripple carry counter to show instantiation CO1 1, 2
and instances.
6. Explain the following verilog data types with an example: (i)
CO2 1, 2, 3
Nets (ii) Registers (iii) Integers (iv) Parameters (v) Arrays.
7. Declare the following variables in verilog: (i) An 8bit vector net
called a_in (ii) An integer called count (iii) A memory MEM
CO2 1, 2, 3
containing 256 words of 64 bits each (iv) A parameter
cache_size equal to 512.
8. A 4-bit parallel shift register has I/O pins as shown in the figure below.
Write the module definition for this module shift_reg.
CO2 1, 2, 3
