COMPARISON AND ANALYSIS OF DELAY ELEMENTS

Nihur R. Mahupatra: Alwin Tureent, and Srirum V. Gurimellut

University at Buffalo -The State University of New York

Buffalo, NY 14260. USA

ABSTRACT charge or discharge a load Capacitance CLat its output through the
equivalent resistance Re, of the two transistors connected in paral-
This paper comprehensively reviews ten different delay element ar-
lel. That is. K,,(t) = (1 - eC*/ReqCL)VDD, so {hat propagation
chitectures for use in CMOS VLSI design. They can be categorized
delay (V,,t(t,) = VDD/Z) is given by (21:
into three separate families: transmission gate based, cascaded in-
verter based. and voltage-controlled based. Six of these delay ele-
ments are already in use and we propose four new ones. We com-
pare these delay elements, both analytically and using simulations,
in terms of four important parameters: delay, signal integrity, power
consumption. and area, and find that they have widely varying char- Here VT,, and V T ~ denote NMOS and PMOS transistor threshold
acteristics. The results.presented in this paper, expressed as parame- voltages, respectively, and k, and k, denote gain factors (K ratio
ter ranges, will enable a designer to select the most appropriate delay of width and length of the channel between source and drain (F))
element that meets delay, signal integrity, power consumption, and of the two transistors. For a given fan-out, delay may be increased
area specifications. compared to that of a minimum-size transmission gate by increasing
L of the transistors, which linearly increases Req.There is very lit-
1. INTRODUCTION tle power consumption in a transmission gate since it is not driven
A delay element is a circuit that produces an output waveform simi- by any of the supply rails. Most of the power consumed is that for
lar to its input waveform, only delayed by a certain amount of time. charging and discharging the output load capacitance from the in-
In this paper, we consider six delay elements that are currently in put. Since the transmission gate is not driven by any of the supply
use and propose four new ones and compare all of them in terms of rails, the output load capacitance is charged or discharged by the
four relevant parameters: delay, signal integrity. power consumption, input. This causes its signal integrity to be not very good. Since
and area. These delay elements can be categorized into three fami- Vout ( t ) = (1- e-*lReqcL)VD~, signal integrity, which is the time
lies: transmission gate based (Fig.l(a), (b)). cascaded inverter based for the output to transition between 10% and 90% of V D D ,is given
(Fig.l(c). (d), (e), (0). and voltage-controlled based 131 (Fig.l(g), by: t,lf = In(S)R,,C'. The transmission gate requires relatively
(h), (i), U)). Based on these architectures, we propose four new delay less area with just two transistors, although it does require two com-
elements, two of which are based on the voltage-controlled princi- plementary control signals.
ple, and two that utilize a Schmitt trigger in the output stage. These
new architectures are compared with the other previously proposed 2.2. Transmission Gate Cascaded With Schmitt Trigger
delay elements. Each delay element has its own advantages and dis- One of the disadvantages of using a transmission gate as a delay
advantages. Comparison results presented in this paper should prove element is that the signal integrity of its output waveform is poor.
useful to designers in selecting the best delay element for their ap- We can overcome this deficiency by placing a Schmitt trigger at
plication. In the following sections, we describe the functionality the output of the transmission gate. A Schmitt trigger (Fig. l(b))
of the various delay elements, analyze their four parameters, and is a circuit that generates a fast, clean output signal from a noisy or
present simulation results. slowly varying input signal. This is not only useful for noise sup-
2. TRANSMISSION GATE BASED pression, but also the steep output minimizes power consumption
2.1. Transmission Gate due to direct-path currents. If the output of the Schmitt trigger is
A transmission gate is a bidirectional switch consisting of a parallel initially low, then the output will go high only when the rising input
connection of an NMOS and a PMOS transistor that are controlled signal reaches VM+.Similarly, if the output is high, then it will go
by complementaq control signals as shown in Fig. ](a). The NMOS low only when the falling input signal reaches VM-.The delay of
this element can be changed in two ways. The first is by altering the
and PMOS transistors pass a logic 0 and I , respectively. The de-
lay of a transmission gate is effectively determined by the time to ratio of the transistors of the transmission gate. Decreasing the
ratio will increase the gate's delay. The second is by changing the
*This research was supported by stanup funds fmm the University at switching thresholds of the Schmitt trigger. If we raise the switch-
Buffalo and US National Science Foundation Grant # 0102830. A prelimi- ing threshold that is active during a rising input transition, VM+,the
nary version of this paper appears in Pmc. IEEE Computer Society Annual
rise delay will increase. Lowering the switching threshold VM- that
Workhop on V U / (WU/ 2OW)J. pp. 81-86. Orlando, FL, Apr. 27-28,
2000. N.R. Mahapaua is with the Dept. of Comp. Sc. & Eng.; e-mail: is active during a falling input transition will have the same effect
[email protected]. on the fall delay. Due to the use of positive feedback, the signal in-
t Dept. of Electncd Eng.: e-mail: [email protected]. tegrity of this delay element is very good. A particularly desirable
'Andiamo Systems. Inc., San lose. CA 95134, USA; e-mail: characteristic is that the signal integrity remains virtually unchanged
[email protected]. as the delay value increases. The power consumed by a transmission

0-7803-7523-81021$17.0002002 IEEE
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 where t , L x and t , x L denote propagation delays for low to high and
high to low output transitions, respectively. The above expression is
valid when the input signal makes an abNpt transition from VDDto
Vss or vice versa. The effect of a nonzero input rise timet, > tpHL
on propagation delay t P x L is captured by the following equation [21:

(4)

A similar expression is valid for tpLH. An approximate expression

for signal integrity is computed using the average (dis)charging cur-
rent expression in Eq. 2 and finding out the time to charge from
to O . ~ V D D or
O . l V D ~ , vice versa, as follows:

The signal integrity depends upon the same factors that the propaga-
tion delay depends upon. Since the PMOS and NMOS transistors are
never on simultaneously in steady-state operation, the static power
consumption in an inverter occurs only due to leakage currents and is
generally small: PSt.,,= I h k V D D . Most of the power is consumed
during switching. This dynamic power consists of two components.
The major component is due to charging and discharging of the load
capacitance. During a low-to-high transition. a certain amount of
power is consumed, half of which is dissipated in the PMOS tran-
sistor and the other half stored on the load capacitance. During a
high-to-low transition, the stored energy in the load capacitance is
discharged and dissipated in the NMOS transistor. If an inverter
switches on and off f times per second, this capacitive power is
given by [Z]: PCap = C L V 2 , f . Hence this power depends quadrat-
Figure I: (a) Transmission gate, (b) T-gate with Schmitt trigger, ically upon VDDand linearly upon C L and f. The second com-
(c) Cascaded inverter, (d) m-transistor cascaded inverters, (e) Cur- ponent of dynamic power arises due to nonzero rise and fall times
rent starved cascaded inverters, (0 Staged cascaded inverters, (9) of the input signal, which results in both NMOS and PMOS tran-
n-voltage controlled, (h) p-voltage controlled. (i) np-voltage con- sistors being on (a short circuit) briefly. Let the peak current flow
trolled. cj) np-voltage controlled with Schmitt trigger. durine- this period be I n e a k , then the short-circuit power consumv-
. t +i
tion is (21: Pae = A & V D D I , , , , f . This means that short-circuit
power consumption depends linearly upon the input signal integrity
gate was discussed in the previous section. Since the structure of and the supply voltage. 1, has heen shown that in a chain of inverters
a Schmitt trigger is very similar to that of a cascaded i~verter,the with equal input rise and fall times, the short-circuit dissipation is
power consumption analysis is similar. This delay element requires less than 20% ofthe dynamic power dissipation [*I, ~h~ total power
eight transistors. is therefore given by [Z]:
3. CASCADED INVERTER BASED
3.1. Cascaded Inverters P*d =
A pair of cascaded inverters can also function as a simple delay ele- = IleakVDD f cL.vsDf+ + v D D I p e a k f . (6)
mint that delays the input signal by an amount equal toihe combined
Of this, the power consumed during capacitive charging (Pcop) is
propagation delays of the two inverters (see Fig. l(c)). The propaga-
tion delay of an inverter depends upon the time taken to (dis)charge the dominant one, followed by Pa=,and then Pstot. A generalized
the load capacitance. An exact computation of this delay is nontriv- cascaded inverter requires 4m transistors.
ial because of the nonlinear dependence of the (dislcharging current
3.2. rn-Transistor Cascaded Inverters
on the output voltage. An approximate expression is derived by us-
ing an average value of this current equal to the saturation current of This delay element is a modified version of the simple cascaded in-
the PMOS (NMOS) transistor given by 121: verter configuration. It has m series-connected NMOS transistors
and m series-connected PMOS transistors in its pull-down and pull-
up networks, respectively. The gates to all of these transistors are
connected to the input. Increasing the fan-in (m) not only increases
the effective (dis)charging resistance, but also increases the gate and
The above holds since V D D>> IVT~I, V T , . Based on this I., value, diffusion capacitances. which contribute to more capacitance at the
the propagation delay is as follows [Z]: input and output. respectively. Therefore, the propagation delay
(proportional to R and C) depends quadratically on fan-in or m [Z].
Further, it increases the delay of the fan-in gate by presenting i t a
larger load capacitance. Consequently, more delay per unit area may

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be obtained by using a generalized inverter with m series-connected inverter controlled by a global control voltage V,,, varying which
transistors than by using a chain of m simple inverters. The increased changes the delay of this delay element. Note that this delay element
fan-in (m) has a similar effect on the signal integrity as it does on may he generalized in a manner similar lo the m-transistor cascaded
the delay. That is, the increased effective (dis)charging resistance inverter case (Sec. 3.2) by having m-series connected NMOS and
and increased gate and diffusion capacitances lead to a larger sig- PMOS transistors per inverter in addition to the controlled NMOS
nal integrity value. The increases are roughly the same for both the transistor. There are three ways to change the delay of this ele-
rise (low-to-high) and fall (high-to-low) times. This delay element ment. First is by changing the sizes of the transistors and the sec-
consumes slightly more power than the cascaded inverter element. ond by changing the fan-in m-similar to the cascaded inverter case
Since there are more transistors in the pull-up and pull-down net- (Sec. 3.2). The third way is to change the control voltage V,. Note
works, more energy will he dissipated in these additional devices. that during any transition of the input V,,, one of the two inverters
An m-transistor cascaded inverter requires 4m transistors. of the delay element will be discharging through a controlled tran-
sistor, and the other charging normally through a PMOS transistor.
3.3. Current Starved Cascaded Inverters Therefore, the overall delay is the sum of the normal inverter de-
A larger fan-in and a clever configuration of control transistors is lay (see Eq. 3) and a controlled inverter delay. The latter delay is
utilized in the delay element proposed in [I]. The basic architec- inversely proportional to the discharging drain current ID through
ture is similar to the cascaded inverters. However, two additional the control transistor. Approximating the average discharging cur-
PMOS and NMOS devices are added to extend the delay value. The rent by the saturation current of the controlled NMOS transistor
gate voltage V, is applied lo the additional NMOS devices, and they (IO" = $(VGS - V,")Z 0 +v& = %V,), the propagation
control the maximum current available lo the inverter. The gates of delay of this delay element becomes:
the additional PMOS devices are connected to the source of the first
additional NMOS device. The delay that can he achieved with this
delay element is considerably greater than that achieved with the cas-
caded inverter or m-transistor cascaded inverter configurations. This
is primarily because of its control transistors that limit the amount This shows that t , is inversely proportional to V,. In 131, the value
of current that can (dis)charge the load capacitor CL.The extended of the delay assumed is that corresponding to V, = 3.5V,and then
(dis)charging time is what gives this element an impressive value of V,,is varied after fabrication to fine tune the delay. A delay variation
delay. One of the drawbacks of this circuit is that its signal integrity of up lo 30% was obtained by changing V.,in I .2 p m CMOS tech-
value is very poor, due to the same property that makes its delay nology in [3]. The signal integrity is computed in a manner similar
very good: the current-limiting capability of its control transistors. to that for the cascaded inverter case. The only difference is that the
An extended (dislcharging time on the load capacitor means that the rise time is similar to the cascaded inverter. but the fall time depends
output signal slopes will be much less steep. Due to their similar upon V,.Therefore:
architectures, the current starved cascaded inverter has a similar rate
t,,, = 0.9CL 1 VDD
of power consumption as the cascaded inverter. The extra fan-in of
m)
~

the current-limiting transistors will increase this parameter slightly. (k,VDD +

A current starved cascaded inverter requires eight transistors. The signal integrity depends upon the same factors that the propaga-
tion delay depends upon. It will be worse than that for the cascaded
3.4. Staged Cascaded Inverters
inverter case because of the additional resistance and diffusion ca-
This delay element consists of an arrangement of three inverters, in pacitance of the controlled transistors. The power consumption is
two stages. The first stage consists of two inverters. where each in- computed similar to the cascaded inverter case. It will he slightly
verter output controls a transistor on the second stage's inverter. The more because of the additional diffusion capacitance of the con-
key intuition in this design is that the two large transistors in the trolled transistors that contributes to the total load capacitance. A
output stage are never on at the same time, thus eliminating short +
generalized voltage-controlled delay element requires 4m 2 tran-
circuit power dissipation. The delay is obtained by dimensioning the sistors, two more transistors compared to cascaded inverters.
resistances of the two inverters in the first stage. The transition that
controls the output edge is always produced by the transistor in se- 4.2. p-Voltage Controlled
ries with the resistance and it can be slowed down using large values The voltage-controlled technique can be applied to a delay element
of R I and R2. The penalty is in less sharp output edges (although the in several different manners. This delay element uses a cascaded in-
gain of the output inverter mitigates this effect), and, when both out- verter pair with an additional series-connected PMOS transistor in
put transistors are off, the input line is susceptible to cross-talk. Both the pull-up network of each inverter. The gates of these additional
of these effects are greatly reduced by adding another output stage
transistors are controlled by a control voltage V,,and this value can
(i.e., two inverters). The power consumption analysis for this delay be varied to control the amount of delay. Changing the delay of this
element is very similar to one for the cascaded inverters. However,
element can he accomplished by altering the sizes of the transistors,
this delay element architecture virtually eliminates the component or increasing the fan-in m of the gate (m-transistor cascaded inverter
due to short circuit power consumption. Therefore, it only consumes
case, Sec. 3.2). Another way is to change the gate voltage of the
static and capacitive power consumption. A generalized staged cas-
control transistor, V,. In this case, the delay can be analyzed in a
caded inverter requires 6m transistors. manner similar to the n-voltage controlled element. During an in-
4. VOLTAGE-CONTROLLED BASED put transition of V,,,, one inverter will charge its load capacitance
4.1. n-Voltage Controlled through a controlled PMOS transistor, and the other will discharge
An n-voltage-controlled delay element, proposed in [ 3 ] , is shown regularly through an NMOS transistor. The overall delay is the sum
in Fig. I(g). It consists of a cascaded inverter pair with an addi- of a controlled inverter delay and a normal invener delay. The for-
tional series-connected NMOS transistor in the pull-down of each mer delay is inversely proportional to the charging drain current I D

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 thniugh ths m m o l transistor Approximating thc 3!erage .'hJrgtng producing a greater delay. The final way is to change the switching
iiiiicnt h! thr. rxurdm11 ciirrcnt oi ]he c~introllsJPMOS trJnrl*tUr. thresholds of the Schmitt trigger, and this method is discussed in
more detail in Sec. 2.2. This delay element produces the best sig-
nal integrity characteristic out of all the delay elements proposed in
this chapter. As the delay is altered by changing the f ratios of
The propagation delay becomes: the np-voltage controlled gate, the signal integrity remains virtually
unchanged. The main drawback of this circuit is that it consumes a
great deal of power. much more than the other delay elements. The
power analysis is similar to that of a cascaded inverter. The addition
of a Schmitt trigger means that this delay element requires 4m + 10
transistors.
Hence, t p is proportional to Vpl. The signal integrity analysis is
very similar to the cascaded inverter delay element. In the p-voltage 5. COMPARISONS
controlled element. the rise time depends on the value of V,, and the Experiments were performed for these delay elements using the Spec-
fall time is similar to that of a regular inverter. tres tool from Cadence in 0.18pm technology. The parameters that
were taken into account include the delay, the signal integrity. the
power dissipation, and the area. We altered the lengths of the de-
lay elements' appropriate transistors, while keeping their widths at
a constant minimum value. Then, we extracted the necessary pa-
The power consumption is computed similar to the cascaded inverter rameters. We began with L = 0.2pm, and increased the transistor
case. It will be slightly more because of the additional diffusion length in steps of 0.2pm to L = 1.2pm. A standard cell inverter
capacitance of the controlled transistors that contributes to the total was used as the fan-in and fan-out for each delay element. Due to
load capacitance. Similar to the n-voltage controlled delay element, space constraints, we summarize only the main results here. We
this one requires 4m + 2 transistors. found that overall, the cascaded inverters and n-voltage controlled
elements gave a reasonable amount of delay without large power
4.3. np-Voltage Controlled costs. The np-voltage controlled with Schmitt trigger gave the best
This delay element is a combination of the n-voltage controlled and delay and signal integrity results, but it consumed the most power.
p-voltage controlled configurations. It employs control transistors in The transmission gate based elements proved to be unreliable.
both the pull-up and pull-down networks. The delay for this element 6. CONCLUSIONS
can be altered by using the methods outlined in the n-voltage con-
trolled and p-voltage controlled sections. One advantage is that the Several principles can be identified in the design of delay elements.
delay can be altered by changing V, or V,. The delay analysis is sim- of the most reliable ways to increase a circuit's delay i s to increase
ilar to both n-voltage controlled and p-voltage controlled elements. the length L of one or more of its transistors. Another is to create a
The only difference is that all (dis)charging takes place through a network of transistors to be placed in series with then or p network
controlled transistor. The propagation delay of this element is: and one of the supply lines. This strategy was successfully utilized
in the m-transistor cascaded inverters. The use of a series transistor
whose gate voltage can be varied to regulate the current has been
shown to create delays. Also. adding a Schmitt trigger to the out-
put of an existing delay element can improve its delay and signal
integrity. Overall, the cascaded inverters and n-voltage controlled
Note that in this case, tp is proportional to both Vpa and Vna. The
elements gave a reasonable amount of delay without large power
presence of control transistors in both pull-up and pull-down net-
works influence the rise and fall components of the signal integrity. costs. The np-voltage controlled with Schmitt trigger gave the best
delay and signal integrity results. but it consumed the most power.
That is, the rise time depends on V, and the fall time depends on Vn.
The transmission gate based elements proved to be unreliable.
7. REFERENCES
It1 G. Kim, M.-K. Kim, 8:s. Chang. and W. Kim. "A low-voltage, low~power
CMOS delay element,'' IEEE Journul ,>fSolid Sllrlc Cinrurrr. Vol. 31. No. 7.
The power consumption is computed similar to the cascaded inverter pp. 966-971. Jul. 1996.
case. It will be slightly more because of the additional diffusion 121 J.M. Rabaey, '"Digiral inregrated circuils: A design perspective," Prmics-Hall
capacitance of the controlled transistors that contributes to the total Book Cnmplmy. 151 edition. ISBN Ul-13-178609-1. Upper Saddle River. NI.
1996.
load capacitance, This delay element requires 4m + 4 transistors.
[ 3 ] Yuk-Wah Pang. Wing-yun Sit. Chiu-sing Choy. Cheong-fat Chan and Wr-kuen
Cham. "An asynchronous cell l i h a r y for self-timed system designs:' IElCE
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for forward and inverse discrete uosinc tranriorm."Pmcrrilrnglr,fSPIE The
to its output. As described in Sec. 2.2, a Schmitt trigger can produce
~

lnivrnulinnul Sncirryfor O p t i d Eagineerittg, Vol. 2669. pp. 59-6s. 1996

a fast, clean signal from a noisy, slowly varying input. A special I51 N.R. Mahaparm. S.V. Garimellu. and A. Tareen, "Efficient techniques hsed on
advantage of this delay element is that its delay can be changed in gate triggering for designing static CMOS ICEwith very low glitch power dir-
four ways, The first way involves altering the ratios of the tran- ripatmn:' Proc. 20W IEEE Inrrmnrionol Symposium on Circuirr and Sysum,
Vol. 11, pp. S37-540,Geneva. Switzerland, May 28-31. ZWO.
sistors in the np-voltage controlled gate. Another way is to change
the gate voltages applied to the control transistors in the pull-up and
pull-down networks. Also, the fan-in m of the gate can be increased,

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