Ethernet Design Example

Components User Guide

Updated for Intel® Quartus® Prime Design Suite: 22.3

Online Version 683044

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 Contents

Contents

1. Time-of-day Clock........................................................................................................... 3
1.1. Release Information...............................................................................................3
1.1.1. Pulse Per Second Device Speed Grade Support.............................................. 4
1.2. Resource Utilization............................................................................................... 4
1.3. Configuring the TOD Clock...................................................................................... 5
1.4. Using the TOD Clock.............................................................................................. 7
1.4.1. Adjusting TOD Drift....................................................................................7
1.4.2. Adjusting Offset, Jitter, and Wander............................................................. 8
1.4.3. Correcting TOD Offset...............................................................................10
1.4.4. IOPLL and TOD Setup for Pulse Per Second (Advanced Accuracy Mode)........... 10
1.5. Interface Signals..................................................................................................15
1.5.1. Avalon Memory-Mapped Signals................................................................. 15
1.5.2. Time-of-day Signals................................................................................. 16
1.5.3. Pulse-Per-Second Signals ......................................................................... 16
1.5.4. Clocking Requirements ............................................................................ 17
1.6. Configuration Registers.........................................................................................17
2. Time-of-day Synchronizer............................................................................................. 20
2.1. Release Information............................................................................................. 20
2.2. Resource Utilization..............................................................................................21
2.3. Configuring the TOD Synchronizer..........................................................................21
2.4. Using the TOD Synchronizer.................................................................................. 23
2.4.1. Sampling Clock Frequency........................................................................ 24
2.5. Interface Signals..................................................................................................27
3. Packet Classifier........................................................................................................... 29
3.1. Release Information............................................................................................. 29
3.2. Resource Utilization..............................................................................................30
3.3. Configuring the Packet Classifier............................................................................ 30
3.4. Interface Signals..................................................................................................31
3.4.1. Clock and Reset Signals............................................................................ 31
3.4.2. Avalon Streaming Interface Signals............................................................ 31
3.4.3. Control Signals........................................................................................ 32
4. Ethernet Design Example Components User Guide Archives......................................... 35

5. Document Revision History for the Ethernet Design Example Components User
Guide....................................................................................................................... 36

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1. Time-of-day Clock
The Time-of-day (TOD) Clock streams 96-bit and 64-bit time-of-day to one or more
timestamping units in an IEEE 1588v2 solution. The time-of-day consist of the
following fields.
Field 96-bit Timestamp Format 64-bit Timestamp Format

Second 48 bits —

Nanosecond 32 bits 48 bits

Fractional nanosecond 16 bits 16 bits

This component supports coarse and fine adjustments, and period correction. It also
supports configurable period adjustment and offset adjustment.

You can instantiate the TOD clock through the Ethernet IEEE 1588 Time of Day
Clock Intel® FPGA IP in the Intel Quartus® Prime software.

1.1. Release Information

Intel FPGA IP versions match the Intel Quartus Prime Design Suite software versions
until v19.1. Starting in Intel Quartus Prime Design Suite software version 19.2, Intel
FPGA IP has a new versioning scheme.

The Intel FPGA IP version (X.Y.Z) number can change with each Intel Quartus Prime
software version. A change in:

• X indicates a major revision of the IP. If you update the Intel Quartus Prime
software, you must regenerate the IP.
• Y indicates the IP includes new features. Regenerate your IP to include these new
features.
• Z indicates the IP includes minor changes. Regenerate your IP to include these
changes.

Table 1. Ethernet IEEE 1588 Time of Day Clock Intel FPGA IP Release Information
Item Description

IP Version 20.0.0

Intel Quartus Prime Version 22.3

Release Date 2022.09.26

Supported Devices • Arria® V GX/GT/GZ/SX/ST

• Intel Arria 10 GX/GT/SX
• Cyclone® V SE/SX/ST
• Intel MAX® 10
continued...

Intel Corporation. All rights reserved. Intel, the Intel logo, and other Intel marks are trademarks of Intel
Corporation or its subsidiaries. Intel warrants performance of its FPGA and semiconductor products to current
specifications in accordance with Intel's standard warranty, but reserves the right to make changes to any ISO
products and services at any time without notice. Intel assumes no responsibility or liability arising out of the 9001:2015
application or use of any information, product, or service described herein except as expressly agreed to in Registered
writing by Intel. Intel customers are advised to obtain the latest version of device specifications before relying
on any published information and before placing orders for products or services.
*Other names and brands may be claimed as the property of others.
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Item Description

• Stratix® V GX/GT
• Intel Stratix 10
• Intel Cyclone 10 GX
• Intel Agilex® 7

Related Information
Ethernet Design Example Components Release Notes
Describes changes to the IP in a particular release.

1.1.1. Pulse Per Second Device Speed Grade Support

Starting Intel Quartus Prime version 21.3, Time-of-day clock also supports Pulse Per
Second (PPS) generation for the following device families and speed grades:

Table 2. Supported Device Speed Grades

Device Family Supported Speed Grades

Intel Stratix 10 Core speed grade: -1, -2 and -3

Intel Agilex 7 Core speed grade: -1, -2 and -3

1.2. Resource Utilization

Table 3. Estimated Resource Utilization in Stratix V Devices (5SGXEA7H3F35C3)
Configuration ALMs Combinational Logic Memory
ALUTs Registers (M20K Blocks)

PERIOD_CLOCK_FREQUENCY = 0 522 727 1038 0

OFFSET_JITTER_WANDER_EN = 0

PERIOD_CLOCK_FREQUENCY = 0 1722 2729 2586 0

OFFSET_JITTER_WANDER_EN = 1

PERIOD_CLOCK_FREQUENCY = 1 561 731 1230 0

OFFSET_JITTER_WANDER_EN = 0

Table 4. Estimated Resource Utilization in Intel Arria 10 Devices

(10AX115H1F34I1SG)
Configuration ALMs Combinational Logic Memory
ALUTs Registers (M20K Blocks)

PERIOD_CLOCK_FREQUENCY = 0 512 752 1059 0

OFFSET_JITTER_WANDER_EN = 0

PERIOD_CLOCK_FREQUENCY = 0 1618 2569 2648 0

OFFSET_JITTER_WANDER_EN = 1

PERIOD_CLOCK_FREQUENCY = 1 581 814 1251 0

OFFSET_JITTER_WANDER_EN = 0

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Table 5. Estimated Resource Utilization in Intel Stratix 10 Devices

(1SG280HN2F43E1VG )
Configuration ALMs Combinational Logic Registers Memory
ALUTs (M20K Blocks)

PERIOD_CLOCK_FREQUENCY = 0 626 861 1309 0

OFFSET_JITTER_WANDER_EN = 0
ENABLE PPS = 0

PERIOD_CLOCK_FREQUENCY = 0 1756 2698 2589 0

OFFSET_JITTER_WANDER_EN = 1
ENABLE PPS = 0

PERIOD_CLOCK_FREQUENCY = 1 908 919 2560 0

OFFSET_JITTER_WANDER_EN = 0
ENABLE PPS = 0

PERIOD_CLOCK_FREQUENCY = 0 621 863 1311 0

OFFSET_JITTER_WANDER_EN = 0
ENABLE_PPS = 1
PPS_ADVANCE = 0

PERIOD_CLOCK_FREQUENCY = 0 1086 1706 2020 1

OFFSET_JITTER_WANDER_EN = 0
ENABLE_PPS = 1
PPS_ADVANCE = 1

Table 6. Estimated Resource Utilization in Intel Agilex 7 Devices (AGFB014R24A2E2V)

Configuration ALMs Combinational Logic Registers Memory
ALUTs (M20K Blocks)

PERIOD_CLOCK_FREQUENCY = 0 575 812 1040 0

OFFSET_JITTER_WANDER_EN = 0
ENABLE PPS = 0

PERIOD_CLOCK_FREQUENCY = 0 1706 2702 2589 0

OFFSET_JITTER_WANDER_EN = 1
ENABLE PPS = 0

PERIOD_CLOCK_FREQUENCY = 1 706 868 1270 0

OFFSET_JITTER_WANDER_EN = 0
ENABLE PPS = 0

PERIOD_CLOCK_FREQUENCY = 0 576 814 1081 0

OFFSET_JITTER_WANDER_EN = 0
ENABLE_PPS = 1
PPS_ADVANCE = 0

PERIOD_CLOCK_FREQUENCY = 0 1018 1660 1817 1

OFFSET_JITTER_WANDER_EN = 0
ENABLE_PPS = 1
PPS_ADVANCE = 1

1.3. Configuring the TOD Clock

In the Intel Quartus Prime software, instantiate the TOD clock by selecting Ethernet
IEEE 1588 Time of Day Clock Intel FPGA IP from the IP Catalog or Platform
Designer (Interface Protocols > Ethernet > Reference Design
Components). Specify the following parameters.

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Table 7. TOD Clock Parameters Description

Name Value Default Value Description

Enable high clock frequency On or Off On Turn off this parameter if the MAC connected to
mode the TOD clock requires low period clock
(PERIOD_CLOCK_FREQUENCY) frequency, such as the Triple-speed Ethernet or
legacy 10G Ethernet MAC. For this setting, the
nanosecond field in the Period and
AdjustPeriod registers is 9 bits wide.
Turn on this parameter if the MAC connected to
the TOD clock requires high period clock
frequency, such as Low-latency 10G Ethernet,
25G Ethernet, or 40G/100G Ethernet MAC. For
this setting, the nanosecond field in the
Period and AdjustPeriod registers is 4 bits
wide.

Enable offset, jitter, and On or Off Off Turn on this parameter to enable the offset,
wander supports jitter, and wander timers. This parameter is
(OFFSET_JITTER_WANDER_E available only when high clock frequency mode
N) is disabled (PERIOD_CLOCK_FREQUENCY= 0).

DEFAULT_NSEC_PERIOD 0–n 0x0006 The reset value of the nanosecond field in the
Period register.
n is 0xF if the nanosecond field is 4 bits wide.
Otherwise, n is 0x1FF.

DEFAULT_FNSEC_PERIOD 0 – 0xFFFF 0x6666 The reset value of the fractional nanosecond

field in the Period register.

DEFAULT_NSEC_ADJPERIOD 0–n 0x0006 The reset value of the nanosecond field in the
AdjustPeriod register.
n is 0xF if the nanosecond field is 4 bits wide.
Otherwise, n is 0x1FF.

DEFAULT_FNSEC_ADJPERIOD 0 – 0xFFFF 0x6666 The reset value of the fractional nanosecond

field in the AdjustPeriod register.

Table 8. Pulse Per Second Parameter Description

Pulse per second parameters are only supported in Intel Stratix 10 and Intel Agilex 7 devices with specific core
speed grades. For more information, refer to Pulse Per Second Device Speed Grade Support on page 4.

Name Value Default Value Description

Enable pulse per second On or Off Off Turn on this parameter to enable pulse per
interface second (PPS) feature of TOD.
IP needs to be regenerated if you modify this
parameter.

Accuracy mode Basic or Advanced Basic Basic: Generates pps pulse with <TOD period>
accuracy.
Advanced: Generates pps pulse with 2 ns
accuracy.
Advanced accuracy mode requires additional
IOPLL instantiation with specific clock settings
and with Enable access to dynamic phase
shift ports selected. See Section IOPLL and
TOD Setup for Pulse Per Second (Advanced
Accuracy Mode) on page 10 for the guidelines.
IP needs to be regenerated if you modify this
parameter.

Pulse width 2 - 125,000 2 Defines the number of clock cycles the pps
pulse will stay asserted, based on
period_clk.
continued...

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Name Value Default Value Description

For example, when Pulse width is set to 2, the

PPS pulse width equals to 2 clock cycles of
period_clk.

PLL scan clock frequency 50 MHz - 100 MHz 100 MHz This parameter is only available if Advanced
Accuracy Mode is enabled.
The frequency of scan clock feeds to the
corresponding IOPLL.
Time of Day PPS feature currently supports
only scan clock frequency of 50 MHz to 100
MHz regardless of the IOPLL support range.
Round down the clock frequency and enter only
the integer value. For example, enter 81 MHz
for 81.25 MHz scan clock frequency.

PLL unit phase shift 1/8 of IOPLL VCO 100 ps This parameter is only available if Advanced
clock period Accuracy Mode is enabled.
Minimum phase shift in picosecond is
achievable by corresponding IOPLL in single
phase shift cycle. The value equals to 1/8 of
IOPLL VCO clock period. Round down the clock
frequency by entering only the integer value.
For example:
VCO clock frequency = 1250 MHz
VCO clock period = 800 ps
PLL unit phase shift = 1/8 x 800 = 100ps

1.4. Using the TOD Clock

Follow these guidelines when using the TOD clock:
• 96-bit timestamp format—load the time-of-day using the
time_of_day_96b_load_data[] bus or the SecondsH, SecondsL, and
NanoSec registers. The bus value always takes precedence over the register
values. When loading the time-of-day through the
time_of_day_96b_load_data[] bus, the output is available in the
time_of_day_96[] bus after one clock cycle. Hence, Intel recommends that you
add one clock cycle to the value of the time_of_day_96b_load_data[] bus to
accommodate the latency.
• 64-bit timestamp format—load the time-of-day using the
time_of_day_64b_load_data[] bus. The output is available in the
time_of_day_64[] bus after one clock cycle. Hence, Intel recommends that you
add one clock cycle to the value of the incoming time-of-day to accommodate the
latency.
• The TOD clock does not synchronize the 96-bit and 64-bit timestamp format.
• The drift, jitter, and wander timers restart each time a new time-of-day is loaded,
either through the signal or configuration registers.

1.4.1. Adjusting TOD Drift

You can use the DriftAdjust and DriftAdjustRate registers to correct drifts in
the TOD clock due to insufficient binary representation of the 16-bit fractional
nanosecond field in the Period register.

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For example, the Period register is set to 6.4 ns for a 10G Ethernet application. The
hexadecimal representation of this value is 0x6 ns and 0x6666.4 fns.
• Fractional nanosecond field is 16 bits wide: 0.4 fns = 0.4 * 216 = 26214.4 in
decimal.
• Converting to hexadecimal: 26214 + 0.4 = 0x6666 + 0x0000.4 = 0x6666.4 fns.

The fractional nanosecond value, 0x0000.4, cannot be represented in 16 bits thus

causing the time of day to drift from the actual time by 0x0002 fns every 5 clock
cycles. In other words, the time of day drifts 953.6 ns every 1 second. To correct this
situation, configure the registers as follow:
• DriftAdjust = 0x02, which sets the nanosecond field to 0x0 and the fractional
nanosecond field to 0x2.
• DriftAdjustRate = 0x5.

1.4.2. Adjusting Offset, Jitter, and Wander

The TOD clock supports several types of adjustments:

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• Offset—use the OffsetNS and OffsetFNS registers to adjust large offsets in

assisting faster system convergence. The offset can be positive or negative. The
maximum correction is (109 - 50) ns.
• Jitter—use the JitterTimer and JitterAdjust registers to achieve small time
scales (milliseconds or microseconds) frequency correction.
The jitter adjustment can either be a positive or negative adjustment per unit
time. This helps achieve better frequency corrections. For very low values of the
jitter, such as 1 ns correction for every second, the timer must be larger and the
adjustment value must be smaller.
For example, to achieve 1 ns correction every second in a clock domain of 3.2 ns
period, configure the registers as follow:
— JitterTimer = 0x12A05F20, which is the hexadecimal value of
(1000000000/3.2).
— JitterAdjust = 0x10000, which sets the nanosecond field to 0x1 and the
fractional nanosecond field to 0x0.
• Wander—use the WanderTimeLSB, WanderTimeMSB, and WanderAdjust
registers to achieve large time scale correction.
The wander adjustment can either be a positive or negative adjustment per unit
time. Wander adjustments are typically on larger time scales such as per hour. For
very low values of the wander such as 1 ns per 24 hours, the timer must be larger
and the adjustment value must be smaller.
For example, to achieve 1 ns positive correction every 24 hours
(86,400,000,000,000 ns) in a clock domain of 3.2 ns period, configure the
registers as follow:
— WanderAdjust[31:16] = 0x0001 (1 nanosecond)
— WanderAdjust[15:0] = 0x0000 (0 fractional nanosecond)
— WanderTimerLSB[30] = 0x0 (positive direction)
— WanderTimerLSB[29:0] = 0x2D68_B000 (lower 30-bit of 86400000000000
ns/3.2 ns)
— WanderTimerMSB[15:0] = 0x6239 (upper 16-bit of 86400000000000 ns/3.2
ns)
For example, to achieve 1 ns negative correction every 24 hours
(86,400,000,000,000 ns) in a clock domain of 3.2 ns period, configure the
registers as follow:
— WanderAdjust[31:16] = 0x0001 (1 nanosecond)
— WanderAdjust[15:0] = 0x0000 (0 fractional nanosecond)
— WanderTimerLSB[30] = 0x1 (negative direction)
— WanderTimerLSB[29:0] = 0x2D68_B000 (lower 30-bit of 86400000000000
ns/3.2 ns)
— WanderTimerMSB[15:0] = 0x6239 (upper 16-bit of 86400000000000 ns/3.2
ns)

Note: The adjustments are available only when PERIOD_CLOCK_FREQUENCY is set to 0.

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1.4.3. Correcting TOD Offset

You can use the AdjustPeriod and AdjustCount registers to correct TOD offset
between master and slave TOD. AdjustPeriod register value is used as effective
period value when AdjustCount register is a non-zero value. Write to these registers
in sequence: AdjustPeriod register, followed by AdjustCount register. Adjustment
happens whenever there is a write to the AdjustCount register.

For example, if the slave TOD is faster than master TOD by 'a' ns, to correct the TOD
offset of 'a' ns by increasing the value of 'a' for a TOD clock running at 125 MHz
(Period register value is 0x8 ns):
• set AdjustPeriod to '8+b' ns
• set AdjustCount to 'c'
where 'a = b * c' is fulfilled.

By setting a = 16 ns, b = 2 ns, and c = 8, the logic produces TOD with effective
period value of 10 ns (slower) in the next 8 clock cycles. After 8 clock cycles, the logic
resumes the normal operation where effective period value = 8 ns.

Similarly, if the slave TOD is slower than master TOD, to correct negative TOD offset,
set AdjustPeriod to '<Period register value> – b'.

1.4.4. IOPLL and TOD Setup for Pulse Per Second (Advanced Accuracy
Mode)
There are two ways to set up IOPLL and TOD to enable advanced accuracy mode for
pulse per second:
• Using IOPLL dynamic phase shift interface.
Note: Some devices do not support this setup.
• Using IOPLL with IOPLL Reconfig IP.

1.4.4.1. IOPLL and TOD Setup using Dynamic Phase Shift Interface

To set up the IOPLL with dynamic phase shift interface and enable pulse per second
(advanced accuracy mode) on a TOD Clock running on 125MHz period clock for Intel
Agilex 7 device, follow these steps:

1. Create an Intel Quartus Prime project with Intel Agilex 7 device selected.
2. From IP Catalog, select IOPLL Intel FPGA IP.
3. In IP Parameter Editor, apply the following settings and generate the IOPLL
instance:
a. Use the same clock source as TOD period_clk to drive IOPLL reference clock.
Thus, set Reference Clock Frequency to 125 MHz.
b. For Output Clocks section, set Number of Clocks to 2.

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i. Outclk0: Generate pps_sampling_clk, set Desired Frequency to

85.33MHz (pps_sampling_clk = period_clk *256/375). Sampling
clock factor of 256/375 is suitable for all supported period_clk
frequencies.
ii. Outclk1: Second clock port of the IOPLL must be allocated for TOD
iopll_phased_clk. Set Desired Frequency to the same as TOD
period_clk frequency (125MHz).
c. In the same Output Clocks section, enable Specify VCO frequency and set
Desired VCO Frequency to 1375 MHz.
• Intel recommends you to specify the VCO frequency value as this value
will be used to determine PLL unit phase shift parameter value of TOD.
Otherwise, you can refer to Advanced Parameters tab for auto assigned
VCO frequency.
d. At Dynamic Reconfiguration tab, select Enable access to dynamic phase
shift ports.
4. From IP Catalog, select Ethernet IEEE 1588 Time of Day Clock Intel FPGA IP.
5. In IP Parameter Editor , apply the following settings and generate the TOD
Clock instance:
a. De-select Enable high clock frequency mode
b. Set DEFAULT_NSEC_PERIOD to 8
c. Set DEFAULT_FNSEC_PERIOD to 0x0
d. Set DEFAULT_NSEC_ADJPERIOD to 8
e. Set DEFAULT_FNSEC_ADJPERIOD to 0x0
f. Select Enable pulse per second interface
g. Select Advanced for Accuracy mode
h. Enter desired value for Pulse width.
i. Enter “100” for PLL scan clock frequency. This example uses 100 MHz as
clock for iopll_scan_clk.
j. Enter “90” for PLL unit phase shift. This example has set IOPLL VCO
frequency to 1375 MHz, the unit phase shift equals to 1/8 of IOPLL VCO
period, thus 90 ps.
The diagram below illustrates the connection between IOPLL and TOD instances.
Note that the diagram does not elaborate on all interfaces of the TOD instance.

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Figure 1. Example of connections between IOPLL Interface and TOD Clock’s Advanced
Accuracy Pulse Per Second Interface

Period Clock Source Scan Clock Source

IOPLL Time of Day Clock

period_clk
refclk outclk0 pps_sampling_clk
scanclk iopll_scan_clk
outclk1 iopll_phased_clk

phase_en iopll_phase_en
updn iopll_updn
cntsel [4.0] iopll_cntsel [4.0]
num_phase_shifts[2.0] iopll_num_phase_shifts[2.0]
phase_done iopll_phase_done

locked iopll_locked

1.4.4.2. IOPLL and TOD Setup using IOPLL Reconfig IP

To set up the IOPLL using the IOPLL Reconfig IP and enable pulse-per-second
(advanced accuracy mode) on a TOD clock running on 125MHz period clock for Intel
Agilex 7 devices, follow these steps:
1. Create an Intel Quartus Prime project with Intel Agilex 7 device selected.
2. From IP Catalog, select IOPLL Intel FPGA IP.
3. In IP Parameter Editor, apply the following settings and generate the IOPLL
instance:
a. Use the same clock source as TOD period_clk to drive IOPLL reference clock.
Set Reference Clock Frequency to 125 MHz.
b. For Output Clocks section, set Number of Clocks to 2.
i. Outclk0: Generate pps_sampling_clk, set Desired Frequency to
85.33 MHz (pps_sampling_clk = period_clk *256/375). Sampling
clock factor of 256/375 is suitable for all supported period_clk
frequencies.
ii. Outclk1: Second clock port of the IOPLL must be allocated for
iopll_phased_clk. Set Desired Frequency to the TOD period_clk
frequency (125 MHz).
c. Enable Specify VCO frequency and set Desired VCO Frequency to 1375
MHz.
• Intel recommends you to specify the VCO frequency value as this value
will be used to determine PLL unit phase shift parameter value of TOD.
Otherwise, you can refer to Advanced Parameters tab for auto assigned
VCO frequency.
d. At Dynamic Reconfiguration tab:

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i. Select Enable dynamic reconfiguration of PLL.

ii. In MIF Generation Options, select Create MIF file during IP
Generation.
e. Generate the IP.
4. From IP Catalog, select IOPLL Reconfig Intel FPGA IP.
5. In IP Parameter Editor, apply the following settings and generate the IOPLL
Reconfig IP instance:
a. Under MIF File settings, paste the path of the generated MIF File.
b. Generate the IP.
6. From IP Catalog, select Ethernet IEEE 1588 Time of Day Clock Intel FPGA IP.
7. In IP Parameter Editor, apply the following settings and generate the TOD Clock
instance:
a. De-select Enable high clock frequency mode.
b. Set DEFAULT_NSEC_PERIOD to 8.
c. Set DEFAULT_FNSEC_PERIOD to 0x0.
d. Set DEFAULT_NSEC_ADJPERIOD to 8.
e. Set DEFAULT_FNSEC_ADJPERIOD to 0x0.
f. Select Enable pulse per second interface.
g. Select Advanced for Accuracy mode.
h. Enter desired value for Pulse width.
i. Enter "100" for PLL scan clock frequency. This example uses a 100 MHz
clock to feed iopll_scan_clk.
j. Enter "90" for PLL unit phase shift. This example has set the IOPLL VCO
frequency to 1375 MHz, the unit phase shift equals to 1/8 of IOPLL VCO
period, thus 90 ps.
k. Generate the IP.

When using IOPLL Reconfig IP, the dynamic phase shift interface of the TOD IP is
mapped to the IOPLL Reconfig IP ports. The following table shows the mapping of the
ports.

Table 9. TOD Dynamic Phase Shift Ports to IOPLL Reconfig IP Ports Mapping
TOD Dynamic Phase Shift Interface IOPLL Reconfig IP Ports

iopll_phase_done ~ mgmt_waitrequest (inverted assignment)

iopll_phase_en mgmt_write

iopll_num_phase_shifts[2:0] mgmt_writedata[2:0]

iopll_updn mgmt_writedata[3]

iopll_cnt_sel[3:0] mgmt_writedata[7:4]

The diagram below illustrates the connection between IOPLL, IOPLL Reconfig IP, and
TOD instances. mgmt_address of IOPLL Reconfig IP can be tied to 10'h300 to select
Dynamic phase shift reconfiguration operation mode. Note that the diagram does not
elaborate all interfaces of the TOD instance.

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Figure 2. Example of connection between IOPLL, IOPLL reconfig IP, and TOD's
Advanced Accuracy Pulse Per Second Interfaces
Period Clock Source Scan Clock Source

refclk period_clk
outclk0 pps_sampling_clk
outclk1 iopll_phased_clk
locked iopll_locked
iopll_scan_clk

IOPLL Reconfig IP 10’h300

IOPLL IP ToD IP
mgmt_clk
mgmt_address
mgmt_waitrequest iopll_phase_done
mgmt_write iopll_phase_en
mgmt_read iopll_cnt_sel [3:0]
mgmt_writedata[7:0] iopll_updn
mgmt_readdata[7:0] iopll_num_phase_shifts [2:0]
reconfig_to_pll reconfig_to_pll
reconfig_from_pll reconfig_from_pll

Related Information
IOPLL Reconfig IP Core Reconfiguration Modes

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1.5. Interface Signals

Figure 3. Interface Signals of TOD Clock

TOD Clock

csr_address[n:0] time_of_day_96b_load_valid
csr_read time_of_day_96b_load_data[95:0]
Avalon csr_readdata[31:0] time_of_day_64b_load_valid
Memory-
Mapped csr_write time_of_day_64b_load_data[63:0] Time-of-day
Control csr_writedata[31:0] time_of_day_96b[95:0] Interface
Interface
clk time_of_day_64b[63:0]
rst_n period_clk
period_rst_n

iopll_scan_clk
pps_sampling_clk
iopll_phased_clk
iopll_phased_done
iopll_locked Pulse Per Second
iopll_phase_en Interface
iopll_updn
iopll_cnt_sel[4:0]
iopll_num_phase_shifts[2:0]
pps_pulse_per_second

Note: Pulse Per Second Interface is only available for selected option and specific devices.
For more information, refer to Pulse-Per-Second Signals on page 16 and Pulse Per
Second Device Speed Grade Support on page 4.

1.5.1. Avalon Memory-Mapped Signals

Table 10. Avalon Memory-Mapped Signals Description
Name Direction Width Description

csr_address[] In n Use this bus to specify the register address you

want to read from or write to.
By default, the width of this signal is 4. When the
OFFSET_JITTER_WANDER_EN parameter is set to
1, the width of this signal is 5.

csr_read In 1 Assert this signal to request a read.

csr_readdata[] Out 32 Data read from the specified register.

csr_write In 1 Assert this signal to request a write.

csr_writedata[] In 32 Data to be written to the specified register.

clk In 1 Clock for the Avalon® memory-mapped interface,

whose frequency is not more than 100 MHz.

rst_n In 1 Active-low reset signal for the clk domain.

Synchronous to clk.

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1.5.2. Time-of-day Signals

Table 11. Time-of-day Signals Description
Name Direction Width Description

time_of_day_96[] Out 96 96-bit time of day streamed by the TOD clock.

time_of_day_64[] Out 64 64-bit time of day streamed by the TOD clock.

time_of_day_96b_l In 1 Assert this signal for one clock cycle to indicate that the
oad_valid time_of_day_96b_load_data[] bus is valid. It indicates that the 96-
bit time of day is synchronized and loaded into the TOD clock.

time_of_day_64b_l In 1 Assert this signal for one clock cycle to indicate that the
oad_valid time_of_day_64b_load_data[] bus is valid. It indicates that the 64-
bit time of day is synchronized and loaded into the TOD clock.

time_of_day_96b_l In 96 96-bit time of day from the master TOD clock.

oad_data[]

time_of_day_64b_l In 64 64-bit time of day from the master TOD clock.

oad_data[]

period_clk In 1 Clock for the TOD clock. Ensure that this clock is in the same clock
domain as the TX and RX clock signals of the MAC IP.

period_rst_n In 1 Active-low reset signal for the period_clk domain. Synchronous to

period_clk.

1.5.3. Pulse-Per-Second Signals

Table 12. Pulse-Per-Second Signals
Name Direction Width Description

The following signals are available when parameter Enable pulse per second interface is enabled.

pps_pulse_per_second Out 1 Pulse generated once in every second, aligned with the second
boundary, with pulse width defined by Pulse width parameter.

The following signals are available when parameter Enable pulse per second interface is enabled and Accuracy mode
is Advanced. You must also instantiate IOPLL parameter and select Enable access to dynamic phase shift ports to
support these interfaces. Refer to related information for the related user guides.

pps_sampling_clk Input 1 Sampling clock input used to support pps pulse generation with
advanced accuracy.
Required frequency (MHz):
pps_sampling_clk= period_clk x 256/375

iopll_scan_clk Input 1 Drive this port with the same clock as IOPLL scan clock source.
Please refer to Example of connections between IOPLL Interface
and TOD Clock’s Advanced Accuracy Pulse Per Second Interface
diagram and Example of connection between IOPLL, IOPLL reconfig
IP, and TOD's Advanced Accuracy Pulse Per Second Interfaces
diagram for examples of port connection.
Supported frequency (MHz):
50 MHz to 100 MHz.
Note: As IOPLL phase shift operation is running on
iopll_scan_clk, faster iopll_scan_clk is
recommended for faster IOPLL phase shift operation.

iopll_phased_clk Input 1 Phase shifted version of period_clk from IOPLL. This signal is
expected to be fed by second output clock of IOPLL, e.g. outclk1,
which runs on period_clk frequency. Refer to
iopll_cnt_sel signal description for more details.
continued...

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Name Direction Width Description

iopll_locked Input 1 PLL lock status signal from IOPLL.

iopll_phase_en Output 1 Connect this signal to phase_en input port of IOPLL.

iopll_updn Output 5 Connect this signal to updn input port of IOPLL.

iopll_cnt_sel Output 5 Connect this signal to cntsel input port of IOPLL. This signal
always select second output clock of IOPLL, e.g. outclk1, to be the
one being phase shifted. Therefore, iopll_phased_clk signal is
expected to connect to the second output clock of IOPLL.

iopll_num_phase_shift Output 3 Connect this signal to num_phase_shifts input port of IOPLL.

s

iopll_phase_done Input 1 Connect this signal to phase_done output port of IOPLL.

Related Information
• Intel Stratix 10 Clocking and PLL User Guide
• Intel Agilex 7 Clocking and PLL User Guide: F-Series and I-Series

1.5.4. Clocking Requirements

• Expect the clk frequency to be equal or less than 100 MHz.
• The period_clk must have the same clock source as the timestamping
consumer, e.g. MAC. In case the frequency exceeds 156.25 MHz, when
OFFSET_JITTER_WANDER_EN is enabled, use the ToD in conjunction with the
TOD Synchronizer.
• For advanced accuracy Pulse per Second feature, IOPLL instantiation is required
and must meet the following clocking requirements:
— The IOPLL reference clock must be driven by TOD period clock or any clock
with zero ppm difference from TOD period clock.
— The IOPLL scan clock must be the same clock connecting to
iopll_scan_clk. Set the iopll_scan_clk with any value between 50MHz
and 100 MHz. The lower the frequency of the iopll_scan_clk, the longer
the IOPLL takes to carry out the phase shift operation.
— Set the pps_sampling_clk frequency as close as possible to the formula
given in the interface description per Pulse-Per-Second Signals. Deviation from
the formula can affect the accuracy of the PPS signal. However, a few MHz
difference is acceptable and still gives an accuracy within 2ns range.

1.6. Configuration Registers

Table 13. Register Description
Word Name Description Access HW
Offset Reset
Value

0x00 SecondsH The upper 16-bit second field of the 96-bit TOD. The value RW 0x0
occupies bits 0 to 15. Bits 16 to 31 are not used.
Read the TOD registers in this sequence: NanoSec, SecondsL,
and SecondsH. 96-bit TOD is snapshot whenever the NanoSec
register is read.
continued...

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Word Name Description Access HW

Offset Reset
Value

Write the TOD registers in this sequence: SecondsH,

SecondsL, and NanoSec.
Reading the SecondsH, SecondsL, and NanoSec registers
does not necessarily return the last values written to these
registers.

0x01 SecondsL The lower 32-bit second field of the 96-bit TOD. RW 0x0
To read from or write to the TOD registers, refer to the
guidelines provided in the SecondsH register description.

0x02 NanoSec The 32-bit nanosecond field of the 96-bit TOD. Loading this RW 0x0
register with a value equal to or larger than a billion leads to an
incorrect timestamp.
To read from or write to TOD registers, refer to the guidelines
provided in the SecondsH register description.

0x03 Reserved – – –

0x04 Period The period for the frequency adjustment. RW n

• Bits [24:16]: The nanosecond field if the
PERIOD_CLOCK_FREQUENCY parameter is set to 0.
• Bits [19:16]: The nanosecond field if the
PERIOD_CLOCK_FREQUENCY parameter is set to 1.
• Bits [15:0]: The fractional nanosecond field.
• The remaining bits are not used.
The reset value of this register, n, is determined by the value of
the DEFAULT_NSEC_PERIOD and DEFAULT_FNSEC_PERIOD
parameters.

0x05 AdjustPeriod The period for the offset adjustment. RW n

• Bits [24:16]: The nanosecond field if the
PERIOD_CLOCK_FREQUENCY parameter is set to 0.
• Bits [19:16]: The nanosecond field if the
PERIOD_CLOCK_FREQUENCY parameter is set to 1.
• Bits [15:0]: The fractional nanosecond field.
• The remaining bits are not used.
The reset value of this register, n, is determined by the value of
the DEFAULT_NSEC_ADJPERIOD and
DEFAULT_FNSEC_ADJPERIOD parameters.
For offset adjustment, write to AdjustPeriod register followed
by AdjustCount register. The TOD offset adjustment starts
after the AdjustCount register is written.

0x06 AdjustCount • Bits [31:20]: Not used. RW 0x0

• Bits [19:0]: The number of clock cycles used during offset
adjustment.
For offset adjustment, write to AdjustPeriod register followed
by AdjustCount register. The TOD offset adjustment starts
after the AdjustCount register is written.

0x07 DriftAdjust The value that the TOD clock uses to periodically adjust the time RW 0x0
of day.
• Bits [31:20]: Not used.
• Bits [19:16]: The nanosecond field.
• Bits [15:0]: The fractional nanosecond field.
continued...

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Word Name Description Access HW

Offset Reset
Value

0x08 DriftAdjustRate • Bit 31: The drift direction: 0 for addition and 1 for RW 0x0
subtraction.
• Bits [30:16]: Not used.
• Bits [15:0]: The interval between drift adjustments in
number of clock cycles.
Writing a value other than 0 to this register triggers the drift
adjustment.

0x09 OffsetNS • Bit 31: Not used. RW 0x0

• Bit 30: The offset direction: 0 for addition and 1 for
subtraction.
• Bits [29:0]: The nanosecond field of the offset.
Writing a value other than 0 to this register triggers the offset in
the time of day.

0x0A OffsetFNS • Bits [31:16]: Not used. RW 0x0

• Bits [15:0]: The fractional nanosecond field of the offset.

0x0B routing_adj_val • Bits [31:20]: Unused RW 0x0

• Bits [19:0]: routing_adj_val
• This is a 20-bit register to adjust the routing delay of the pps
(pulse per second) pulse. The routing adjustment register
has two components, the nanosecond part, and the
fractional part.
— routing_adj_val[15:0]: fractional nanosecond part
— routing_adj_val[19:16]: nanosecond part
Example: if routing delay = 4.3 ns then,
routing_adj_val[19:16] = 0x4
routing_adj_val[15:0] = 0x4CCC (0.3 fns * 2^16 =
19660.8 in 16-bit decimal = 0x4CCC; ignore 0.8)

0x0C JitterTimer • Bit 31: Unused RW 0x0

• Bit 30: The direction of the jitter adjustment: 0 for addition
and 1 for subtraction.
• Bits [29:0]: The timer value in number of clock cycles.
Periodic jitter adjustment is disabled when this register is set to
0.
Writing a value other than 0 to this register enables period jitter
adjustment. Hence, write to this register last.

0x0D JitterAdjust • Bits [31:16]: The nanosecond field of the jitter adjustment. RW 0x0
• Bits [15:0]: The fractional nanosecond field of the jitter
adjustment.

0x10 WanderTimerLSB • Bit 31: Unused RW 0x0

• Bit 30: The direction of the timer adjustment: 0 for addition
and 1 for subtraction.
• Bits [29:0]: The least significant byte of the timer in number
of clock cycles.
Writing a value other than 0 to this register enables wander
timer adjustment. Hence, write to the WanderTimerLSB and
WanderTimerMSB registers last.

0x11 WanderTimerMSB • Bits [31:16]: Unused. RW 0x0

• Bits [15:0]: The most significant byte of the timer in number
of clock cycles.

0x12 WanderAdjust • Bits [31:16]: The nanosecond field of the wander RW 0x0
adjustment.
• Bits [15:0]: The fractional nanosecond field of the wander
adjustment.

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Send Feedback

2. Time-of-day Synchronizer
The Time-of-day (TOD) Synchronizer provides an accurate synchronization between
the time of day of a master TOD clock and a slave TOD clock. This component can
synchronize the following combination of master and slave TOD clocks:
• Master and slave TOD clocks that operate at the same frequency, between 125
MHz and 390.625 MHz. The synchronizer also supports different clock phases and
PPM.
• Master and slave TOD clocks that operate at different frequencies: 62.5 MHz, 125
MHz, 156.25 MHz, 312.5 MHz, 390.625 MHz, or 402.83 MHz.

You can instantiate the TOD synchronizer through the Ethernet IEEE 1588 TOD
Synchronizer Intel FPGA IP in the Intel Quartus Prime software.

2.1. Release Information

Intel FPGA IP versions match the Intel Quartus Prime Design Suite software versions
until v19.1. Starting in Intel Quartus Prime Design Suite software version 19.2, Intel
FPGA IP has a new versioning scheme.

The Intel FPGA IP version (X.Y.Z) number can change with each Intel Quartus Prime
software version. A change in:

• X indicates a major revision of the IP. If you update the Intel Quartus Prime
software, you must regenerate the IP.
• Y indicates the IP includes new features. Regenerate your IP to include these new
features.
• Z indicates the IP includes minor changes. Regenerate your IP to include these
changes.

Table 14. Ethernet IEEE 1588 TOD Synchronizer Intel FPGA IP Release Information
Item Description

IP Version 20.0.0

Intel Quartus Prime Version 22.3

Release Date 2022.09.26

Supported Devices • Arria V GX/GT/GZ/SX/ST

• Intel Arria 10 GX/GT/SX
• Cyclone V SE/SX/ST
• Stratix V GX/GT
• Intel Stratix 10
• Intel Cyclone 10 GX
• Intel Agilex 7

Intel Corporation. All rights reserved. Intel, the Intel logo, and other Intel marks are trademarks of Intel
Corporation or its subsidiaries. Intel warrants performance of its FPGA and semiconductor products to current
specifications in accordance with Intel's standard warranty, but reserves the right to make changes to any ISO
products and services at any time without notice. Intel assumes no responsibility or liability arising out of the 9001:2015
application or use of any information, product, or service described herein except as expressly agreed to in Registered
writing by Intel. Intel customers are advised to obtain the latest version of device specifications before relying
on any published information and before placing orders for products or services.
*Other names and brands may be claimed as the property of others.
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Related Information
Ethernet Design Example Components Release Notes
Describes changes to the IP in a particular release.

2.2. Resource Utilization

Table 15. Estimated Resource Utilization in Intel Arria 10 Devices
(10AX115H1F34I1SG)
Configuration ALMs Combinational Logic Registers Memory
ALUTs (M20K Blocks)

Default Mode 524 652 1732 3

Table 16. Estimated Resource Utilization in Intel Stratix 10 Devices

(1SG280HN2F43E1VG)
Configuration ALMs Combinational Logic Registers Memory
ALUTs (M20K Blocks)

Default Mode 752 953 2134 3

Table 17. Estimated Resource Utilization in Intel Agilex 7 Devices (AGFB014R24A2E2V)

Configuration ALMs Combinational Logic Registers Memory
ALUTs (Memory
LABs)

Default Mode 615 777 1826 5

2.3. Configuring the TOD Synchronizer

In the Intel Quartus Prime software, instantiate the TOD Synchronizer by selecting
Ethernet IEEE 1588 TOD Synchronizer Intel FPGA IP from the IP Catalog or
Platform Designer (Interface Protocols > Ethernet > Reference Design
Components). Specify the following parameters.

Table 18. TOD Synchronizer Parameters Description

Name Valid Values Description

TOD_MODE 0, 1 Specifies the format of the time of day.

• 0: 64 bits. 48 bits nanosecond and 16 bits fractional
nanosecond.
• 1: 96 bits. 48 bits seconds, 32 bits nanosecond and 16 bits
fractional nanosecond.
The default value is 1.

SYNC_MODE 0 – 18 Specifies the synchronization type between the master and

slave TOD clocks.
continued...

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Name Valid Values Description

• 0: 125-MHz master TOD clock and 156.25 MHz slave TOD

clock.
• 1: 156.25-MHz master TOD clock and 125-MHz slave TOD
clock.
• 2: The frequencies of the master and slave TOD clocks are
the same, between 125 MHz and 402.83 MHz. This
synchronization type supports different phase or PPM.
Ensure that you also specify the period of the master and
slave clocks using the PERIOD_NSEC and PERIOD_FNSEC
parameters.
• 3: 156.25-MHz master TOD clock and 312.5-MHz slave TOD
clock.
• 4: 312.5-MHz master TOD clock and 156.25-MHz slave TOD
clock.
• 5: 125-MHz master TOD clock and 312.5-MHz slave TOD
clock.
• 6: 312.5-MHz master TOD clock and 125-MHz slave TOD
clock.
• 7: 125-MHz master TOD clock and 390.625-MHz slave TOD
clock.
• 8: 390.625-MHz master TOD clock and 125-MHz slave TOD
clock.
• 9: 156.25-MHz master TOD clock and 390.625-MHz slave
TOD clock.
• 10: 390.625-MHz master TOD clock and 156.25-MHz slave
TOD clock.
• 11: 312.5-MHz master TOD clock and 390.625-MHz slave
TOD clock.
• 12: 390.625-MHz master TOD clock and 312.5-MHz slave
TOD clock.
• 13: 125-MHz master TOD clock and 62.5-MHz slave TOD
clock.
• 14: 156.25-MHz master TOD clock and 62.5-MHz slave TOD
clock.
• 15: 312.5-MHz master TOD clock and 62.5-MHz slave TOD
clock.
• 16: Reserved.
• 17: Reserved.
• 18: 125-MHz master TOD clock and 402.83-MHz slave TOD
clock.
The default value is 1.

PERIOD_NSEC 0 – 4'hF Specifies the respective 4-bit nanosecond field for the reset
value for the following clock frequencies:
• 125 MHz: Set this parameter to 4'h8 for 8 ns.
• 156.25 MHz: Set this parameter to 4'h6 for 6.4 ns. This
value is the default value.
• 312.5 MHz: Set this parameter to 4'h3 for 3.2 ns.
• 390.625 MHz: Set this parameter to 4'h2 for 2.56 ns.
• 402.83 MHz: Set this parameter to 4’h2 for 2.482 ns.
This parameter is only applicable for SYNC_MODE = 2.

PERIOD_FNSEC 0 – 16h'FFFF Specifies the respective 16-bit fractional nanosecond field for
the reset value for the following clock frequencies:
• 125 MHz: Set this parameter to 16'h0 for 8 ns.
• 156.25 MHz: Set this parameter to 16'h6666 for 6.4 ns. This
value is the default value.
• 312.5 MHz: Set this parameter to 16'h3333 for 3.2 ns.
• 390.625 MHz: Set this parameter to 16'h8F5C for 2.56 ns.
• 402.83 MHz: Set this parameter to 16’h7B80 for 2.482 ns.
continued...

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Name Valid Values Description

This parameter is only applicable for SYNC_MODE = 2.

SAMPLE_SIZE 64, 128, or 256 Specifies the number of samples to use in calculating the FIFO
buffer’s fill level. More samples results in a more accurate
estimation of the fill level. However, the calculation time
increases with the number of samples.
The default value is 64.
This parameter is not applicable for SYNC_MODE = 18.

2.4. Using the TOD Synchronizer

Figure 4. TOD Synchronizer in a Design (SYNC_MODE 0 to 15)

Master TOD Clock TOD Synchronizer Slave TOD Clock

1’b1 start_tod_synch tod_slave_valid time_of_day_96b_load_valid
period_rst_n
tod_slave_data time_of_day_96b_load_data
period_clk
reset_slave period_rst_n
clk_slave period_clk

time_of_day_96b time_master_data
reset_master
clk_master

PLL clk_sampling

Figure 5. TOD Synchronizer in a Design (SYNC_MODE 18)

Master TOD Clock TOD Synchronizer Slave TOD Clock

1’b1 start_tod_synch tod_slave_valid time_of_day_96b_load_valid
period_rst_n
tod_slave_data time_of_day_96b_load_data
period_clk
reset_slave period_rst_n
clk_slave period_clk

time_of_day_96b time_master_data
reset_master
clk_master

The TOD synchronizer with SYNC_MODE = 0 to 15 uses a dual-clock FIFO buffer to

receive the time of day from the master TOD clock and transmits it to the slave TOD
clock. To ensure that the synchronization is accurate, the transfer latency must be
taken into consideration. The sampling clock (clk_sampling) samples the fill level of
the FIFO buffer and calculates the latency. Derive this clock signal from the same
source as the master TOD clock or the slave TOD clock using a PLL.

The sampling clock (clk_sampling) is not required for TOD synchronizer with
SYNC_MODE = 18 as it uses a different technique for synchronization.

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2.4.1. Sampling Clock Frequency

To achieve the recommended frequency for the sampling clock, follow these steps:
1. The SYNC_MODE and SAMPLE_SIZE parameters determine the sampling clock
factor, which is then used to determine the required PLL settings. Use the
Sampling Clock Factor to identify the sampling clock factor for your configuration.
2. Use the sampling clock factor identified in the previous step to determine the M,
N, and C counter settings of PLL. Scale factor for Stratix V PLL, Intel Stratix 10 I/O
PLL and Intel Agilex 7 I/O PLL is M/(N x C). For examples, refer to PLL Settings for
Stratix V Devices for M, N, and C counter settings for Stratix V PLL Intel FPGA IP.
3. In the case where the sampling clock factor is not achievable using the current
PLL, Intel recommends that you use an alternative sampling clock frequency of 80
MHz.
4. Sampling clock granularity determines the accuracy of synchronization where
smaller granularity gives better accuracy. Sampling Clock Granularity for Sampling
Clock Factor and Sampling Clock Granularity Using 80 MHz Sampling Clock show
the granularity for each recommended sampling clock.

Table 19. Sampling Clock Factor

SYNC_MODE Reference Clock Sampling Clock Factor
Frequency
(MHz) SAMPLE_SIZE = 64 SAMPLE_SIZE = 128 SAMPLE_SIZE = 256

0, 1 125 16/63 32/33 64/63

156.25 64/315 128/155 256/375

2 Master/slave 64/63 128/153 256/375

frequency

3, 4 156.25 64/63 128/153 256/375

312.5 32/33 64/63 128/153

5, 6 125 32/63 64/63 128/63

312.5 64/315 128/155 256/375

7, 8 125 N/A N/A 32/13

390.625 N/A N/A 256/375

9, 10 156.25 32/33 64/31 128/63

390.625 64/155 128/185 256/375

11, 12 312.5 16/15 32/33 64/63

390.625 64/75 128/185 256/253

13 62.5 64/63 128/153 256/253

125 32/33 64/63 128/153

14 62.5 32/33 64/63 128/153

156.25 64/155 128/155 256/375

15 62.5 64/63 128/153 256/253

312.5 64/155 128/155 256/375

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Table 20. Sampling Clock Granularity for Sampling Clock Factor

The following is the sampling clock granularity for sampling clock factor in Sampling Clock Factor.

SYNC_MODE Reference Clock Sampling Clock Granularity (ns)

Frequency
(MHz) SAMPLE_SIZE = 64 SAMPLE_SIZE = 128 SAMPLE_SIZE = 256

0, 1 125 0.5 0.25 0.125

156.25

2 Master/slave Ref clock period/64 Ref clock period/128 Ref clock period/256
frequency

3, 4 156.25 0.1 0.05 0.025

312.5

5, 6 125 0.25 0.125 0.0625

312.5

7, 8 125 N/A N/A 0.25

390.625

9, 10 156.25 0.2 0.1 0.05

390.625

11, 12 312.5 0.2 0.1 0.05

390.625

13 62.5 0.25 0.125 0.0625

125

14 62.5 0.5 0.25 0.125

156.25

15 62.5 0.25 0.125 0.0625

312.5

Table 21. Sampling Clock Granularity Using 80 MHz Sampling Clock

SYNC_MODE Time of Day Sampling Clock Granularity (ns)
Frequency
(MHz) SAMPLE_SIZE = 64 SAMPLE_SIZE = 128 SAMPLE_SIZE = 256

0, 1 125 0.5 0.5 0.5

156.25

2 62.5 0.5 0.5 0.5

125 0.5 0.5 0.5

156.25 0.1 0.1 0.1

312.5 0.1 0.1 0.1

390.625 N/A 0.02 0.02

402.83 N/A N/A N/A

3, 4 156.25 0.1 0.1 0.1

312.5
continued...

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SYNC_MODE Time of Day Sampling Clock Granularity (ns)

Frequency
(MHz) SAMPLE_SIZE = 64 SAMPLE_SIZE = 128 SAMPLE_SIZE = 256

5, 6 125 0.5 0.5 0.5

312.5

7, 8 125 N/A 0.5 0.5

390.625

9, 10 156.25 N/A 0.1 0.1

390.625

11, 12 312.5 N/A 0.1 0.1

390.625

13 62.5 0.5 0.5 0.5

125

14 62.5 0.5 0.5 0.5

156.25

15 62.5 0.5 0.5 0.5

312.5

Table 22. PLL Settings for Stratix V Devices

Sampling Clock Factor PLL Counter

M N C

16/15 16 5 3

16/63 16 3 21

32/13 32 13 1

32 3 11
32/33
32 11 3

32/63 32 3 21

64/31 64 31 1

64 9 7
64/63
64 21 3

64/75 64 25 3

64/155 64 31 5

64/315 64 21 15

128/63 128 21 3

128 51 3

128/153 128 17 9

128 9 17

128/155 128 31 5
continued...

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Sampling Clock Factor PLL Counter

M N C

128/185 128 37 5

256/253 256 11 23

256/375 256 75 5

256 25 15

Related Information
• Intel Agilex 7 Clocking and PLL User Guide: F-Series and I-Series
Provides guidance on achieving sampling clock frequency for Intel Agilex 7 F-
Series and I-Series devices.
• Intel Stratix 10 Clocking and PLL User Guide
Provides guidance on achieving sampling clock frequency for Intel Stratix 10
devices.

2.5. Interface Signals

Figure 6. Interface Signals of TOD Synchronizer

TOD Synchronizer

clk_master start_tod_synch
reset_master tod_master_data[n] Synchronizer
Clock
clk_slave tod_slave_valid Interface
and
Reset
reset_slave tod_slave_data[n]
clk_sampling

n = 64 or 96

Table 23. Signals Description

Name Direction Width Description

Clock and Reset Signals

clk_master In 1 Master TOD clock domain.

reset_master In 1 Synchronous reset signal in the master TOD clock

domain.

clk_slave In 1 Slave TOD clock domain.

reset_slave In 1 Synchronous reset signal in the slave TOD clock

domain.

clk_sampling In 1 Sampling clock to measure the transfer latency.

Not available for SYNC_MODE = 18.

Interface Signals

start_tod_sync In 1 Assert this signal to start the synchronization

process. Synchronization continues as long as
this signal is asserted.
continued...

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Name Direction Width Description

tod_master_data[] In 64 or 96 Carries the 64-bit or 96-bit time of day from the

master TOD clock. The width of this signal is
determined by the TOD_MODE parameter

tod_slave_valid Out 1 When asserted, the signal indicates that the data
on the tod_data_slave bus is valid and ready
for transfer in the following cycle. This signal
stays asserted for only 1 clock cycle.

tod_slave_data[] Out 64 or 96 Carries the 64-bit or 96-bit time of day for the
slave TOD clock. This time of day is synchronized
to the master TOD clock with an additional one
clock cycle because it takes one clock cycle to
transfer the time of day to the slave TOD clock.
The width of this signal is determined by the
TOD_MODE parameter.

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3. Packet Classifier
The Packet Classifier decodes the packet type of incoming PTP packets, Avalon
streaming PTP packets from client interface to the TX MAC, and returns the decoded
information to the MAC IP core. The decoded information includes:
• Timestamp request and fingerprint (2-step clock)
• Timestamp insert (1-step clock)
• Timestamp format (96-bit or 64-bit)
• Residence time update, TX ingress timestamp, and format
• PTP packet header information (location of timestamp field, correction field,
checksum field, and checksum correction field)

The decoded information is aligned to the start of packet of the corresponding PTP
packet.

You can instantiate the packet classifier through the Ethernet Packet Classifier
Intel FPGA IP in the Intel Quartus Prime software.

3.1. Release Information

Intel FPGA IP versions match the Intel Quartus Prime Design Suite software versions
until v19.1. Starting in Intel Quartus Prime Design Suite software version 19.2, Intel
FPGA IP has a new versioning scheme.

The Intel FPGA IP version (X.Y.Z) number can change with each Intel Quartus Prime
software version. A change in:

• X indicates a major revision of the IP. If you update the Intel Quartus Prime
software, you must regenerate the IP.
• Y indicates the IP includes new features. Regenerate your IP to include these new
features.
• Z indicates the IP includes minor changes. Regenerate your IP to include these
changes.

Intel Corporation. All rights reserved. Intel, the Intel logo, and other Intel marks are trademarks of Intel
Corporation or its subsidiaries. Intel warrants performance of its FPGA and semiconductor products to current
specifications in accordance with Intel's standard warranty, but reserves the right to make changes to any ISO
products and services at any time without notice. Intel assumes no responsibility or liability arising out of the 9001:2015
application or use of any information, product, or service described herein except as expressly agreed to in Registered
writing by Intel. Intel customers are advised to obtain the latest version of device specifications before relying
on any published information and before placing orders for products or services.
*Other names and brands may be claimed as the property of others.
 3. Packet Classifier
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Table 24. Ethernet Packet Classifier Intel FPGA IP Release Information

Item Description

IP Version 19.2.0

Intel Quartus Prime Version 21.1

Release Date 2021.03.29

Supported Devices • Arria V GX/GT/GZ/SX/ST

• Intel Arria 10 GX/GT/SX
• Cyclone V SE/SX/ST
• Intel MAX 10
• Stratix V GX/GT
• Intel Stratix 10

Related Information
Ethernet Design Example Components Release Notes
Describes changes to the IP in a particular release.

3.2. Resource Utilization

Table 25. Estimated Resource Utilization in Intel Arria 10 Devices
(10AX115U2F45I2SGES)
Configuration ALMs Combinational Logic Memory
ALUTs Registers (M20K Blocks)

Default Mode 212 297 179 8

Table 26. Estimated Resource Utilization in Intel Stratix 10 Devices

(1SX280LN2F43E2LG)
Configuration ALMs Combinational Logic Memory
ALUTs Registers (M20K Blocks)

Default Mode 292 332 533 9

3.3. Configuring the Packet Classifier

In the Intel Quartus Prime software, instantiate the Packet Classifier by selecting
Ethernet Packet Classifier Intel FPGA IP from the IP Catalog or Platform Designer
(Interface Protocols > Ethernet > Reference Design Components).
Specify the parameters in the following table.

Table 27. Packet Classifier Parameters Description

Name Value Default Description

TSTAMP_FP_WIDTH 1 – 32 4 The width of the timestamp fingerprint.

SYMBOLSPERBEAT 1, 4, or 8 8 The number of symbols transferred in a clock

cycle.

BITSPERSYMBOL 8 8 The number of bits per symbol transferred in a

clock cycle.

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3.4. Interface Signals

Packet Classifier
tx_etstamp_ins_ctrl_in_ingress_timestamp_96b[]
data_sink_sop
tx_etstamp_ins_ctrl_in_ingress_timestamp_64b[]
data_sink_eop
tx_etstamp_ins_ctrl_out_ingress_timestamp_96b[]
data_sink_valid
tx_etstamp_ins_ctrl_out_ingress_timestamp_64b[]
data_sink_ready
tx_egress_timestamp_request_in_valid
data_sink_data[]
tx_egress_timestamp_request_in_fingerprint[]
data_sink_empty
tx_egress_timestamp_request_out_valid
Avalon data_sink_error
tx_egress_timestamp_request_out_fingerprint[]
Streaming
Interface data_source_sop clock_mode[]
data_source_eop pkt_with_crc
data_source_valid tx_etstamp_ins_ctrl_in_residence_time_update Timestamping
data_source_ready tx_etstamp_ins_ctrl_in_residence_time_calc_format Interface

data_source_data[] tx_etstamp_ins_ctrl_out_residence_time_calc_format
data_source_empty tx_etstamp_ins_ctrl_out_checksum_zero
data_source_error tx_etstamp_ins_ctrl_out_checksum_correct
tx_etstamp_ins_ctrl_out_timestamp_format
tx_etstamp_ins_ctrl_out_timestamp_insert
tx_etstamp_ins_ctrl_out_residence_time_update
tx_etstamp_ins_ctrl_out_offset_timestamp[]
clk tx_etstamp_ins_ctrl_out_offset_correction_field[]
tx_etstamp_ins_ctrl_out_offset_checksum_field[]
reset
tx_etstamp_ins_ctrl_out_offset_checksum_correction[]

3.4.1. Clock and Reset Signals

Table 28. Clock and Reset Signals Description
Name Direction Width Description

clk In 1 Reference clock for the packet classifier. Connect

this signal to the MAC TX clock.

reset In 1 Synchronous reset signal for the packet classifier.

3.4.2. Avalon Streaming Interface Signals

Table 29. Avalon Streaming Signals Description
Name Direction Width Description

data_sink_sop In 1 Assert this signal to indicate the beginning of the

packet.

data_sink_eop In 1 Assert this signal to indicate the end of the packet.

data_sink_valid In 1 Assert this signal to indicate that the

data_sink_data[] signal and other signals on
this interface are valid.
continued...

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Name Direction Width Description

data_sink_ready Out 1 When asserted, this signal indicates that the

packet classifier is ready to accept data.

data_sink_data[] In n(1) The input packet.

data_sink_empty[] In 2, 3 Use this signal to specify the number of empty

bytes in the cycle that contain the end of packet.
The width of this signal is 2 when the
SYMBOLSPERBEAT parameter is 4; 3 when the
parameter is 8. This signal does not exist when the
SYMBOLSPERBEAT is 1.

data_sink_error In 1 Assert this signal to indicate that the current input

packet contains errors.

data_src_sop Out 1 When asserted, this signal indicates the beginning

of the packet.

data_src_eop Out 1 When asserted, this signal indicates the end of the
packet.

data_src_valid Out 1 When asserted, this signal indicates that the

data_src_data[] signal and other signals on
this interface are valid.

data_src_ready In 1 Assert this signal when the receiving component is

ready to accept data.

data_src_data[] Out n(1) The output data.

data_src_empty[] Out 2, 3 Contains the number of empty bytes in the cycle

that contain the end of packet.
The width of this signal is 2 when the
SYMBOLSPERBEAT parameter is 4; 3 when the
parameter is 8. This signal does not exist when the
SYMBOLSPERBEAT is 1.

data_src_error Out 1 When asserted, this signal indicates that the

current output packet contains errors.

3.4.3. Control Signals

Table 30. Control Signals Description
Name Direction Width Description

tx_etstamp_ins_ctrl_in_ingress_timestamp In 96 The 96-bit ingress timestamp of the TX

_96b Packet, aligned to the start of packet of
the corresponding PTP packet.

tx_etstamp_ins_ctrl_in_ingress_timestamp In 64 The 64-bit ingress timestamp of the TX

_64b Packet, aligned to the start of packet of
the corresponding PTP packet.

tx_etstamp_ins_ctrl_out_ingress_timestam Out 96 The 96-bit timestamp to the MAC TX,

p_96b aligned to the corresponding output
PTP packet.

tx_etstamp_ins_ctrl_out_ingress_timestam Out 64 The 64-bit timestamp to the MAC TX,

p_64b aligned to the start of packet of the
corresponding output PTP packet.
continued...

(1)
n=SYMBOLSPERBEAT*BITSPERSYMBOL

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Name Direction Width Description

tx_egress_timestamp_request_in_valid In 1 Assert this signal to indicate that a

timestamp is required for the packet.
This signal must align to the start of an
input packet.

tx_egress_timestamp_request_in_fingerpri In TSTAMP_F The timestamp's fingerprint for the

nt P_WIDTH input packet.

tx_egress_timestamp_request_out_valid Out 1 Assert this signal when timestamp is

required for the particular frame. This
signal is aligned to the start of packet
of the corresponding output PTP
packet.

tx_egress_timestamp_request_out_fingerpr Out TSTAMP_F The timestamp's fingerprint for the

int P_WIDTH output packet.

clock mode In 2 Specify the clock mode:

• 00: Ordinary clock
• 01: Boundary clock
• 10: End to end transparent clock
• 11: Peer to peer transparent clock

pkt_with_crc In 1 Use this signal to indicate whether or

not the incoming packet contains 4-
byte CRC field.
• 0: the incoming packet contains the
CRC field.
• 1: the incoming packet does not
contain the CRC field.

tx_etstamp_ins_ctrl_in_residence_time_ca In 1 Use the following values to specify the

lc_format format of the timestamp to use when
calculating the residence time.
• 0: 96-bit timestamp
• 1: 64-bit timestamp
Align this signal to the start of the
input packet.

tx_etstamp_ins_ctrl_out_residence_time_c Out 1 The format of the timestamp used to

alc_format calculate the residence time.
• 0: 96-bit timestamp
• 1: 64-bit timestamp
This signal is aligned to the start of the
output packet.

tx_etstamp_ins_ctrl_out_checksum_zero Out 1 When asserted, indicates that the

checksum field of the PTP packet is set
to zero. This signal is aligned to the
start of packet of the corresponding
PTP packet.

tx_etstamp_ins_ctrl_out_checksum_correct Out 1 When asserted, indicates that the

checksum of the PTP packet is
corrected by updating the checksum
correction offset. This signal is aligned
to the start of packet of the
corresponding PTP packet.

tx_etstamp_ins_ctrl_out_timestamp_format Out 1 The format of the timestamp.

continued...

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Name Direction Width Description

• 0: 1588v2 format. 96-bit

timestamp that consists of 48-bit
second field, 32-bit nanosecond
field, and 16-bit correction field for
fractional nanosecond.
• 1: 1588v1 format. 64-bit
timestamp that consists of 32-bit
second field and 32-bit nanosecond
field.
This signal is aligned to the start of
packet of the corresponding output PTP
packet.

tx_etstamp_ins_ctrl_out_timestamp_insert Out 1 When asserted, indicates that an

egress timestamp must be inserted
into the corresponding PTP packet. This
signal is aligned to the start of packet
of the corresponding PTP packet.

tx_etstamp_ins_ctrl_out_residence_time_u Out 1 When asserted, indicates that the

pdate residence time is added to the
correction field of the PTP packet. This
signal is aligned to the start of packet
of the corresponding PTP packet.

tx_etstamp_ins_ctrl_out_offset_timestamp Out 16 The location of the timestamp field,

relative to the first byte of the packet.

tx_etstamp_ins_ctrl_out_offset_correctio Out 16 The location of the correction field,

n_field relative to the first byte of the packet.

tx_etstamp_ins_ctrl_out_offset_checksum_ Out 16 The location of the checksum field,

field relative to the first byte of the packet.

tx_etstamp_ins_ctrl_out_offset_checksum_ Out 16 The location of the checksum

correction correction field, relative to the first
byte of the packet.

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4. Ethernet Design Example Components User Guide

Archives
For the latest and previous versions of this user guide, refer to Ethernet Design
Example Components User Guide. If an IP or software version is not listed, the user
guide for the previous IP or software version applies.

IP versions are the same as the Intel Quartus Prime Design Suite software versions up
to v19.1. From Intel Quartus Prime Design Suite software version 19.2 or later, IP
cores have a new IP versioning scheme.

Intel Corporation. All rights reserved. Intel, the Intel logo, and other Intel marks are trademarks of Intel
Corporation or its subsidiaries. Intel warrants performance of its FPGA and semiconductor products to current
specifications in accordance with Intel's standard warranty, but reserves the right to make changes to any ISO
products and services at any time without notice. Intel assumes no responsibility or liability arising out of the 9001:2015
application or use of any information, product, or service described herein except as expressly agreed to in Registered
writing by Intel. Intel customers are advised to obtain the latest version of device specifications before relying
on any published information and before placing orders for products or services.
*Other names and brands may be claimed as the property of others.
683044 | 2023.11.21

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5. Document Revision History for the Ethernet Design

Example Components User Guide
Document Version Intel Quartus Changes
Prime Version

2023.11.21 22.3 Updated iopll_scan_clk description in the Pulse Per Second Signals
table.

2023.10.02 22.3 Updated the Sampling Clock Frequency topic. Added links to the Intel
Agilex 7 Clocking and PLL User Guide: F-Series and I-Series and the Intel
Stratix 10 Clocking and PLL User Guide.

2023.08.21 22.3 • Updated Adjusting Offset, Jitter, and Wander topic.

• Updated IOPLL and TOD Setup using Dynamic Phase Shift Interface
topic.
• Updated IOPLL and TOD Setup using IOPLL Reconfig IP topic.
• Updated Example of connection between IOPLL, IOPLL reconfig IP, and
TOD's Advanced Accuracy Pulse Per Second Interfaces figure.
• Updated product family name to "Intel Agilex 7".

2022.09.27 22.3 • Updated the following Resource Utilization tables for Time-of-day Clock:
— Estimated Resource Utilization in Stratix V Devices
(5SGXEA7H3F35C3)
— Estimated Resource Utilization in Intel Arria 10 Devices
(10AX115H1F34I1SG)
— Estimated Resource Utilization in Intel Stratix 10 Devices
(1SG280HN2F43E1VG)
— Estimated Resource Utilization in Intel Agilex Devices
(AGFB014R24A2E2V)
• Updated the following Resource Utilization tables for Time-of-day
Synchronizer:
— Estimated Resource Utilization in Intel Arria 10 Devices
(10AX115H1F34I1SG)
— Estimated Resource Utilization in Intel Stratix 10 Devices
(1SG280HN2F43E1VG)
— Estimated Resource Utilization in Intel Agilex Devices
(AGFB014R24A2E2V)
• Updated Pulse Width parameter description in Pulse Per Second
Parameter Description table.

2022.03.28 22.1 Added new IOPLL and TOD Setup using IOPLL Reconfig IP topic.

2021.12.13 21.4 • Edited the following tables:

— Estimated Resource Utilization in Intel Stratix 10 Devices
(1SG280LN2F43E1VG)
— Estimated Resource Utilization in Intel Agilex Devices
(AGFA022R24C212V)
• Updated Clocking Requirements topic.
• Updated Supported Speed Grades in Pulse Per Second Device Speed
Grade Support topic.
continued...

Intel Corporation. All rights reserved. Intel, the Intel logo, and other Intel marks are trademarks of Intel
Corporation or its subsidiaries. Intel warrants performance of its FPGA and semiconductor products to current
specifications in accordance with Intel's standard warranty, but reserves the right to make changes to any ISO
products and services at any time without notice. Intel assumes no responsibility or liability arising out of the 9001:2015
application or use of any information, product, or service described herein except as expressly agreed to in Registered
writing by Intel. Intel customers are advised to obtain the latest version of device specifications before relying
on any published information and before placing orders for products or services.
*Other names and brands may be claimed as the property of others.
5. Document Revision History for the Ethernet Design Example Components User Guide
683044 | 2023.11.21

Document Version Intel Quartus Changes

Prime Version

2021.09.27 21.3 • Added new section Pulse Per Second Device Speed Grade Support in
the topic Release Information.
• Edited Resource Utilization and added Pulse Per Second Configuration
to the following tables:
— Estimated Resource Utilization in Intel Arria 10 Devices
(10AX115U2F45I2SGES).
— Estimated Resource Utilization in Intel Agilex Devices
(AGFA014F25AA212V).
• Added new table: Pulse Per Second Parameter in Configuring the TOD
Clock.
• Added new section IOPLL and TOD Setup for Pulse Per Second
(Advanced Accuracy Mode) in Using the TOD Clock.
• Added new section Pulse-Per-Second Signals in the topic Interface
Signals.
• Edited table: Register Description
— Changed Byte Offset to Word Offset.
— Added new row for 0x0B Word Offset.
• Removed Intel Max 10 as the Supported Devices from table: Ethernet
IEEE 1588 TOD Synchronizer Intel FPGA IP Release Information.

2021.03.29 21.1 • Added new tables:

— Sampling Clock Granularity for Sampling Clock Factor
— Sampling Clock Granularity Using 80 MHz Sampling Clock

2020.12.14 20.4 • Updated chapter Time-of-day Synchronizer and table TOD Synchronizer
Parameters Description to include frequency 402.83 MHz and also its
parameters.
• Added figure TOD Synchronizer in a Design (SYNC_MODE 18) to section
Using the TOD Synchronizer.
• Updated the description for clk_sampling in table Signals
Description.
• Updated the names, values, default values, and descriptions for the
following parameters in Table: TOD Clock Parameters Description:
— Updated parameter name PERIOD_CLOCK_FREQUENCY to Enable
high clock frequency mode.
— Updated parameter name OFFSET_JITTER_WANDER_EN to Enable
offset, jitter, and wander supports.
• Updated the description for AdjustPeriod in Table: Configuration
Registers for Time-of-day clock.

2020.07.14 20.2 Updated Adjusting Offset, Jitter, and Wander:

• Corrected the bits for WanderTimerLSB from [29:1] to [29:0].
• Corrected the values for WanderTimerMSB[15:0] from 0x06239 to
0x6239.

2020.06.22 20.2 • Added the following tables in the Time-of-day Clock chapter:
— Estimated Resource Utilization in Intel Stratix 10 Devices
(1SG280LN2F43E1VG).
— Estimated Resource Utilization in Intel Agilex Devices
(AGFA014F25AA212V).
• Added the following tables in the Time-of-day Synchronizer chapter:
— Estimated Resource Utilization in Intel Stratix 10 Devices
(1SX280LN2F43E2LG)
— Estimated Resource Utilization in Intel Agilex Devices
(AGFB014F25A2E2V)
• Updated the description for PERIOD_CLOCK_FREQUENCY in Table: TOD
Clock Parameters Description.
continued...

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 5. Document Revision History for the Ethernet Design Example Components User Guide
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Document Version Intel Quartus Changes

Prime Version

• Updated the following topics:

— Adjusting TOD Drift
— Adjusting Offset, Jitter, and Wander
— Correcting TOD Offset
— Packet Classifier
• Updated the description for the following registers in Table: Register
Description:
— SecondsH
— AdjustPeriod
— AdjustCount
• Added a new Table: Estimated Resource Utilization in Intel Stratix 10
Devices (1SX280LN2F43E2LG).
• Updated the descriptions to the following signals in Table: Control
Signals Description:
— tx_etstamp_ins_ctrl_in_ingress_timestamp_96b
— tx_etstamp_ins_ctrl_in_ingress_timestamp_64b
• Updated for latest Intel branding standards.

2019.09.30 19.3 • Added support for Intel Agilex devices in the Time-of-day Clock and
Time-of-day Synchronizer chapters.
• Updated the following tables to include Intel Quartus Prime version:
— Ethernet IEEE 1588 Time of Day Clock Intel FPGA IP Release
Information
— Ethernet IEEE 1588 TOD Synchronizer Intel FPGA IP Release
Information
— Ethernet Packet Classifier Intel FPGA IP Release Information

2019.07.01 19.2 • Renamed the Supported Devices sections to Release Information in the
respective chapters to include IP release information as well as
supported devices.
• Added support for Intel Stratix 10 and Intel Cyclone 10 GX devices in
the Time-of-day Clock and Time-of-day Synchronizer chapters.
• Added support for Intel Stratix 10 devices in the Packet Classifier
chapter.

2018.12.03 18.0 • Rebranded as Intel.

• Renamed the following Ethernet design example component names as
per Intel rebranding:
— "Ethernet IEEE 1588 TOD Synchronizer" to "Ethernet IEEE 1588
TOD Synchronizer Intel FPGA IP"
— "Ethernet IEEE 1588 Time of Day Clock" to "Ethernet IEEE 1588
Time of Day Clock Intel FPGA IP"
— "Ethernet Packet Classifier" to "Ethernet Packet Classifier Intel FPGA
IP"
• Updated the following topics:
— Time-of-day Clock
— Using the TOD Clock
• Updated Table: Register Description to correct the byte offsets of
SecondsL, NanoSec, Reserved, Period, AdjustPeriod,
AdjustCount, DriftAdjust, DriftAdjustRate, OffsetNS,
OffsetFNS, JitterTimer, JitterAdjust, WanderTimerLSB, and
WanderAdjust registers.
• Made editorial updates throughout the document.

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Date Version Changes

March 2017 2017.03.08 • Added a new topic: Correcting ToD Offset.

• Updated the "Time-of-day Signals Description" table.
• Added resource utilization for Arria 10 Devices for 16.1 release:
— "Time-of-day Clock" section
— "Time-of-day Synchronizer" section
— "Packet Classifier" section

May 2016 2016.05.02 Initial release.

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