VHDL and Verilog – Module 1

Introduction

Jim Duckworth
ECE Department, WPI

Jim Duckworth, WPI 1 ECE 574 - Module 1

 Topics
• Background to VHDL
• Introduction to language
• Programmable Logic Devices
– CPLDs and FPGAs
– FPGA architecture
– Spartan 3 Starter Board and Nexys 2 Board
• Using VHDL to synthesize and implement a design
• Verilog overview

Jim Duckworth, WPI 2 ECE 574 - Module 1

 Hardware Description Languages
• Example HDL's : ABEL, VERILOG, VHDL
• Advantages:
– Documentation
– Flexibility (easier to make design changes or mods)
– Portability (if HDL is standard)
– One language for modeling, simulation (test benches), and
synthesis
– Let synthesis worry about gate generation
• Engineer productivity
• However: A different way of approaching design
– engineers are used to thinking and designing using graphics
(schematics) instead of text.

Jim Duckworth, WPI 3 ECE 574 - Module 1

 VHDL
• VHSIC Hardware Description Language
– Very High Speed Integrated Circuit
• Standard language used to describe digital hardware
devices, systems and components
– Developed initially for documentation
• VHDL program was an offshoot of the US Government's
VHSIC Program
• Approved as an IEEE Standard in December 1987 (IEEE
standard 1076-1987)
– Revised - now 1076-1993 (supported by all tools)
– Work under way on VHDL-200X
• Integration of 1164 std
• General improvements, etc

Jim Duckworth, WPI 4 ECE 574 - Module 1

 VHDL References
• IEEE Standard VHDL Language Reference Manual (1076
– 1993) (1076-2002)
• “RTL Hardware Design using VHDL – Coding for
Efficiency, Portability, and Scalability” by Pong P. Chu,
Wiley-InterScience, 2006
• “Introductory VHDL From Simulation to Synthesis by
Sudhakar Yalamanchilli, 2002, Xilinx Design Series,
Prentice Hall
• “VHDL Made Easy” by David Pellerin and Douglas
Taylor, 1997, Prentice Hall

Jim Duckworth, WPI 5 ECE 574 - Module 1

 What exactly is VHDL ?
• A way of describing the operation of a system.
– Example: a 2-input multiplexer

ENTITY mux IS
PORT (a, b, sel : IN std_logic;
y : OUT std_logic);
END mux;

ARCHITECTURE behavior OF mux IS

BEGIN

y <= a WHEN sel = ‘0’ ELSE

b;

END behavior;

Jim Duckworth, WPI 6 ECE 574 - Module 1

 Example Synthesis Results (not Xilinx)

Jim Duckworth, WPI 7 ECE 574 - Module 1

 Basic Terminology
• Note: VHDL is case insensitive, free format.
• Semicolon (;) terminates statement
• Comments are preceded by two consecutive dashes.
– comment ends at end of current line
• A digital component is described using an
– ENTITY DECLARATION and a corresponding
– ARCHITECTURE BODY.
• Std_logic is an enumeration type defined in an IEEE
package
– has the values '0' and ‘1’ and ‘Z’ (and others)
• Ports are like IC pins, connected by wires called SIGNALS

Jim Duckworth, WPI 8 ECE 574 - Module 1

 IEEE STANDARD 1164
• Provides a standard data type (std_logic) - nine values
– U unitialized
– X forcing unknown
– 0 forcing logic 0
– 1 forcing logic 1
– Z high impedance
– W weak unknown
– L weak logic 0
– H weak logic 1
– - don’t care
• To use standard logic data types place at top of source file
– LIBRARY ieee; -- library
– USE ieee.std_logic_1164.ALL; -- package

Jim Duckworth, WPI 9 ECE 574 - Module 1

 Entity
• The ENTITY defines the external view of the
component
• PORTS are the communication links between
entities or connections to the device pins
• Note the use of libraries before entity description
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;

ENTITY mux IS
PORT (a, b, sel : IN std_logic;
y : OUT std_logic);
END mux;

Jim Duckworth, WPI 10 ECE 574 - Module 1

 Architecture
• The ARCHITECTURE defines the function or behavior or
structure of the ENTITY
• Consists of concurrent statements, e.g.
– Process statements
– Concurrent Signal Assignment statements
– Conditional Signal Assignment statements
• An entity may have several architectures
ARCHITECTURE behavior OF mux IS
BEGIN

y <= a WHEN sel = ‘0’ ELSE

b;

END behavior;

Jim Duckworth, WPI 11 ECE 574 - Module 1

 VHDL Notes
• There is no explicit reference to actual hardware
components
– There are no D-type flip-flops, mux, etc
– Required logic is inferred from the VHDL description
– Same VHDL can target many different devices
• There are many alternative ways to describe the required
behavior of the final system
– Exactly the same hardware will be produced
– Some ways are more intuitive and easier to read
• Remember that the synthesis tools must be able to deduce
your intent and system requirements
– For sequential circuits it is usually necessary to follow
recommended templates and style

Jim Duckworth, WPI 12 ECE 574 - Module 1

 Programmable Logic Devices
• Xilinx user programmable devices
– FPGAs – Field Programmable Gate Array
• Virtex 4, Virtex 5, Virtex 6, and Virtex 7
• Spartan 3, Spartan 6
• Consist of configurable logic blocks
– Provides look-up tables to implement logic
– Storage devices to implement flip-flops and latches
– CPLDs – Complex Programmable Logic Devices
• CoolRunner-II CPLDS (1.8 and 3.3 volt devices)
• XC9500 Series (3.3 and 5 volt devices)
• Consist of macrocells that contain programmable and-or matrix with
flip-flops
• Altera has a similar range of devices

Jim Duckworth, WPI 13 ECE 574 - Module 1

 Electronic Components (Xilinx)

Source: Dataquest
Logic

Standard
ASIC
Logic

Programmable
Logic Devices Gate Cell-Based Full Custom
(PLDs) Arrays ICs ICs

SPLDs
(PALs) CPLDs FPGAs

Common Resources
Acronyms Configurable Logic Blocks (CLB)
SPLD = Simple Prog. Logic Device – Memory Look-Up Table
– AND-OR planes
PAL = Prog. Array of Logic – Simple gates
CPLD = Complex PLD Input / Output Blocks (IOB)
– Bidirectional, latches, inverters, pullup/pulldowns
FPGA = Field Prog. Gate Array Interconnect or Routing
– Local, internal feedback, and global

Jim Duckworth, WPI 14 ECE 574 - Module 1

 Xilinx Products (Xilinx)

CPLDs and FPGAs

Complex Programmable Logic Field-Programmable Gate Array
Device (CPLD) (FPGA)

Architecture PAL/22V10-like Gate array-like

More Combinational More Registers + RAM
Density Low-to-medium Medium-to-high
0.5-10K logic gates 1K to 3.2M system gates
Performance Predictable timing Application dependent
Up to 250 MHz today Up to 200 MHz today
Interconnect “Crossbar Switch” Incremental

Jim Duckworth, WPI 15 ECE 574 - Module 1

 Overview of Xilinx FPGA Architecture (Xilinx)

I/O Blocks (IOBs)

Programmable
Interconnect
Configurable
Logic Blocks (CLBs)
Tristate
Buffers

Global
Resources

Jim Duckworth, WPI 16 ECE 574 - Module 1

 Spartan-3 FPGA Family
• “Designed to meet the needs of high-volume, cost-
sensitive consumer electronic applications”
• 326 MHz system clock rate
• Programmed by loading configuration data into static
memory cells – place serial PROM on board

Device System CLBs CLB Block User Price

Gates (4 slices) flip-flops Ram (bits) IO (250K)

XC3S200 200K 480 3,840 216K 173 $2.95

XC3S1000 1M 1,920 15,360 432K 391 $12

XC3S4000 4M 6,912 55,296 1,728K 712 $100

Jim Duckworth, WPI 17 ECE 574 - Module 1

 Spartan-3E FPGA Family
• Also “specifically designed to meet the needs of high volume, cost-
sensitive consumer electronic applications.
• builds on the success of the earlier Spartan-3 family by increasing the
amount of logic per I/O, significantly reducing the cost per logic cell.
New features improve system performance.
• Because of their exceptionally low cost, are ideally suited to a wide
range of consumer electronics applications, including broadband access,
home networking, display/projection, and digital television equipment”.
Device System CLBs CLB Block User Price
Gates (4 slices) flip-flops Ram (bits) IO (250K)

XC3S100E 100K 240 1,920 72K 108 <$2

XC3S500E 500K 1,164 9,312 360K 232 $30 1-off
XC3S1600E 1.6M 3,688 29,504 648K 376 <$9

Jim Duckworth, WPI 18 ECE 574 - Module 1

 Programmable Functional Elements
• Configurable Logic Blocks (CLBs)
– RAM-based look-up tables to implement logic
– Storage elements for flip-flops or latches
• Input/Output Blocks
– Supports bidirectional data flow and 3-state operation
– Supports different signal standards including LVDS
– Double-data rate registers included
– Digitally controlled impedance provides on-chip terminations
• Block RAM provides data storage
– 18-Kbit dual-port blocks
• Multiplier blocks (accepts two 18-bit binary numbers)
• Digital Clock Manager (DCM)
– Provides distribution, delaying, mult, div, phase shift of clocks

Jim Duckworth, WPI 19 ECE 574 - Module 1

 Slices and CLBs (Xilinx)
• Each Virtex-II CLB
contains COUT COUT
four slices BUFT
BUF T
– Local routing provides Slice S3
feedback between slices in the
same CLB, and it provides
routing to Slice S2
Switch SHIFT
neighboring CLBs Matrix
– A switch matrix provides
Slice S1
access
to general routing resources
Slice S0 Local Routing

CIN CIN

Jim Duckworth, WPI 20 ECE 574 - Module 1

 Simplified Slice Structure (Xilinx)
• Each slice has four outputs
– Two registered outputs,
two non-registered outputs
– Two BUFTs associated
Slice 0
with each CLB, accessible
by all 16 CLB outputs PRE
LUT Carry D Q
CE
• Carry logic runs vertically,
CLR
up only
– Two independent
carry chains per CLB
LUT Carry D PRE
CE Q

CLR

Jim Duckworth, WPI 21 ECE 574 - Module 1

 Detailed Slice Structure (Xilinx)
• The next slides will
discuss the slice
features
– LUTs
– MUXF5, MUXF6,
MUXF7, MUXF8
(only the F5 and
F6 MUX are shown
in the diagram)
– Carry Logic
– MULT_ANDs
– Sequential Elements

Jim Duckworth, WPI 22 ECE 574 - Module 1

 Look-Up Tables (Xilinx)
• Combinatorial logic is stored in Look-Up Tables (LUTs)
– Also called Function Generators (FGs) A B C D Z
– Capacity is limited by number of inputs, not complexity
0 0 0 0 0
• Delay through the LUT is constant 0 0 0 1 0
0 0 1 0 0
0 0 1 1 1
0 1 0 0 1
Combinatorial Logic
0 1 0 1 1
A
B . . .
Z 1 1 0 0 0
C
D 1 1 0 1 0
1 1 1 0 0
1 1 1 1 1

Jim Duckworth, WPI 23 ECE 574 - Module 1

 Flexible Sequential Elements (Xilinx)
• Can be flip-flops or latches
FDRSE _1
• Two in each slice; eight in each
D S Q
CLB CE

• Inputs can come from LUTs or R

from an independent CLB FDCPE

input D PRE Q
CE
• Separate set and reset controls
CLR
– Can be synchronous or
asynchronous
LDCPE
• All controls are shared within a D PRE Q
slice CE

G
– Control signals can be inverted CLR

locally within a slice

Jim Duckworth, WPI 24 ECE 574 - Module 1
 IOB Element (Xilinx)
• Input path
– Two DDR registers
IOB
• Output path Input
– Two DDR registers Reg DDR MUX
OCK1 Reg
– Two 3-state enable ICK1
DDR registers Reg
OCK2 3-state Reg
• Separate clocks and ICK2
clock enables for I and O
• Set and reset signals Reg DDR MUX
are shared OCK1
PAD
Reg
OCK2 Output

Jim Duckworth, WPI 25 ECE 574 - Module 1

 SelectIO Standard (Xilinx)
• Allows direct connections to external signals of varied
voltages and thresholds
– Optimizes the speed/noise tradeoff
– Saves having to place interface components onto your board
• Differential signaling standards
– LVDS, BLVDS, ULVDS
– LDT
– LVPECL
• Single-ended I/O standards
– LVTTL, LVCMOS (3.3V, 2.5V, 1.8V, and 1.5V)
– PCI-X at 133 MHz, PCI (3.3V at 33 MHz and 66 MHz)
– GTL, GTLP
– and more!

Jim Duckworth, WPI 26 ECE 574 - Module 1

 Digital Controlled Impedance (DCI)
• DCI provides
– Output drivers that match the impedance of the traces
– On-chip termination for receivers and transmitters
• DCI advantages
– Improves signal integrity by eliminating stub reflections
– Reduces board routing complexity and component count by
eliminating external resistors
– Internal feedback circuit eliminates the effects of temperature,
voltage, and process variations

Jim Duckworth, WPI 27 ECE 574 - Module 1

 Block SelectRAM Resources (Xilinx)
• Up to 3.5 Mb of RAM in 18-
kb blocks
– Synchronous read and write
• True dual-port memory
– Each port has synchronous read
and write capability
– Different clocks for each port
• Supports initial values
• Synchronous reset on output
latches
• Supports parity bits
– One parity bit per eight data
bits
Jim Duckworth, WPI 28 ECE 574 - Module 1
 Dedicated Multiplier Blocks (Xilinx)
• 18-bit twos complement signed operation
• Optimized to implement multiply and accumulate
functions
• Multipliers are physically located next to block
SelectRAM™ memory

Data_A
(18 bits)
4 x 4 signed
8 x 8 signed
18 x 18 Output
Multiplier (36 bits) 12 x 12 signed
18 x 18 signed
Data_B
(18 bits)

Jim Duckworth, WPI 29 ECE 574 - Module 1

 Spartan-3 Starter Board

Jim Duckworth, WPI 30 ECE 574 - Module 1

 Nexys 2 Board ($99)

Jim Duckworth, WPI 31 ECE 574 - Module 1

 Logic Synthesis
• A process which takes a digital circuit description and
translates it into a gate level design, optimized for a
particular implementation technology.

Jim Duckworth, WPI 32 ECE 574 - Module 1

 Xilinx Design Process (Xilinx)

HDL code Schematic

• Step1: Design
– Two design entry methods: HDL(Verilog or
VHDL) or schematic drawings
Synthesize Synthesis
• Step 2: Synthesize to create Netlist CONSTRAINTS
– Translates V, VHD, SCH files into an industry
standard format EDIF file Netlist
• Step 3: Implement design (netlist)
Implementation
– Translate, Map, Place & Route
Implement CONSTRAINTS
• Step 4: Configure FPGA
– Download BIT file into FPGA BIT File

Jim Duckworth, WPI 33 ECE 574 - Module 1

 Xilinx Design Flow (Xilinx)

Plan & Budget Create Code/ HDL RTL

Schematic Simulation
Implement
Functional Synthesize
Translate to create netlist
Simulation

Map

Place & Route

Attain Timing Timing Create

Closure Simulation Bit File

Jim Duckworth, WPI 34 ECE 574 - Module 1

 Program the FPGA (Xilinx)

• There are three ways to

program an FPGA
– Through a PROM device
• You will need to generate a
file that the PROM
programmer will understand
– Directly from the computer
• Use the iMPACT
configuration tool
• (need JTAG)
– Use USB connector
• Digilent Adept tool

Jim Duckworth, WPI 35 ECE 574 - Module 1

 Decoder Tutorial Demo Example

y0
y1
sel0
y2
sel1
y3
sel2 y4
y5
y6
y7

Jim Duckworth, WPI 36 ECE 574 - Module 1

 VHDL Source Code

Jim Duckworth, WPI 37 ECE 574 - Module 1

 Synthesizing the Design

=========================================================================
* HDL Synthesis *
=========================================================================

Synthesizing Unit <decoder>.

Related source file is "C:/ee574/nexsys2/decoder/decoder.vhd".
Found 1-of-8 decoder for signal <y>.
Summary:
inferred 1 Decoder(s).
Unit <decoder> synthesized.

Jim Duckworth, WPI 38 ECE 574 - Module 1

 View the Schematic Representation

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 Decoder Implemented on FPGA

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 Zooming in on Logic Slice

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 Assigning Package Pins

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 New Implementation to Match Target

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 Verilog Background
• 1983: Gateway Design Automation released Verilog HDL
“Verilog” and simulator
• 1985: Verilog enhanced version – “Verilog-XL”
• 1987: Verilog-XL becoming more popular (same year
VHDL released as IEEE standard)
• 1989: Cadence bought Gateway
• 1995: Verilog adopted by IEEE as standard 1364
– Verilog HDL, Verilog 1995
• 2001: First major revision (cleanup and enhancements)
– Standard 1364-2001 (or Verilog 2001)
• System Verilog under development

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 Create Verilog Module

Jim Duckworth, WPI 45 ECE 574 - Module 1

 Module Created
• No separate entity and arch –
just module
• Ports can be input, output, or
inout
• Note: Verilog 2001 has
alternative port style:
– (input a, b, sel, output y);

Jim Duckworth, WPI 46 ECE 574 - Module 1

 Add Assign Statement
• Similar to VHDL conditional signal assignment – continuous assignment
• Exactly same hardware produced

Jim Duckworth, WPI 47 ECE 574 - Module 1

 Verilog - General Comments
• VHDL is like ADA and Pascal in style
• Strongly typed – more robust
• Verilog is more like the ‘C’ language
• Verilog is case sensitive
• White space is OK (tabs, new lines, etc)
• Statements terminated with semicolon (;)
• Verilog statements between
• module and endmodule
• Comments // single line and /* and */

Jim Duckworth, WPI 48 ECE 574 - Module 1

 Verilog Logic
• Four-value logic system
• 0 – logic zero, or false condition
• 1 – logic 1, or true condition
• x, X – unknown logic value
• z, Z - high-impedance state
• Number formats
• b, B binary
• d, D decimal (default)
• h, H hexadecimal
• o, O octal
• 16’H789A – 16-bit number in hex format
• 1’b0 – 1-bit

Jim Duckworth, WPI 49 ECE 574 - Module 1

 Verilog and VHDL – Reminder
• VHDL - like Pascal and Ada programming languages
• Verilog - more like ‘C’ programming language
• But remember they are Hardware Description Languages -
They are NOT programming languages
– FPGAs do NOT contain an hidden microprocessor or interpreter or
memory that executes the VHDL or Verilog code
– Synthesis tools prepare a hardware design that is inferred from the
behavior described by the HDL
– A bit stream is transferred to the programmable device to configure
the device
– No shortcuts! Need to understand combinational/sequential logic
• Uses subset of language for synthesis
• Check - could you design circuit from description?
Jim Duckworth, WPI 50 ECE 574 - Module 1