5.
2 Introduction to the CPU
The relationship between the memory, processor, and program
Program
500 Get 100 //100 is address of r
501 square
502 multiply 200 //200 is address of PI
503 output 300 //300 is address of A
500
IR
Execution of instruction get 100 located at address 500
500
501
get 100
get 100
Fetch of instruction get 100 located at address 500
100
501
get 100
20
20
R
Execution of instruction get 100 located at address 500
501
502
square
square
20
R
Fetch of instruction square located at address 501
501
502
square
square
20
R
ALU
Execution of instruction square located at address 501
501
502
square
square
400
R
ALU
Execution of instruction square located at address 501
502
503
multiply 200
multiply 200
400
R
ALU
Fetch of instruction multiply 200 located at address 502
200
503
multiply 200
3
400
R
ALU
Execution of instruction multiply 200 located at address 502
200
503
multiply 200
3
1200
R
ALU
Execution of instruction multiply 200 located at address 502
503
504
output 300
output 300
1200
R
ALU
Fetch of instruction output 300 located at address 503
300
504
output 300
1200
1200
W
ALU
Execution of instruction output 300 located at address 503
68K's visible register set
The 68K's visible register set consists of
• eight 32-bit data registers (DO to D7)
• eight 32-bit address registers (pointers) (A0 to
A7) 68K's visible register set
• a 16-bit status register (SR)
• a 32-bit program counter (PC).
registers visible and invisible
Some registers are said to be visible and some
are invisible to the programmer.
A register is visible if it can be directly accessed
by the programmer though a computer
operation.
A register is invisible if it is required for internal
operations but cannot be directly accessed by
the programmer.
Arrangement of Memory Cells
Each cell has a unique address
Longer strings stored by using consecutive
cells
value = 01101101
RAM (random access
memory)
Memory cells
n-bit cells
Can hold
m cells m*n bits
Decoder with N Address Lines
Main Memory
0000…0000
a0
a1 0000…0001
0000…0010
N add. 2N
lines add
cell
1111…1111
AN-1
Address lines and memory locations
Address lines memory locations
4 16
12 4K
24 16M
36 64G
5.2.2 Register transfer language (RTL)
• Throughout this course we adopt register transfer language
(RTL) to help us to explain how the CPU operates.
• RTL is an algebraic notation (not a programming language)
that describes how information is accessed from memories
and registers and how it is operated on.
• RTL uses variables like algebra or computer languages; for
example, one or more letters (or letters followed by
numbers) to denote registers or storage locations.
• It's very important to distinguish between a memory
location and its contents. RTL uses square brackets to
indicate the contents of a memory location; for example,
the expression [6] = 3 is interpreted as the contents of
memory location 6 contains the value 3.
Examples
• [MAR] [PC]
• [3] [5]
• [PC] [PC]+1
• [R6(0:7)] 0
Examples
• [20] = 6
• [20] 6
• [20] [6]
• [20] [6]+3
5.2.3 Structure of the CPU
Example:
Instruction ADD X, Y, Z corresponds to X = Y + Z
The CPU fetches it from memory and brings it to
the CPU.
The values of Z and Y are read from the memory
and sent to the CPU.
The CPU adds these values and sends the result, X,
back to memory for storage.
Remember that X, Y, and Z are symbolic names for
the locations of data in memory.
5.2.3 Structure of the CPU
Length of an instruction
ADD X, Y, Z Op-code +3 addresses
ADD R1,R2 //R1, R2 are registers
op-code+2 registers
CiSC and RISC
– CISC is an acronym for complex instruction
set computer.
– RISC stands for reduced instruction set
computer.
CiSC and RISC
• MIPS was one of the first RISC microprocessors.
• The original MIPS architecture had only 55 different
instructions, as compared with the 8086 which had over
100.
• MIPS was designed with performance in mind: It is a
load/store architecture, meaning that only the load and
store instructions can access memory.
• The large number of registers in the MIPS architecture
keeps bus traffic to a minimum.
• Intel, along with many others, is marrying many of the
ideas of RISC architectures with microprocessors that
are largely CISC.
CISC
• In the 1970’s, memory was expansive and small in size ,so people
designed computers that would pack as many action as possible in a
single instruction this saved memory space ,but added complexity.
• Most CISC machines have a single instruction to load the operand
from memory and then add operand to a register. Two things are
performed with a single instruction.
• Microprogrammed control unit
• Large number of instructions (200-500)
• Instructions can do more than 1 thing (that is, an instruction could
carry out 2 or more actions)
• Many addressing modes
• Instructions vary in length, format and time
RISC
• Hardwired control unit
• Instruction lengths fixed (usually 32 bits long)
• Instruction set limited (80-100 instructions)
• Instructions rely mostly on registers, memory accessed only on
loads and stores (load/store machine)
• The RISC instruction set includes only very simple operations
that can ideally be executed in a small number of clock cycles.
• Few addressing modes
• Easy to pipeline for great speedup in performance
• Two advantages of a simple load and store
machine code only takes a few bits
machine code can be quickly decoded, which makes
pipelines easier to design
RISC
• The goal of RISC processor design was to execute an
average of one instruction per clock cycle by
overlapping the execution of consecutive instructions
(i.e. starting executing the next instruction before the
current instruction has finished).
• A problem with pure RISC is that it takes many small
instructions to do anything, which uses a lot of
memory; this excessive use of memory is cold “code
bloat”
