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DLD Ta1 2024 - 2025

Ugg7oc ykci6c6oc v7of7of7o

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Gauri Thakre
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0% found this document useful (0 votes)
50 views2 pages

DLD Ta1 2024 - 2025

Ugg7oc ykci6c6oc v7of7of7o

Uploaded by

Gauri Thakre
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
Available Formats
Download as PDF, TXT or read online on Scribd
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15. 14. 13. 12. 11. 10. 9. 8. 7. 6. 5. 4. 3. 2. 1.

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Implement table,Design Design Design Design Design Design Design Design RAMDEOBABA
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using

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8:1 and 16: 1 multiplexer.
16. Implement alogic function F(A, B,C, D) =Em (1,3,4,11,12,13,14,15) +d(25)
using 8: 1 multiplexer.
17.Implement the following function using 8:1 MUX
F (A, B,C, D)= AB + BD + B'CD'
18. Design BCD to Decimal (4:10) Decoder
19. Design a 3:8 Decoder

20. Design 4:16 Decoder from 3:8 Decoders

21. Design a Decimal to BCD (10:4) Encoder


22. Design Octal to Binary (8:3) Encoder
23. Design 4:2 Priority Encoder OR Design 4 input Priority Encoder

24. Design a SOP circuit that will generate an even parity bit for 3 bit input

25. Design a SOP circuit that will generate an odd parity bit for 3 bit input

Submission Date: 22/11/2024

Dr. (Mrs.) Meghana A. Hasamnis


Dr. (Mrs.) Jayu P. Kalambe
Prof. (Mrs.) PoorviK. Joshi
Alu
Prof. Pooja Khangar 12|n24
Course Teachers

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