Digital Systems & Boolean Algebra Basics
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Unit-I
Module-IV
Number Systems, Boolean Algebra and
Logic Gates
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Sir John Ambrose Fleming (29 November 1849 – 18 April 1945) was
an English electrical engineer and physicist who invented the first
thermionic valve or vacuum tube, designed the radio transmitter with
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which the first transatlantic radio transmission was made, and also
established the right-hand rule used in physics. He was the eldest of
seven children of James Fleming DD (died 1879), a Congregational
minister, and his wife Mary Ann, at Lancaster, Lancashire, and baptised
on 11 February 1850.
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Ambrose Fleming was born in Lancaster and educated at Lancaster
Royal Grammar School, University College School, London, and then
University College London. He entered St John's College, Cambridge
in 1877, gaining his BA in 1881 and becoming a Fellow of St John's in
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1883. He went on to lecture at several universities including the Uni-
versity of Cambridge, University College Nottingham, and University
College London, where he was the first professor of electrical engi-
neering. He was also consultant to the Marconi Wireless Telegraph
Company, Swan Company, Ferranti, Edison Telephone, and later the
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Edison Electric Light Company. In 1892, Fleming presented an im-
portant paper on electrical transformer theory to the Institution of
Electrical Engineers in London.
Digital systems, binary numbers, number base conversions, octal and hexa-
decimal numbers, complements, signed binary numbers, binary codes, ham-
ming code. Axiomatic definition of Boolean algebra, theorems and properties
of Boolean algebra, Boolean functions, canonical and standard forms, logic
gates.
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Digital System Design
1.0 OBJECTIVES
To understand common form of number systems in logic design.
To understand the representations of different binary codes.
To understand basic theorems and properties of boolean algebra.
To understand the difficulty in using boolean algebra theorems and simplifying a boolean
expressions.
To understand basic gates and their applications in digital electronics
1.1 INTRODUCTION
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Many number systems are used in digital electronics. Digital electronics is an exciting and most
applicable field within electronics.
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Number systems are useful in digital computers and the knowledge of this system is neces-
sary to perform reliable and understandable arithmetic operations. The term digital implies a
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system of counting discrete units. A physical system whose behavior is described by mathemati-
cal equations is simulated in a digital computer by means of number systems. Many of the sys-
and symbols.
1.2 DIGITAL AND ANALOG SYSTEM
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tems are required with various digital codes to handle the data in the form of numbers, alphabets
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1. Analog systems. e
System: System is a combination of elements which gives the expected output for a given input.
Systems are classified in to two types.
2. Digital systems.
Digital Systems: A signal is a variation in a physical parameter with respect to time, for example
1.
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temperature, speech, video signal etc. If we consider in electrical engineering domain, so the
electrical signal is a variation of an electrical quantity i.e., voltage or current with respect to time.
Signals are classified into three categories.
1. Analog Signal. 2. Discrete time signal. 3. Digital signal.
Analog Signal: A signal which is continuous or which takes a value at any instant of time is
known as analog signal.
Vmax
V(t)
o
t
Figure-1.1: Analog signal
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Number Systems, Boolean Algebra and Logic Gates
2. Discrete Time Signal
a. A signal which is defined at discrete instants of time is known as analog signal. i.e., it is
continuous in amplitude but discrete in time.
Vmax
V(t)
o t1 t2 t3 t4 t
Figure-1.2: Discrete time signal
3. Digital Signal: A signal which is defined in both time and amplitude is known as digital
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signal.
V(t) Vmax
l5
l4
l3
l2
l1
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1.
o t1 t2 t3 t4
Figure-1.3: Digital signal
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Analog System: The system which processes an analog signal is known as analog system.
In an analog system, the physical quantities can vary over a continuous range of values. The
2.
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examples of analog systems are telephone system and magnetic tape recording etc.
Digital System: The physical quantities or signals can assume only discrete values, while in
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analog systems the physical quantities or signals may vary continuously over a specific
range. Digital signals are easy to store and can have one value from a finite set of possible
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values at any given time. The accuracy and reliability of digital systems is greater than
analog system. So, the digital systems are used extensively in computation and data process-
ing control systems, communications and measurement.
The design of digital systems may be divided roughly into 3 parts.
1. System Design. 2. Logic design.
3. Circuit Design.
System design involves breaking the overall system into subsystem and specifying the char-
acteristics’ of each sub system. For example, system design of a digital computer could involve
specifying the number and type of memory units, and input output devices as well as the intercon-
nection and control of these subsystems.
Logic design involves determining how to inter connect basic logic building blocks to perform
a specific function. An example of logic design is determining the interconnection of logic gates
and filp-flops required to perform binary operations.
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Digital System Design
Circuit design involves specifying the interconnection of specific components such as resis-
tors, diodes and transistors to form a gate, diodes and transistors to form a gate, flip-flop or other
logic building block.
1.2.1 Difference Between Analog and Digital Signals
Analog Signal Digital Signal
1. Analog signals are continuous in nature 1. Digital signals are discrete in nature and can
and can have infinite number of values. have fixed number of values (normally two
values).
2. Basic analog signal is represented by 2. Basic digital signal is represented by square
sine wave. wave.
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3. Analog signals are stored in the form of 3. Digital signals are stored in the form of
wave signals. binary bits.
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4. Analog signal transmission requires less 4. Digital signal transmission requires large
bandwidth. bandwidth.
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5. Processing and transmission of analog 5. Processing and transmission of digital signal
signal is more prone to noise. is less prone to noise.
6. Examples of analog signals are output of
Linear Variable differential Transformer
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LVDT, strain gauge, temperature sensor,
microphone etc. t
6. Examples of digital signals are output of Flip-
Flop, shift registers, Analog to Digital
Converter (ADC) etc.
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7. For example in analog watches we 7. For example in digital watches displays time
calculate time with the help of hours and in the form of digits and numbers usually on an
minutes needle we calculate accurate time. LED screen, so no need to calculate manually.
Advantages of Digital System over Analog System
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In this section, we are discussing about the advantages of digital systems over analog systems.
1. Flexibility: Digital system hardware are very flexible as compared to analog system hard-
ware.
2. Effect of Noise: In digital systems, effect of noise is very less as compared to in analog
system.
3. Reliability: Digital systems are more reliable as compared to analog system.
4. Storage: It is very easy, reliable and compact to store information in digital form as com-
pared to in analog form. It is also easy to access and share information in digital form.
5. Observational Error: Analog instruments are prone to observational error while digital
instruments are free from observational errors like parallax and approximation error.
6. Design: With the advancement of digital technology and availability of large variety IC’s, it
is very easy to design a complex logic in digital system as compared to in analog system.
7. Easy to Use: The digital systems are easier to use because they directly display data in
alpha-numeric form on the screen.
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Number Systems, Boolean Algebra and Logic Gates
Disadvantages of Digital Systems over Analog System
1. Bandwidth: Digital systems require large bandwidth as compared to analog systems.
2. Quantization Noise: Quantization noise is available in digital systems which is not present
in analog systems.
3. Complexity: Digital systems are more complex as compared to analog systems.
Need Of Digitization: Digitization is the process of converting information into a digital format.
Most of the quantities are analog in nature. But storing, retrieving, processing and sharing of these
quantities in digital form is easy and more reliable as compared in analog form. Due to this we
require digitization.
So, to convert an analog signal into a digital signal, we require an analog to digital converter.
The block diagram of a analog to digital converter is shown in figure below.
Analog
Signal Sample and
Hold Circuit
Figure-1.4
Quantizer and
Encoding
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Digital signal
and keep it till next sample.
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Sample and Hold Circuit: The analog signal is applied to a sample and hold circuit. The sample
and hold circuits takes the samples of continuous varying input signal at a periodic interval of time
Quantization and Encoding: The sampled values are then approximated to nearest digital dis-
Applications Of Digital System
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crete value and this process is called quantization. The quantized values are converted to binary
form using appropriate encoding.
Digital systems are widely used almost in every sphere of life. Some of the applications are:
1.
2.
3.
4.
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Data Base Management Systems (DBMS) used in banks, offices, institutes, shops etc using
computers.
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Process Monitoring and Control system in industries using computers, PLC’s, Robots.
Digital signal processing and Digital Communication.
Entertainment appliances like CD/DVD Players, LED TV’s, Digital Cameras.
5. Appliances like photostat machines, fax machine, EPABX machines, microwave ovens.
6. Medical Instruments like Digital X-ray machines, Ultrasound machines, ECG machines.
7. Combustion control in modern vehicles.
1.3 NUMBER SYSTEMS
As we know very well that CPU of our computer can understand information which is composed
of zeros and ones. So a number system which can have only two values 0 and 1 is known as
binary number system. Binary number system is very important in digital system, but there are
three other number systems which are used in digital systems. These three number systems are
5
Digital System Design
decimal number system, octal number system and hexadecimal number system. These number
systems are widely used in microprocessor and computers. So, the knowledge of these number
systems is very essential for designing of digital system. So, there are four number systems which
are given below.
(a) Decimal Number System. (b) Binary Number System.
(c) Octal Number System. (d) Hexadecimal Number System.
Base (or) radix: It is defined as the number of different symbols used in the number systems.
The base or radix of a binary number system is 2, that it uses two different symbols as 0 & 1 to
write the number sequence. The base or radix of a octal number system is 8.i.e. it uses eight
different symbols (0,1,2,3,4,5,6 & 7) to write the number sequence. The base or radix of a Deci-
mal number system is 10.i.e. it uses ten different symbols (0 to 9) to write the number sequence.
the number sequence.
1.3.1 Decimal Number Systems
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Similarly the base or radix of a Hexadecimal number system is 16.i.e. it uses sixteen different
symbols (0 to 9 & A, B, C, D, E, F) 10-Numerical symbols and 6 Alpha numerical symbols to write
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The Decimal number systems contains ‘10’ unique symbols 0, 1, 2,3,4,5,6,7,8 and 9. Since in
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decimal involves the symbols with the base (or) radix is ‘10’. Each symbol in the number system
is called a ‘digit’. The decimal number system is a positional weighted system, means that the
value attached to a digit depends on its location with respect to a decimal point. A number has 2
Example
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parts integer and fractional parts, set a part by a radix point.
369.18
S p Integer
part radix
point
Fractional
part
In this system any number (integer, fractional (or) mixed) of any magnitude can be repre-
sented by the use of above mentioned 10 digits only.
The left most digit in any number representation which has the greatest positional weight out
of all the digits present in that number is called the most significant digit (MSD), and the right most
digit which has the least positional weight out of all the digits present in that number is called least
significant digit (LSD)
For example a decimal number such as 7432 should be written as.
7 x10 3 4 x10 2 3 x10 1 2 x10 0
In the above representation the greatest positional weight is 10 3 and the most significant
digit is 7, the least positional weight is 10 0 , and the least significant digit is 2.
In general a number with a decimal point represented by a series of coefficient as
a 5 a 4 a 3 a 2 a 1a 0 .a 1a 2 a 3 .....
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Number Systems, Boolean Algebra and Logic Gates
The digits on the left side of the decimal point form the integer part of a decimal number and
those on the right side form the fractional part. The digits to the right of the decimal point have
weights which are negative powers of 10 and the digits to the left of the decimal point have
weights which are positive powers of 10. To be more exact, the above given series of coefficients
should be written as.
.. a 5 x10 5 a 4 x10 4 a 3 x10 3 a 2 x10 2 a 1 x10 1 a 0 x10 0 a 1 x10 1 a 2 x10 2 xa 3 x10 3 ...
In general a number with series of coefficient expressed in base (or) radix ‘r’ system should
be written as
a n xr n a n 1xr n 1 ..... a1xr1 a 0 xr 0 a 1xr 1 a 2 xr 2 .... a m 1xr m 1 a m xr m
Here a n , a n 1 ,......a 0 , a 1 , a 2 ,......a m 1 , a 1 are the digits of the given number systems.
Note: The range of coefficient in base ‘r’ number system is from 0 to r-1.
1.3.2 Binary Number System
The Binary number system is a positional weighted system with positional weight as powers of
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‘2’. The base (or) radix of this number system is ‘2’, hence it has two independent symbols that
are 0 and 1. The left most bit is known as most significant bit (MSB) and the right most bit is
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in binary number system are expressed as
MSB 23 22 21 20 2-1 2-2 2-3 LSB
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known as least significant bit (LSB) in binary number system. The weight values (position weights)
e cBinary Point
Figure-1.5
A binary digit is called a ‘bit’. A binary number consist of a sequence of bits each of which
is either a zero (0) or a ‘1’ one the binary point separates a group and fractional part. In binary
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number system a group of ‘16’ bits is known a “word”, and a group of 4 bits is known as “Nibble”,
and a group of 8 bits is known as “byte”, and a group of 32 bits is known as “double word”.
Note:Bit = X where X can 0 or 1.
1 Nibble = X X X X (4 bits)
1 Byte = X X X X X X X X (8 bits)
List of decimal numbers and their equivalent binary representations.
Decimal number Binary number
0 0
1 1
2 10
3 11
4 100
5 101
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Digital System Design
6 110
7 111
8 1000
9 1001
10 1010
11 1011
12 1100
13 1101
14 1110
Advantages of Binary Numbers
1.
15 1111
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Binary numbers have numerous advantages in digital computers, because the switching
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circuits used in these computers use two state devices, so these two states can be repre-
sented by the symbol 0 and 1 respectively.
2. A card with punched holes can also be used to represent the binary numbers. Binary data
and instructions are stored in the card with the help of a card punching machine which
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punches the card in a pre-arranged code.
3. A magnetic tape may also be used as a two state device. Some points of magnetic tape are
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magnetized while leaving other points unmagnified. A row of the points represent data or
instructions. So a magnetic tape reel can be used to store thousands of binary data and
instructions.
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1.3.3 Octal Number System
Octal number system is a positional weighted system with positional weight as power of ‘8’. The
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base (or) radix of this number system is ‘8’; hence it has eight independent symbols that are 0, 1,
2, 3, 4, 5, 6, and 7. Since its base is 8 2 3 , every 3 bit group of binary can be represented by an
octal digit.
The position weight in octal system is:
83 82 81 80 8-1 8-2 8-3 8-4
Octal Point
Figure-1.6: Position weight in octal system
For example the octal number 5632.471 can be represented in the power of 8. As show in figure.
5 6 3 2 . 4 7 1
5x83 5x82 5x81 5x80 . 5x8-1 5x8-2 5x8-3
Figure-1.7: Octal representation of number 5632.471
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Number Systems, Boolean Algebra and Logic Gates
1.3.4 Hexadecimal Number System
Hexadecimal system is a positional weighted system with positional weight as power of ‘16’. The
base (or) radix of this number system is ‘16’, hence it has sixteen independent symbols that are
0, 1, 2, 3, 4, 5, 6, 7, 8, 9, A, B, C, D, E, and F. Since its base 16 2 4 , every 4 bit group of binary
can be represented by a Hexadecimal digit. Remember that the letters A to F in hex represents
decimal equivalents of 10 to 15 respectively as given in below table.
Since numeric digits and alphabets both are used to represent the digits in the hex decimal
number system therefore this is also called as “Alphanumeric number system “.The advantage of
hexadecimal number system is useful in converting directly from a 4 bit binary number. For
Example Hexadecimal representation of 16 is 00010110 (4 bit binary for digit 1=0001, 4 bit
binary for digit 6 = 0110).
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Decimal number Binary number
0 0
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1 1
2 2
3
4
5
t
3
4
5r
e c 6
7
8
6
7
8
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9 9
10 A
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11 B
12 C
13 D
14 E
15 F
Table-1.1: Representation decimal number and equivalent hexa decimal number
Below Table gives the Representation of different Number Systems
Decimal Binary Octal Hexadecimal
(r = 10) (r = 2) (r = 8) (r = 16)
0 0 0 0
1 1 1 1
2 10 2 2
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Digital System Design
3 11 3 3
4 100 4 4
5 101 5 5
6 110 6 6
7 111 7 7
8 1000 10 8
9 1001 11 9
10 1010 12 A
11 1011 13 B
12
13
14
1100
1101
1110
14
15
16
C
D
E
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15
16
17
1111
10000
10001
17
t
20
21 r F
10
11
18
19
20
e c 10010
10011
10100
22
23
24
12
13
14
S p 21
22
23
24
25
10101
10110
10111
11000
11001
25
26
27
30
31
15
16
17
18
19
26 11010 32 1A
27 11011 33 1B
28 11100 34 1C
29 11101 35 1D
30 11110 36 1E
31 11111 37 1F
32 100000 40 20
Table-1.2: Representation of different number system
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Number Systems, Boolean Algebra and Logic Gates
1.4 CONVERSION OF NUMBERS FROM ONE RADIX TO ANOTHER RADIX
1.4.1 Decimal to Base-r Conversion
1. Converting of mixed decimal number into its equivalent base r- number consists of two
parts.
2. Converting the decimal integer number into its equivalent base-r number using successive
division by ‘r’ method.
3. Converting the decimal fractional number into its equivalent base-r fractional number using
successive multiplication by ‘r’.
4. This procedure is also known as “Double-Dabble” method.
In successive division by ‘r’ method the given decimal integer number is successively di-
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vided by ‘r’ fill the quotient is zero. The last remainder of successive division is the most signifi-
cant bit (MSB), the remainder are read from bottom to top to give the equivalent integer number.
In successive multiplication by ‘r’ method the given decimal fraction and the subsequent
decimal fractions are successively multiplied by ‘r’ till the fractional part of the product is zero
t r
(or) till the desired accuracy is obtained. For each and every successive multiplication collect the
integer part of the product terms and write separately. The first integer obtained is MSB and read
the integers from top to bottom to get the equivalent base-r fraction.
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Example: Convert the following decimal numbers in to their equivalent binary, octal and hexa
decimal.
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(a) (123)10 (b) (98.75)10
Ans:(a) i) (123)10 (?) 2
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Decimal to Binary: For binary number systems radix is 2. So we have to make the LCM for the
given decimal number with 2, we have to take all the reminders in upward directions from MSB
to LSB bit as like given in below example.
S 2 123
2 61-1
2 30-1
2 15-0
2 7-1
2 3-1
2 1-1
0-1
M.S.B
123 10 11110112
ii) (123)10 (?)8
Decimal to Octal: For octal number systems radix is 8. So we have to make the LCM for the
given decimal number with 8, we have to take all the reminders in upward directions from MSB
to LSB bit as like given in below example.
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Digital System Design
8 123
8 15-3
8 1-7
0-1
M.S.B
12310 1738
iii) (123)10 (?)16
Decimal to Hexadecimal: For hexadecimal number systems radix is 16. So we have to make
the LCM for the given decimal number with 16, we have to take all the reminders in upward
directions from MSB to LSB bit as like given in below example.
16 123
16 7-B
0-7
M.S.B
12310 7 B16
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Ans:(b)
i) 98 .75 10 = (?) 2
t r
For Integer part we have to make the LCM for the given decimal number with 2, we have to take
1.
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all the reminders in upward directions from MSB to LSB bit.
A) Convert the integral part of decimal to binary equivalent
Divide the decimal number by 2 and store remainders in array.
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2. Divide the quotient by 2.
3. Repeat step 2 until we get the quotient equal to zero.
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4. Equivalent binary number would be reverse of all remainders of step 1.
B) Convert the fractional part of decimal to binary equivalent
1. Multiply the fractional decimal number by 2.
2. Integral part of resultant decimal number will be first digit of fraction binary number.
3. Repeat step 1 using only fractional part of decimal number and then step 2.
2 98
2 49-0
2 24-1
2 12-0
2 6-0
2 3-0
2 1-1
0-1
M.S.B
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Number Systems, Boolean Algebra and Logic Gates
9810 11000102
98.75 10 1100010 .112
Fractional part
M.S.B
0.75x2=1.50 1
0.50x2=1.00 1
Therefore 0.75 10 0.112
ii) 98.7510 = (?) 8
Integer part
8 98
8 12-2
8 1-4
u m
r
0-1
M.S.B
98 10 142 8
Fractional part
c
0.75 8 6.00 6 0.75 10 0.6 8
t
Therefore 98.75 10 142 .6 8
iii) 98.7510
Integer part
16 98
p
= (?) 16
e
S
16 6-2
0-6
M.S.B
9810 62 16
Fractional part
0.75 16 12.00 12 0.75 10 0.C 16
Therefore 98.7510 62.C 16
1.4.2 Base r to Decimal Conversion
Base-r numbers may be converted to their decimal equivalents by the positional weights method.
In this method each digit of the base-r number is multiplied with its positional weight and the
product terms are added to obtain the decimal number. The LSB in a base-r number has a weight
of r 0 1 and weights increases successively by a power of base-r for each digit from right to left
13
Digital System Design
in case of integer part. In case of fractional part the weights increases by a negative power of
base-r from left to right starting with ‘-1’.
Example-1: Convert the following numbers into Decimal
(a) 1101012 (b) 101101 .1011012 (c ) 362 8
(d) 6327.40518 (e) E6C416 (f) 3A.2F16
Sol. (a) 1101012
1101012 1x 2 5 1x 2 4 0 x 2 3 1x 2 2 0 x 21 1x 2 0 =32+16+0+4+0+1
5310
(b) 101101.1011012
1
32 0 8 4 0 1 0 0
1 1 1
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1x 2 5 0 x 2 4 1x 2 3 1x 2 2 0 x 21 1x 2 0 1x 2 1 0 x 2 2 1x 2 3 1x 2 4 0 x 2 5 1x 2 6
r
2 8 16 64
= 45+0.5+0.125+0.0625+0.015625 = 45+0.703125 = 45.703125
Therefore 101101 .1011012 45.703125 10
(c ) 2 1 0
c t
362 8 8 x 3 8 x 6 8 x 2 = 64x3+8x6+1x2 =192+48+2 = 242
Therefore 362 8 242 10
512 x 6 3x 64 2 x8 1x 7 e
(d) 6327 .40518 8 3 x 6 8 2 x 3 81 x 2 8 0 x 7 4 x8 1 0 x 8 2 5x 8 3 1x8 4
p
4
8
0
5
1
512 4096
3072 192 16 7 0.5 9.76x10 3 2.441x10 4 3287.5100110
(e) S
Therefore 6327.40518 3287.5100110
E6C4 16
Ex16 3 6 x16 2 Cx161 4 x16 0 14 x16 3 6 x16 2 12 x161 4 x16 0
14 4096 6 256 12 16 4 1 57344 1536 192 4 59076
Therefore E 6C 4 16 59076 10
(f) 3A.2 F 16
3x161 Ax16 0 2 x16 1 Fx16 2 3x16 10 x16 0 2 x16 1 15 x16 2
2 15
48 10 2 = 58+0.1836 = 58.1836
16 16
Therefore 3A.2 F 16 58.1836 10
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Number Systems, Boolean Algebra and Logic Gates
1.4.3 Binary - to-octal Conversion
For integer part of the number, binary numbers can be converted into equivalent octal numbers by
making groups of three bits starting for LSB and moving towards MSB, and then replacing each
group of three bits by its octal representation.
For fractional part, the groupings of three bits are made starting from the binary point and
proceeding to the right.
Example-2: Convert (1001110 ) 2 to its octal equivalent.
Sol. (1001110 ) 2
00
1 001
110
1 1 6
Therefore 1101012 116 8
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Example-3: Convert ( 0.10100110) 2 to its equivalent octal number..
Sol. (0.10100110 ) 2
=0.
101 001 100
5 1 4
0.514 8
Therefore (0.10100110) 2 0.514 8
r u
t
3. Convert the following binary to octal numbers.
a. 11001 110 001. 000 101 111001 (3161.0571)8
b.
e c
1011011110.11001010011 (1336 .6246 )8
c. 1 110 001.100 110 011 01 161 .4632 8
1.4.4 Binary to Hexadecimal Conversion
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Binary numbers can be converted into the equivalent hexadecimal numbers by making groups of
four bits starting from LSB and moving towards MSB for integer part and then replacing each
group of four bits by its hexadecimal representation.
For fractional part, the above procedure is repeated starting from the bit next to the binary
point and moving towards the right.
Example-4: Convert the following binary numbers to their equivalent hexadecimal num-
bers.
Sol.
0010 1001 1010 1111
a. 1010011010 11112 = 29 AF 16
2 9 A F
Therefore 1010011010 11112 = 29 AF 16
b. 0.0001111010 11012
0001 1110 1011 0100
0. 0.1EB4 16
1 E B 4
Therefore 0.0001111010 11012 0.1EB4 16
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Digital System Design
1.4.5 Octal to Binary Conversion
Octal numbers can be converted into equivalent binary numbers by replacing each octal digit by
its 3-bit equivalent binary.
Example-5: Convert 736 8 into an equivalent binary number..
Sol. 7368 7 3 6
111 011 110
Therefore 736 8 111011110 2
Since 2 3 8 , each octal digit corresponds to three binary digits.
Example-6: Convert the following octal numbers into binary.
a) 75 b) 6352.754
Sol.
a) 75 = 7 5
111 101
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Therefore 75 8 111101 2
b) 6352 .754 8
6 3 5 2 . 7
t r 5 4
110 011 101 010
c . 111
Therefore 6352 .754 8 1100111010 10.111101100 2
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1.4.6 Hexadecimal to Binary Conversion
101 100
a) 8BC
S p
Hexadecimal number can be converted into equivalent binary number by replacing each hexa
digit by its 4-bit equivalent number.
Example-7: Convert the following hexadecimal numbers into binary numbers.
b) 9C5E
Sol.
a) 8BC= (?)2
= 8 B C
1000 1011 1100
Therefore 8BC 16 1000101111 00 2
b) 9C5E= (?)2
= 9 C 5 E
1001 1100 0101 1110
Therefore 9C5E 16 1001110000 1011110 2
16
Number Systems, Boolean Algebra and Logic Gates
Example-8: Convert 2F9A16 to Equivalent binary number..
Sol. 2F 9A = (?)2
2 F 9 A
0010 1111 1001 1010
Therefore 2F9A 16 0010111110011010 2
1.4.7 Conversion from Hex-to-octal and Vice-versa
Hexadecimal numbers can be converted to equivalent octal numbers, first converting hexadeci-
mal number to binary by representing each hex number into 4 bit binary group, then making a
group of 3 bit binary in to octal equivalent number.
m
Hexadecimal numbers can be converted to octal numbers and octal numbers can be con-
verted to equivalent hex numbers by converting the hex/octal number to equivalent binary and
then octal/hex, respectively.
u
r
Example-9: Convert the following hex numbers to octal numbers.
a. A72E b. 0.BF85
Sol.
a) Given number = A72E
Equivalent binary = 1010 0111 0101 1110
c t
Making 3-bit group starting from LSB
= 001 010
p e
011 100 101 110 1 2 3 4 5 68
Therefore (A75E)16=(001010011101011110)2
S
b) 0.BF85 16 0.101111111000 01012
Given number = 0.BF85
Equivalent binary = 0.101111111000 0101
Making 3-bit group on both sides from binary point
= 0. 101 111 111 000 010 100
0.5770248
5 7 7 0 2 4
Example-10: Convert 247 .36 8 to equivalent hex number..
Sol. Given number = 247.36
Equivalent binary = 010100111.011110
Making 4-bit group on both sides from binary point
247 .36 8 101100111.011110 2 0 A 7.78 16 A 7.78 16
17
Digital System Design
Other Number Systems: The other number systems with bases 4, 6 and 12 the representation
of integers with these number systems with respect to decimal system is shown in below table.
Decimal Base 4 Base 6 Base 12
0 0 0 0
1 1 1 1
2 2 2 2
3 3 3 3
4 10 4 4
5 11 5 5
6
7
8
12
13
20
10
11
12
6
7
8
u m
9
10
11
21
22
23
13
14
15
t r 9
12
e c 30 20 10
Table-1.3: Representation of other number systems
Conversion of base -b to base -r number System: To convert a base -b to number to base-r
S p
we should follow two steps.
In step-1 we should convert base-b number to its equivalent decimal number using procedure
explained in converting any number base system to decimal conversion.
In step-2 we should convert the above decimal number (step-1) to base-r number using the
procedure explains in decimal to base-r conversion.
Example-11: Convert 49 6 12 in to Binary?
4 9 6
0100 1001 1010 01101011
49 6 12 0100100110 1001101011 2
Example-12: Convert 2034 into binary?
4 2 41 4 0
Sol.
2 0 3
4 2 2 41 x 0 41 3 16 2 4 x 0 1 3 32 0 3 = 35
2034 3510 x 2
18
Number Systems, Boolean Algebra and Logic Gates
2 35
2 17-1
2 8-1
2 4-0
2 2-0
2 1-0
0-1
3510 (100011) 2 2034 1000112
1.5 REPRESENTATION OF BINARY NUMBER
1. Signed Binary Number Representation
m
Binary numbers are represented with a separate sign bit along with the magnitude. For example,
in an 8 bit binary number, the MSB is the sign bit and the remaining 7 bits corresponds to magni-
tude.
Number
+13
Sign bit
0
Magnitude
000 1101
r u
Total Representation
00001101
t
-46 1 010 1110 10101110
-37 1 010 0101 10100101
2.
Binary Number
11011
e c
1’s Complement Representation: The 1’s complement form of any binary number is
obtained simply by changing 0 to 1 and 1 to 0.
1’s Complement
00100
3.
S p 1110011
tained by adding 1 to its 1’s complement.
2’s complement = 1’s complement + 1.
Binary Number
0001100
2’s Complement Representation: The 2’s Complement of binary number can be ob-
2’s Complement
11011 00100
1110011 0001101
Example-13: Represent the following decimal numbers as (a) sign and magnitude bi-
nary numbers (b) 1’s complement form (c) 2’s complement form
(i) 378 (ii) 12.25 (iii) -13.75
Sol.
(i) 378
The binary form of 37810 is 101111010 2 .
19
Digital System Design
(a) The sign and magnitude representation of 37810 is
0 101111010
Indicating the magnitude
Indicating the sign
(b) The 1’s complement form of 0101111010 is 0010000101
[Note: No need to complement the sign bit]
(c) The 2’s complement form of 0101111010 is 0010000110
(ii) 12.25
The binary form of 12.2510 is 1100 .012
(a) The sign and magnitude representation of 12.2510 is
0 1100.01
Indicating the magnitude
u m
r
Indicating the sign
(b) The 1’s complement form of 0 1100.01 is 1 0011.10
[Note: No need to complement the sign bit]
c
(c) The 2’s complement form of 0100.01 is
0 0 0 1 1 . 1 0
t
0 0 0 1 1
p
.
1
1 1
e
[Note: To find 2’s complement, 1 is added to the LSB bit]
The 2’s complement form of 01100.01 is 00011.112 .
S
(iii) -13.75
The binary form of 13.7510 is 1101 .112
(a) The sign and magnitude representation of -13.75 is
1 1101.11
Indicating the magnitude
Indicating the sign
(b) The 1’s complement form 1 1101.11 is 1 0010.00
[note: No need to complement the sign bit]
(c) The 2’s complement form of 11101.11 is
1 0 0 1 0 . 0 0
1
1 0 0 1 0 . 0 1
20
Number Systems, Boolean Algebra and Logic Gates
[Note: Find 2’s complement, 1 is added to the LSB bit]
The 2’s complement form of 11101.11 is 10010.012
1.6 COMPLEMENTS
Complements are used in digital computers for simplifying the subtraction operation and for logi-
cal manipulation. There are two types of complements.
(i) r’s complement (ii) (r-1)’s complement
Where r is the base of the respective number system.
For binary number (Base = r = 2), we have the following complements.
1. 2’s complement (r’s complement) 2. 1’s complement ((r-1)’s complement)
For decimal numbers (Base = r = 10), we have the following complements.
m
1. 10’s complement (r’s complement) 2. 9’s complement ((r-1)’s complement)
1.6.1 1’s Complement
u
The 1’s complement of given number can be obtained by simply changing all 1’s into 0’s and 0’s
into 1’s.
Sol.
Binary Number r
Example-14: Find the 1’s complement of the Binary numbers 0101, 00011, 11111110.
t 1’s Complement
0101
00011
1111 1110
1.6.2 1’s Complement Arithmetic
e c 1010
11100
0000 0001
p
Subtraction of two binary numbers can be accomplished by using 1’s complement method, which
allows us to subtract using only addition. Two basic situations arise in subtractions.
S
(a) To subtract a smaller number from a larger number.
(b) To subtract a large number from a smaller number.
(a) To Subtract a Smaller Number from a Larger Number: Subtraction of two binary using
1’s complement can be performed by the following steps.
(i) Take 1’s complement to the smaller number.
(ii) Add the 1’s complement to the larger number
(iii) Remove the carry and add carry to the result. This is called end-around carry.
Example-15: Subtract the following binary number using 1’s complement method.
(i) 1100 from 1111 (ii) 1010 from 1110
Sol. (i) 1100 from 1111
Step-1: Take 1’s complement to the smaller number.
Binary 1’s Complement
1100 0011
21
Digital System Design
Step-2: Add the 1’s complement to the larger number.
1111
0011
Carry bit 1 0010
Step-3: Remove the carry and add carry to the result.
1111 Direct Subtraction
0011 1111
1 0010 1100
+ 1 0011 = 3
0 0 1 1 = 3 in decimal
Verification
Bianry
1111
1100
0011
Decimal
15
-12
3
u m
(ii) 1010 from 1110
Smaller value is 1010.
1’s complement of 1010 is 0101.
t r
c
1110 Direct Subtraction
0101 1110
e
1 0011 1010
+ 1 0100 = 4
p
0 1 0 0 = 4 in decimal
Verification
Bianry Decimal
1110
1010
0100
S 14
-10
4
(b) To subtract a large number from a smaller number.
Subtraction of two binary using 1’s complement can be performed by the following steps.
(i) Take the 1’s complement for the large number.
(ii) Add the 1’s complement to the smaller number.
(iii) The answer has a opposite sign and is the 1’s complement of the result. There is no carry.
Example-16: Subtract (i) 1111 from 1100 and (ii) 1110 from 1010.
Sol.
(i) 1111 from 1100
Here large number is 1111 0000 is 1’s complement form.
22
Number Systems, Boolean Algebra and Logic Gates
1's complement method Direct Subtraction
0000 1100
+ 1100 - 1111
+1100 - 0011
Take 1’s complement for 1100 0011 is the result.
(ii) 1110 from 1010
1's complement method Direct Subtraction
0001 1010
+ 1010 - 1110
+1011 - 0100
Take 1’s complement for 1011 0100 is the result.
1.6.3 2’s Complement
number and adding 1 to the least significant bit (LSB) position.
2’s complement = 1’s complement + 1
u m
The 2’s complement form of a binary number is formed by taking the 1’s complement of the
Sol. (i) 1101
Bianry number 1101 r
Example-17: Find 2’s complement for a given binary number 1101 and 1010.
t
c
1's complement 0010
+1
e
2's complement 0011
(ii) 1010
p
Bianry number 1010
1's complement 0101
+1
S
2's complement 0110
1.6.4 2’s Complement Arithmetic
Arithmetic operation using 2’s complement is illustrated by the following example.
Example-18: Add the following decimal number using binary addition.
(i) 12 +4 (ii) 12+(-4) (iii) (-12)+4 (iv) (-12) + (-4)
Sol.
(i) 12 + 4
Decimal Binary
1
12 1100
+
4 0100
16 10000
23
Digital System Design
(ii) 12 + (-4)
For a signed decimal addition using binary numbers. Follow the following rules.
(i) Take the two numbers in binary form (size should be 8 bits).
(ii) Take 2’s complement for a negative signed number.
(iii) Add the positive number and 2’s complement number.
(iv) Addition will be the result. If the result will be a negative signed number, then the result is 2’s
complement of the number.
12 0000 .1100 4 0000 .0100
For (-4) take 2’s complement to the binary value of 4.
0000 0100 Add 12+(-4)
1's Complement 1111 1011 12 00001100
m
+ 1 -4 11111100
2's Complement 1111 1100 (-4) +8 00001000
u
iii. - (12) + (4)
Take 2’s complement to the 12.
1's Complement
12
0000 1100
1111 0011
+ 1
-12
4
-8
t r
00001100
11111100
00001000
c
2's Complement 1111 0100
Since the addition was result in negative number, so the produced result will be in 2’s comple-
e
ment of 8.
To verify the result, take 2’s complement of 8.
p
8 0000 1000
1's Complement 1111 0111
S
+ 1
2's Complement 1111 1000 = (-8)
The 2’s complement of 8 and resultant values of (-12) + 4 is equal. Hence the addition was
found correct.
(v) - (12) + (-4)
Here both the numbers are negative numbers. Hence take 2’s complement of 12 and 4.
12 0000 1100 4 0000 0100
1111 0011 1111 1011
1 1
-12 1111 0100 -4 1111 1100
-12 1111 0100
-4 1111 1100
-16 1111 0000
24
Number Systems, Boolean Algebra and Logic Gates
Since the addition results in negative number, the produced result will be in 2’s complement
of 16.
To verify the result, take 2’s complement of 16.
16 0001 0000
1's Complement 1110 1111
1
2's Complement 1111 0000 = (-16)
The 2’s complement of 16 and resultant value of (-12) + (-4) is equal. Hence the addition
was found correct.
1.6.5 9’s Complements
The 9’s complement of decimal number is found by subtracting each digit in the number from 9.
The 9’s complement of decimal digit 0 to 9 is shown in the below table 1.4.
Decimal digit
0
9’s complement
9
u m
r
1 8
2 7
3
4
5
6
c t 6
5
4
3
e
7 2
8 1
p
9 0
Table-1.4: 9’s Complement of decimal numbers
Example-19: Find the 9’s complement of the following decimal number.
Sol.
(i) 8
S (ii) 27 (iii) 368 (iv) 4516
To find 9’s complement, subtract each decimal digit from the value 9.
(i) 8
Here only one digit is there
(ii) 27
Here two digits are there, so
9 99
-8 -27
1 9's complement of 8 72 9's complement of 27
(iii) 368 (iv) 4516
999 9999
-368 -4516
631 9's complement of 368 5483 9's complement of 4516
25
Digital System Design
1.6.6 9’s Complement Arithmetic
The 9’s complement can be used to perform the arithmetic operation of the decimal numbers.
Example-20: Perform subtraction of the given decimal number using 9’s complement.
(i) 5 from 9 (ii) 16 from 25 (iii) 18 from 11
Sol.
(i) 5 from 9
9's Complement Direct Subtraction
Take 9's complement of 5 9
5 4 is 9's complement of 5 -5
Carry 1
9
4
3
4
u m
r
+1
4
t
(ii) 16 from 25
99 Direct Subtraction
16
83
25
83
e c
9's complement of 16 25
16
09
p
Carry 1
08
+1
S
(iii) 18 from 11
99
18
81
09
9's complement of 18
Direct Subtraction
11
-18
-07
11
81
92
Negative sign indicated in 9’s complement
99
92
- 07
26
Number Systems, Boolean Algebra and Logic Gates
1.6.7 10’s Complement
The 10’s complement of decimal number is obtained by 9’s complement plus 1.
10’s complement = 9’s complement + 1
Example-21: Find the 10’s complement of the following decimal number.
(i) 6; (ii) 64 (iii) 562 (iv) 4621
Sol.
(i) 6 (ii) 64
6 64
9 99
-6 - 64
3 35
+1
(iii) 562
4 10's complement of 6
(iv) 4621
+1
36
m
10's complement of 64
u
r
562 4621
999 9999
t
- 562 4621
437 5378
c
+1 +1
438 10's complement of 562 5379 10's complement of 4621
e
1.6.8 10’s Complement Arithmetic
10’s complement can be used to perform arithmetic operation of the decimal numbers.
p
Example-22: Perform the subtraction of the given decimal number using 10’s comple-
ment.
S
(i) 6 from 9 (ii) 16 from 25 (iii) 18 from 11
Sol.
(i) 6 from 9
10's complement of 6 is 4 Direct Subtraction
9 9
+4 6
Carry 1 3 3
Discard carry, hence result is 03
(ii) 16 from 25
10's complement of 16 is 84 Direct Subtraction
25 25
+ 84 16
Carry 1 09 09
27
Digital System Design
(iii) 18 from 11
10's complement of 18 is 82 Direct Subtraction
11 11
+ 82 -18
93 -07
Result is negative signed number
Take 10’s complement of 93.
Negative sign indicate 10’s complement
99
93
m
06
+1
-07
Hence result is -07.
1.7 BINARY CODES
r u
c t
A code is symbolic representation of an information transform. The bit combinations are referred
to as ‘WORD’ or code WORDS. Coding and encoding is the process of assigning a group of
binary digits. Encoding of information can be complicated and involved process particularly when
data security is of importance. Digital systems represent and manipulate not only binary numbers,
e
but also many other discrete elements of information. Any discrete element of information distinct
among a group of quantities can be represented by a code known as “binary code”. There are
many different coding schemes, each having some particular advantages and characteristics. To
p
represent a group of ‘ 2 n ’ distinct elements in a binary code requires a minimum of ‘n’ bits. For
Example a group of 16 distinct elements can be represented by 16 2 4 , n 4 a four bit code.
S
Digital data is represented, stored and transmitted as group of binary (digits) bits, also known
as binary codes these codes are classified as
1. Numeric codes 2. Alphanumeric codes
1. Numeric codes: Numeric codes are codes which represent numeric information i.e., only
numbers as a series of 0’s and 1’s numeric codes are further classified into.
(a) Weighted codes. (b) Non weighted codes
(c) Self complementing codes. (d) Cyclic codes
(e) Reflective codes. (f) Error detecting and correcting codes.
(a) Weighted code: The weighted codes are those which obey the position weighting principle.
Each digit position of the number represents a specific weight. For Example: BCD code,
2421, 5211 codes etc.
28
Number Systems, Boolean Algebra and Logic Gates
BCD is an abbreviation for Binary Coded Decimal. The most common BCD code is 8-4-2-
1 BCD, in which each decimal digit is represented by a 4 bit binary number
Binary Coded Decimal (BCD): Binary coded Decimal is a way to express each of the decimal
digits with a binary code. There are only ten code groups in the BCD system, so it is very easy to
convert between decimal and Binary coded Decimal.
The 8421 is a type of BCD code, the designation 8421 indicates the weight of four bits
2 ,2 ,2 ,2 .
3 2 1 0
BCD code
Decimal digit
8 4 2 1
0 0 0 0 0
1
2
3
4
0 0 0 1
0 0 1 0
0 0 1 1
0 1 0 0
u m
5
6
7
0 1 0 1
0 1 1 0
0 1 1 1
t r
c
8 1 0 0 0
9 1 0 0 1
e
Table-1.5: Representation of BCP numbers
The remaining combination i.e., 1010, 1011, 1100, 1101, 1110 and 1111 are invalid. In 4-bit
BCD code ten are valid and 6(six) are invalid.
bit BCD code.
S p
Decimal to BCD Conversion
To express any decimal number in BCD, simply replace each decimal digit with the appropriate 4-
Ex: convert each of the following decimal numbers to BCD .
a) 35
For 3 0011 5 0101
3510 00110101 BCD representation
b) 2469
2 4 6 9 Decimal
0010 BCD
0100 0110 1001
2469 10 0010 0100 0110 1001in BCD
29
Digital System Design
BCD to Decimal Conversion: To represent a given BCD code in to its equivalent decimal,
consider the right bit (LSB) and break the code in to group of four bits, then write the equivalent
decimal represented by each 4-bit group.
Ex: Convert each of the following BCD codes to decimal
a. 10000110
1000 0110 BCD code
8 6 Decimal
b.
10000110 BCD 86 10
1001010001110000
1001 0100 0111 0000 BCD code
u m
9 4 7 0
1001010001 110000 BCD 9470 10
Decimal
t r
e c
BCD Addition: BCD is a numerical code and can be used in arithmetic operations. Addition is
the most important operation because the other three operations ( subtraction, multiplication and
division)m can be accomplished by the use of addition.
p
The steps to accomplish the BCD addition are.
S
Step-1: Add the two BCD numbers, using the rules for binary addition.
Step-2: If a 4-bit sum is equal to or less then ‘9’. It is a valid BCD number
Step-3: If a 4-bit sum is greater than ‘9’, or if a carry out of the 4-bit group is generated, it is an
invalid result. Add ‘6’ (0110) to the 4-bit sum in order to skip the six invalid states and
return the code to 8421 BCD.
If a carry results when ‘6’ is added, simply add the carry to the next 4-bit group.
Ex: add the following BCD numbers
1. 0011+0100
0111 3
0100 4
0. 1 1 1 7
30
Number Systems, Boolean Algebra and Logic Gates
i.e., valid
2. 00100011+00010101
00100011 +0001 0101
111
00100011 2 3
+ 00010101 +1 5
00111000 3 8
In the result we did not get a value >9, so the result is a valid BCD.
2. 0110 0111+0101 0011
m
0110 0111
0101 0011
1 111
1011 1010
here both are invalid, so
r u
t
11111 11
1011 1010
0110 0110
00010010 000
e c
(120)10
in addition to 8421 weighted BCD code, there are some other weighted codes, those are 2421,
3321, 5211, 4311, 84-2-1, 64-2-3 etc.
p
Decimal 2 4 2 1 4 3 1 1 5 2 1 1 8 4 -2 -1 6 4 -2 -3
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
0 0 0 0
S
1 0 0 0 1 0 0 0 1 0 0 0 1 0 1 1 1
0 1 0 1
2 0 0 1 0 0 0 1 1 0 0 1 1 0 1 1 0
0 1 1 0
3 0 0 1 1 0 1 0 0 0 1 1 0 0 1 0 1
1 0 0 1
4 0 1 0 0 0 1 1 0 0 1 1 1 0 1 0 0
0 1 0 0
5 1 0 1 1 1 0 0 1 1 0 0 0 1 0 1 1
1 1 1 1
6 1 1 0 0 1 0 1 1 1 0 0 1 1 0 1 0
1 0 0 0
7 1 1 0 1 1 1 0 0 1 1 0 0 1 0 0 1
1 1 0 1
8 1 1 1 0 1 1 1 0 1 1 1 0 1 0 0 0
1 1 1 0
9 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1
Table-1.6: Weighted BCD code
In the above table, except 64 - 2 - 3, remaining all are weighted BCD codes.
Observation
2421, 4311, 5211, 84-2-1 are self-complementing and weighted codes.
For 4311 BCD code 1 0001 .
31
Digital System Design
The 9’s complement of ‘1’ is 9 - 1=8.
The equivalent code of ‘8’ in 4311 can be obtained just by changing 0’s and 1’s of 1 0001
i.e., "1110 " 8
(b) Non weighted code: Non - weighted codes are codes which are not assigned with any
weight to each digit position.
Example: Excess -3 code, gray code.
Excess-3 (Ex-3) Code: It is a sequential and non weighted BCD code. A decimal code that has
been used in some computers is the excess-3 code. This is an “unweighted code” and also not a
self-complementing code. Its code assignment is obtained from the corresponding value of BCD
after the addition of ‘3’ (0011). i.e., It is derived by adding 3 to each decimal digit and then
converting the result into 4-bit binary as shown in below table 1.7.
m
Decimal BCD Excess-3
8 4 2 1
u
0 0 0 0 0 0 0 1 1
1 0 0 0 1 0 1 0 0
2
3
4
0 0 1 0 0 1 0 1
t
0 0 1 1 0 1 1 0
0 1 0 0 0 1 1 1
r
c
5 0 1 0 1 1 0 0 0
6 0 1 1 0 1 0 0 1
e
7 0 1 1 1 1 0 1 0
8 1 0 0 0 1 0 1 1
9 1 0 0 1 1 1 0 0
S p Table-1.7: Representation of ex-3code
In excess-3, 0000, 0001, 0010, 1101, 1110, and 1111 are invalid codes i.e, 10 are valid codes
and 6 are invalid codes out of total 16 codes.
To express any decimal number in Excess-3, simply replace each decimal digit with the
appropriate 4-bit binary code and then add 4-bit binary of 3.
Example-23: Convert the following decimal numbers in to Excess-3 code.
(a) 23 b) 643
Sol.
a) 23
2 3
+3 +3
5 6
Binary of 5=0101
Binary of 6=0110
Therefore excess 3-code for given decimal number 23 is 01010110.
32
Number Systems, Boolean Algebra and Logic Gates
b) 643
6 4 3
+3 +3 +3
9 7 6
Binary of 9 = 1001
Binary of 7 = 0111
Binary of 6 = 0110
Therefore excess 3-code for given decimal number 643 is 100101110110.
Gray Code: The gray code is an unweighted code i.e. there are no specific weights assigned to
the bit positions. It is a “cyclic code” and not a self-complementing code. Gray code is a special
case of unit distance code ,In unit distance code bit patterns for two consecutive numbers differ
in only one bit position
Binary to Gray Code Conversion
Decimal
0 0 0
Binary
0 0 0 0 0
Gray
u m 0
1
2
3
4
0
0
0
0
0
0
0
1
0
1
1
0
1
0
1
0
0
0
0
0
t r
0
0
0
1
0
1
1
1
1
1
0
0
c
5 0 1 0 1 0 1 1 1
6 0 1 1 0 0 1 0 1
e
7 0 1 1 1 0 1 0 0
8 1 0 0 0 1 1 0 0
9 1 0 0 1 1 1 0 1
10
11
12
S
13
14
15
p 1
1
1
1
1
1
0
0
1
1
1
1
1
1
0
0
1
1
0
1
0
1
0
1
1
1
1
1
1
1
1
1
0
0
0
0
1
1
1
1
0
0
Table-1.8: Representation of 4 bit binary into gray
1
0
0
1
1
0
The rules for converting binary to gray code are
1. The most significant bit (MSB) in the gray code is the same as the corresponding MSB in the
binary number.
2. Going from left to right, add each adjacent pair of binary code bits and the sum bit to get the
next gray code bit, and discard carries.(or)Ex-OR operation of adjacent pair of binary code
bits.
For a binary number B3 B 2 B1B0 the equivalent gray code was G 3 G 2 G 1G 0 then converted
as by the equations
G3=B3 G2=B3 B2 G1=B2 B1 G0=B1 B0
33
Digital System Design
Ex: convert the binary 10110 to equivalent gray code. Ex-OR truth table
X Y Output
Binary 1 + 0 + 1 + 1+ 0 0 0 0
0 1 1
1 0 1
Gray code 1 1 1 0 1 1 1 0
Gray to Binary Conversion: Rules for converting gray to binary code are.
1. The most significant bit (MSB) in the binary is the same as the corresponding bit in the gray
code.
2. Add each binary code bit generated to the gray code bit in the next adjacent position and
write the sum as next binary bit, discard carries.(or) EX-OR operation of each binary code
bit generated to the gray code bit in the next adjacent position.
converted as by the equations
B3=G3 B2=B3 G2
u m
For a given gray code of G 3G 2 G 1G 0 the equivalent binary code was B 3 B 2 B1B 0 then
r
B1=B2 G1 B0=B1 G0
Ex: convert gray code 11011 to binary
t
The binary to gray and gray to binary conversion can be performed using “modulo-2 sum”
procedure. The symbol for modulo-2 sum is , and it is defined as follows.
0 0 0; 0 1 1;
c
e
1 0 1; 1 1 0
Convert 11010 2 to gray
p 1 1 0 1 0
Gray
+ + + +
S
Binary 1 0 0 1 1
Another property that the gray code got is, it is a “reflected code” i.e., 3-bit gray code can be
constructed using 2-bit gray code and 4-bit gray code can be constructed using 3-bit gray code.
Self Complementing Code: Self-complementing codes provide the 9’s complement of a deci-
mal number, just by interchanging 1’s and 0’s in its equivalent 2421 representation. 2421, the
excess 3 and the 84-2-1 codes are examples of self complementing codes.
Cyclic Codes: Cyclic codes are those in which each successive code word differs from the
preceding one in only one bit position they are also called “unit distance codes”.
Ex: gray code.
Reflective Codes: Reflective code is a code in which the n-bit code can be represented by
reflecting the (n-1) st -bit code. i.e., the 3-bit code can be obtained by reflecting the 2-bit code
about an axis at the end of the code, and assigning a MSB of ‘0’ above the axis and ‘1’ below the
axis.
Ex: Ex-3, 5211 etc.
34
Number Systems, Boolean Algebra and Logic Gates
Sequential Code: In Sequential codes each succeeding code is one binary number greater than
its preceding codes. The 8421 BCD code and Gray codes are sequential codes
2. Alphanumeric Codes: Alphanumeric codes are codes which represent alphanumeric in-
formation i.e letters of the alphabet and decimal numbers as a sequence of 0’s and 1’s.
Ex: ASCII, EBCDIC.
Many applications of digit computers require the handling of data not only of numbers, but
also of letters. To represent the names and other information, it is necessary to formulate a binary
code for the letters of the alphabet, numerals and special characters. i.e alphanumeric codes are
used to encode the characters of alphabet and special characters in addition to the decimal num-
bers.
m
Alphanumeric codes are used primarily for transmitting data between computers and its I/O
devices such as printers, keyboards and video display terminals. The most popular modern alpha-
numeric, codes are.
u
r
1. ASCII 2. EBCDIC
1. ASCII: ASCII stands for “ American standard code for information interchange”. it uses 7
being the most-significant bit.
c t
bits to code 128 characters. The 7-bits of the code are designated by b1 through b 7 , with b 7
The ASCII code contains 94 graphic characters that can be printed and 34 nonprinting
e
characters used for various control functions. The graphic characters consist of the 26 uppercase
letters (A to Z, the 26 lowercase letters (a to z), the 10 numbers ( 0 to 9) and 32 special printable
charcters such as %, $ etc.
For uppercase
S p
A 65 10 100001 4116
Z 90 10 1011010 5A 16
For lower case alphabets
a 97 10 1100001 6116
to
to
z 122 10 1111010 7 A 16
For numerical digits
0 48 10 0110000 30 16 to
9 57 10 0111001 39 16
American standard code for information interchange (ASCII) is a standardized code used in
most microcomputer by its manufacturers. The ASCII code represents a character with 7 bits,
which can be stored as one byte with one bit unused. The unused extra bit is often used to extend
the ASCII code to represents an additional 128 characters.
35
Digital System Design
The format of the ASCII code is A 6 A 5 A 4 A 3A 2 A1A 0 , where each bit is a ‘0’ or a ‘1’. For
example the letter A is coded as 100 0001, and B is coded as 100 0010 etc.
Character 7-bit ASCII Character 7-bit ASCII
Blank 010 0000 > 011 1110
! 010 0001 ? 011 1111
“ 010 0010 A 100 0001
$ 010 0100 B 100 0010
% 010 0101 C 100 0011
& 010 0110 D 100 0100
‘ 010 0111 E 100 0101
( 010 1000 F 100 0110
) 010 1001
m
G 100 0111
* 010 1010 H 100 1000
+ 010 1011 I 100 1001
u
, 010 1100 J 100 1010
- 010 1101 K 100 1011
0
1
.
/
010 1110
010 1111
011 0000
011 0001
t r M
L
N
O
100 1100
100 1101
100 1110
100 1111
2
3
4
5
6
011 0001
011 0011
e
011 0100
011 0101
011 0110
c P
Q
R
S
T
101 0000
101 0001
101 0010
101 0011
101 0100
S p
7
8
9
<
:
;
011 0111
011 1000
011 1001
011 1010
011 1011
011 1100
W
U
V
X
Y
Z
101 0101
101 0110
101 0111
101 1000
101 1001
101 1010
= 011 1101
Table-1.9: ASCII codes
2. EBCDIC code: EBCDIC stands for “Extended Binary Coded Decimal Interchange Code”.
It uses 8-bits to codes 28 256 characters. This is used to encode all the symbols and
control characters found in ASCII. It encodes many other symbols too. In fact, many of the
bit patterns in the EBCDIC code are unassigned. It is used by most large computers to
communicate in alphanumeric data.
Another alphanumeric code used in IBM equipment is the EBCDIC or Extended Binary
Coded Decimal Information Code. It differs from ASCII only in its code grouping for the different
alphanumeric characters. It uses eight bits for each character and a ninth bit for parity.
Error Detecting and Correcting Codes: Error detection codes “ are used to detect the errors
present in the received data bitstream. These codes contain some bits, which are included ap-
36
Number Systems, Boolean Algebra and Logic Gates
pended to the original bit stream. These codes detect the error, if it is occurred during transmis-
sion of the original data bitstream. Codes which allow error detection as well as error correction
are called error correcting codes.
Ex: Hamming code.
When the digital information in the binary form is transmitted from one system to another
system an error may occur. This means a signal corresponding to ‘0’ may change to ‘1’ or ‘1’ may
change to ‘0’. To maintain the data integrity between transmitter and receiver, extra bit or more
than one bit is added in the data. These extra bits allow the detection and sometimes correction of
error in the data. The most simple and commonly used error detecting method is the parity check.
The parity check method is classified into (i) Odd parity method (ii) Even parity method.
In the even parity method the total number of 1’s in the code group (including the parity bit)
must be an even number. Similarly in the odd-parity method, the total number of 1’s (including the
parity bit) must be an odd number.
The parity bit can be placed at either end of the code word, such that the receiver should be
able to understand the parity bit and the actual data.
Message
1000001
Even parity code
01000001
Odd parity code
11000001
u m
r
1010100 11010100 01010100
c
Parity bit
t
Table-1.10: Message with even and odd parity bit
The parity of each character is checked in the receiving end. This detects the presence of
error in the received message. This method detects one, three or any odd combination of errors.
p
(Parity Check Code & Hamming Code)
3-bit
e
Hamming code is used in detection and correction of error.
1.7.1 Error Dectecting and Correcting Codes
S
Message with odd parity Message with even parity
message
A B C Message Parity Message Parity
0 0 0 000 1 000 0
0 0 1 001 0 001 1
0 1 0 010 0 010 1
0 1 1 011 1 011 0
1 0 0 100 0 100 1
1 0 1 101 1 101 0
1 1 0 110 1 110 0
1 1 1 111 0 111 1
Table-1.11: Message with even and odd parity
37
Digital System Design
Example-24: 1) For Decimal digit 9 write ASCII code with even parity?
Sol. The decimal digit 9
ASCII code for given decimal digit is 0111 001
The added parity bit 00111001
Example-25: ASCII code for alphabet A with an odd parity.
Sol. 7-bit ASCII code for alphabet ‘A’ is 1000001.
Added parity bit 11000001
1.7.2 Hamming Codes
Hamming code is used to detect the error in the transmitted data. So it is an “Error Detection &
m
Correction Code”.
It was originally invented by Richard W. Hamming in the year 1950. Hamming codes detect
u
1-bit.
While Transmitting the message, it is encoded with the redundant bits. The redundant bits are
t r
the extra bits that are placed at certain locations of the data bits to detect the error. At the receiver
end, the code is decoded to detect errors & the original message is received.
So before Transmitting, the sender has to encode the message with the redundant bits. It
involves the following steps:
e c
Encoding the message with hamming code selecting the number of redundant bits
The hamming code uses the number of redundant bits depending on the no. of information bits in
the message.
S p
Let n be the number of information or data bits, then the number of redundant bits P is
determined from the formula
2P n P 1
Example: If a 4-bit information is to be transmitted, then n=4. The number of redundant bits is
determined by the trial and error method.
Let P 2 22 4 2 1
P 2 is wrong
Similarly try P=3
23 4 3 1 8 8
P 3 is correct
Choosing the location of Redundant Bits
For n=4 bits, we use 3 redundant bits by following 2 p n p 1 .
Let the right most bit be designated as bit 1, the next successive bit as bit 2 and so on.
The seven bits are bit 7, bit 6, bit 5, bit 4, bit 3, bit 2, bit 1.
38
Number Systems, Boolean Algebra and Logic Gates
In this the redundant bits are placed at the positions that are numbered corresponding to the
power of 2, i.e.., 1, 2, 4, 8. Thus the locations of data bit and redundant bit are
D 4 , D 3 , D 2 , P3 , D1 , P2 , P1.
Assigning the Values to Redundant Bits
Now it is time to assign bit value to the redundant bits in the formed hamming code group. The
assigned bits are called a parity bit.
Each parity bit will check certain other bits in the total code group.
Bit location:- 7 6 5 4 3 2 1
Bit Designation D4 D3 D2 P3 D1 P2 P1
Binary 111 110 101 100 011 010 001
u m
r
Parity Bits
P3 P2 P1
t
Parity bit P1 covers all data bits in positions whose binary representation has 1 in the least
significant position (001, 011, 101, 111, etc.) Thus P1 checks the bit in locations 1,3,5,7,9,11 etc..,
c
Parity bit P2 covers all data bits in positions whose binary representation has 1 in the second
e
least significant position (010, 011, 110, 111 etc..,). Thus P2 checks the bit in locations 2, 3, 6, 7,
etc.
etc..,
S p
Parity bit P3 covers all data bits in positions whose binary representation has ‘1’ in the third
least significant position (100, 101, 110, 111, etc..,). Thus P3 checks the bit in locations 4, 5, 6, 7
Each parity bit checks the corresponding bit locations and assign the bit value as ‘1’ or ‘0’.
So as to make the number of 1’s as even for even parity and odd for odd parity.
Example-26: Encode a binary word 11001 into the even parity Hamming code.
Sol.
Given, number of data bits, n=5
To find the number of redundant bits,
Let us try P=4
24 5 4 1
The equation is satisfied and so 4 redundant bits are selected.
39
Digital System Design
So, total code bit n p 9
The redundant bits are placed at bit positions 1, 2, 4 and 8.
Construction the bit location table
Bit location 9 8 7 6 5 4 3 2 1
D5 P4 D4 D3 D2 P3 D1 P2 P1
Bit Binary 1001 1000 0111 0110 0101 0100 0011 0010 0001
1 P4
P1 : P1 D1 D 2 D 4 D5 0
1 0 0
P1 1 0 1 1 0 P1 1 0 P1 0 1 1
P2 : P2 D1 D 3 D 4 0
P3 1
u m P2 P1
P2 1 0 1 0 P2 0 0 P2 0 0 0
P3 : P3 D 2 D3 D 4 0
P3 0 0 1 0 P3 1 0 P3 0 1 1
t r
c
P4 : P4 D 5 0 P4 1 0 P4 0 1 1
The encoded 9-bit hamming code is 111001101
e
How to Detect and Correct the Error in the Hamming Code
p
After receiving the encoded message, each parity bit along with its corresponding group of bits
are checked for proper parity. While checking, the correct result of individual parity is marked as
‘0’ and the wrong result is marked as ‘1’.
S
After checking all the parity bits, a binary word is formed talking the results bits for P1 as
LSB. So formed binary word gives the bit location, where there is an error.
Example-27: Let us assume the even parity hamming code from the above example
(111 00 11 01) is transmitted and the received code is (110001101). Now from the
received code, let us detect and correct the error.
Bit location 9 8 7 6 5 4 3 2 1
Bit Designation D5 P4 D4 D3 D2 P3 D1 P2 P1
Binary 1001 1000 0111 0110 0101 0100 0011 0010 0001
Received code 1 1 0 0 0 1 1 0 1
40
Number Systems, Boolean Algebra and Logic Gates
Calculate the parity bits
P1 : P2 :
1 + 3 + 5 + 7 + 9 2 + 3 + 6 + 7
P1 + D1 + D2 + D4 + D5 P2 + D1 + D3 + D4
1 + 1 + 0 + 0 + 1 0 + 1 + 0 + 0
= 1 = 1
P3 : P4 :
4 + 5 + 6 + 7
P3 + D2 + D3 + D4 8 + 9
=
1 + 0 + 0 + 0
1
P4 0 (P4 P3 P2 P1)2 = (0 1 1 1)2 =(7)10
P4 + D5
1 + 1 =0
u m
i.e.., Error is in 7 th position.
i.e.., Bit value ‘0’ in 7 th position is wrong
t r
c
Correct code word is = 1 1 1 0 0 1 1 0 1
Example-28: A 7 bit hamming code is received as 1011011. Assume even parity & state
e
whether the received code is correct (or) wrong, if wrong locate the bit in error.
Sol. Hence parity is even parity. Received hamming code is
1
D7
Detecting Errors
S p D6
0
Step-1: Analyzing bits 1, 3, 5, 7.
We have
D5
1
P4
1
D3
0
P2
1
P1
1
P1 D 3 D 5 D 7 1011
Odd parity
error exists
Now keep P1 1 .
Step-2: Analyzing bits 2, 3, 6, 7.
P2 D 3 D 6 D 7
1 0 0 1
So, P2 0 .
Even parity
no error
No error.
41
Digital System Design
Step-3: Analyzing bits 4, 5, 6 & 7.
We have
P4 D 5 D 6 D 7
1 1 0 1
Odd parity
error exists
Keep P4 1 .
P4 & P1 are not equal to zero, so received code is wrong.
Correcting errors: Error word (E) =
P4 P1 P1
1 0 1
m
decimal
value 5
u
Which shows that the 5th bit is in error so we write the correct word by simply inverting the
5th bit.
Correct word is 1001011
t r
Example-29: A bit word 1011 is to be transmitted construct the even parity seven-bit
hamming code for this data.
Sol. Code word format
7
D7
1
e c 6
D6
0
5
D5
1
4
P4
3
D3
1
2
P2
1
P1
S p
Calculation of P1
Consider the position:
1, 3, 5, 7
1 1 1 1
To be decided
Here it was given even parity.
so keep P1 1 .
Calculation of P2
Consider the positions:
2, 3, 6, 7
0 1 0 1
Keep P2 0 .
42
Number Systems, Boolean Algebra and Logic Gates
Calculation of P4
Consider bits :
4, 5, 6, 7
0 1 0 1
Keep P4 0 , because it was even parity..
Final code word is
1010101
Example-30: Encode the data (or) message bits 0011 into the 7-bit even parity ham-
ming code.
Sol.
Given message = 0011
No. of message bits m = 4.
u m
No. of parity bits required to calculate is given by
2P m p 1
p3
t r
c
3
2 4 3 1
8 8 True .
So, no. of parity bit, p = 3.
Total no. of bits = m + p = 4 + 3 = 7
7
D7
p 6
D6 D5
e
5 4
P4
3
D3
2
P2
1
P1
S
0 0 1 1
Calculation of P1
Consider the position 1, 3, 5,7
P1 ,1, 1, 0
It is even
parity
Keep P1 0
Calculation of P2
Consider the position 2, 3, 6, 7
P2 ,1, 0, 0
Keep P2 1 , to maintain even parity
43
Digital System Design
Calculation of P4
Consider bit positions 4, 5, 6, 7
P3 ,1, 0 ,0
Keep P3 1
Error position
= P4 P2 P1
1 0 0
Decimal value = 4.
So error is located at 4th position.
Total message bits
=0011100
u m
After correcting
Error position
Message bits = 0010100.
t r
Sol. Given hamming code is
010110110
e c
Example-30: The Hamming code 010110110 is received at the receiving end, correct
the received data if there is any error.
p
This data is a combinatio n of
message bits & parity bits .
9 8 7 6 5 4 3 2 1
D9
0
S1
P8 D7
0
Parity Bits P8 P4 P2 P1
1 0 1 0
Message Bits D 9 D 7 D 6 D 5 D 3
D6
1
D5
1
P4
0
D3
1
P2
1
P1
0
0 0 1 1 1
Consider odd parity here.
P1
Consider the bit positions : P1 , 3, 5, 7, 9.
P1 3 5 7 9
11 0 0 0
44
Number Systems, Boolean Algebra and Logic Gates
Similarly P2 3 6 7
11 0 0
P4 5 6 7
11 0 0
P8 9 0
P8 P4 P2 P1
Parity bits that are calculated = 0 0 0 0
Parity bits in given message = 1 0 1 0
We are getting the error at 2nd & 8th positions.
Message after calculating parity bits 0 0 0 1 1 0 1 0 0
Received message 0 1 0 1 1 0 1 1 0.
Error is located at 2nd & 8th positions.
The correct data after detecting the error is 0 0 0 1 1 0 1 0 0
u m
Example-31: Encode the data (or) message bits 1 0 1 1 0 0 1 using even parity hamming
r
code. Generate it.
Sol. Given message = 1 0 1 1 0 0 1
No of message bits M 7
No of parity bits was
2P M p 1
c t
2P 7 p 1
P = 4.
p
24 7 4 1
16 12
e
P 4
D11
S
Total no of bits: M + P
= 7 + 4 = 11
11 10
D10
9
D9
8
P8
7
D7
6
D6
5
D5
4
P4
3
D3
2
P2
1
P1
1 0 1 1 0 0 1
Calculation of P1
Consider the bit positions
P1 , 3, 5, 7, 9,11
P1 ,1, 0, 1, 1, 1
Keep P1 0 because we are considering even parity..
45
Digital System Design
Calculation of P2
Consider the bit positions: P2 , 3, 6, 7,10,11
P2 ,1, 0,1, 0,1
Keep P2 1
Calculation of P4
Consider the bit positions: P4 , 5, 6, 7
P4 , 0, 0,1
Keep P4 1
Calculation of P8
Consider the bit positions: P8 , 9,10,11
P8 ,1, 0,1
Keep P8 0
Total message generated = 1 0 1 0 1 0 0 1 1 1 0. To identify the error.
u m
r
P8 P4 P2 P1
0 1 1 0
Decimal equivalent = 6.
At 6th position the error is occurred.
101010 01110
c t
p
Error occured.
Correcting the error
10101101110 e
This is the message without error..
S
Example-32: Given the 8 bit data word 10111001, generate the 12 bit composite word
for the hamming code that detects & corrects single bit error using odd parity. At
the receiving end, it can be received as 101101001110. Find out the error position.
Sol. m = 8
10111001
‘p’ can be calculated as
2P m p 1
p=4
24 8 4 1
16 13 True
P 4
Total no of bits = M + P = 8 + 4 = 12
46
Number Systems, Boolean Algebra and Logic Gates
12 11 10 9 8 7 6 5 4 3 2 1
D12 D11 D10 D9 P8 D7 D6 D5 P4 D3 P2 P1
1 0 1 1 1 0 0 1
Calculation of P1
Consider the bit positions: P1 , 3, 5, 7, 9,11
P1 , 1, 0,1,1, 0
Keep P1 0
Calculation of P2
Positions P2 ,3, 6, 7,10,11
P2 ,1, 0,1,1, 0
Keep P2 0
Calculation of P4
Consider the bit positions P4 , 5, 6, 7, 12
P4 , 0, 0,1,1
u m
r
Keep P4 1
Calculation of P8
Consider the bit positions: P8 , 9,10,11,12
Keep P8 0
P8 ,1,1, 0,1
c t
e
Generated 12 bit message is
101101001100
p
Received message at the receiver is
101101001110
S
Comparing generated & received message
101101001100
101101001110
At the 2nd position, error is occurred. To correct the error, at the 2nd position, change the bit
at 2nd position, change the bit at 2nd position 0 to 1 in the generated message.
The 12-bit hamming corrected code is 101101001110.
1.8 AXIOMATIC DEFINITION OF BOOLEAN ALGEBRA
The sets of logical expressions are known as Axioms or postulates of Boolean Algebra. An
axiom is nothing more than the definition of three basic logic operations (AND, OR, and NOT).
Here,
+ denotes the Logical OR operation
. denotes the Logical AND operation
47
Digital System Design
! denotes the Logical NOT operation
0 and 1 denotes the Logical False and True respectively
0.0 = 0
0.1 = 0
1.0 = 0
1.1 = 1
0+0 = 0
0+1 = 1
1+0 = 1
1+1 = 1
!0=1
!1=0
u m
t r
OR Operator: The functions of OR(+) operator is as follows:If any one of the input is logic 1
output is logic 1.Where as output logic 0 when all the inputs are logic 0.
0 + 0 = 0
0 + 1 = 1
1 + 0 = 1
1 + 1 = 1
e c
p
AND Operator: The functions of AND(.) operator is as follows:If any one of the input is logic
0 output is logic 0.Where as output logic 1 when all the inputs are logic 1.
0 . 0 = 0
S
0 . 1 = 0
1 . 0 = 0
1 . 1 = 1
1.8.1 Laws in Boolean Algebra (Properties)
The basic Laws of Boolean Algebra that relate to the Commutative Law allowing a change in
position for addition and multiplication, the Associative Law allowing the removal of brackets for
addition and multiplication, as well as the Distributive Law allowing the factoring of an expres-
sion, are the same as in ordinary algebra.
Boolean algebra consist of 6 basic laws.
1. Commutative laws. 2. Associative laws.
3. Distributive laws. 4. Identity law
5. Idempotent law 6. Complement law
48
Number Systems, Boolean Algebra and Logic Gates
1 Commutative laws
(i) A + B = B + A (ii) A . B = B . A
(i) A + B = B + A: This states that the order in which the variables are ORed makes no
differnce in the output. The truth table for A + B and B + A are indentical.
Therefore A + B = B + A
A B AB BA
0 0 0 0
0 1 1 1
1 0 1 1
1 1 1 1
m
Table-1.12: Truth table of commutative law for OR operator
(ii) A . B = B . A: The Commutative law of multiplication states that the order in which the
variables are ANDed makes no difference in the output. The truth tables are identical.
A B A .B B.A
0 0 0 0
r u
t
0 1 0 0
1 0 0 0
c
1 1 1 1
Table-1.13: Truth table of commutative law for AND operator
2.
(i)
Associate Laws
(i) A + (B+C) = (A+B) + C
p e (ii) (AB) C = A (BC)
A + (B+C) = (A+B) + C: The associative law of addition states that it makes no differ-
ence in what order the variables are grouped when ORing several variables.
S A B C A B B C A B C
0 0 0
0
0
0
0
1
1
0
1
0
1
0
0
1
1
0
1
1
1
1
1
1
A B C
0
1
1
1
1 0 0 1 0 1 1
1 0 1 1 1 1 1
1 1 0 1 1 1 1
1 1 1 1 1 1 1
Table-1.14: Truth table of associative OR operator
(ii) (AB) C = A (BC): The associative law of Multiplication states that it makes no difference
in what order the variables are grouped when ANDing several variables.
49
Digital System Design
A B C AB BC ABC ABC
0 0 0 0 0 0 0
0 0 1 0 0 0 0
0 1 0 0 0 0 0
0 1 1 0 1 0 0
1 0 0 0 0 0 0
1 0 1 0 0 0 0
1 1 0 1 0 0 0
1 1 1 1 1 1 1
m
Table-1.15: Truth table of associative law for AND operator
3. Distributive Law: A (B+C) = AB + AC
u
The Distributive Law states that the multiplication of two variables and adding the result
with a variable will result in the same value as multiplication of addition of the variable with
r
individual variables.
Therefore A + (B.C) = (A + B).(A + C) (AND Distributive Law)
Therefore A(B + C) = A.B + A.C
c
several variables and then adding the products. t
The distributive law also states that adding several variables and multiplying the result with
a single variable is equivalent to multiplying the result with a single variable with each of the
(OR Distributive Law)
p
0
0
0
0 e
A B C B C AB AC AB C AB AC
0
1
0
1
0
0
0
0
0
0
0
0
S
0 1 0 1 0 0 0 0
0 1 1 1 0 0 0 0
1 0 0 0 0 0 0 0
1 0 1 1 0 1 1 1
1 1 0 1 1 0 1 1
1 1 1 1 1 1 1 1
Tabl-1.16: Truth table of distributive law
4. Identity Law: In this law variable remain unchanged it is ORed with ‘0’ or ANDed with
‘1’, i.e.,
A.1 = A
A+ 0 =A
5. Idempotent law: A variable remains unchanged when it is ORed or ANDed with itself,
i.e.,
50
Number Systems, Boolean Algebra and Logic Gates
A+A=A
A.A = A
6. Complement Law: In this Law if a complement is added to a variable it gives one, if a
variable is multiplied with its complement it results in ‘0’, i.e.,
A + A’ = 1
A.A’ = 0
1.9 BOOLEAN ALGEBRA AND LAWS
Boolean algebra is a branch of mathematics that deals with operations on logical values with
binary variables.The variables used in Boolean Algebra only have one of two possible values, a
logic “0” and a logic “1” but an expression can have an infinite number of variables all labelled
ment of variables, logical AND operator and logical OR operator.
For example, consider the following expression.
u m
individually to represent inputs to the expression.A Boolean algebra may contain variables, Comple-
r
Y=A+ B.C +C .A
AND Operator
Variables OR Operator
c
C is the Complement of variable C.
t
OR Operator: The functions of OR(+) operator is as follows:If any one of the input is logic 1
p
0 + 1 = 1
1 + 0 = 1
e
output is logic 1.Where as output logic 0 when all the inputs are logic 0.
0 + 0 = 0
S
1 + 1 = 1
AND Operator: The functions of AND(.) operator is as follows:If any one of the input is logic 0
output is logic 0.Where as output logic 1 when all the inputs are logic 1.
0 . 0 = 0
0 . 1 = 0
1 . 0 = 0
1 . 1 = 1
1.9.1 Laws in Boolean Algebra
The basic Laws of Boolean Algebra that relate to the Commutative Law allowing a change in
position for addition and multiplication, the Associative Law allowing the removal of brackets for
addition and multiplication, as well as the Distributive Law allowing the factoring of an expression,
are the same as in ordinary algebra.
51
Digital System Design
Boolean algebra consist of 3 basic laws
1. Commutative laws. 2. Associative laws. 3. Distributive laws.
1 Commutative laws
(i) A + B = B + A (ii) A . B = B . A
(i) A + B = B + A: This states that the order in which the variables are ORed makes no
differnce in the output. The truth table for A + B and B + A are indentical.
Therefore A + B = B + A
A B AB BA
0 0 0 0
0 1 1 1
1 0
1 1
1
1
1
1
Table-1.17: Truth table of commutative law for OR operator
u m
r
(ii) A . B = B . A: The Commutative law of multiplication states that the order in which the
variables are ANDed makes no difference in the output. The truth tables are identical.
A B A .B B.A
0 0
c
0 1
1 0
0
0
0
0
0
0
t
2.
p
Associate Laws
(i) A + (B+C) = (A+B) + C
e
1 1 1 1
Table-1.18: Truth table of commutative law for AND operator
(ii) (AB) C = A (BC)
(i)
S
A + (B+C) = (A+B) + C: The associative law of addition states that it makes no difference
in what order the variables are grouped when ORing several variables.
A B C A B B C A B C
0
0
0
0
0
1
0
0
0
1
0
1
A B C
0
1
0 1 0 1 1 1 1
0 1 1 1 1 1 1
1 0 0 1 0 1 1
1 0 1 1 1 1 1
1 1 0 1 1 1 1
1 1 1 1 1 1 1
Table-1.19: Truth table of associative OR operator
52
Number Systems, Boolean Algebra and Logic Gates
(ii) (AB) C = A (BC): The associative law of Multiplication states that it makes no difference
in what order the variables are grouped when ANDing several variables.
A B C AB BC ABC A BC
0 0 0 0 0 0 0
0 0 1 0 0 0 0
0 1 0 0 0 0 0
0 1 1 0 1 0 0
1 0 0 0 0 0 0
1 0 1 0 0 0 0
1 1 0 1 0 0 0
m
1 1 1 1 1 1 1
Table-1.20: Truth table of associative law for AND operator
3. Distributive Law: A (B+C) = AB + AC
A B C B C AB AC AB C AB AC
0 0 0 0 0 0
r 0 u
0
0
0
0
0
1
1
1
0
1
c
1
1
1
0
0
0
0
0
0 t 0
0
0
0
0
0
e
1 0 0 0 0 0 0 0
1 0 1 1 0 1 1 1
p
1 1 0 1 1 0 1 1
1 1 1 1 1 1 1 1
S
Table-1.21: Truth table of distributive law
The Distributive Law states that the multiplication of two variables and adding the result
with a variable will result in the same value as multiplication of addition of the variable with
individual variables.
Therefore A + (B.C) = (A + B).(A + C) (AND Distributive Law)
The distributive law also states that adding several variables and multiplying the result with a
single variable is equivalent to multiplying the result with a single variable with each of the several
variables and then adding the products.
Therefore A(B + C) = A.B + A.C (OR Distributive Law)
1.9.2 Demorgan’s Theorem
A mathematician named Augustus DeMorgan developed a pair of important theorems regarding
the complementation of groups in Boolean algebra. DeMorgan found that an OR gate with all
inputs inverted (a Negative-OR gate) behaves the same as a NAND gate with non-inverted
53
Digital System Design
inputs; and an AND gate with all inputs inverted (a Negative-AND gate) behaves the same as a
NOR gate with non-inverted inputs. DeMorgan's theorem states that inverting the output of any
gate is the same as using the opposite type of gate with inverted inputs. To put this in circuit terms,
DeMorgan's theorem states that the AND gate with inverted output and the OR gate with in-
verted inputs are functionally equivalent.
Demorgan suggested two theorems that form an important part of Boolean algebra. In the
equation form, they are.
(i) AB A B (ii) A B A .B
(i) AB A B : The complement of a product is equal to the sum of the complements.This
formula shows how a two-input NAND gate is "broken" to form an OR gate with two
inverted inputs.The below table shows the proof it.
m
NAND
u
A.B A.B
B A B AB AB A B A B
r
0 0 0 1 1 1 1
0 1 0 1 1 0 1
A
B
A
c
A+B
1
1
t0
1
0
1
1
0
0
0
1
0
1
0
p
Hence AB A B
Negative-OR
e
Table-1.22: Truth table of demorgan’s theorem
(ii) A B A .B : The complement of a sum is equal to the product of the complements.
A
B
S
This formula shows how a two-input NOR gate is "broken" to form an AND gate with two
inverted inputs.The below table shows the proof of it.
NOR
A+B A+B
A B A B A .B A B A B
0 0 1 1 1 0 1
0 1 1 0 0 1 0
A
A 1 0 0 1 0 1 0
A.B
B
1 1 0 0 0 1 0
B
Negative-AND
Table-1.23: Truth table of demorgan’s theorem
Hence A B A .B
54
Number Systems, Boolean Algebra and Logic Gates
1.9.3 Consensus Theorem (Included Factor Theorem)
Redundancy theorem is used as a Boolean algebra trick in Digital Electronics. It is also known as
Consensus Theorem.
AB AC BC AB AC
The consensus or resolvent of the terms AB and AC is BC. It is the conjunction of all the
unique literals of the terms, excluding the literal that appears unnegated in one term and negated
in the other.
The conjunctive dual of this equation is:
A B A C B C A B A C
In the second line, we omit the third product term BC.Here, the term BC is known as
m
Redundant term. In this way we use this theorem to simplify the Boolean Algebra. Conditions for
applying Redundancy theorem are.
u
1. Three variables must present in the expression. Here A, B and C are used as variables.
r
2. Each variables is repeated twice.
3. One variable must present in complemented form.
variable.
c t
After applying this theorem we can only take those terms which contains the complemented
In simplification of boolean expression, an expression of the form AB AC BC , the term
p
AB AC BC AB AC e
BC is redundant and can be eliminated to form the equivalent expression AB AC . The theo-
rem used for this simplification is known as consensus theorem and it is stated as
The key to recognize the consensus terms is first find a pair of terms, one of which contains
S
a variable and other contains its complement. Then we have to find the third term which should
contain the remaining variables and its complement.
Proof: LHS AB AC BC AB AC A A BC AB AC ABC ABC
AB ABC AC ABC AB1 C AC1 B
Since 1+C=1 and 1+B=1
Therefore AB AC BC AB AC
Example-33: Minimize the given expression using consenus theorem
A B AC BC BC AB
Sol. A .B AC BC BC AB
By Consensus theroem A B A C BC A B AC
A .B AC BC AB A .B AC BC
55
Digital System Design
Example-34: A B A C B C A B A C .
Sol. LHS, A B A C B C AA AC AB BC B C
AC AB BC B C A A 0
ABC AC AB ABC BC BC
ABC AC AB ABC BC BC A A AC AB BC
BC AC AB BC A A 1 BC AC AB
RHS, A B A C AA AC AB BC
0 AC BC AB BC AC AB
m
LHS = RHS.
Example-35: Simplify xy x z yz
u
Sol. By consensus theorem, xy x z yz xy x z x x yz xy x z xyz x yz
xy xyz x z x yz xy1 z x z 1 y
Here 1+z=1 and 1+y=1
Therefore xy x z yz xy x z
1.9.4 Duality Theorem
t r
c
This theorem states that the dual of the Boolean function is obtained by interchanging the logical
AND operator with logical OR operator and zeros with ones. For every Boolean function, there
e
will be a corresponding Dual function
The principle of duality theorem says that, starting with a boolean relation, we can drive
another Boolean relation by,
S p
1. Changing each OR sign to an AND sign.
2. Changing each AND sign to an OR sign.
3. Complementing any 0 or 1 appearing in the expression.
For example, consider the Boolean relation A A 1 . Applying principle of duality we get
another Boolean relation A .A 0
Boolean Relation Dual
A0 A A .1 A
A 1 A A .0 0
AA A A.A A
A A 1 A.A 0
A AB A A .A B A
A AB A B
A B A C A BC
A . A B AB
AB AC A B C
AB AC BC AB AC
A B A C B C A B A C
Table-1.24
56
Number Systems, Boolean Algebra and Logic Gates
1.10 BOOLEAN EXPRESSION
1.10.1 Minimization of Boolean Expression
Rule 1 : 0 + 0 = 0 Rule 2 : 1 + 0 = 1
0 + 1 = 1 1 + 1 = 1
0 + A = A (or) A + 0 = A 1 + A = 1 (or) A + 1 = 1
0 + 0 = 0 0 + 1 = 1
Rule 3 : Rule 4 : 1 + 0 = 1
1 + 1 = 1
A+A=A A A 1 (or) A A 1
0 . 0 = 0 1 . 0 = 0
Rule 5: 0 . 1 = 0 Rule 6 : 1 . 1 = 1
0 . A = 0 (or) A . 0 = 0
0 . 0 = 0
Rule 7: 1 . 1 = 1
0 . 1 = 0
Rule 8 : 1 . 0 = 0
u m
1 . A = A (or) A . 1 = A
r
A.A=A A .A 0 (or) A .A 0
t
Rule 9: 0 = 0
1 = 1
AA
Rule 10: A + AB = A
LHS = A + AB
= A(1+B)
e c
From[Rule 2 : 1 + B = 1 ]
= A = RHS
p
Rule 11: A AB A B
S
Proof: LHS A AB A AB AB
ABAA
=A+B
[Rule 10 : A + AB = A ]
[Rule 4 : A A 1 ]
Rule 12 : A B A C A BC
Proof: LHS A BA C = AA + AC + AB + BC [Rule 7 : A . A = A ]
= A + AC + AB + BC A 1 C AB BC [Rule 2 : 1 + C = 1 ]
= A + AB + BC A 1 B BC [Rule 2 : 1 + B = 1 ]
= A + BC = RHS
Example-36: Simplify the following Boolean expression.
(a) ABCD A BCD (b) AB ABC ABD E
(c) AB A AB
57
Digital System Design
Sol.
(a) ABCD A BCD ACD B B [ B B 1]
= ACD.
(b) AB ABC ABD E AB ABC ABD ABE
AB1 C ABD ABE AB ABD ABE
AB1 D ABE AB ABE AB1 E AB
(c) AB A AB A B A AB [Demorgan’s theorem]
A B AB A A A
A.B. A B AB A B
A.A 0
and B.B 0 = 0.
m
ABA ABB
1.11 SWITCHING FUNCTIONS - CANONICAL AND STANDARD FORMS
1.11.1 Minterm and Maxterm
r u
Minterms are called products because they are the logical AND of a set of variables, and maxterms
t
are called sums because they are the logical OR of a set of variables.In Minterm, we look for the
functions where the output results in “1” while in Maxterm we look for function where the output
results in “0”.We perform Sum of minterm also known as Sum of Products (SOP) . We perform
canonical form.
e c
Product of Maxterm also known as Product of sum (POS).
Boolean functions expressed as a sum of minterms or product of maxterms are said to be in
Standard Form - A Boolean variable can be expressed in either true form or complemented
p
form. In standard form Boolean function will contain all the variables in either true form or comple-
mented form while in canonical number of variables depends on the output of SOP or POS.
S
Each individual term in standard Sop form is called minterm and each individual term is standard
Pos form is called maxterm. In an ‘n’ variable logical function there are 2 n minterms and 2 n
maxterms. Table 1.25 shows the 3 variables functions with 23 8 number of minterms and
maxterms.
POS: Product of sums Ex: (A+B) (B+C) (C+A)
SOP: Sum of products Ex: (AB)+(BC)+(CA)
Variables Minterms Maxterms
A B C m1 M1
0 0 0 A BC m 0 A B C M0
0 0 1 A BC m1 A B C M1
0 1 0 ABC m 2 A B C M2
0 1 1 ABC m3 A B C M3
58
Number Systems, Boolean Algebra and Logic Gates
1 0 0 A BC m 4 A B C M4
1 0 1 A BC m5 A B C M5
1 1 0 ABC m 6 A B C M6
1 1 1 ABC m 7 A B C M7
Table-1.25
Table 1.25 Minterms and maxterms for 3 variables. Representing a SOP or POS expression
using minterm or maxterm provides a very convenient short hand notation for example, the SOP
expression.
FA , B, C A BC ABC A BC A BC can be written in minterm notation as
FA , B, C A BC ABC A BC A BC m 0 m 2 m 4 m 5 m0,2,4,5
where denotes sum of products.
Similarly the POS expression can be represented using Maxterm notation
u m
FA, B, C A B C . A B C A B C
FA , B, C M 0 .M 2 .M 7 FA, B, C M 0,2,7
Where denotes product of sum.
t r
Consider the minterm logical function
FA, B, C m1,2,3,5
e c
The truth table corresponding to the above expression can be written as shown in table 1.26.
Therefore the standard SOP form of the given function is
A B C
0
0 S p
FA, B, C A BC ABC ABC A BC
Variables
0
0
0 0
1 1
F
ABC
0
0
Variables
A B C
0
0
0
1 1
F
0 A+B+C
0 1 0 1 ABC 0 1 0 1
0 1 1 1 ABC 0 1 1 1
1 0 0 0 1 0 0 0 A+B+C
1 0 1 1 ABC 1 0 1 1
1 1 0 0 1 1 0 0 A+B+C
1 1 1 0 1 1 1 0 A+B+C
Table-1.26: Truth table for SOP form function Table-1.27: Truth table for POS form
function
59
Digital System Design
Consider the max term logical function, FA, B, C M 0, 4, 6, 7
The truth table corresponding to the above function can be written as shown in table 1.27.
Therefore the standard POS form of the given function is
FA, B, C A B C A B C A B C A B C .
1.11.2 Sum of Products (SOP)
A sum of products (SOP) is a group of products terms ORed together.
Sum
Ex: f(A,B,C) = AB + BC + ABC
Product tems
u m
The product terms whose sum defines the Boolean function are those which give the 1’s of
the function in a truth table. Since the function can be either 1 or 0 for each product term, and
since there are 2^n product terms. It is sometimes convenient to express a Boolean function in its
sum of minterm form. The sum of product form is also known as disjunctive normal formula or
disjunctive normal form.
1.11.2.1 Canonical SOP form or Minterm Canonical form
t r
If each term in Canonical SOP form contains all the literals(either true or complimentary form of
c
the variables) then the SOP form is known as standard or canonical SOP form. Each individual in
the standard SOP form is called minterm canonical form.
e
1.11.2.2 Converting Expressions to Canonical SOP form
Sum of products can be converted to Canonical sum of products by using following steps:
S p
Step 1: Find the missing literals in each product terms if any.
Step 2: AND each product term have missing literals with terms form by ORing the literals and
its complement.
Step 3: Expand the terms by applying distributive law and reorder the literals in the product
terms.
Step 4: Reduce the expression by omitting repeated product terms if any.
Example-37: Convert the given expression in the Canonical SOP form.
f A , B, C AC AB BC
Sol.
Step-1: Find the missing literals in each product term
f(A,B,C) = AC + AB + BC
Literal A is missing
Literal C is missing
Literal B is missing
60
Number Systems, Boolean Algebra and Logic Gates
Step-2: AND product term with sum of missing literals and its complement.
f A , B, C AC B B AB C C BC A A
Step-3: Expand the terms and reorder the results
f A , B, C ABC A BC ABC ABC ABC ABC
Step-4: Omit repeated product terms
f A , B, C ABC A BC ABC ABC ABC.
Example-38: Obtain the canonical sum of product form of the function.
Y A , B, C A BC ABC
Sol.
Step-1: Find the missing literals in each product term
Y(A,B,C) =A + BC + ABC
Literal A is missing
u m
Y A , B, C A B B C C BC A A ABC
t
Step-2: AND product term with sum of missing literal and its components.
r
Literal B and C are missing
e c
Step-3: Expand the terms and reorder the literals
Y A , B, C AB A B C C BC A A ABC
ABC ABC A BC A BC ABC ABC ABC
S p
Step-4: Omit repeated product terms
Y A , B, C ABC ABC A BC A BC ABC
1.11.3 Product of Sums (POS)
The product of Sum form is a form in which products of different sum terms of inputs are taken.
These are not arithmetic product and sum but they are logical Boolean AND and OR respec-
tively.
A product of sums is a group of sum terms ANDed together.
Ex:
Product
f(A,B,C) = (A+B) . (B+C) . (A+B+C)
Sum terms
The product of sum term form is also known as conjunctive normal formula or conjunctive
normal form.
61
Digital System Design
1.11.3.1 Canonical POS Form or Maxterm Canonical form
Canonical POS form means Canonical Product of Sums form. In this form, each sum term con-
tains all literals. So, these sum terms are nothing but the Max terms. Hence, canonical PoS form
is also called as product of Max terms form
If each term in POS form contains all the literals then the POS form is known as standard or
canonical POS form. Each individual term in the Canonical POS form is called maxterm. There-
fore, canonical POS form is known as maxterm canonical form.
Ex: f A , B, C A B C A B C
In the above Boolean expression all the literals are present in each term. Hence the above
expression is in canonical POS form.
1.11.3.2 Converting Expressions to Canonical POS Form
Step 1: Find the missing literals in each sum term if any
u m
Product of sum can be converted to standard product of sum by using following steps.
Step 2: OR each term having missing literals with terms form by ANDing the literals and its
complement.
t r
Step 3: Expand the terms by applying the distributive and recorder the literals in the sum terms.
Step 4: Reduce the expression by omitting repeated sum terms if any.
Sol.
e c
Example-39: Convert the following function into canonical product of Max-terms.
FA , B, C A BB C A C
Step-1: Find the missing literals in each term.
S p
F(A,B,C) = (A+B')(B+C)(A+C')
Literal B is missing
Literal A is missing
Literal C is missing
Step-2: OR sum terms with product of mising literals and its complements.
FA, B, C A B C.C B C A.A A C B.B
Step-3: Expand the terms and recorder the literals since A BC A BA C we can write
FA , B, C A B C A B C A B C A B C A B C .A B C .
Step-4: Omit repeated sum term
FA , B, C A B C A B C A B C A B C A B C .
Example-40: Convert the given expression in canonical product of Max-terms form
Y A , B, C A BB C A C
Sol.
Step-1: Finding the missing literals in each sum term
62
Number Systems, Boolean Algebra and Logic Gates
Y(A,B,C) = (A+B)(B+C)(A+C)
Literal B is missing
Literal A is missing
Literal C is missing
Step-2: OR sum terms with product of missing literals and its complements.
Y A , B, C A B C.C B C A .A A C B.B
Step-3: Expand the terms and reorder the literals. Since A BC A BA C we can write
Y A , B, C A B C A B C .A B C . A B C .A B C A B C
Step-4: Omit repeated sum term
Y A , B, C A B C A B C A B C A B C
m
Example-41: Convert the given expression in canonical POS form f A .A B C .
Sol.
Step-1: Find the missing literals in each sum term
f(A,B,C) = A.(A+B+C)
Literal B and C missing
r u
f A , B, C A B.B C.C .A B C
Step-3: Expand the terms and reorder the literals
t
Step-2: OR sum terms with product of missing literal and its complements.
c
e
f A , B, C A B.B C A B.B C A B C
f A , B, C A B C A B C A B C A B C A B C
p
Step-4: Omit repeated sum term
f A , B, C A B C A B C A B C A B C
S
1.12 BOOLEAN ALGEBRA – SIMPLIFICATION
A simplified Boolean expression uses the fewest gates possible to implement a given expression.
Example-42: Simplify - AB + A(B + C) + B(B + C)
Sol. AB + AB + AC + BB + BC
AB + AB + AC + B + BC
AB + AC + B + BC
AB + AC + B
B+AC
Example-43: Simplify C BC .
Sol. C BC = C B C C C B 1 B 1
63
Digital System Design
Example-44: Simplify AB A B B B .
Sol. AB A B B B
AB A B A B A B A A AB A B BB A A B B A A A
Example-45: Simplify A C AD AD AC C .
Sol. A C AD AD AC C
A C AD D AC C A CA C AA AC C A C
Example-46: Simplify AA B B AA A B .
Sol. AA B B AA A B
AA AB B A A B 0 AB AB BB AA AB
AB AB 0 A AB AB AB 1 B
1.13 BASIC LOGIC GATES
AB A1 1 AB A A A A B A B .
u m
called the AND gate, the OR gate, and the NOT gate.
t r
All digital systems can be constructed by only three basic logic gates. These basic gates are
1. Not Gate: It is called NOT gate because its output is always opposite to the input. It is also
c
called an inverter because it inverts the input signal. It has one input and one output. The
inverter changes the one logic level to the opposite level. It changes a input 1 to output 0 and
input 0 to output 1. The symbol and truth table for NOT gate is given below
p
(a) NOT Gate symbol
Y=A
e A
0
1
YA
1
0
(b) NOT Gate Truth Table
S
Figure-1.8 Table-1.28: Truth table
If the input at the NOT gate is A, then the logical expression for NOT gate output is given by
YA.
Pulsed Operation of NOT Gate: The pulsed operation of NOT gate is shown below:
1 1 1
Input A
0 0 0
1 1 1
Output Y
0 0 0
Figure-1.9: Timing diagram of NOT gate
64
Number Systems, Boolean Algebra and Logic Gates
As the pulsed operation shows that if the applied input to a NOT gate is 0, then the output is
1 and if the input is 1, then the output is 0.
2. OR Gate: The OR gate can have two or more inputs and one output. The output of an OR
gate is equal to the logical addition of inputs. The output of a OR gate is high (1) when any
of the input is high (1). The output of a OR gate is low (0) when all the inputs are low (0).
The logic symbol for OR gates is given below.
A A
Y=A+B Y=A+B+...+N
B
B N
(a) Two input OR gate symbol (b) N input OR gate symbol
m
Figure-1.10
If the applied inputs are A and B, then the logical expression for OR gate is given by
Y=A+B
Truth table for two inputs OR gate is given below:
r u
t
INPUT OUTPUT
A B Y=A+B
0
0
1
1
e c 0
1
0
1
0
1
1
1
p Table-1.29: Truth table or gate (2 input)
Pulsed Operation of Two Input OR Gate
S Input A
1
0
0 0
1 1
1 1
1
Input B
0 0
0
1 1 1
1
Output Y
0
0
Figure-1.11: Timing diagram of OR gate
65
Digital System Design
Logical Symbol for Three Input OR Gate
A
Y=A+B+C
B
C
Figure-1.12: OR gate symbol
Logical expression for three input OR gate: Y=A+B+C
Truth table for three input OR gate
INPUT OUTPUT
A B C Y=A+B+C
0 0 0 0
0
0
0
0
1
1
1
0
1
1
1
1
u m
1
1
1
0
0
1
0
1
0
t r 1
1
1
c
1 1 1 1
Table-1.30: Truth table OR Gate (3 input)
3.
e
AND Gate: The AND gate can have two or more inputs and one output. The output of an
AND gate is equal to the logical multiplication of inputs. The output of a AND gate is high
p
(1) when all the inputs are high (1). The output of a AND gate is low (0) when any one input
is low (0). The logic symbol for AND gate is drawn below:
A Y=A.B A Y=A.B. .... .N
S B
(a) Two input AND gate symbol
Figure-1.13
B
N
(b) N input AND symbol
Truth table: The truth table for two inputs AND gate is written below.
INPUT OUTPUT
A B Y=A.B
0 0 0
0 1 0
1 0 0
1 1 1
Table-1.31: Truth table AND gate (2 input)
66
Number Systems, Boolean Algebra and Logic Gates
Operation of an AND Gate: As the truth table for AND gate shows that the output (Y) is high
(1) when both the inputs (A and B) are high (1). The output of AND gate is low (0) when any of
the inputs (A and B) is low (0). The logical expression for 2-input AND gate output is Y=A.B
Pulsed Operation of Two Input AND Gate: The pulsed operation of two inputs AND gate is
shown below.
1 1
1
Input A
0 0
0
m
1 1
1
Input B
u
0 0
0
Output Y
1
0
0 0 0
t r 1
A
B
e c
Figure-1.14: Timing diagram of AND gate
Logical Symbol for Three Input AND Gate
Y=A.B.C
p
C
Figure-1.15: AND gate symbol
S
Logical Expression: Y=A.B.C
INPUT OUTPUT
A B C D
0 0 0 0
0 0 1 0
0 1 0 0
0 1 1 0
1 0 0 0
1 0 1 0
1 1 0 0
1 1 1 1
Table-1.32: Truth table AND gate (3 input)
67
Digital System Design
Advantages of Logic Gates
1. They are the building blocks of analog and digital device.
2. Logic gates are faster when it’s comes to solving any complex problems.
Disadvantages of Logic Gates
1. It’s operating voltage is limited.
2. Time delay occurs between input and output.
1.14 OTHER LOGIC GATES
Individual logic gates can be connected together to form a variety of different switching functions
and combinational logic circuits. The three most basic logic gates are
m
the: AND, OR and NOT gates, and given this set of logic gates it is possible to implement all of
the possible Boolean switching functions. For designing complex functions some of other logic
u
gates also be developed by using the logic gates are NAND, NOR, Exclusive OR (EX-OR) and
r
Exclusive NOR (EX-NOR) gates. NAND and NOR gates are called universal gates, where as
Exclusive OR (EX-OR) and Exclusive NOR (EX-NOR) gates are called application gates
c t
A universal gate is a gate which can implement any Boolean function without need to use
any other gate type. The NAND and NOR gates are universal gates. In practice, this is advan-
tageous since NAND and NOR gates are economical and easier to fabricate and are the basic
gates used in all IC digital logic families
1.14.1 NOR Gate
p e
NOR gate is the logic gate and is one of the universal gates. By combining NOT gate and OR
gate, NOR gate can be constructed. The output of NOR gate is reversal of OR gate. The NOR
S
gate operation is equal to the NOT-OR operation. NOR gate is a combination of OR gate fol-
lowed by an inverter.
Logic Symbol for NOR Gate
A Y=A+B A Y=A+B Y'=A+B
B B
Figure-1.16: (a) 2 Input NOT gate Figure-1.16(b): Equivalent circuit for 2-Input NOR
gate
A
Y=A+B+...+N
B
N
Figure-1.16(c): N-Input NOR gate
Truth table: The truth table for two inputs NOR gate is written below:
68
Number Systems, Boolean Algebra and Logic Gates
INPUT OUTPUT
A B Y A B
0 0 1
0 1 0
1 0 0
1 1 0
Table-1.33: Two input NOR gate truth table
Logical Expression: The logical expression for two input (A and B) NOR gate is given by:
YAB
For N input NOR gate: Y A B N
u m
Operation of NOR gate: As seen from the truth table of NOR gate, the output is high (1), when
both the inputs are low (0). When any of the input is high (1), the output is low (0).
Pulsed Operation of Two Input NOR Gate: The pulsed operation of two input NOR gate is
shown below.
1
Input A
0
1
0
1
t r
c
0
e
1 1
1
Input B
p
0 0
0
S
1
1
Output Y
0 0 0
0
Figure-1.17: Timing diagram of NOR gate
Logical Symbol for Three Input NOR Gate
A Y=A+B
B
Figure-1.18: NOR gate symbol
Logical Expression for Three Input NOR Gate
Y A B C If the inputs are A, B, and C and output is Y
69
Digital System Design
INPUTS OUTPUTS
A B C Y ABC
0 0 0 1
0 0 1 0
0 1 0 0
0 1 1 0
1 0 0 0
1 0 1 0
1 1 0 0
1 1 1 0
Table-1.34: Truth table NOR gate (3 input)
m
1.14.2 NAND Gate
NAND gate is the logic gate and is one of the universal gates .In digital electronics, a NAND gate
u
(AND-NOT) is a logic gate which produces an output which is false only if all its inputs are true,
thus its output is complement to that of an AND gate. A LOW (0) output results only if all the
r
inputs to the gate are HIGH (1); if any input is LOW (0), a HIGH (1) output results The NAND
gate operation is equal to the NOT-AND operation. NAND gate is a combination of AND gate
followed by an inverter.
Logic Symbol for NAND Gate
A Y=A.B
c A t A.B Y=A.B
p A
e
Figure-1.19(a): 2-Input NAND gate
B
Figure-1.19(b): Equivalent circuit for 2-in
-put NAND gate
S
Y=A.B. .... .N
B
N
Figure-1.19(c): N-Input NAND gate
Logic Expression: The logic expression for two input NAND gate is given by Y A .B
For N input NAND gate: Y A.B............N
Truth table: Thetruth table for two input (A and B) NAND gate is given below.
INPUT OUTPUT
A B Y A .B
0 0 1
0 1 1
1 0 1
1 1 0
Table-1.35: Truth table NAND gate (2 input)
70
Number Systems, Boolean Algebra and Logic Gates
Operation of NAND Gate: As seen from the truth table of two input NAND gate, the output of
NAND gate is high (1), when any of the input is low (0). The output of NAND gate is low (0),
when all the inputs are high (1).
Pulsed Operation of Two Input NAND Gate: The pulsed operations of two input NAND gate
is shown below.
1 1
1
Input A
0 0
0
1 1
1
Input B
0
0
1 1
0
u m
r
1
Output Y
0
c t 0
Figure-1.20: Pulsed operation of 2 input NAND gate
Logic Symbol for Three Input NAND Gate
p
A
B
C e Y=A.B.C
Figure-1.21: NAND gate symbol
S
Logical Expression for Three Input NAND Gate: If the inputs are A, B, and C are output is
Y then Y A .B.C
Inputs Outputs
A B C Y A.B.C
0 0 0 1
0 0 1 1
0 1 0 1
0 1 1 1
1 0 0 1
1 0 1 1
1 1 0 1
1 1 1 0
Table-1.36: Truth table NAND gate (3 input)
71
Digital System Design
1.14.3 EX-OR Gate (XOR Gate)
Exclusive OR gate is normally abbreviated as EXOR Gate or as XOR Gate. It is two or more
input and one output gate. This gate is widely used for designing digital circuits. The operation of
XOR gate is performed by using basic gates NOT, OR, AND, NOR and NAND gates. XOR
gate is called application gate, this gate is used for checking the even parity of binary information.
It is widely used for building half adder, full adder, binary to gray code converter etc.
Logical Symbol for the XOR Gate: Two Input XOR gate
A
Y=A + B
B
Figure-1.22: XOR gate symbol, (2 input)
Where the symbol represents A XOR B. For N input XOR gate
u m
A
B
N
t r
Y=A + B + ... + N
e c
Figure-1.23: N input XOR gate symbol
Logical Expression: The logical expression for two input XOR gate is given by
Y AB
p
i.e. Y AB A B
Where A and B are inputs and Y is output.
S
INPUTS OUTPUTS
A B Y AB
0 0 0
0 1 1
1 0 1
1 1 0
Table-1.37: Truth table XNOR gate
Operation of XOR Gate: As seen from the table of two input XOR gate, the output of XOR
gate is high (1), when both the inputs have different values means if. AB=01 or 10.
The output of XOR gate is low (0), when both the inputs have same values which means if
AB = 00 or 11.
72
Number Systems, Boolean Algebra and Logic Gates
Pulsed Operation of two Input XOR Gate
1 1
1
Input A
0 0
0
1 1
1
Input B
0 0
0
m
1 1
1
Output Y
u
0 0
0
Figure-1.24: Pulsed operation of XOR gate
1.14.4 EX-NOR Gate (XNOR Gate)
t r
Exclusive-NOR gate is normally abbreviated as EXNOR gate or as XNOR gate. It is two or
c
more input and one output gate. Exclusive-NOR gate is one of the application gate this gate is
used for checking the odd parity of binary information.
p
Logical Symbol for XNOR Gate e
As the name implies it performs the complement operation of XOR gate. If we apply an
inverter (NOT gate) at the output of XOR gate, then it becomes an XNOR gate.
The logic symbol for two input XNOR gate is given below:
S A
B
Y=A B
Figure-1.25: XNOR gate symbol (2 input)
Equivalent Logic Circuit for two Input XNOR Gate
A Y=A + B Y'=A B
B
Figure-1.26: Equivalent logic circuit for XNOR gate
Logical Expression: The logical expression for two input XNOR gate is given by
Y A .B A B AB A B AB A B A B A B Y A B AB
Where A and B are inputs and Y is output.
73
Digital System Design
Inputs Output
A B Y=A + B= A . B
0 0 1
0 1 0
1 0 0
1 1 1
Table-1.38: Truth table XNOR gate
Operation of XNOR Gate: As seen from the truth table of XNOR gate, the output of XNOR
gate is high (1), when both the inputs are same which means when AB=00 or 11. The output of
m
XNOR gate is low (0), when both the inputs have different values which means when AB=01 or
10. The XNOR gate is widely used for the binary word comparator circuit.
u
Pulsed Operation of XNOR Gate: The pulsed operation of two input XNOR gate is shown below:
1 1
1
Input A
0
0 0
t r
c
1 1
1
Input B
e
0 0
0
1 1
p
1
Output Y
0 0
0
S
1.15 GATE CONVERSIONS
Figure-1.27: Pulsed operation of XNOR gate
Any logic gate can be replaced by sets of other interconnected logic gates. Therefore any digital
design can be implemented with a small number of logic gate types. The gate conversion circuits
are shown in figure 1.28.
NAND
NOR
NOT
74
Number Systems, Boolean Algebra and Logic Gates
NOT
AND
OR
XOR
Figure-1.28: Gate conversions
u m
r
1.16 NAND AND NOR GATES AS UINIVERSAL GATES
t
The basic logic gates NOT, AND and OR are used for the realization of any logic expression. By
using these three operations, we can drive two more operations NAND and NOR operations.
e c
The NAND and NOR gates can be used for the realization of any logic expression. So, NAND
and NOR gates are called as universal gates. The NAND and NOR gates are called universal
gates because we can make any gate by using these gates.
NOR Gate as Universal Gate (NOR Realization of Logic Gates)
1.
S p
NOR Gate as NOT Gate (NOR Realization of NOT Gate): If we apply one input at the
input of a NOR gate as shown, then the output of NOR gate is equal to the NOT gate.
A
Y=A
Figure-1.29: : NOR realization of NOT gate
2. NOR Gate as OR Gate (NOR Realization of OR Gate): By using two NOR gates, we
can make an OR gate as shown below. NOR gate is the complimentary gate of OR, so
inversion of NOR gate is nothing but OR gate. The output expression shows the logical
expression for an OR gate.
A Y=A+B Y'=A+B=A+B
B
Figure-1.30: NOR realization of OR gate
75
Digital System Design
3. NOR gate as AND gate (NOR Realization of AND gate): By using NOR gates only, we
can make AND gate. We need three NOR gates to realize AND gate, NOR realization of
AND gate as shown below.
A
A
C=A+B=A.B=A.B
B
B
Figure-1.31: Not realization of AND gate
m
The output expression shows the logical expression for an AND gate.
Thus, we can realize any of the three basic gates (NOT, NOR, AND) using NOR gates
u
only. This means that by using only NOR gates, one can realize any logical expression and hence
NOR gate is called universal gate.
t r
NAND gate as universal gate (NAND Realization of logic gates)
1. NAND gate as NOT gate (NAND Realization of NOT gate): If we apply one input at
e c
the inputs of a NAND gate as shown, then it becomes a NOT gate.
Y=A
2.
S p Figure-1.32: NAND realization of NOT gate
The output expression shows the logical expression for NOT gate.
NAND gate as AND gate (NAND Realization of AND gate): By using two NAND
gates, we can make an AND gate as shown below. NAND gate is the complimentary gate
of AND, so inversion of NAND gate is nothing but AND gate.
A Y=A.B Y'=A.B=A.B
B
Figure-1.33: NAND realization of AND gate
The output expression shows the logical expression for an AND gate.
3. NAND gate as OR gate (NAND Realization of OR gate): By using three NAND gates,
we can make an OR gate as shown below.
76
Number Systems, Boolean Algebra and Logic Gates
A
A
C=A+B=A+B=A+B
B
B
Figure-1.34: NAND realization of OR gate
The output expression shows the logical expression for an OR gate.
Thus, we can realize any of the three basic gates (NOT, OR, AND) using only NAND gate,
one can realize any logic expression and hence NAND gate is also called as universal gate.
Sol.
A AB
m
Example-47: Draw the logic circuit for the following Boolean expression Y AB BC .
u
B
B
t r Y=AB+BC
c
BC
C
Figure-1.35: Logic circuit for y
Sol. Design of XOR gate
A
e
Example-48: Design XOR and XNOR gate by using NAND gates only.
p A.AB
B
S AB
B.AB
(A.AB).(B.AB)=AB+AB=A + B
Figure-1.36: Four input NAND gate using input NAND gate
A .AB B.AB
A .AB B.AB A A B B A B
A A A B BA BB
A B AB
77
Digital System Design
Design of XNOR gate
A A.AB
AB A+B Y=A + B
B.AB
B
Figure-1.37: NAND realization of XNOR gate
Example-49: Realize the following Boolean expression Y A B C D by using XOR
m
gates:
Sol.
u
A A+B
B
C C+D
t r Y=A + B + C + D
e c
Figure-1.38: Logic circuit for y
Example-50: Design a 4 input NAND gate by using two input NAND gates only.
p
Sol. Let the four inputs are A, B, C, D and output is Y.
A AB AB
S
B
Y=A.B.C.D
C CD CD
D
Figure-1.39: Four input NAND gate using to input NAND gate
1.17 IMPLEMENTATION OF LOGIC FUNCTIONS USING GATES
If the operation of the circuit is defined by a logic function, a logic circuit can be implemented
directly from that function. For example, suppose we need a circuit that is defined by X ABC.
Then we immediately know that all that is needed is a 3 input AND gate. If we need a circuit that
is defined by X A B , we will use a two input OR gate with an inverter on one of the in-
78
Number Systems, Boolean Algebra and Logic Gates
puts B . The same reasoning used for these examples for these simple cases can be extended to
more complex logic circuits.
Example-51: Draw the logic circuit using gate for the given function: F AB CD E .
Sol.
A
B
C
F=AB+CD+E
D
E
Figure-1.40: Logic circuit for F = AB + CD + E
Example-52: Draw the logic circuit for F AB CDE .
Sol.
A AB
u m
B
t r F=AB+CDE
c
C CDE
D
E
e
Figure-1.41: Logic circuit for F = AB+CDE
Example-53: Draw the logic circuit using basic gates for the function
Sol.
S p A
B
F A B A C B D .
(A+B)
(A+C)
C F=(A+B) (A +C) (B+D)
B+D
D
Figure-1.42: Logic circuit for given function
Example-54: Draw the logic circuit using basic gates for EX-OR gate and EX-NOR
gate.
Sol.
(i) The Boolean expression for EX-OR gate is Y A B A B AB
79
Digital System Design
A AB
B
F=AB+AB
AB
Figure-1.43: Logic circuit for EX-OR gate
(ii) The Boolean expression for EX-NOR gate is, Y A B AB A B
A AB
B
Y.B+A.B
u m
AB
t r
Figure-1.44: Logic circuit for EX-NOR gate
Examples-55: Draw the logic circuit using basic gates for the function F AB CD EF .
c
Sol. F AB CD EF ABCD ABEF (SOP form)
A
B
e
p
C CD
D
Y=AB(CD+EF)
S A
B
E
F EF
CD+EF
Figure-1.45: Logic circuit for Y AB CD EF
C ABCD
D
Y=ABCD+ABEF
E
F ABEF
Figure-1.46: Logic circuit for Y ABC D ABEF
80
Number Systems, Boolean Algebra and Logic Gates
Example-56: Draw the logic diagram for Y ABC D .
Sol.
A AB
B
Y=AB (C+D)
C
D C+D
Figure-1.47: Logic diagram for y ABC D
Example-57: Draw the logic circuit using NAND gates for Y A BC D .
Sol.
m
A
A
Y=A (BCD)
B
C
D
BCD
r u
= A+BCD
t
D
Figure-1.48: NAND requization for y A BCD
X
Y
e c X+Y
(X+Y).Z
Example-58: Draw the logic diagram for the function F X Y .Z XY Z.
Sol.
S p Z
XYZ
F
Figure-1.49: Logic diagram for F x y z xyz
Example-59: Reduce the given combinations logic circuit to a minimum form.
A
D
Figure-1.50: Logic circuit
81
Digital System Design
Sol. Y A BC C A BC D
Applying Demorgan’s theorem an Boolean algebra,
Y ABC CABCD
AC BC CC A B C D AC BC C A B C D
CA B 1 A B D (C+C=C)
CABD (A+B+1=1)
ABCD
The simplified circuit is,
A
B
C Y=A+B+C+D
m
D
Figure-1.51: Simplified logic circuit
1.18 OUTCOMES
At the end of the Unit have a glimpse at
r u
Understand the concept of number systems.
Understand the concept of complements.
c t
Learn the difference between Binary codes and BCD codes.
e
Understand the concept of all basic gates.
Understands the difficulty in using Boolean algebra theorems.
I.
1.
2. S p
1.19 REVIEW QUESTION
Short Answer Questions
What is the fundamental difference between analog and digital systems?
How are binary numbers used to represent information in digital systems?
3. Explain the process of converting a binary number to its decimal equivalent.
4. How do you perform number base conversion from binary to octal?
5. What are the advantages of using hexadecimal numbers in digital systems?
6. Describe the concept of two’s complement and its significance in representing negative
numbers.
7. Compare and contrast signed magnitude and two’s complement representations of negative
binary numbers.
8. Provide examples of common binary codes and their applications.
82
Number Systems, Boolean Algebra and Logic Gates
9. What are the basic logic gates, and what are their respective truth tables?
10. Define Boolean Algebra and explain its importance in digital system design.
11. State and explain the identity property of Boolean Algebra.
12. How is the distributive property applied in Boolean Algebra?
13. What are Boolean functions, and how are they represented?
14. Differentiate between canonical and standard forms of Boolean expressions.
15. Describe the operation of the NOT, AND, and OR logic gates with truth tables.
16. Explain the concept of XOR (exclusive OR) gate and its applications.
17. How do you simplify Boolean expressions using theorems of Boolean Algebra?
m
18. What are De Morgan’s laws, and how are they used to simplify Boolean expressions?
19. Given that (292) = ( 1204) . Determine b, [JNTUH-Dec-2019]
10 b
20. Add 98 and 89 in excess-3 form,
21. What is a self complimenting code?
22. Convert (FFF) = ( ) .
r u [JNTUH-Dec-2018]
[JNTUH-Apr-2018]
[JNTUH-Nov-2015]
t
H 10
23. Convert Gray code 10110 into Binary? [JNTUH-May-2015]
24. Convert (101101) into Octal?
c
2
25. Subtract the given numbers using 1’s complement method?
e
(a)18 from 30 (b) 69.25 from 86.75
26. Subtract the given numbers using 2’s complement method?
p
(a)17 from 29
27. Compute (1011.1) X(1111.01) .
S
28. Compute (1111) /(0100) .
29. Convert (AFF) = (?) .
16
2
2
8
2
(b) 59.15 from 88.25
30. Convert (7654) = (?)
8 16..
31. Calculate the value of Z if (33) =(201)
10 z.
II. Long Answer Questions
1. Explain the binary number system and how it is used in digital systems. Provide an example
of converting a decimal number to binary, octal, and hexadecimal forms.
2. Given the Boolean expression F = A’B + AB’ + AB, simplify it using Boolean algebra
theorems. Show each simplification step.
3. Discuss the importance of number base conversions in digital systems. Walk through the
step-by-step process of converting a binary number to its octal and hexadecimal equivalents.
83
Digital System Design
4. Define two’s complement representation for signed binary numbers. Illustrate the process
of finding the two’s complement of a negative binary number and explain why it’s useful.
5. Convert the 8-bit binary number 11011010 to its corresponding Gray code. Explain the
conversion process step by step.
6. Compare the advantages of using hexadecimal numbers over decimal and binary in terms of
representation and readability in digital systems.
7. Differentiate between canonical and standard forms of Boolean expressions. Provide
examples of each form and explain their significance in logic simplification.
m
8. Discuss De Morgan’s theorems and their applications in simplifying Boolean expressions.
Illustrate with examples how these theorems aid in logic simplification.
9.
u
Explain the operation of AND, OR, and NOT gates with their respective truth tables. Provide
r
a scenario in which combining these gates can solve a practical problem.
t
10. Show different weighted BCD codes and explain self complementary pattern?
[JNTUH- 2019]
e c
11. For the data 1011011, find the 11 bit hamming code.
12. Subtract the following decimal numbers by 9’s complement method
a) 274-86 b) 93-615
[JNTUH-Mar-2016,18]
[JNTUH-May- 2016]
p
13. Subtract (45) - (36) using complement method
G
8
2
8
14. Convert the following numbers to decimal
S
a) (1101101) b) (1101.11)
2
c) (2057.64)
B
8
d) (2EB7)
16
15. Convert (101101) into binary and (010110) into Gray code where B is Binary and G is gray
code.
16. Write about weighted and non weighted codes with example?
17. Find (1101) – (1000) using 1’s compliment and 2’s complement methods?
2 2
1.20 MULTIPLE CHOICE QUESTIONS
1. The binary number system uses base: ( )
(a) 8 (b) 10 (c) 16 (d) 2
2. What is the decimal equivalent of the binary number 101101? ( )
(a) 45 (b) 37 (c) 21 (d) 53
84
Number Systems, Boolean Algebra and Logic Gates
3. A hexadecimal number “3F” is equivalent to what decimal number? ( )
(a) 47 (b) 63 (c) 32 (d) 15
4. In two’s complement representation, the leftmost bit is used to indicate: ( )
(a) Sign (b) Magnitude (c) Overflow (d) Parity
5. Which of the following is a self-complementing code? ( )
(a) BCD (b) Gray code (c) Excess-3 code (d) ASCII code
6. Which logic gate is equivalent to a NOT-OR (NOR) gate? ( )
(a) AND (b) XOR (c) NAND (d) XNOR
7.
8.
What is the dual of the Boolean expression AB + C?
(a) A + B’C (b) A’B + C
De Morgan’s theorem states:
(c) A + BC’
u m (d) A’B’ + C’
( )
( )
(a) A’ + B’ = (A + B)’
(c) AB’ = (A + B)’
t r
(b) A’ + B’ = (AB)’
(d) A’B = (A + B)’
9.
(b) AND gate
e c
A logic gate that produces an output of 1 only when all inputs are 1 is:
(a) OR gate (c) NOT gate
10. Which of the following is a canonical form of Boolean expression?
(d) XOR gate
( )
( )
(a) SOP
(a) OR
S p (b) POS
(b) AND
(c) XOR
11. The logic operation represented by the expression A’ + B is:
(c) NOT
12. Which logic gate is used to implement subtraction in digital circuits?
(d) XNOR
(d) XOR
( )
( )
(a) OR (b) AND (c) NOT (d) XOR
13. Which gate is used as a building block for all other logic gates? ( )
(a) AND (b) OR (c) NAND (d) XOR
14. In digital systems, which logic family consumes less power but has slower speed? ( )
(a) TTL (b) CMOS (c) ECL (d) RTL
15. The expression A + AB simplifies to: ( )
(a) A (b) AB (c) 0 (d) 1
85
Digital System Design
16. The hexadecimal number system is commonly used in computer science because: ( )
(a) It requires fewer digits than binary.
(b) It is easier to convert to decimal.
(c) It allows direct conversion between octal and binary.
(d) It provides a compact representation of binary data.
17. Which of the following logic gates is reversible, meaning that the input can be uniquely
determined from the output? ( )
(a) OR (b) AND (c) NOT (d) XOR
m
18. The main advantage of using Gray code in rotary encoders is: ( )
(a) Lower power consumption. (b) Reduced error propagation during encoding.
(c) Faster conversion to decimal
u
(d) Direct compatibility with ASCII code.
r
19. The minimum number of bits required to represent negative numbers in the range of -1 to -
t
11 using 2’s complement arithmetic is ( )
(a) 2 (b) 3 (c) 4 (d) 5
(a) Gray code
e c
20. The following code is not a BCD code.
(b) Xs-3 code
21. A 15-bit hamming code requires
(c) 8421 code (d) All of these
( )
( )
(a) 2 S
(a) 5 p
(a) 4 parity bits (b) 5 parity bits
(b) 6
(b) 10
x
(c) 15 parity bits
(c) 7
23. Determine the value of base x if : (211) = (152)8
(c) 8
(d) 7 parity bits
22. If Maximum No in a No system =5,the base(radix) of the number system is
(d) 8
(d) 7
( )
( )
24. Determine the value of base x, if (193)x = (623)8 ( )
(a) 16 (b) 4 (c) 2 (d) 5
25. Which of the following is an unweighted code? ( )
(a) 8421 (b) Excess-3 code (c) 2421 (d) 63210
26. The fraction (0.68)10 isequalto ( )
(a) (0.010101)2 (b) (0.101)2 (c) (0.10101)2 (d) (0.10111)2
27. The Hexadecimal number A0 has the decimal value ( )
(a) 80 (b) 256 (c) 100 (d) 160
86
Number Systems, Boolean Algebra and Logic Gates
28. Given two numbers A & B in sign magnitude representation in an eight bit format A =00011110
& B=10011100,A XOR B gives ( )
(a) 10000010 (b) 00011111 (c) 10011101 (d) 11100001
29. When two n bit binary numbers are added , the sum will contain at the most ( )
(a) n bits (b) n+1 bits (c) n+2 bits (d) n +n bits
30. Convert (45)8 into Decimal ( )
(a) 35 (b) 36 (c) 37 (d) 38
31. Hamming Codes are used for _______ bit error detection and correction ( )
(a) 1 (b) 2 (c) 3 (d) 4
(a) 8 (b) 9 (c) 10
m
32. The MSB of a binary number has a weight of 512, the number consists of ____ bits. ( )
u
(d) 11
r
33. For odd number of ones, at the input, the output of EX-OR gate is________ ( )
(a) Low (b) High (c) Medium (d) All the above
34. Which of the following are called Universal gates
(a) NAND,NOR (b) AND,OR
c
35. The boolan expression (Y=AB+ABC is equal to
t
(c) XOR XNOR (d) OR,XOR
( )
( )
(a) AC
p
(b) BC
e (c) C
36. The minimum number of NAND gates required to implement XOR gate are
(a) 2 (b) 3 (c) 4
(d) None of these
(d) 5
( )
S
37. Given two numbers A & B in sign magnitude representation in an eight bit format A =
00011110 & B=10011100,A XOR B gives
(a) 10000010 (b) 00011111 (c) 10011101
( )
(d) 11100001
38. Decimal 43 in Hexadecimal and BCD number system is respectively [GATE-2005] ( )
(a) 2B,0100 0011 (b) 2C,1100 (c) 2A,0100 1100 (d) None
39. An equivalent 2’s complement representation of the 2’s complement number 1101 is
[GATE-1998] ( )
(a) 111111 (b) 111101 (c) 011111 (d) None
40. 2’s complement representation of a 16-bit number (one sign bit and 15 magnitude bits) is
FFFI. Its magnitude in decimal representation is__ [GATE-1993] ( )
(a) 0 (b) 1 (c) 255 (d) None
87
Digital System Design
Keys
1. (b) 2. (a) 3. (b) 4. (a) 5. (b)
6. (c) 7. (b) 8. (a) 9. (b) 10. (a)
11. (a) 12. (d) 13. (c) 14. (b) 15. (a)
16. (b) 17. (d) 18. (b) 19. (d) 21. (a)
21. (a) 22. (b) 23. (d) 24. (a) 25. (b)
26. (d) 27. (d) 28. (a) 29. (b) 30. (c)
31. (a) 32. (c) 33. (b) 34. (a) 35. (d)
36. (d) 37. (a) 38. (a) 39. (b) 40. (b)
u m
t r
e c
S p
88
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