CD4001BC/CD4011BC Quad 2-Input NOR Buffered B Series Gate • Quad 2-Input NAND Buffered B Series Gate

October 1987
Revised March 2002

CD4001BC/CD4011BC
Quad 2-Input NOR Buffered B Series Gate •
Quad 2-Input NAND Buffered B Series Gate
General Description Features
The CD4001BC and CD4011BC quad gates are monolithic ■ Low power TTL:
complementary MOS (CMOS) integrated circuits con- Fan out of 2 driving 74L compatibility: or 1
driving 74LS structed with N- and P-channel enhancement mode tran- ■ 5V–10V–15V parametric
ratings
sistors. They have equal source and sink current
capabilities and conform to standard B series output drive. ■ Symmetrical output characteristics
The devices also have buffered outputs which improve ■ Maximum input leakage 1 A at
15V over full transfer characteristics by providing very high gain. temperature
range
All inputs are protected against static discharge
with diodes to VDD and VSS.

Ordering Code:
Order Number Package Number Package Description
CD4001BCM M14A 14-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150"
Narrow
CD4001BCSJ M14D 14-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide
CD4001BCN N14A 14-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300" Wide
CD4011BCM M14A 14-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150"
Narrow
CD4011BCN N14A 14-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300" Wide

© 2002 Fairchild Semiconductor DS00593 www.fairchildsemi.c

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Devices also available in Tape and Reel. Specify by appending the suffix letter “X” to the ordering code.

Connection Diagrams
Pin Assignments for DIP, SOIC and SOP Pin Assignments for DIP and
SOIC CD4001BC CD4011BC

Top View
Top View

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CD4001BC/CD4011BC
Schematic Diagrams
CD4001BC

1
/4 of device shown
JA+B
Logical “1”  HIGH
Logical “0”  LOW
All inputs protected by standard
CMOS protection circuit.

CD4011BC

1
/4 of device shown
JA•B
Logical “1”  HIGH
Logical “0”  LOW
All inputs protected by standard
CMOS protection circuit.

© 2002 Fairchild Semiconductor DS00593 www.fairchildsemi.c

Corporation 9 om
 CD4001BC/CD4011BC
Absolute Maximum Ratings(Note 1) Recommended Operating
(Note 2) Conditions
Voltage at any Pin 0.5V to VDD 0.5V Operating Range (VDD) 3 VDC to 15
Power Dissipation (PD) Operating Temperature Range
VDC
Dual-In-Line 700 mW CD4001BC, CD4011BC 55C to 125C
Small Outline 500 mW Note 1: “Absolute Maximum Ratings” are those values beyond which
the

0.5 VDC to 18 VDC safety of the device cannot be guaranteed. Except for “Operating
VDD Range Tempera- ture Range” they are not meant to imply that the
devices should be oper-
Storage Temperature (TS) 65C to 150C ated at these limits. The Electrical Characteristics tables provide
conditions
for actual device operation.
Lead Temperature (TL) Note 2: All voltages measured with respect to VSS unless otherwise
speci-
(Soldering, 10 seconds) 260C fied.
55C 25C 125C
Symbol Parameter Conditions Units
DC Electrical Characteristics (Note 2) Min Max Min Typ Max Min Max
IDD Quiescent VDD  5V, VIN  VDD or VSS 0.25 0.004 0.25 7.5
Device Current VDD  10V, VIN  VDD or 0.5 0.005 0.50 15 A
VSS 1.0 0.006 1.0 30
VDD  15V, VIN  VDD or VSS
VOL LOW Level VDD  5V 0.05 0 0.05 0.05
Output VDD  10V |IO|  1 A 0.05 0 0.05 0.05 V
Voltage VDD  15V 0.05 0 0.05 0.05

VOH HIGH Level VDD  5V 4.95 4.95 5 4.95

Output VDD  10V |IO|  1 A 9.95 9.95 10 9.95 V
Voltage VDD  15V 14.95 14.95 15 14.95

VIL LOW Level VDD  5V, VO  4.5V 1.5 2 1.5 1.5

Input Voltage VDD  10V, VO  3.0 4 3.0 3.0 V
9.0V 4.0 6 4.0 4.0
VDD  15V, VO  13.5V
VIH HIGH Level VDD  5V, VO  0.5V 3.5 3.5 3 3.5
Input Voltage VDD  10V, VO  7.0 7.0 6 7.0 V
1.0V 11.0 11.0 9 11.0
VDD  15V, VO  1.5V
IOL LOW Level VDD  5V, VO  0.4V 0.64 0.51 0.88 0.36
Output Current VDD  10V, VO  1.6 1.3 2.25 0.9 mA
(Note 3) 0.5V 4.2 3.4 8.8 2.4
VDD  15V, VO  1.5V
IOH HIGH Level VDD  5V, VO  4.6V 0.64 0.51 0.88 0.36
Output Current VDD  10V, VO  1.6 1.3 2.25 0.9 mA
(Note 3) 9.5V 4.2 3.4 8.8 2.4

Note 3: IOL and IOH are tested one output at a time.

AC Electrical Characteristics (Note 4)

CD4001BC: TA  25C, Input tr; tf  20 ns. CL  50 pF, RL  200k. Typical temperature coefficient is 0.3%/C.
Symbol Parameter Conditions Typ Max Units
tPHL Propagation Delay VDD  5V 120 250
Time, HIGH-to-LOW VDD  10V 50 100 ns
Level VDD  15V 35 70

tPLH Propagation Delay VDD  5V 110 250

Time, LOW-to-HIGH VDD  10V 50 100 ns
Level VDD  15V 35 70

tTHL, tTLH Transition Time VDD  5V 90 200

VDD  10V 50 100 ns
VDD  15V 40 80
CIN Average Input Capacitance Any Input 5 7.5 pF
CPD Power Dissipation Capacity Any Gate 14 pF

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Note 4: AC Parameters are guaranteed by DC correlated testing.

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CD4001BC/CD4011BC
AC Electrical Characteristics (Note 5)
CD4011BC: TA 25C, Input tr; tf  20 ns. CL  50 pF, RL  200k. Typical Temperature Coefficient is 0.3%/C.
Symbol Parameter Conditions Typ Max Units
tPHL Propagation Delay, VDD  5V 120 250
HIGH-to-LOW Level VDD  10V 50 100 ns
VDD  15V 35 70
tPLH Propagation Delay, VDD  5V 85 250
LOW-to-HIGH Level VDD  10V 40 100 ns
VDD  15V 30 70
tTHL, tTLH Transition Time VDD  5V 90 200
VDD  10V 50 100 ns
VDD  15V 40 80
CIN Average Input Capacitance Any Input 5 7.5 pF
CPD Power Dissipation Capacity Any Gate 14 pF
Note 5: AC Parameters are guaranteed by DC correlated testing.

Typical Performance Characteristics

Typical
Transfer Characteristics
Typical
Transfer Characteristics

Typical
Transfer Characteristics

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 CD4001BC/CD4011BC
Typical Performance Characteristics (Continued)

Typical Transfer Characteristics

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CD4001BC/CD4011BC
Typical Performance Characteristics (Continued)

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 CD4001BC/CD4011BC
Physical Dimensions inches (millimeters) unless otherwise noted

14-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150" Narrow
Package Number M14A

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CD4001BC/CD4011BC
Physical Dimensions inches (millimeters) unless otherwise noted (Continued)

14-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide
Package Number M14D

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 CD4001BC/CD4011BC Quad 2-Input NOR Buffered B Series Gate • Quad 2-Input NAND Buffered B Series Gate
Physical Dimensions inches (millimeters) unless otherwise noted
(Continued)

14-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300"

Wide Package Number N14A

Fairchild does not assume any responsibility for use of any circuitry described, no circuit patent licenses
are implied and Fairchild reserves the right at any time without notice to change said circuitry and
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