Wave Digital Filter based Analog Circuit Emulation on FPGA

∗ ∗†
Wei Wu, Yen-Lung Chen, ∗ Yue Ma, † Chien-Nan Jimmy Liu, † Jing-Yang Jou, ∗ Sudhakar Pamarti, ‡∗
Lei He
∗
EE Dept., University of California, Los Angeles, CA, USA
†
EE Dept., National Central University, Taiwan, R.O.C
‡
State Key Laboratory of ASIC and Systems, Fudan University, China
Email: [email protected], [email protected]

Abstract— Unlike well accepted FPGA emulation for digital WDFs in FPGA to form a reconfigurable emulation hardware platform
circuits, there is no winning emulation solution for analog and with high speed and small area. This is the primary contribution of this
mixed-signal (AMS) circuits. This paper presents an analog circuit paper.
emulation based on wave digital filters (WDFs), which covers More specifically, while it is known how to map linear circuit
the entire flow of transforming an AMS circuit from SPICE components to WDFs [10], [12], we present the emulation of nonlinear
netlist to hardware implementation in FPGA. More specifically, it transistor with linearized WDFs and a nonlinear lookup table (LUT).
presents the theoretical support of how to map linear and nonlinear The implementation and optimization of these WDFs in FPGA are non-
circuit components to WDF. The detail implementation of each trivial, but we cannot elaborate them in this paper given the page limit.
WDF component in FPGA is not elaborated due to the page Instead, we present the performance and resource consumption of the
limit. Experiments show that there is a virtually perfect match final FPGA implementation.
between FPGA emulation and HSPICE simulations on two small Experiments on two small but representative analog circuits show
but representative analog circuits, indicating high accuracy of the that there is a perfect match between FPGA emulation and HSPICE
proposed emulation, and the FPGA-based WDF emulation can simulations, indicating high accuracy of the proposed emulation. The
process analog signal sampled at as high as 512KHz, which is FPGA-based WDF emulation can process analog signal sampled at
adequate for a variety of biomedical sensing applications. 512KHz, which is more than adequate for a variety of biomedical
sensing applications, such as electrocardiogram (ECG) and Electroen-
I. I NTRODUCTION
cephalogram (EEG) sensing, which typically operate at KHz level or
Analog/Mixed-Signal (AMS) components such as I/O circuits,
lower [13].
PLLs and DLLs are key bottlenecks with growing importance in
today’s advanced process technologies (32nm and below). Moreover, The remaining of this paper is organized as follows. Preliminary
an increasingly significant proportion of overall design bugs are now knowledge of wave digital filter is covered in Section II. Emulation of
attributable to on-chip AMS components [1]. However, the design cycle linear and nonlinear circuit components are expatiated in Section III.
of AMS circuit is prohibitively long because of iterative phase of design, The WaveACE framework and experiment results on a transmission
simulation, fabrication, and verification. line and a differential amplifier are presented in Section IV. Finally, we
conclude this paper in Section V.
Unlike well accepted FPGA emulation for digital circuits, AMS
circuit can only be simulated before tapeout [2], [3], [4], and there is no
winning solution for emulation of AMS circuits. Existing AMS emula- II. P RELIMINARIES OF WDF
tion research includes Field Programmable Analog Arrays (FPAAs) [5], A. Digital Filter Models for RLC Circuits
[6], [7] and Programmable ANalog Device Array (PANDA) [8]. Analog Conceptually, an analog circuit consisting of linear components (R,
macros of FPAA include switched capacitor circuits [9], operational L, C, etc.) can be mapped to a digital system through component-by-
and transconductance amplifiers [6], and mega-modules such as ADCs, component digitalization [14]. However, using Kirchoff variables (K-
DACs, track and hold circuits [7]. Whereas, these FPAAs still do not variables in short, including current 𝑖 and voltage 𝑣) makes the resulting
provide sufficient versatility because of the limited type and number of digital system have delay-free loops that are not realizable.
primitive building blocks [8]. PANDA offers more functional versatility Inductor (L)
x(n) u(n) i(n)
by providing transistor-level programmability [8].
+ u(t) - T/2L
However, in both FPAAs and PANDA, the analog building blocks + + T T
i(t)
and interconnections inevitably introduce undesired parasitics (and in -1
x(t) v(t)
turn, loss of accuracy) to the emulation circuit. Therefore they cannot T T
Delay-Free T/2C
perform accurate emulation which is necessary for AMS circuits. Both - - Loop v(n)
FPAAs and PANDA need special hardware supports, such as analog Capacitor (C)

macros, which are not available in existing commercial products. (a) Analog LC circuit (b) Digital filter representation

In this paper, we apply the theory of wave digital filter (WDF) to Fig. 1: Component-by-component digitalization of an analog LC circuit
analog circuit emulation. The WDF theory was originally developed for Take the LC circuit in Figure 1(a) as example: the original analog
designing digital filters with low sensitivity to coefficient quantization circuit is described by a system of ordinary differential equations
[10], [11]. Any linear analog continuous time circuit can be mapped (ODEs) as follows,
to a sampled digital equivalent while preserving circuit topology.
They employ incident and reflected wave signals rather than voltages 𝑢 = 𝐿 ∗ 𝑑𝑖/𝑑𝑡 (1)
and currents to render the realizable digital equivalent circuit. We 𝑖 = 𝐶 ∗ 𝑑𝑣/𝑑𝑡 (2)
will show that both linear components (R, L, C, etc.) and nonlinear
components (e.g. transistors) in AMS circuits can be mapped to their 𝑥=𝑢+𝑣 (3)
WDF equivalent, and these WDF modules can form a WDF equivalent
of the AMS circuit. Therefore, the digital implementations of WDF where (1) and (2) represent Ohm’s Law1 for L and C, and (3)
modules immediately lead to an accurate emulation for the original corresponds to the constraint of Kirchoff Voltage Law (KVL).
AMS circuits. We call the resulting emulation as Wave digital filter This circuit can be digitalized component-by-component by apply-
based Analog Circuit Emulation, in short, WaveACE. ing trapezoidal rule [15] to the ODE for each component. ODEs for L
To the best of our knowledge, this paper presents the first in-depth and C are discretized to difference equations in (4) and (5) respectively,
study of WDF emulation for the AMS circuit using FPGA. We develop
both software and hardware platform, which obtain an optimal WDF 1
The Ohm’s Law stands for the general Law that applies to R, L, and C, with 𝑉 = 𝑅𝑠 𝐼,
implementation based on the original circuit netlist, and implements where 𝑅𝑠 equals 𝑅, 𝑠𝐿, and 1/𝑠𝐶 for R, L, and C respectively.
while (3) is rewritten as (6).
V
V
𝑖[𝑛] = 𝑖[𝑛 − 1] + 𝑇 /2𝐿 ∗ (𝑢[𝑛] + 𝑢[𝑛 − 1]) (4)
𝑣[𝑛] = 𝑣[𝑛 − 1] + 𝑇 /2𝐶 ∗ (𝑖[𝑛] + 𝑖[𝑛 − 1]) (5) Rp Rp Z-1 Rp
Z-1
R0 -1
2 Rp
+ E
𝑥[𝑛] = 𝑢[𝑛] + 𝑣[𝑛] (6) 0 E

b[n]=0 b[n]=a[n-1] b[n]=-a[n-1] b[n]=2E-a[n] b[n]=E

where 𝑇 is the time step of digitalized system. Rp=R Rp=T/2C Rp=2L/T Rp=N/A Rp=R

Difference equations (4), (5), and (6) do form a digital filter (a)Resistor (b)Capacitor (c)Inductor
(d)Voltage (e)Resistive
and fully represent the original analog LC circuit. However, it is not Source Source

realizable due to the presence of a delay-free loop. This is apparent in Fig. 3: WDF modules for resistor, capacitor, inductor, resistive source
Figure 1(b), the signal flow representation of these difference equations. and voltage source
Note that the digital modules for both L and C contain direct paths from supports the component-by-component mapping. For a analog capacitor,
input to output. When combined together, they form a delay-free loop the reflectance is defined as
of combinational components marked as a border line in Figure 1(b). 𝑇
𝐵 𝑉 − 𝑅𝑝 𝐼 1 − 𝑅𝑝 𝐶𝑠 1− 2
𝑠
B. Wave Digital Filter = = = 𝑇
(10)
𝐴 𝑉 + 𝑅𝑝 𝐼 1 + 𝑅𝑝 𝐶𝑠 1+ 2
𝑠
Wave digital filter [10] was proposed to eliminate the aforemen-
tioned delay-free loop. Instead of using the original K-variables, wave considering Ohm’s Law 𝑠𝐶𝑉 = 𝐼 and choosing 𝑅𝑝 = 𝑇 /2𝐶.
variables (W-variables in short) are introduced, 2) Serial and Parallel Adaptors: WDF eliminates the delay-
{ { free path in the digital models of analog components. However, they
𝑎 = 𝑣 + 𝑅𝑝 𝑖 𝑣 = 𝑎+𝑏
2 can not be directly connected together because the WDF modules may
and 𝑎−𝑏 (7)
𝑏 = 𝑣 − 𝑅𝑝 𝑖 𝑖 = 2𝑅 𝑝 assume different port resistances. Consequently, adaptors are needed to
“equalize” the port resistance.
where 𝑎 and 𝑏 are incident wave and reflected wave respectively, and - v2 +
𝑅𝑝 is called the port resistance. Each analog component is digitalized as b2 a2
b2 a2 b2 a2
i2 Rp2 Rp2
a one-port WDF module, where W-variables 𝑎 and 𝑏 are its interface. i1 a1 a1
+
For each component, the port resistance, 𝑅𝑝 , is chosen such that no v1
a1
Rp1 Rp1
delay-free path exists from the input to the output. -
b1
b1 b1
RpN RpN
+ i a iN
aN bN
aN bN aN bN
+ vN -
v Rp=T/2C Z-1
v1 + v2 + … + vN = 0 bk=ak-γk*(a1+a2+…+aN) In addition to (b),
- b i1 = i 2 = … = iN Where γk=2Rk/(R1+R2+…+RN) bN=-(a1+a2+…+aN-1)
(a) Analog component (b) WDF module (a) Serial connection (b) Serial adaptor (c) Serial adaptor with
reflection-free port
Fig. 2: WDF module for capacitor
- v2 +
Take the capacitor as example, substituting 𝑖 and 𝑣 in (5) with 𝑎 b2 a2
b2 a2 b2 a2
and 𝑏 leads to i1
i2
a1
Rp2
a1
Rp2
+
a1
𝑎[𝑛] + 𝑏[𝑛] 𝑎[𝑛 − 1] + 𝑏[𝑛 − 1] v1 Rp1 Rp1
= (8) b1
2 2 -
b1 b1
RpN RpN
𝑇 𝑎[𝑛] − 𝑏[𝑛] 𝑎[𝑛 − 1] − 𝑏[𝑛 − 1] iN
bN aN
+ ( + ) aN bN aN bN
2𝐶 2𝑅𝑝 2𝑅𝑝 - vN +
v 1 = v2 = … = vN bk=(γ1a1+γ2a2+…+γNaN) - ak In addition to (e),
i 1 + i2 + … + iN = 0 Where γk=2Gk/(G1+G2+…+GN) bN= γ1a1+γ2a2+…+γN-1aN-1
Choosing 𝑅𝑝 = 𝑇 /2𝐶 eliminates 𝑎[𝑛] from (8) and results in a (d) Parallel connection (e) Parallel adaptor (f) Parallel adaptor with
simplified equation reflection-free port

Fig. 4: Serial and parallel adaptors [10]

𝑏[𝑛] = 𝑎[𝑛 − 1] (9) Another interpretation of adaptors is that they represent the KVL
and KCL in the ODEs, while other WDF modules for linear components
In (9) the output 𝑏[𝑛] only depends on the input of the previous cycle.
only represent Ohm’s Law. The digital adaptor for serial and parallel
That is equivalent to inserting a delay module and eliminating the direct
connections are presented in Figure 4.
path in between WDF input 𝑎[𝑛] and the output 𝑏[𝑛]. The WDF module
for capacitor behaves as a register as shown in Figure 2, which stores For example, a serial adaptor with N ports can be fully described
the input 𝑎[𝑛] and outputs it at the next time step. by KCL and KVL as follows
𝑣1 + 𝑣2 + ⋅ ⋅ ⋅ + 𝑣𝑁 = 0 and 𝑖1 = 𝑖 2 = ⋅ ⋅ ⋅ = 𝑖𝑁 (11)
III. WDF- BASED AMS C IRCUIT E MULATION
In this section, we go through the WDF modules for several typical Substituting the K-variables with W-variables leads to
circuit components, and demonstrate how a circuit is emulated using ∑
WDF modules in practice. Furthermore, we introduce how a nonlinear 𝑏𝑘 = 𝑎𝑘 − 𝛾𝑘 𝑁 𝑛=1 𝑎𝑛 , ∀𝑘 ∈ {1, 2, ⋅ ⋅ ⋅ , 𝑁 } (12)
transistor is represented using WDF module, and explain it with a ∑𝑁
simple common source amplifier circuit. where 𝛾𝑘 = 2𝑅𝑘 / 𝑛=1 𝑅𝑛 , and 𝑅𝑛 is the port resistance of the 𝑛𝑡ℎ
component serially connected to the adaptor.
A. Emulating linear circuits The N-port serial adaptor implements these equations using mul-
1) Mapping RLC and power sources to WDF modules: WDF tipliers and adders of appropriate resolution. So, to connect the WDF
modules for linear circuit components are obtained by substituting the modules of N analog components in series, an N-port series adaptor
K-variables with W-variables and properly choosing port resistance. is employed with the 𝛾𝑘 coefficients chosen according to the port
Several frequently used WDF modules are presented in Figure 3, while resistances. Similar equations can be derived for parallel adaptors,
a more comprehensive list of WDF modules are available in [10]. which are included in Figure 4(d) and Figure 4(e).
Note that, the delay-free path is removed for resistor, inductor, With the WDF of linear circuit components and adaptors, the LC
capacitor, and resistive source. However, the voltage source in Figure circuit in Figure 1(a) can be converted in WDF modules as shown
3(d) still has a direct path from input to output, but this could be trivially in Figure 5. In Figure 5, the ideal voltage source is connected to the
addressed by the reflection-free port in the next subsection. reflection-free port because it has a delay-free path. The port resistance
Furthermore, each WDF module is linked to the original analog for L and C are 2𝐿/𝑇 and 𝑇 /2𝐶 respectively, while the equivalent
circuit component through a bilinear transform [16], which theoretically port resistance of the voltage source is calculated as 2𝐿/𝑇 + 𝑇 /2𝐶.
 Rp1=2L/T
L Rp2=T/2C
In detail, the HSPICE netlist of an AMS circuit is parsed and
RpN=2L/T+T/2C automatically converted into FPGA implementation of WDF modules
Rp1 in Verilog. During emulation, instead of using an ADC to sample the
Vs RpN Rp2 C analog inputs, we store the digitalized analog signals in a ROM, then
load them to the V2W module in each time step. Outputs of WDF
Fig. 5: WDF implementation of the LC circuit implementation are dumped into a file and compared with HSPICE
B. Emulating Nonlinear Circuits transient simulation results.
Different from linear components, whose I-V behavior can be Digital Voltage Variables
depicted by Ohm’s Law, the I-V behavior of a transistor is nonlinear
Voltage-to-Wave Wave-to-Voltage
and more complicated to describe. Most of the existing WDF theory Conversion Conversion

does not deal with nonlinear circuits directly. However, some WDF
extensions with special nonlinear transistor models are available [17], Analog Analog
ADC Wave Digital Filter DAC
Signals Signals
[18], [19]. These models are intended for software simulation of WDF Implementation of
and difficult to be implement in hardware such as FPGA. Analog Circuits
(Circuit component modules, adaptor modules,
In this paper, we model the transistor as a linearized equivalent cir- lookup tables, etc.)

cuit with offline nonlinear lookup table (LUT) that stores the equivalent Digital Wave Variables

circuit parameters at different nodal voltage. The LUT is characterized Fig. 8: WDF based Analog Circuit Emulation (WaveACE)
by the HSPICE simulation of a single transistor. An AMS circuit usually consists of both linear RLC part and
VDD VDD
nonlinear part. In the following discussion, we validate the WDF
Rd Rd
Vout
based analog circuit emulation on two simple but representative analog
AC
Rgs Cgs vds
ro
Cds circuits: a linear transmission line and a nonlinear 2-stage differential
Vout amplifier. The emulation accuracy is verified by comparing outputs
V DC of the WDF emulator with HSPICE simulation results of the original
Rs Rs Nonlinear
Lookup Table
analog circuits.
(a) Original circuit (b) linearized equivalent circuit with nonlinear LUT B. Linear Transmission Line Circuit
Fig. 6: Common source amplifier and its its linearized equivalent To demonstrate WaveACE’s capability of emulating linear circuit,
As shown in Figure 6(b), 𝑅𝑔𝑠 and 𝐶𝑔𝑠 represent the gate resistance we implement the WDF equivalent of a lumped RLGC circuit, which
and capacitor respectively, while 𝐶𝑑𝑠 and 𝑟𝑜 model the parasitic is a well-accepted model for transmission line based on Telegrapher’s
capacitor and output resistance. A voltage controlled voltage source equations [20]. As shown in Figure 9, parameters of each RLGC block
(VCVS) 𝑣𝑑𝑠 2 is used to model the transconductance 𝑔𝑚 . During the can be extracted using existing EM simulation tool. A 50 Ohm matched
implementation, 𝑅𝑔𝑠 , 𝐶𝑔𝑠 , 𝐶𝑑𝑠 , 𝑔𝑚 , and 𝑟𝑜 are looked up from the load is connected to the right hand side of the transmission line, while
offline LUT based on the precalculated nodal voltages at operation the power source is also configured with 50 Ohm internal resistance.
point, 𝑉𝑔 , 𝑉𝑑 , and 𝑉𝑠 . Dynamic table lookup based on the actual nodal
voltage will be implemented in the future.
50Ω ...
V 50Ω
Vin Rs Rd
...
Transistor
Fig. 9: A transmission line modeled as lumped RLGC circuit based on
Rgs VDD telegrapher’s equations [20]
Vout An interesting observation is that a RLGC block can be viewed as
Nonlinear Cgs vdS+ro Cds the serial connection of 4 modules if we look into the module from the
Lookup Table
left hand side. Those 4 modules are input port resistance on the left
Fig. 7: WDF equivalent of the common source amplifier hand side, R, L, and the parallel connection of all the components on
Putting this transistor in a common source (CS) amplifier circuit the right hand side. In the meantime, it can be considered as 4 parallel
in Figure 6(a), we can get its WDF equivalent as shown in Figure 7. connected modules if it is observed from right hand side. Therefore,
In detail, the circuit can be considered as the serial connection of 3 each RLGC block can be abstracted as a regular 2-port WDF modules,
part, 1) voltage source 𝑉𝑖𝑛 , 2) modules in between gate and source, while the entire lumped RLGC is implemented by cascading multiple
i.e. 𝑅𝑔𝑠 and 𝐶𝑔𝑠 , and 3) the remainder of the circuit. These three parts RLGC modules as illustrated in Figure 10. Note that all the 4-port
are connected to a serial adaptor on the top-middle of Figure 7. The adaptor in Figure 10 are implemented using 3-port adaptors in FPGA.
WDF modules corresponding to the transistor are highlighted in Figure
7. The amplified voltage can be read out from the serial adapter on the R G
right hand side of Figure 7.
Note that the same circuit may be represented by several different
WDFs based on the choice and ordering of the adaptors. During the
WDF based emulation, the incident wave from 𝑉𝑖𝑛 has to propagate L C
through all the adaptors until it hits the 1-port modules and reflects back.
Since the wave can propagate to multiple branches simultaneously, ...
VR RLGC RLGC RLGC 50Ω
the emulation speed is only limited by the longest path in the WDF ...
equivalent. Therefore, the achievable emulation speed and emulator Fig. 10: WDF implementation of the lumped RLGC circuit
hardware requirement depend heavily on adaptor choice. A set of random binary signals at the frequency of 1GHz, as shown
IV. E XPERIMENTS in Figure 11, are generated and loaded as the input of the WDF module.
A. Framework of WaveACE In Figure 11, we can observe that the WaveACE results totally agree
The Framework of WaveACE is illustrated in Figure 8. It consists with the HSPICE simulation results.
of an ADC, an DAC, a Voltage-to-Wave (V2W), a Wave-to-Voltage
(W2V), and WDF implementation of the original circuit. All the C. Differential Amplifier Circuit
In this experiment, a two-stage differential amplifier circuit with
modules except ADC and DAC are implemented in Verilog and mapped
7 transistors is used to verify the capability of emulating nonlinear
to FPGA.
circuits. As shown in Figure 12(a), the first stage, 𝑀3 , 𝑀4 , is designed
2
In the implementation, 𝑣𝑑𝑠 and 𝑟𝑜 are modeled as a single WDF module, a voltage to eliminate the noise, while the second stage is used to enhance the
source with internal resistance, as shown in Figure 7. gain. Transistors 𝑀1 and 𝑀2 form an active bias to ensure proper
 Input Signal HSPICE WaveACE
Input Signal HSPICE WaveACE
1
Voltage (V) 0 0.9

0.5
0.68

Voltage (v)
0.67
0
0.66
0 5 10 15 20 25 0.65
Time (ns)
0.64
Fig. 11: Comparison between WaveACE and HSPICE transient simu- 0.63

lation results 0.62

0.61
0 100 200 300 400 500 600
operation region for other transistors. In the bottom of Figure 12(a), Time (ns)

𝑀5 and 𝑀7 work as current sources. Fig. 13: Transient simulation of the differential amplifier circuit with
The WDF implementation of this differential amplifier consists 10MHz sinusoid input
of 38 adaptors, including 11 serial adaptors and 27 parallel ones. It previous incident or reflect operation to finish. In this example, we
is too crowded to show all 38 adaptors here. Instead, we present a create only one instance of parallel and serial adaptor in all three
simplified WDF implementation in Figure 12(b), where each transistor WaveACE implementations. Second, those implementations use the
is considered as a WDF modules. Detail implementation of transistor same BRAM size for nonlinear LUTs. It consumes 125 BRAM blocks
module is similar to the shaded block in Figure 7. (25 for each LUT), which is less than 7% of the total number of BRAM
The WDF implementation of this differential amplifier circuit is blocks in XC7VX690T.
verified with a 10MHz sinusoid signal. One of the differential input is
configured as 0.9V DC voltage. The other one is a small signal with V. C ONCLUSIONS
an amplitude of 1mV imposing on 0.9V bias, which is presented in This paper presents the first study on an FPGA-based WDF
Figure 13. The amplifier output swings around 0.647V with 30mV emulation for AMS circuits. We develop both software and hardware
amplitude. Perfect accuracy is demonstrated because the emulation platform, which obtains an WDF implementation based on the original
results from WDF totally overlap to the transient simulation results of circuit netlist, and implements WDFs in FPGA to form a reconfigurable
HSPICE in Figure 13. We also configure the WDF implementation at emulation hardware platform. Experiments on two simple but represen-
several different frequency points and they again match to the HSPICE tation circuits show perfect match between the FPGA emulation and
simulation results perfectly. HSPICE simulation results. And the FPGA-based WDF emulation can
TABLE I: Emulation speed and resource utilization of WaveACE on process analog signal sampled at about MHz level, which covers a
differential amplifier variety of biomedical sensing applications, which typically sampled at
Speed Resource
KHz level or lower. Furthermore, good scalability can be expected on
clock cycles/step Max throughput LUT Reg DSP BRAM emulating larger circuit due to the balanced adaptor-tree architecture.
Sequential WaveACE 1482 135KHz 1% 0% 1% 8.5%
Optimal WaveACE 390 512KHz 1% 1% 1% 8.5% R EFERENCES
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