‘POL: PULSE CODE MODULATION TRANSMITTER KITADCLOM: PULSE CODE DEMODULATION RECEIVER KITV.2.0 er tee eee eee tt EXPERIMENT NO: § NAME ‘Synchronization Techniques OBJECTIVE ‘Study of Synchronization techniques THEORY ‘Synchronization Techniques For the recovery of information from the transmitted data stream, the transmitter and receiver should be perfectly synchronized. Synchronization between transmitter and receiver is achieved in two stages: 01) Bit Synchronization; and 02) Frame Synchronization. Bit Synchronization To recover the information from the serial bit stream, the receiver has to know, if the received data bit at a given instant of time, is a ONE or a ZERO. For determining the data bit, the clocks of transmitter and réceiver are to be perfectly synchronized. Once this Synchronization is achieved, the receiver recovers the data, with reference to the clock. For achieving this Synchronization, normally known as bit Synchronization. the ‘clock of the transmitter (TXCLK) can be sent along with the data, This calls for an additional channel for clock transmission. So normally a phase locked loop (PLL) Is used at the Receiver for recovering the clock. The phase locked loop is made to lock with the Incoming data whose VCO reproduces the clock at the Receiver. Frame Synchronization To recover the information transmitted from the data stream, the data is first converted to parallel code words. Then code words are decoded using the D/A converter, demultiplexing logic assigns the samples to the corresponding channel reconstruction units. For ensuring proper recovery of code words, and proper assignment of channel information of the demultiplexing unit, the recelver has to know where the data begins exactly. For this, at the start of every frame, a 14-bit pseudo random sequence (PRBS) is sent, which forms the header of the data pattern. Subsequently what follows is data corresponding to the number of channels multiplexed. The frame sync pulse can be sent by the Transmitter along with the data and clock to achieve frame Synchronization. But normally it is not sent, since it calls for an additional channel. Gel 67 DIGITAL COMMUNICATION LAB. & scanned with OKEN Scannerarv2.0 (PEL PULSE CODE MODULATION TRANSMITTER KITADCLOK: PULSE CODE DEMODUAATION RECEIVER NOLWZINOUHONAS 118 Hod MYUDYIO NOE Esa DIGITAL COMMUNICATION LAB & scanned with OKEN ScannerZz SCOSHHYOHHHYHKYHKHKEHHE THEE HEHEHE HCHO OH COE ‘DCL: PULSE CODE MODULATION TRANSMITTER KITADCL-O: PULSE CODE DEMOOULATION RECEIVER KIV.20 To recover the frame sync at the recelver from the data stream, a sequence. To Recover the frame sync at the recelver from the data stream, a sequence similar to the one transmitted, Is generated at the Recelver. The PRBS detector compares the generated sequence with the Incoming data and locks whenever the incoming data matches with the generated sequence. The PRBS sequence Is. chosen in such a way that it have minimum correlation with the data to avold false locks of the detector with the data bits. Once the PRBS detector Is locked, It generates a frame sync pulse, whose rising edge corresponds to tho start of the frame and the time to the slot when the pseudo random sequence occurs in tho data stream. This frame syne pulse Is used to code word and for demultiplexing Purposes. EQUIPMENT Experimenter kits DCL-03 & DCL-04 Connecting chords Power supply 20 MHz Dual Trace Oscilloscope NOTE: Keep The Switch Faults In Off Position. PROCEDURE I. Bit Synchronization © Refer to the Block Diagram (Fig. 5.1) & Carry out the following connections. © Connect the power supply in proper polarity o the kits DCL-03 and DCL-04 and switch ton. © Connect sine wave of frequency 500Hz and 1 KHz to the input CHO and CCHi of the sample and hold logic. Connect OUT 0 to CHO IN & OUT 1 to CH1 IN. * Select the speed selection switch SW1 to FAST mode, © Select parity selection switch to NONE mode on both the kit DCL-03 and DCL-04 as shown in switch setting diagram (Fig. A). Connect TXDATA of DCLW03 to the DATA IN of the receiver sectionDCL-04, Ensure that FAULT SWITCH SF 1 Introduces no fault as shown In switch setting diagram (Fig. A). + Connect DATAOUT to RXDATA, VCO CLOCK post to RXCLK and 'SYNCOUT to the RXSYNC with the help of connecting chords in DCL-04 Kit, Connect DAG OUT to IN posts on DCL-04 © “Take the observations as mentioned below. ‘Connect ground points of both the kits with the help of connecting chord provided during the all experiments, Il, Frame Synchronization © Referto the Block Diagram (Fig. 5.2) & Carry out the following connections, ical] +09 DIGITAL COMMUNICATION LAB & scanned with OKEN ScannerLDEMODULATION RECEIVER KITV:2.0 'DCL-03: PULSE CODE MODULATION TRANSMITTER KITZDCL-U: PULSE CODE TION * Connect the power supply in proper polarity to the kits DCL-03 and DCL-04 i and switch it on. * Connect sine wave of frequency 500Hz and 1 KHz to the input CHO and CH of the sample and hold logic. * Connect OUT 0 to CHO IN & OUT 4 to CH1 IN. Select the speed selection switch SW1 to FAST mode. , * Select parity selection switch to NONE mode on both the kit DCL-03 and ‘ DCL.04 as shown in switch setting diagram (Fig. A). a * Connect TXDATA of DCL-03 to RXDATA of the receiver section of DCL- 5 04, * Ensure that FAULT SWICH SF1 as shown In switch setting diagram (Fig. A) introduces no fault. Q + Connect the TXCLK of DCL-03 to the RXCLK of DCL-04, 4 * Connect the SYNCOUT of DCL-04 to RXSYNC of DCL-04, £ * Connect DAC OUT to IN posts on DCL-04 a + Take the observation as mentioned below. “1 * Connect ground points of both the kits with the help of connecting chord Q Provided during all the experiments. v OBSERVATION Observe the following signal on CRO and plot it on the paper. ON KIT DcL-03 ‘* Input signal CH 0 and CH 1. ~ ° * Sample and Hold output OUT 0 and OUT1 7 * Multiplexer clock GLK 4 and CLK 2 “ * Multiplexed data MUX OUT. * PCM Data TX DATA, TXCLK, TXSYNC. lor ON KIT DCL-04 oO + RXCLK, RXSYNG, RXDATA pe * VCO CLOCK, SYNCoUT ae + Demuitiplexer clock CLK 4 and CLK 2 & * — Demultiplexed Data CH 0 and CH 4 a * Received signal OUT 0 and OUT 4 oe as ra oo - o« oo ox ox eel DIGITAL communacarion LAB e~ oe & scanned with OKEN Scanner'PCL-03: PULSE CODE MODULATION TRANSMITTER KITADCLOK: PULSE CODE DEMODULATION RECEIVER KITV-2.0, a ee SWITCH FAULTS Note: Keep the connections as per the procedure. N ‘switch button in ON condition & observe the differer faults are normally used one at a time, low switch corresponding fault nt effect on the output. The * Put switch 2 of SF2 (DCL-03) in Switch Fault section to ON position. This cence itted Data. Synchronization will will remove PRBS sequence from Transm bo only possible in case of direct connection of TXSYNC fo RXSYNC. In any other case no synchronization Is possible. : * Put switch 3 of SF2 (DCL-03) in Switch Fault section to ON position. This will increase the duty cycle (on period) of CHO. Due to which, some portion of CHO signal present in CH1 signals time slot. Hence demultiplexed output for CH1 is disturbed. * Put switch 4 of SF2 (DCL.03) In Switch Fault section to ON position. This will disable Data from going to TX Data, only PRBS will be present. ‘* Put switch 4 of SF1 (DCL-04) in Switch Fault section to ON position. This will disable Synch signal in Bit Synchronization. Filter output will be disturbed, ‘+ Put switch 2 of SF4 (DCL-04) in Switch Fault section to ON position. This will disable clock signal for Demultiplexer. One channel output is absent and other channel output is disturbed. * Put switch 4 of SF1 (DCL-04) in Switch Fault section to ON position. This will remove CHO filter capacitor connection from ground. Filter output will be distorted. CONCLUSION The PLL will lock onto the frequency of the generated sync pulse and the PLL along with the associated circuitry will generate the sync and clock signals, which are same in phase and frequency as that of the TXCLK and TXSYNC. This ‘enables the receiver to get the output. DIGITAL COMMUNICATION LAB & scanned with OKEN Scanner