270 IEEE TRANSACTIONS ON COMPUTER-AIDED DESIGN. VOL. CAD-6. NO. 2.
MARCH 1987
CMOS Circuit Speed and Buffer Optimization
NILS HEDENSTIERNA AND KJELL O. JEPPSON, SENIOR MEMBER, IEEE
Abstract-An improved timing model for CMOS combinational logic cently, some more precise delay models have been pre
is presented. The model is based on an analytical solution for the CMOS sented for NMOS logic [2]-[4].
inverter output response to an input ramp. This model yields a better
In this paper, an analytical solution for the CMOS in
understanding of the switching behavior of the CMOS inverter than
the step-response model by considering the slope of the input wave
verter output response to an input voltage ramp is pre
form. Essentially, the propagation delay is shown to be the sum of the sented in Section II. The model yields an analytical
step-response delay and an input dependent delay that may account expression for the propagation delay as a function of the
for as much as 50-100 percent of the total delay. The matching between input ramp rise (fall) time with excellent agreement with
the ramp input and the characteristic input waveforms is shown to be
SPICE simulations. The analytical model neglects the
easily performed for excellent agreement in output response and prop
agation delay. Even though the short-circuit current is neglected, its
short-circuit power dissipation but, in a typical situation
influence is shown to be small and may be corrected. As an example, with equal input and output slopes, the error in propaga
the timing model is used to optimize CMOS output buffers for mini tion delay will be less than a few percent. Also, after
mum delay. If the intrinsic output load capacitance is included in the comparisons with SPICE simulations, we are able to con
model, the optimum tapering factor is shown to be not e but a value in
clude that an average input voltage ramp may be used as
the range 3-5 depending on process parameters and design style. Also,
due to the input dependence of the propagation delay, the last inverter
a very good approximation for most typical input wave
stage in the buffer should have a larger tapering factor than the other forms. Therefore, we may generalize our analytical
stages for minimum delay. expression for characteristic input waveforms. The prop
agation is then a function not only of the fan-out and the
driving capability of the stage itself, as in the step-re
I. I NTRODUCTION sponse model, but also a function of the fan-out and the
driving capability of the preceding stage. In a typical
Das a major technology for VLSI design. The use of
URING the 1980's, CMOS technology has evolved CMOS circuit application, the input-dependent propaga
tion delay may well account for as much as 50-100 per
algorithms to optimize circuit performance and software cent of the total delay.
simulations to verify logic and timing operation have be Even if the short-circuit power dissipation is neglected
come major tools in VLSI design. As a result, there is a in the analysis, the expression for the output waveform
strong need for accurate analytical models to describe cir may be used to approximately estimate the short-circuit
cuit operation in general and CMOS circuit operation in dissipation as long as it is small compared to the dynamic
particular. power dissipation. This is done in Section III. The prop
One important problem for VLSI design verification is agation delay may then be corrected to improve agree
to find precise models for the propagation delay. Circuit ment with SPICE simulations.
simulators, e.g., SPICE, consume too much CPU time to The capacitive loads of the CMOS inverter are studied
be practical for other than small circuits with less than a in Section IV in order to include the intrinsic delay of the
few hundred transistors, and logic simulators, e.g., inverter itself. Using this model, the optimum ratio be
TEGAS, that can handle up to several tens of thousands tween the widths of the P- and N-channel transistors in
of gates usually rely on insufficient delay models. Most the inverter may be determined. The analysis is per
textbook analytical models [I] for the transient response formed for inverters but may easily be extended to more
of CMOS inverters rely on step input waveforms. These complex logic gates.
delay models are generally insufficient since they do not In Section V, we give a few examples on how to apply
consider a realistic input waveform and consequently do the propagation delay model to buffers driving large ca
not take into account the influence of the input waveform pacitive loads in order to optimize the buffer for minimum
on the propagation delay. In real circuit applications, the delay. As a result, the optimum tapering factor between
input waveform will depend on the fan-out and the driving two individual inverter stages may be determined as a
capability of the preceding stage and, therefore, the prop process and design-style-dependent constant. The main
agation delay will also depend on these parameters. Re- result of the buffer optimization is that, when the intrinsic
delay is taken into account, the optimum tapering factor
Manuscript received March 3, 1986; revised November 14, 1986. is approximately 3-5, depending on th.e processing pa
The authors are with the Department of Solid State Electronics, School
of Electrical and Computer Engineering. Chalmers University of Technol
rameters and the design style, and not e (the base of the
ogy. S-412 96 G6teborg, Sweden. natural logarithm) as shown by Mead and Conway [5].
IEEE Log Number 8612996. Also, due to the input dependence of the delay, the ta-
0278-0070/87/0300-0270$01. 00 © 1987 IEEE
