Bridging RF and Power : An Introduction to

Envelope Tracking System and Building Blocks

Ji-Seon Paek ([email protected])

Pusan National University, Republic of Korea

February 20, 2023

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Self Introduction
 BS, MS, and PhD from Korea Advanced Institute of Science
and Technology (KAIST), South Korea, in 2004, 2006, 2011,
respectively

 Was with Samsung Electronics, Hwaseong, in 2011-2022

Aug.

 Associate Professor at Department of Electronics Engineering

of Pusan National University, Pusan, South Korea

 My research interests include RF integrated circuits (RFICs)

for wireless communication and sensing, power management
integrated circuits (PMICs) for various electronic devices

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Outline
 Envelope Tracking (ET) Motivation and History

 ET System Architecture and Building Blocks

 ET PA Link Budget Design

 Power Link Budget
 Noise Link Budget

 RF Transmission Requirements and SM-IC Technologies

 ET Evaluation

 Analog ET Limitations and Next

 Summary

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© 2023 IEEE International Solid-State Circuits Conference

Outline
 Envelope Tracking (ET) Motivation and History

 ET System Architecture and Building Blocks

 ET PA Link Budget Design

 Power Link Budget
 Noise Link Budget

 RF Transmission Requirements and SM-IC Technologies

 ET Evaluation

 Analog ET Limitations and Next

 Summary

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© 2023 IEEE International Solid-State Circuits Conference

Introduction : Envelope Tracking (ET)
 ET is one of the key power saving techniques in the mobile handset.

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 Motivation – Why ET?
 To amplify high PAPR RF signals  High linearity of an RF-PA required
 To get the high linearity  Large Power Back-OFF (PBO) operation required
 Large PBO operation  Very poor power efficiency of the RF-PA

VDD
Class-B linear PA ideal eff. =78.5%
VRFout(t)
VRFin(t)
Linear Class-B linear PA real peak eff. ~35%
PA
Cellular DFT-s-OFDM

PAE (%)
39.25% PAPR ~5.8dB

WiFi, Cellular CP-OFDM

ET can provide both of PAPR ~9dB
high linearity and high efficiency ~10% ! 6dB PBO
PBO Psat
* PAPR (Peak to Average Power Ratio) Output Power (dBm)
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 Power Back-Off by Signal PAPR
 6dB PAPR requires 6dB PBO  Ideal Class-B RF-PA efficiency
 Large PBO limits max. linear Pout  Max. efficiency 𝜂𝜂𝑚𝑚𝑚𝑚𝑚𝑚 = 78.5%
 6n dB PBO  𝜂𝜂 ⁄𝜂𝜂𝑚𝑚𝑚𝑚𝑚𝑚 =1/2n

Psat 30dBm Ideal Class-B RF-PA eff. @ Psat =78.5%

6dB PAPR
Pout.max 24dBm
Ideal Class-B RF-PA eff. @ Pout.max =39.25%
39.25%

PAE (%)
6dB PBO
10V
5V
t Pout.max Psat
@ 50Ω load
Output Power, Pout (dBm)
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 Power Back-Off by Transmit Power Control
PTX,DL 78.5%
Downlink PTX,UL=27dBm
Path
PRX,UL UE Ideal Class-B PA
Loss
Moving 39.25%

PAE (%)
PRX,DL PTX,UL=0dBm 6dB PBO
PTX,UL
Base Station
Uplink 24.8%
UE UE 10dB PBO
PTX,UL=23dBm Moving 1.8%
33dB PBO
0dBm 23dBm 27dBm 33dBm
Subframe #n, PTX,UL=23dBm Subframe #k, PTX,UL=0dBm Subframe #n, PTX,UL=27dBm
 To maximize cell capacity
Psat=29dBm
Pout.avg=23dBm
1 TTI = 1msec  UE transmit power control
(TPC) required
 Additional PBO for TPC required
* TTI (Transmission Time Interval) (DR : Pout.max – Pout.min)
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 Average Power Tracking (APT)
 Average power update time
 1 Transmit Time Interval (1TTI) = 1 sub-frame
 Average power transition time
 20μs (4G LTE), 10μs (5G NR)

VAPT
3.15V 1 TTI = 1m sec
VBAT 5V
APT DC-DC 0.225V
Converter
Psat (33dBm)
VAPT Vout(t) Psat (29dBm) Psat (6dBm) Pout.avg (27dBm)
Vin(t) Pout.avg (23dBm) Pout.avg (0dBm)
Linear
PA

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© 2023 IEEE International Solid-State Circuits Conference

Average Power Tracking (APT)
 Average power tracking provides a DC supply voltage to the RF-PA.
 APT-IC can be implemented by simple DC-DC converters.
 APT-IC should provide sufficiently high supply voltage to the RF-PA for
generating the Psat.
0.225V 78.5% 3.15V 5V
VBAT
APT DC-DC
Converter 6dB PBO
39.25%

PAE (%)
VAPT Vout(t)
Vin(t) 6dB PBO
Linear 6dB PBO
PA

6dBm 29dBm 33dBm

0dBm 23dBm 27dBm

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 Envelope Tracking (ET)
 Envelope tracking tracks the real-time envelope signal.
 Average power of the ET is controlled by the TPC from base-station.
 Peak ET supply voltage (VET.peak) = Max. APT voltage (VAPT.max)
 Average ET supply voltage (VET.ave) = APT voltage at PBO (VAPT.PBO)

VET 5V
VBAT 3.15V
Envelope
Tracker 0.225V
VET Vout(t) Psat (33dBm)
Vin(t) Psat (29dBm) Psat (6dBm) Pout.avg (27dBm)
Linear
PA Pout.avg (23dBm) Pout.avg (0dBm)

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Envelope Tracking (ET)
 ET tracks saturation power points of the RF-PA.
 Theoretically, with an ideal class-B RF-PA and an ideal ET-IC, 78.5% of PA
efficiency is possible over all transmit power range.

VBAT
0.112V 0.225V 1.58V 2.5V 3.15V 5V
78.5%
Envelope
Tracker
VET Vout(t)
Vin(t)

PAE (%)
Linear
PA

6dBm 29dBm 33dBm

0dBm 23dBm 27dBm

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Power Converters for APT and ET

APT Buck Converter Hybrid Supply Modulator

VBAT VBAT VBAT
APT DAC
DC-DC
Gate Gate
Driver Driver
VBB

Ripple β ET DAC SWAPT

SMOUT
APT DAC
To RF-PA β To RF-PA
Key Ref. [9], J. Choi, TMTT 2009

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 Linear Assisted Hybrid Supply Modulator
VBATT VBATT
APT DAC
BB IPA ISW
Gate
Driver
VBB

Current (A)
ILAin
ET DAC SWAPT
ISW 0mA

IPA SMOUT
ILAout ILAout
β To RF-PA Time (s)

 Wideband linear amplifier  regulates output voltage, provides low output

impedance & high frequency AC current to RF-PA
 High efficiency switching amplifier  provides low frequency DC current to RF-PA
 Buck-Boost converter  lowers the supply voltage of the linear amplifier
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SM Techniques for RF-PAs in Mobile Handset

RAT 2G 3G/4G 5G FR1 5G FR2 WiFi

RF-PA
GaAs HBT GaAs HBT GaAs HBT CMOS FET CMOS FET
Technology
MIMO or multi- 2 or 3 TX 4-6 Array 2x2 MIMO
TX EN-DC PAs 2x2 RSDB
TX Power From
O O O O
Control 802.11ax
30dBm
Max. Pout 35dBm 27dBm 27dBm 14-21dBm
EIRP
SM Scheme APT ET SPT SIMO APT

* SPT (Symbol Power Tracking)

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History of ET in Mobile Handset
Research LTE-A 20/40MHz ET 5G NR 100MHz ET & SPT
 EER (Envelope Elimination and
Restoration)


Multi-standard (2G/3G/4G)
Multi-mode (ET/APT)


100MHz ET BW
Fast transition FR1
 ET (Envelope Tracking)  Max. 40MHz ET BW  Multiple transmission
 SM-IC Structure : LDO, Fast switching  Low RX band noise  Memory DPD
Buck, Linear-assisted hybrid  PC2 HPUE
Galaxy S10 5G
 DPD
(1st 5G NR ET)

5G NR 400MHz APT & SPT

Kahn EER
Galaxy Note3
(1st commercial ET) FR2

1952 2013 2019 2023

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What makes it difficult to study ET?
 Need to study a multi-disciplinary area
 RF/analog/power integrated circuits
 Wireless communication system and digital communication

 Need to follow-up latest released wireless standards and different radio

access technologies (RATs)

 Need to learn different circuit analysis methodologies between PMIC and RFIC
 PMIC  Time domain waveform analysis
 RFIC  Frequency domain harmonic balance analysis

 Need to understand various RF calibration techniques for the ET validation

 Complex digital calibration and pre-distortion are required in the measurement.
 ET-PA measurement setup is not easy work.

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The Scope of This Tutorial
 What we will learn from this tutorial
 PM circuit designer
 How to design SM architecture and how to derive the SM design specifications
from wireless standards and RF-PAs
 RF circuit designer
 Difficulties and limitation of the power management circuit design for RF-PAs

 Scope of this tutorial : Bridging wireless communication, RF, and Power

 Wireless communication : 3GPP standards (RF TX requirements of UE)
 RF : Basic RF-PA principles and characteristics in aspect of power supply
 Power : SM-IC architecture and circuit building blocks

 What we will NOT cover (but are essential)…

 ET DPD, RF calibrations, RF TX circuits, digital ET front-end circuits

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Outline
 Envelope Tracking (ET) Motivation and History

 ET System Architecture and Building Blocks

 ET PA Link Budget Design

 Power Link Budget
 Noise Link Budget

 RF Transmission Requirements and SM-IC Technologies

 ET Evaluation

 Analog ET Limitations and Next

 Summary

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© 2023 IEEE International Solid-State Circuits Conference

ET System Architecture
Ref. [19], J.-S. Paek, VLSI-C 2021
Modem
TX Front-End MIPI Battery
Memory
Master
Supply
Shaping Timing
DAC Modulator
Function Alignment

Quadrature Error
CFR AMAM

Calibration
CORDIC

CORDIC
I/Q DPD DAC RF Tx SW PA Duplexer SW
θ PAMiD
AMPM
RFIC

DPD
ADC FBRX
Adaptation

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Hardware Component for ET (1/3)
Ref. [19], J.-S. Paek, VLSI-C 2021
 PAM Key Functions
Li-ion Battery Supply
 RF signal amplification Antenna
Modulator
 RF signal filtering
Vbatt VCCET ANT
 n77 PAM Components
Controller OVP CPLOUT
 GaAs HBT PA
IDACDA IDACPA OCP CPL
 CMOS controller
 Package PCB XFMR DA PA IPD Filter
 SOI SPDT switch Bias Bias

 IPD bandpass filter TX XFMROUT RX

DA PA LNA
 Coupler SOI SPDT SW
 Low Noise Amplifier XFMRIN XFMRINTS
DA PA MIPITX

* PAM (Power Amplifier Module) MIPIRX

GaAs HBT PA RF OVP
* SPDT (Single Pole Double Through) 5G LPA Module
* IPD (Integrated Passive Device)
* LPA (LNA & PA)
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 Hardware Component for ET (2/3)
 RF TX & FBRX Key Functions Ref. [19], J.-S. Paek, VLSI-C 2021

 BB-to-RF up-conversion
 RF-PA input driving
D/AI
 Distorted PA output capture 12b
 RF TX Architecture PA FEM
25%
Direct-conversion 2fLO DA
 LO
 I/Q quadrature modulation 12b
 RF TX Circuits D/AQ RF TX
 I/Q DACs with FBRX
 Baseband filters A/DI
12b Atten.
 TX LO generator
 Quadrature up-mixer A/DQ Buffer
 Drive amplifier 12b
 On-chip output balun * FBRX (Feedback Receiver)

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Hardware Component for ET (3/3)
Ref. [13], J.-S. Paek, ISSCC 2016
 SM-IC Key Functions
VBATT
 RF-PA Power Supply MIPI 2G LDO
 SM-IC Architecture
 Linear-assisted Hybrid MUX Switching
DAC Amplifier
 SM-IC Circuits VBATT
 ET DAC and APT DAC
Buck-
 MIPI digital interface Boost APT SW
 2-stage LA w/ class AB buffer
APT
 Switching amplifier Cap.
 BB converter for LA supply VDD_LA
CAC
 APT switch DAC LPF
 2G LDO and bypass switch CL
FB
 External passive components ET DFE
2-stage Linear Amplifier RF-PA

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Outline
 Envelope Tracking (ET) Motivation and History

 ET System Architecture and Building Blocks

 ET PA Link Budget Design

 Power and Gain Link Budget
 Noise Link Budget

 RF Transmission Requirements and SM-IC Technologies

 ET Evaluation

 Analog ET Limitations and Next

 Summary

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© 2023 IEEE International Solid-State Circuits Conference

ET PA Link Budget Design
 Interface between RF-PA and Antenna
 RF-PA power cell design VBATT
 RF-PA matching network design
SM-IC
 Interface between RF-PA and SM-IC Power Supply & Noise
 SM-IC peak output voltage Link Budget
 SM-IC maximum power capability
 SM-IC 3-dB signal BW RF TX PA M.N RFFE
 Interface between RF-PA and RF TX
 Voltage gain link budget Gain & Noise RF Power & Impedance
 DAC image rejection link budget Link Budget Link Budget
 EVM calculation by SNR link budget
 RX band noise link budget
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Linear RF-PA Operation Principles (1/7)
 Power device assumptions ID
ID Limitation
[reminded from ISSCC 2021 tutorial by Hua Wang]
 Device can be abrupted turned ON or OFF.
 Once ON, the device is completely linear ID=k•(Vgs-Vth)
Linear Response
 Device as ideal current source with ro  ∞
and no triode region
Vgs
 Hard limits on device output voltage and Vth
current ID
Vgs
 For simplicity, Vknee=0 and no parasitics Imax
ID Current ID=k•(Vgs-Vth)
Limit

Vds Vds Supply/Breakdown

Vgs Vgs Limited
Vds
Vknee Voltage Limit VDD

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Linear RF-PA Operation Principles (2/7)
 Ideal PA assumptions
 ro=∞, Vknee=0V, No parasitics VDD
 Ideal harmonic termination
RF Idc
 Ideal RF choke and DC block
Choke i1(f0)
 KCL Theorem iac=in(θ)
Id=Id(DC)+Id(AC)
vd vL
 i2,3,..(2f0,3f0,..)
 Id(AC)+IL(2f0,3f0,..)+IL(f0)=0 Zd DC
Block Ropt
 Ideal Harmonic Termination
id(θ)
 ZLC(f0)= ∞, ZLC(2f0,3f0,..)=0Ω vin
 Zd(f0)=Ropt, Zd(2f0,3f0,..)=0Ω
 Vd=id×Zd ZLC(f0)=∞, ZLC(2f0, 3f0, 4f0,..)=0Ω
 VL=iL(f0)×Ropt Zd(f0)=Ropt, Zd(2f0, 3f0, 4f0,..)=0Ω

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Linear RF-PA Operation Principles (3/7)
 Ideal Class-A and –B RF-PA Class-A Class-B
 ro=∞, Vknee=0V, No parasitics vin vin
 Ideal harmonic termination vin(DC)
 Ideal RF choke and DC block Vth t Vth t
VDD

RF Idc id Imax id Imax

Choke i1(f0)
iac=in(θ) Idc
vd vL Idc
DC i2,3,..(2f0,3f0,..) 0 t t
Zd
Block Ropt
id(θ) iac iac
vin
0 t 0 t
ZLC(f0)=∞, ZLC(2f0, 3f0, 4f0,..)=0Ω
Zd(f0)=Ropt, Zd(2f0, 3f0, 4f0,..)=0Ω

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Linear RF-PA Operation Principles (4/7)
 Magnitude of the nth harmonic of in(θ), In
 DC current (Idc), in(θ)=id(θ)-Idc vin

Iq + Imax − Iq � cos θ , −α⁄2 < θ < α⁄2

Vq
1. id θ = � Vth θ
0, −π < θ < −α⁄2 , −α⁄2 < θ < π α
2. cos α⁄2 = − Iq ⁄ Imax − Iq
3. id θ = (Imax − Iq ) � (cos θ + I
Iq
) id Imax
max −Iq

1 max α⁄ 2 I
4. Idc = 2π � ∫−α⁄2 1−cos( � (cos θ − cos α⁄2 ) � dθ
α⁄2)
Idc
5. In =
1 α⁄ 2
� ∫−α⁄2
Imax
� (cos θ − cos α⁄2 ) � cosnθdθ Iq
π 1−cos(α⁄2) θ
α
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Linear RF-PA Operation Principles (5/7)
id Imax
 I1(Class A)=I1(Class B)=Imax/2
 Idc(Class A)=Imax/2, Idc(Class B)=Imax/π)
 Ideal η = 50% (Class A), 78.5% (Class B) Idc
 Iq=Idc (Class A), Iq=0 (Class B) Iq
θ
α
Imax 2�sin(α⁄2)−α�cos(α⁄2)
6. Idc = 2π
�
1−cos(α⁄2)
Imax α−sinα
7. I1 = 2π
�
1−cos(α⁄2)
(VDD −Vknee ) I1
8. Pout1 = 2
�
2
, Pdc = VDD � Idc
9. R opt = VDD ⁄I1

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Linear RF-PA Operation Principles (6/7)
 For limited VDD and same id Imax id Imax id Imax
power cell size (= Imax) Idc
 I1,classA=I1,classB≠I1,classAB =Iq
Idc Idc
Ropt,classA=Ropt,classB≠Ropt,classAB α Iq
 θ θ Iq θ
α α
 Pout1,classA=Pout1,classB≠Pout1,classAB
i1 Imax/2 i1 Imax/2 i1 Imax/2
VDD
θ θ θ
RF Idc
Choke I1(f0)
Iac=In(θ)
vd vL
DC I2,3,..(2f0,3f0,..)
Zd vd VDD vd VDD vd VDD
Block Ropt VDD θ VDD θ VDD θ
id(θ)
vin
vL VDD vL VDD vL VDD
ZLC(f0)=∞, ZLC(2f0, 3f0, 4f0,..)=0Ω
0 θ 0 θ 0 θ
Zd(f0)=Ropt, Zd(2f0, 3f0, 4f0,..)=0Ω

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Linear RF-PA Operation Principles (7/7)
 Design example : 𝛼𝛼 of Class AB PA = 1.23𝜋𝜋.
 Conduction angle 𝛼𝛼 increase to 2𝜋𝜋 at 6dB PBO. vin
 ET keeps the conduction angle close to 𝜋𝜋 until
large PBO, so it can increase RF-PA efficiency. Vq
Vth θ
6dB PBO
Class A Class B Class AB α=1.23π
PBO
α η α η α η
0dB 2𝜋𝜋 50% 𝜋𝜋 78.5% 1.23𝜋𝜋 69.48% id Imax
6dB 2𝜋𝜋 12.5% 𝜋𝜋 39.25% 2𝜋𝜋 25%
12dB 2𝜋𝜋 3.12% 𝜋𝜋 19.62% 2𝜋𝜋 6.25%
18dB 2𝜋𝜋 0.78% 𝜋𝜋 9.81% 2𝜋𝜋 1.56%
Iq
θ

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 Link Budget (1/6): RF Power & Impedance
 PANT=27dBm, 6dB PAPR input signal VBATT
 Psat=33dBm  37dBm by FE losses
SM-IC
 Trade-off between SM-IC design PANT
and PA matching network design 6dB PAPR
RF TX PA M.N RFFE
𝑽𝑽𝑫𝑫𝑫𝑫 − 𝑽𝑽𝒌𝒌𝒌𝒌𝒌𝒌𝒌𝒌 𝐼𝐼1 𝑽𝑽𝑫𝑫𝑫𝑫 − 𝑽𝑽𝒌𝒌𝒌𝒌𝒌𝒌𝒌𝒌
𝑃𝑃𝑜𝑜𝑜𝑜𝑜𝑜𝑜 = � , 𝑹𝑹𝒐𝒐𝒐𝒐𝒐𝒐 = Loss 1dB 3dB
2 2 𝐼𝐼1
Pout.avg 31dBm 30dBm 27dBm
Psat 37dBm 36dBm 33dBm
VDD 1V 2V 3V 4V 5V
Z=R+jX Ropt 50Ω 50Ω
Ipeak(I1) 10 A 5A 3.34 A 2.5 A 2A
Vpeak VDD 40V 20V
Ropt 0.1 Ω 0.4 Ω 0.9 Ω 1.6 Ω 2.5 Ω
Imax 20 A 10 A 6.68 A 5A 4A Ipeak I1 800mA 400mA

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Link Budget (2/6): Power Supply
 ET tracks Psat points of the RF-PA.
 means a fixed Ropt (load line).
 Assumed ideal Class-B PA VSM.max
SM-IC VSM.rms
Psat=37dBm, Max. VDD=5V, Ropt=2.5Ω

VSM.min
 Max. VDD @Psat = VSM.max ISM.max
 VDD @Pout.avg = VSM.rms ISM.rms
 Idc.max @Psat = ISM.max
 Idc @Pout.avg = ISM.rms RF TX PA M.N RFFE
 VSM.min ≥ Vknee
Pout.avg
PBO VDD Idc Ropt PAPR
Psat
0dB VSM.max 5V ISM.max 1.28 A 2.5 Ω
6dB VSM.rms 2.5 V ISM.rms 0.64 A 2.5 Ω

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© 2023 IEEE International Solid-State Circuits Conference

Link Budget (3/6): Power Supply
 Typical Li-ion battery range : 3.0V ≤ VBATT ≤ 4.2V
 VBB ≥ VSM.max-VAC+VovP, VLA.max = VSM.max-VAC
 VAC = VSM.min-VLA.min, VSM.min ≥ Vknee, VLA.min ≥ VovN

VBATT VBATT

SA VSM.max
BB VBB
≥ VovP
VSW VLA.max
VSM
VBB VBATT
VLA
VovP
DAC LA VLA VSM VAC
VovN - +
VAC VLA.min
≥ VovN
1/β
Ji-Seon Paek T2: Bridging RF and Power : An Introduction to Envelope Tracking System and Building Blocks 35 of 93

© 2023 IEEE International Solid-State Circuits Conference

Link Budget (4/6): Power Supply
 5V of supply voltage requires RF Specification & Fixed Parameters
a design of buck-boost
PANT 27dBm RF-PA Vknee 1V
converter in the SM-IC.
Available
 AC coupling scheme improves RF signal PAPR 6dB
max. VDD
5V
the overall SM-IC efficiency
RFFE & M.N loss 4dB LA VovP & VovN 0.2V
by reducing the supply
voltage of the inefficient linear RF-PA Design SM-IC Design
amplifier (LA). Required Psat 37dBm VSM.max 5V
 1.6Ω of optimum impedance Ropt 1.6Ω VAC 0.8V
requires a large impedance Iq 150mA VBB 4.4V
conversion  Differential
VDD for 6dB PBO 3V VSM.rms 3V
topology is employed in the
latest FR1 cellular HBT GaAs Idc.max @Psat 1.6A ISM.max 1.6A
PA design. Idc @PPBO 0.82A ISM.rms 0.82A

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© 2023 IEEE International Solid-State Circuits Conference

Link Budget (5/6): RX Sensitivity
 Sensitivity  Minimum signal level that a receiver
can detect with acceptable quality of SNR SM-IC
PTX,UL=27dBm
 PA output noise at receiver frequency band
degrades the RX sensitivity in FDD system. Duplexer PA RF TX
PRX,DL=-105dBm
PTX,DL RxBN
RxBN
PTX,UL=27dBm LNA RF RX
Downlink PRX,DL=-105dBm UE2
PRX,UL
Path
Loss Interference
PRX,DL
PTX,UL PTX,UL=23dBm
Base Station PRX,DL=-95dBm
Uplink
UE1
UE3

Ji-Seon Paek T2: Bridging RF and Power : An Introduction to Envelope Tracking System and Building Blocks 37 of 93

© 2023 IEEE International Solid-State Circuits Conference

Link Budget (6/6): Rx Band Noise (RxBN)
1. PRX ≥ Psensitivity|dBm = −174 dBm⁄Hz + NFRX + ILRX + 10 � logBW + NPA.leak + SNR ADC.min
2. NPA.leak|dBm = NPA.tot|dBm + IDuplexer|dB
3. NPA.tot W = NRFIC � GPA + NPA + 𝐍𝐍𝐒𝐒𝐒𝐒 � PSRR PA

VBATT PSD
NSM α1• PTX
NSM DPD
D/A SM PSM Coupler
Atten. A/D
freq.
PTX PRX
LO PSRRPA LO
ILFEM ILRX
SNRADC.min
NRFIC PPA LRX•PRX I/Q
D/A PPA PA A/D
NPA.tot NPA.leak
NPA Duplexer LNA
IDuplexer NFRX

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© 2023 IEEE International Solid-State Circuits Conference

Outline
 Envelope Tracking (ET) Motivation and History

 ET System Architecture and Building Blocks

 ET PA Link Budget Design

 Power and Gain Link Budget
 Noise Link Budget

 RF Transmission Requirements and SM-IC Technologies

 ET Evaluation

 Analog ET Limitations and Next

 Summary

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© 2023 IEEE International Solid-State Circuits Conference

RF TX Challenges From 2G to 5G (1/2)
TX Characteristic Issue & Challenges Solutions
 452.5 - 5925 MHz of wide frequency
- Multi-mode, Multi-band RF Front-End
Operating Bands range
design
 ET BW limitation by multiple PA load - Wideband linear amplifier (LA) design
capacitance and PCB trace inductance - Multiple SM output support by integrated
Channel BW switches
 100 MHz of 1CC NR BW - LA integration in PA module

 35 dBm 2G GSM - Seamless LDO for 2G APT (Bypass to

Max. Output Power battery)
 27 dBm of Power Class2 for HPUE
- Boosted supply voltage generation for RF-
 10 μs of On/Off time mask and TPC PA
TX Power Control timing - Fast transient buck-boost converter
 70 dB output power dynamic range - ET and APT mode support

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© 2023 IEEE International Solid-State Circuits Conference

RF TX Challenges From 2G to 5G (2/2)

TX Characteristic Issue & Challenges Solutions

TX Signal Quality  EVM, Carrier leakage - I/Q calibration in digital front-end

 E-UTRA ACLR and SEM degradation - Memory DPD and closed-loop DPD
by memory effect of 100 MHz - Wideband SM and wideband feedback RX
ORFS Emission
wideband signal - Soft-transition reference generation in SM-
 2G PVT switching ORFS IC

Ref. Sensitivity - Saw-Less TX design, Low noise SM

 Low RX band noise for FDD system
Power design

Ji-Seon Paek T2: Bridging RF and Power : An Introduction to Envelope Tracking System and Building Blocks 41 of 93

© 2023 IEEE International Solid-State Circuits Conference

RF Challenges and SM Technology (1/8)
1. 2G RF challenges : Power Versus Time (PVT) and 35dBm output power

Maximum multi-slot transmission(4slot)

APT supply voltage

Slot3

Guard Ramp up Ramp down

Slot1 Slot2 Slot4
10u 577u 10u 10u 10u 10u
GP 1slot(burst) GP 1slot(burst) GP 1slot(burst) GP 1slot(burst) GP

 2G APT is one of worst operation cases in APT mode.

 Critical transition case is 0.4 to 4.2V transition within 10μs in 2G APT.
 Large current consumption around 2A at peak output power of 35dBm
 4.7uF + fast transition  2.5A peak current (Over Current Protection)

Ji-Seon Paek T2: Bridging RF and Power : An Introduction to Envelope Tracking System and Building Blocks 42 of 93

© 2023 IEEE International Solid-State Circuits Conference

RF Challenges and SM Technology (1/8)
1. SM challenges : DC-DC converter BW limit and Big IR drop at low VBATT

Vin Vout
Vin
1
A0β,ω0 𝜏𝜏 =
4.6𝜏𝜏 99%
1 + 𝛽𝛽𝐴𝐴0 𝜔𝜔0
Vout
1/β

 99% settling time of a one-pole system is 4.6𝜏𝜏.

 A0 (open-loop DC gain), ω0 (dominant pole), A0ω0 (unit GBW), β (feedback gain)
 Large 3-dB signal BW are required to reach the target output voltage within
10μs of guard period.
Ji-Seon Paek T2: Bridging RF and Power : An Introduction to Envelope Tracking System and Building Blocks 43 of 93

© 2023 IEEE International Solid-State Circuits Conference

RF Challenges and SM Technology (1/8)
1. SM challenges : DC-DC converter BW limit and Big IR drop at low VBATT

VBATT
ΔVout
IS Δt ∆𝑉𝑉𝑜𝑜𝑜𝑜𝑜𝑜 Ron Big IR drop
𝐼𝐼𝑆𝑆 = 𝐶𝐶𝐿𝐿 + 𝐼𝐼𝐿𝐿
∆𝑡𝑡
IL Vout
IC IL
𝑉𝑉𝐼𝐼𝐼𝐼 = 𝐼𝐼𝑆𝑆 � (𝑅𝑅𝑜𝑜𝑜𝑜 + 𝑅𝑅𝐸𝐸𝐸𝐸𝐸𝐸 ) RESR
CL >2A

 Large sourcing current is required for both of fast DVS and a current load.
 The buck converter cannot regulate output voltage at low battery level due to
the big IR voltage drop, VIR.
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© 2023 IEEE International Solid-State Circuits Conference

RF Challenges and SM Technology (1/8)
1. SM Technologies : Hysteretic controlled buck & Bypass LDO
VBATT VBATT

VRef VRef
RLDO RON RLDO RON
VOS VOS
Rf1 L RESR Rf1 L RESR
Vout Vout
Rf2 CL Rf2 CL

< Buck mode > < LDO/Bypass mode >

 An ripple-based hysteretic controlled buck converter has wide bandwidth.

 At peak output power in 2G APT, only bypass switch can provide large current
higher than 2A.
Ji-Seon Paek T2: Bridging RF and Power : An Introduction to Envelope Tracking System and Building Blocks 45 of 93

© 2023 IEEE International Solid-State Circuits Conference

RF Challenges and SM Technology (2/8)
2. 4G/5G RF challenges : Cell coverage extension by Power Class2 HPUE

Power Class-2
PTX,UL=27dBm

HP
Coverage Up Power Class-3
PTX,UL=23dBm UE
Base Station

UE

 High Power User Equipment (HPUE) for Power Class-2 (PC2) is required to
increase cell coverage and capacity.
Ji-Seon Paek T2: Bridging RF and Power : An Introduction to Envelope Tracking System and Building Blocks 46 of 93

© 2023 IEEE International Solid-State Circuits Conference

RF Challenges and SM Technology (2/8)
2. SM challenges : Boosted output voltage with Fast DVS speed

1 𝐼𝐼�𝑜𝑜
𝑉𝑉𝑜𝑜𝑜𝑜𝑜𝑜 = 𝑉𝑉𝐵𝐵𝐵𝐵𝐵𝐵𝐵𝐵 𝐼𝐼𝐼𝐼𝐼𝐼𝐼𝐼 =
VBATT ΦB 1 − 𝐷𝐷 1 − 𝐷𝐷
D
ID Io
ΦA ΦB  Discontinuous output current delivery

Vout  Large inductor current

 Slow DVS speed
IInd ID
 Degradation of loop stability
ΦB ΦA Io
 Output spike by parasitic inductance

Ji-Seon Paek T2: Bridging RF and Power : An Introduction to Envelope Tracking System and Building Blocks 47 of 93

© 2023 IEEE International Solid-State Circuits Conference

RF Challenges and SM Technology (2/8)
2. SM Technologies : Voltage-tolerant 3-level Buck-Boost Converter
VBATT Ref. [21], J. Baek, ISSCC 2020
 Continuous output current delivery
 Decrease avg. inductor current, (1-
S1 D) times lower
 Low conduction loss
Continuous
 Voltage-tolerant operation
S5 S2 current delivery
 All switches voltage within VBATT
Vout
CF  No RHP zero
S3 Io
 Wide loop bandwidth
 High phase margin
 Low switching spike at output node
S4  Small output capacitance required
 Decreased device damage issues

Ji-Seon Paek T2: Bridging RF and Power : An Introduction to Envelope Tracking System and Building Blocks 48 of 93

© 2023 IEEE International Solid-State Circuits Conference

RF Challenges and SM Technology (3/8)
3. 4G/5G RF challenges : Narrow or Wide OFDM signal bandwidth

 Signal BW ≠ Channel BW (CBW) =

=
 Min. CBW of 1CC
 4G  1.4MHz
 5G  5MHz (FR1), 50MHz (FR2)
 Max. CBW of 1CC fLO
 4G  20MHz
 5G  100MHz (FR1), 400MHz (FR2) μ LTE 0 1 2 3 4
 Min. signal BW (1RB allocated) fscs
15 15 30 60 120 240
 4G/5G  12×15kHz=180kHz (kHz)
 Max. signal BW (1CA, full RB) Max. CBW
20 50 100 200 200 400
 4G  20 MHz (MHz)
 5G  100MHz (FR1), 400MHz (FR2)

Ji-Seon Paek T2: Bridging RF and Power : An Introduction to Envelope Tracking System and Building Blocks 49 of 93

© 2023 IEEE International Solid-State Circuits Conference

RF Challenges and SM Technology (3/8)
3-1. SM challenges : 3-dB signal BW of an linear stage

LPF
D/AET I2V Rin LA BB
SMOUT

ENV+ Rf
ENV- PA
Cf

 The linear amplifier (LA) with a closed-loop feedback regulates the SM output
and provides low output impedance for AC voltage source.

Ji-Seon Paek T2: Bridging RF and Power : An Introduction to Envelope Tracking System and Building Blocks 50 of 93

© 2023 IEEE International Solid-State Circuits Conference

RF Challenges and SM Technology (3/8)
3-1. SM challenges : 2-stage linear amplifier with class-AB output buffer

Zf |A(s)|
Cf A0
gm2 variation
Rf CCCS
3dB BW variation
Rin+Rf 1
Vi Rin Vo2
-A0 Rin β
Vx' Vx 0dB
Fixed 3dB BW
RPA CPA ωp 1 1 ωu ω
RfCf (Rin//Rf)Cf

 Fixed 3dB signal BW (1⁄𝐶𝐶𝑓𝑓 𝑅𝑅𝑓𝑓 )and large unit gain BW (ωu) are desirable.
 To increase the loop BW while achieving a sufficient phase margin, the
parasitic capacitance, CPA of the RF-PA power cell should be minimized
𝑉𝑉𝑜𝑜𝑜 𝑅𝑅𝑓𝑓 1 1
 𝐴𝐴𝑐𝑐𝑐𝑐 𝜔𝜔 = ≈ � , 𝑖𝑖𝑖𝑖 𝜔𝜔𝑢𝑢 ≫
𝑉𝑉𝑖𝑖 𝑅𝑅𝑖𝑖𝑖𝑖 1+𝑠𝑠𝐶𝐶𝑓𝑓 𝑅𝑅𝑓𝑓 𝐶𝐶𝑓𝑓 𝑅𝑅𝑓𝑓
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© 2023 IEEE International Solid-State Circuits Conference

RF Challenges and SM Technology (3/8)
3-1. SM Technologies : Load and PA supply capacitance control

Cf A0

Rf CCCS
Cf control CL(2.2nF)
3dB BW
Vi Rin -A0 Vo2 Rin CL(0.2nF)
~nF Rin+Rf
CL
~0.2nF
5G Legacy
PA PAs 30MHz 120MHz
Unit GBW

 Adaptive load control and legacy PA parasitic supply capacitor isolation

 Second pole (ω2) frequency and unit gain bandwidth (ωu) ↑
 Zero capacitor (Cf) tuning
 3dB signal bandwidth ↑
Ji-Seon Paek T2: Bridging RF and Power : An Introduction to Envelope Tracking System and Building Blocks 52 of 93

© 2023 IEEE International Solid-State Circuits Conference

RF Challenges and SM Technology (3/8)
3-2. SM challenges : Reverse current at narrow BW and low VBATT
VBATT Normal VBATT
VBATT 0.6
ISW IPA
SMOUT SA 0.4

Current [A]
0.2
VBB ISW
ILAout 0
SMIN
LA -0.2
ILAout
IPA -0.4
10 20 30 40
SMOUT Time [µs]

 When the signal BW is narrow, the inductor current has higher slew rate
(𝑑𝑑𝐼𝐼𝑆𝑆𝑆𝑆 ⁄𝑑𝑑𝑑𝑑) than the envelope signal at any signal frequency.
 Thus, the switching amplifier (SA) provides most of the load current.
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© 2023 IEEE International Solid-State Circuits Conference

RF Challenges and SM Technology (3/8)
3-2. SM challenges : Reverse current at narrow BW and low VBATT
VBATT Low VBATT
0.6
SMOUT ISW
VBATT SA 0.4

Current [A]
0.2
VBB ISW IPA
ILAout 0
SMIN
LA -0.2
ILAout Reverse current
IPA -0.4
10 20 30 40
SMOUT Time [µs]

 Reverse current conditions

 Narrow signal BW, Low battery level, Boosted SM output voltage, Small inductance
 Issues
 Peak signal clipping, Power efficiency degradation
Ji-Seon Paek T2: Bridging RF and Power : An Introduction to Envelope Tracking System and Building Blocks 54 of 93

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RF Challenges and SM Technology (3/8)
3-2. SM Technologies : Dynamic buck supply switching

VBATT VBB VBATT VBB

BB BB
VBB
LA LA
VSW VTX
VSW VBATT
VSW CAC CAC
VSW

VTX VTX Time(s)

@ VTX < VBATT @ VTX > VBATT ET operating waveform
Return-to-Battery
Typical Switching Switching

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RF Challenges and SM Technology (4/8)
4. 4G/5G RF challenges : Transmit Power Control and Transition Time

1. TX Power Control
PTX,DL
PTX,UL=27dBm  70dB dynamic
Downlink
PRX,UL UE range
Path
Loss Moving
PRX,DL PTX,UL=0dBm 2. TX Power Update
PTX,UL
Base Station Time
Uplink
UE UE  LTE = 1 sub-frame
Moving  NR = 1 symbol
PTX,UL=23dBm

3. TX Power Transition
Time
PTX,UL=23dBm PTX,UL=0dBm PTX,UL=27dBm
 LTE = 20μs
 NR = 10μs
Ji-Seon Paek T2: Bridging RF and Power : An Introduction to Envelope Tracking System and Building Blocks 56 of 93

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RF Challenges and SM Technology (4/8)
4-1. SM challenges : Fast DVS for Symbol Power Tracking
5.0V
4G LTE

0.4V
ΔVout
Transition < 10us Time(s) IS Δt
APT, 0.4V ET, 5.0V APT, 2.0V
C
Subframe1 C
Subframe2 C
Subframe3
IL
P P P
IC
IL
CL
5.0V
5G NR

0.4V Transition < 2us Time(s) ∆𝑉𝑉𝑜𝑜𝑜𝑜𝑜𝑜

∆𝑡𝑡 = 𝐶𝐶𝐿𝐿
APT, 0.4V ET, 5.0V APT, 2.0V 𝐼𝐼𝑆𝑆 − 𝐼𝐼𝐿𝐿
C
P Symbol1 C
P Symbol2 C
P Symbol3
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 RF Challenges and SM Technology (4/8)
4-1. SM Technologies : Pre- & Post-transition with background transition

 APT  APT (UP)

Output APT APT APT Output APT APT APT
 Pre-transition (VBB)
Mode APT ET APT Mode APT ET APT
SW APT ON OFF ON SW APT ON OFF ON  APT switch off
SW CHG OFF Charge CL2 OFF SW CHG OFF Charge CL2 OFF
 Fast transition by LA
No transition  Background transition
Voltage (V)

Voltage (V)
Transition by of VDD.LA of SA
Background
linear amplifier
Transition by VAPT transition
Pre-transition (ET mode)
of VDD.LA linear amplifier  APT  APT (DOWN)
Background (ET mode)
VAPT transition  APT switch Off
 Fast transition by LA
 Background transition
Time/Symbol Time/Symbol of SA

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RF Challenges and SM Technology (4/8)
4-2. SM challenges : ET efficiency degradation at large PBO

ET-PA eff. Curve  ET efficiency is lower than APT

w/ ideal SM efficiency from certain back-off
power.
ET
 Optimum operation scenario
PAE (%), Gain (dB)

APT ET  ET for high output power

 APT for mid/low output power
APT Back-off
PAPR
 ET dynamic range is limited by an
ET Dynamic inefficient linear amplifier.
Range Max.  SM efficiency improvement scheme
linear Pout  LA supply voltage scaling
 AC coupling
CW Output Power (dBm)
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 RF Challenges and SM Technology (4/8)
4-2. SM Technologies : AC coupling and scalable supply techniques

Linear stage output SM output

3.6V
3.2V
2.8V  Supply voltage is much
High 1.2V reduced by AC coupling
Power - 0.8V + capacitor.
0.4V
Voffset: Controlled by 5b DAC
 Supply voltage is scaled
1.8V down to 1.8V according
1.8V
1.4V to output swing.
Low
Power - 0.4V + 1.0V
0.6V

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© 2023 IEEE International Solid-State Circuits Conference

RF Challenges and SM Technology (5/8)
5. 4G/5G RF challenges : RX sensitivity degradation in FDD system

VBATT PSD
NSM NSM α1• PTX DPD
D/A SM PSM Coupler
Atten. A/D
freq.
PTX PRX
LO PSRRPA LO
ILFEM ILRX
SNRADC.min
PPA LRX•PRX
PPA NRFIC PA
I/Q
D/A A/D
NPA.tot NPA.leak
NPA Duplexer LNA
IDuplexer NFRX

 SM output noise is modulated to the RF-PA output at RX band offset frequency

and it degrades RX sensitivity in FDD system.

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RF Challenges and SM Technology (5/8)
5. SM challenges : Large buck switching noise

Open-loop Zind w/ Cp
Vn L Cp
Switching noise model
noise
Buck Vn f
Mid. Freq. Offset (50-100 MHz)
Zind Zind
ZLA
ZLA A0
Vout Vout
A0
CL RL Zout RL β
β Low Freq. Offset High Freq. Offset
(<50 MHz) (>100 MHz)

 Major noise source of the SM is the buck switching noise.

 To reduce switching noise, large Zind and small Zout are required.
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RF Challenges and SM Technology (5/8)
5. SM Technologies : Resonant Frequency Tuning (RFT)

Vbatt CVAR

Impedance (ohm)
|L0//(CP±CVAR)|
Gate driver

L0

C2 fopen
CP
Freq. (Hz)

 Parasitic capacitance Cp causes mid-band noise degradation.

 Capacitance in in-phase path reduces the resonance frequency.
 Capacitance in out-phase path increases the resonance frequency.
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Summary of SM Technologies for Cellular FR1 PAs

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SM Example for Cellular FR1 RF-PAs
Ref. [22], D. Kim, ISSCC 2021
VBATT
 Topology
2G LDO VREF.APT (APT) High VOUT/POUT VBATT Interleaved-BB
VREF.APT Buck-boost
S1
Large IOUT
VBAT Buck-boost
Fast DVS  Linear-assisted hybrid
Controller SA3 SA1

MUX
(+OCP, OVP)
Controller
(+OCP, OVP) SA4 SA2
 Sub-blocks
APT S2 CFA
DAC S5 ILA/VCAC (ET)  2-stage linear amplifier
VLX1 S7 S6
CF
S3
LBB1 VBATT  3-level buck-boost
MIPI
High VOUT CAPT
SB3 SB1
converters
RFFE APT Eff. @ Low POUT RFT
S4
micro-BB Capacitor VLX2 SB4 SB2  AC coupling
Pre-charger CFB
Linear Amplifier LBB2  2G LDO
ILA VCAC
LPF/Buffer  RFT
(+ET OVP) VOUT.LA CAC SWCL CL
High POUT OTA Buffer CPA.LMH isolation for NR  APT DAC and switch
Output stage VOUT.APT VOUT.ET1 VOUT.ET2
VOUT.ET1/2
160MHz 3-dB BW β
SWAPT SWOUT  Load cap. Isolation
Modem Power switch
LPCB.UHB Small LPCB/CPA Amplifiers
ET
DAC
Shaping
Function
LPCB.2G
CPA5
(~1nH)
CPA7 (~200pF)
LPCB.LMH
CPA6 (~2nF)
 OTP and MIPI digital
RFIN.2G 2G RFOUT.2G RFIN.UHB RFOUT.UHB RFIN.LMH L/M/H RFOUT.LMH
 Protection circuits
5G PA
CORDIC CFR & DPD To RFIC PA2
Large IOUT (3A)
High P OUT
PA High POUT  BGR and analog circuits
130MHz BW Low Noise

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 RF Challenges and SM Technology (6/8)
6.-8. RF challenges : Various RF and wireless technologies

Coverage  Various wireless technologies

 Cellular : 2G, 3G, 4G, 5G
100km
 Connectivity : WiFi, BT, UWB

250m  Different access technologies

 Network options, multiple access
150m

 Different signal properties

50m
 PAPR, Digital modulation schemes
15m
5m  Different RF specifications
Hz  Max. output power, EVM, SEM, etc.
0.6G 2.4G 10G 28G 60G 77G Sub-THz

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 RF Challenges and SM Technology (6/8)
6. SM challenges : EN-DC network and multiple RF TX support

NSA EN-DC Data/User Plane Control Plane eNB

SM #1 LTE
EPC 5GCN EPC 5GCN 5GCN 5GCN
Backhaul
Link RF TX1 PA1

eNB gNB eNB gNB gNB eNB eNB eNB gNB UE

Radio SM #2
Access 5G gNB
NR
RF TX2 PA2
Option1 Option2 Option3 Option4 Option5 Option7
5G Mobile Handset

 SA (Stand-alone)  Option 1/2/5

 NSA (Non Stand-alone)  Option 3/4/7
 EN-DC  Dual-connectivity between LTE and NR while employing 4G core network
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RF Challenges and SM Technology (6/8)
6. SM techonogies : EN-DC network and multiple RF TX support
L1 L0
BB1 SIMO BB  Multiple simultaneous RF
VBATT
transmission
LA1 SA1 VBATT  requires multiple RF-PAs and SMs.
PA1 LA1 SA1
L2
BB2 PA1  Multiple SMs
VBATT VBATT
 requires many passive components
LA2 SA2 LA2 SA2 such as power inductors and
capacitors.
PA2 PA2
L3 VBATT
BB3  SIMO dc-dc converter technology
VBATT LA3 SA3
PA3  can reduce number of external
LA3 SA3 components and BOM cost.
PA3
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RF Challenges and SM Technology (7/8)
7. SM challenges : Local PMIC and SPT for 5G FR2 mmWave Transceiver

Limitation of ET in mmWave
Low efficiency gain by ET
ET > 600 MHz DPD bandwidth
400 MHz system ~tens of psec time alignment
wideband
Envelope generation
SM-IC > 600 MHz SM bandwidth (w/ large CL)

 PMIC is integrated inside antenna module for stable voltage regulation.

 5G mmWave NR allows symbol level power change. (within CP time <300ns)
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RF Challenges and SM Technology (7/8)
7. SM challenges : Local PMIC and SPT for 5G FR2 mmWave Transceiver

Average Power Tracking in LTE

Subframe n Subframe n+1 Subframe n+2

Tsubframe=1ms

VAPT(t)

Ttran=5µs

APT (LTE, 15kHz SCS) SPT (5G mm-Wave, 240kHz SCS)

Update time 1 Subframe (1ms) 1 Symbol (Min. 4.16µs)
Transition time 1 CP (4.7µs) 1 CP (Min. 290ns)

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RF Challenges and SM Technology (7/8)
7. SM techonogies : Local PMIC and SPT for 5G FR2 mmWave Transceiver

 Sub-blocks
 SPT/SIDO buck converters
 1.1V LDO
 Fast linear charger
 Internal DAC, clock, controller, etc.

 Regulated output voltages

 VSPT (0.4V~3.3V) for mmWave PAs
 1.3V for LDO supply voltage
 1.1V for other mmWave RF circuits
Ref. [20], J.-S. Paek, ISSCC 2019

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 RF Challenges and SM Technology (7/8)
7. SM techonogies : Local PMIC and SPT for 5G FR2 mmWave Transceiver

VSPT
VC1
③ ① Pre- transition by SIDO buck
VC2

② ② APT switch off & Fast DVS by

Voltage (V)

① linear charger
②
① ③ ① ②
③ Capacitor swap
③ : Switch ON for CL1 or CL2

Time/Symbol

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 RF Challenges and SM Technology (8/8)
8. SM challenges : Multiple Simultaneous Supply Modulations for WiFi
Ref. [5], J.-S. Paek, VLSI-C 2022
2.8~4.5V 35% Eff. @Psat ~ 35%

BK4 Buck1 Buck2 Buck3 APT 11% @ 21dBm for 802.11b

1.9V 1.25V 0.9V iPA 8% @ 18dBm for 802.11a

PAE (%)
0.75V 6dB PBO
LDO4 LDO6 LDO1 LDO5 APT 6% @ 15dBm for
802.11ax 9dB PBO
LDO10 LDO7 LDO2 LDO8
iPA 12dB PBO
LDO11 LDO9 LDO3 LDO12 15dB PBO
APT 30dBm
Output Power (dBm)
iPA

APT
WiFi Modem WiFi RF Transceiver iPA

 WiFi RFIC integrates RF-PAs for a low-cost solution.

 SM technique using dc-dc converter is required to increase the low eff of CMOS PA.
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RF Challenges and SM Technology (8/8)
8. SM technologies : Multiple Simultaneous Supply Modulations for WiFi
This work 3-level Interleaving Fully Integrated
BB Converter Capacitor Divider
CMOS PAs
VBATT VAPT
Gate Gate VO6
Driver Driver VDD1
VO5
RFin1 PA

Capacitor Balancer

Supply Selection MUX

VO4
7b Controller & 2.4GHz
APT Compensator VLX VO3 VDD2
VBATT
VO2 RFin2 PA
Gate Gate VO1 2.4GHz
Driver Driver VDD3
VBATT
VBATT RFin3 PA
5GHz
Buck LDOs LDOs LDOs LDOs
VDD4
RFin4 PA
I1/Q1 5GHz
WiFi Modem SoC I4/Q4
WiFi RF Transceiver
Ref. [5], J.-S. Paek, VLSI-C 2022
 SIMO dc-dc converter can provide
an optimum supply voltage to each PA while minimizing external BoM cost
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Outline
 Envelope Tracking (ET) Motivation and History

 ET System Architecture and Building Blocks

 ET PA Link Budget Design

 Power Link Budget
 Noise Link Budget

 RF Transmission Requirements and SM-IC Technologies

 ET Evaluation

 Analog ET Limitations and Next

 Summary

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ET Evaluation

RFIC TX + PA + ETIC Test Condition

MIPI Supply Item Parameter
VBATT
PC (DPD)
SMOUT QPSK/16QAM
DPD I/Q Waveform
SM-IC
SM IC Oscilloscope /64QAM/256QAM
Signal SMIN
Generator RB allocation Outer / Inner

PAOUT
Analog
Digital I/Q I/Q Supply Mode APT / ET
MUX
Spectrum
Coupler Controller

n77 PAM
RFPA Channel BW 10 / 40 / 100 MHz
Filter

RF TX
Switch

Analyzer
PA

PAIN LNA

Test Channel Low / Mid / High

To loopback path (Feedback Receiver)
SCS 30 kHz
Demodulated distorted PA output I/Q data
Duty Cycle 22.8 %

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 ET Evaluation
Reference Signal  ET-DPD Procedure
1. Measure CW Water-fall

Amplitude
Efficiency Tracking Curve
Curve 2. Estimate max.VCC.ET and
ave.VCC.ET from the
Distorted
PAE (%), Gain (dB)

Signal constant gain tracking

curve
Time (s)
AM-AM & AM-PM Curves 3. Setting the Wave shaping
AM-AM
Before DPD function (Detrough,
After DPD
Polymonial, Linear)
Constant Gain
Tracking by ET-DPD 4. Capture the distorted
signal’s AMAM & AMPM
Output

Output Power (dBm) Before DPD curve and DPD coefficient

AM-PM
After DPD extraction
5. Pre-distortion signal
Input generation & PA test

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ET Evaluation
SM Stand-alone Measurement with 3Ω Load ET-PA Measurement with designed n77 PAM
86 4.30 -30

High Power 3.80

84 950mW saving

DC Power Consumption (W)

Mode -32
3.30
APT PA
SM Efficiency (%)

82

ACLR (dBc)
ET PA -34
2.80
80
Low Power 2.30
Mode -36
78
1.80

76 -38
1.30
ACLR
74 0.80 -40
0.5 1 1.5 2 2.5 3 3.5 4 17 19 21 23 25 27
Average SM Output Power (W) PA Output Power (dBm)

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ET Evaluation
Performance Summary
Supply Pout ACLR Pdc (W) *PAEPAcore EVM
CP-OFDM NR 100MHz QPSK Modulation *100%
Mode (dBm) (dBc) (%) (%)
26dBm, -38.4/-41dBc ACLR duty

DFT_QPSK APT 27 -37.15 4.1 24.4 1.4

100MHz ET 27 -37 3.15 31.7 1.54
CP_QPSK APT 26 -38.27 4.13 19.2 1.27
100MHz ET 26 -38.4 3.17 25.1 1.29
DFT_256QA APT 24.5 -38.27 2.54 22.1 1.6
M
CP-OFDM NR 100MHz 256QAM 100MHz ET 24.5 -38.3 2.09 26.9 1.34
23dBm, 1.22% EVM
CP_256QAM APT 23 -42.06 2.54 15.7 1.5
100MHz ET 23 -41.55 1.9 21.0 1.22

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Outline
 Envelope Tracking (ET) Motivation and History

 ET System Architecture and Building Blocks

 ET PA Link Budget Design

 Power Link Budget
 Noise Link Budget

 RF Transmission Requirements and SM-IC Technologies

 ET Evaluation

 Analog ET Limitations and Next

 Summary

Ji-Seon Paek T2: Bridging RF and Power : An Introduction to Envelope Tracking System and Building Blocks 80 of 93

© 2023 IEEE International Solid-State Circuits Conference

Analog ET Limitation
VBATT SM SM Output
CAC Interface
LA

CSM RSM
RDAC CDAC LPCB
CPCB Buck
IPA
SM Input
ET DAC Interface

CPA2 CPA1

Memory
DPD
PA2 PA1

 Analog ET has reached its bandwidth and efficiency limits.

 Digital ET is a next generation technology that can break through technical
limitations.
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Next ET – Digital Envelope Tracking

 Digital ET tracks the discrete level instead of fully tracking the envelope signal.
 Pros : Larger BW, Delay robustness, Smaller die area and BoM cost
 Cons : Complex multiple DPD, Larger RX band noise or spectrum emission

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Next ET – Digital Envelope Tracking
VBAT
2G
LDO
VOUT1_APT PA

VBAT
CAPT1
SWAPT1 RxBN Filter
(TX1, APT)
 Key features
Interleaved VLX1 VOUT1_PRE VOUT1_DET PA
 2G/3G/4G/5G
Switched-Capacitor
Buck-Boost (TX1, APT/DET)
SW1
LBB1 LFIL1 CFIL1
VO6
Voltage Divider (SCVD)  2-TX
DET Loop Controller
MUX
Level Selector (2TX)
CO6  200MHz 5G NR ET
ISW1 VO5
DET
APT

 Architecture
SW
CF3 CF1
APT SWET1 (6:1) Controller DENV1<6:1>
DAC
APT VO6 CO5
VOUT1_DET Controller VO4
VLX1
VC
CO4
VBAT
 Hybrid topology
APT LDO
DAC
VOUT2_DET APT
Controller DAC
VO3
CF4  Interleaved BB  DC
amplifier
VLX2 CO3
SW
SWET2 (6:1)
Controller
DENV2<6:1> VO2
DET
APT

ISW2
MUX
RxBN Filter VO1
CO2  SCVD & Level Sel. SW 
SW2
AC amplifier
CF5 CF2
Interleaved VLX2 VOUT2_PRE VOUT2_DET
PA CO1
Buck-Boost (TX2, APT/DET)
LBB2
SWAPT2
LFIL2 CFIL2  RxBN filter
VBAT
CAPT2
VOUT2_APT PA
(TX2, APT)
Ref. [23], J.-S. Bang, ISSCC 2022

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Next ET – Digital Envelope Tracking

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Outline
 Envelope Tracking (ET) Motivation and History

 ET System Architecture and Building Blocks

 ET PA Link Budget Design

 Power Link Budget
 Noise Link Budget

 RF Transmission Requirements and SM-IC Technologies

 ET Evaluation

 Analog ET Limitations and Next

 Summary

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© 2023 IEEE International Solid-State Circuits Conference

Summary
 Envelope tracking (ET) has been the key power saving technology for mobile
handset applications.

 ET requires a multi-disciplinary area.

 ET system architecture and building blocks

 ET PA link budget design

 Power link budget and noise link budget

 SM-IC technologies to satisfy the RF transmission requirements in the

wireless standard.

 Digital ET is a good candidate to overcome the limitation of analog ET.

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Papers to See This Year
Suggested papers based on Advance Program

 Session 11
 Paper 11.1 is a Scalable Heterogeneous Integrated Two-Stage Vertical Power
Delivery Architecture for High Performance Computing.
 Paper 11.6 is a 42W Reconfigurable Bidirectional Power Delivery Voltage-
Regulating Cable.

 Session 25
 Paper 25.1 is a 4.1W Quadrature Doherty Digital Power Amplifier with 33.6% Peak
PAE in 28nm Bulk CMOS.
 Paper 25.2 is a 19.7-to-43.8GHz Power Amplifier with Broadband Linearization
Technique in 28nm Bulk CMOS

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Key References (1/5)
1. S. C. Cripps, RF Power Amplifier for Wireless Communication, 2nd ed.
Norwood, MA: Artech House, 2006.
2. L. R. Kahn, “Single sideband transmission by envelope elimination and
restoration,” Proc. Inst. Radio Eng., vol. 40, no. 7, pp. 803-806, July 1952.
3. A. A. M. Saleh and D. C. Cox, “Improving the power-added efficiency of FET
amplifiers operating with varying envelope signals,” IEEE Trans. Microwave
Theory Tech., vol. 31, no. 1, pp. 51-55, Jan. 1983.
4. F. Wang, et al., “A Monolithic High-Efficiency 2.4-GHz 20-dBm SiGe BiCMOS
Envelope-Tracking OFDM Power Amplifeir,” IEEE J. Solid-State Circuits, vol.
42, no. 6, pp. 1271-1281, 2007.
5. J.-S. Paek et al., “Fully Integrated 2x2 MIMO Real Simultaneous Dual Band
WiFi CMOS Power Amplifiers; Dig. Tech. Papers, pp. 1-2, June. 2022.

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Key References (2/5)
6. B. Kim, et al., “Push the Envelope: Design Concepts for Envelope-Tracking
Power Amplifiers,” IEEE Microwave Magazine, pp. 68-81, May 2013.
7. P. Asbeck, and Z. Popovic, “ET Comes of Age,” IEEE Microwave Magazine, pp.
16-25, March 2016.
8. J. Choi, et al., “A polar transmitter with CMOS programmable hysteretic-
controlled hybrid switching supply modulator for multistandard applications,”
IEEE Trans. Microwave Theory Tech., vol. 57, no. 7 pp. 1675-1686, July
2009.
9. D. Kim, et al., “Optimization for envelope shaped operation of envelope
tracking power amplifier,” IEEE Trans. Microwave Theory Tech., vol. 59, no.
7, pp. 1787-1795, July 2011.
10. P. Riehl, et al., “An AC-coupled hybrid envelope modulator for HSUPA
transmitters with 80% Modulator” in IEEE Int. Solid-State Circuits Conf.
(ISSCC) Dig. Tech. Papers, pp. 364-365, Feb. 2013.

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Key References (3/5)
11. P. Arno, M. Thomas, V. Molata, and T. Jerabek, “Envelope Modulator for
Multimode Transmitters with AC-Coupled Multilevel Regulators” in IEEE Int.
Solid-State Circuits Conf. (ISSCC) Dig. Tech. Papers, pp. 296-297, Feb. 2014.
12. S. Lee, et al., “A Hybrid Supply Modulator with 10dB ET Operation Dynamic
Range Achieving a PAE of 42.6% at 27.0dBm PA Output Power,” in IEEE Int.
Solid-State Circuits Conf. (ISSCC) Dig. Tech. Papers, pp. 42-43, Feb. 2015.
13. J.-S. Paek et al., “An RF-PA supply modulator achieving 83% efficiency and -
136 dBm/Hz noise for LTE-40MHz and GSM 35dBm applications,” in IEEE Int.
Solid-State Circuits Conf. (ISSCC) Dig. Tech. Papers, pp. 354-355, Feb. 2016.
14. C.-Y. Ho et al., “An 87.1% Efficiency RF-PA Envelope-Tracking Modulator for
80MHz LTE-Advanced Transmitter and 31dBm PA Output Power for HPUE in
0.153μm CMOS,” in IEEE Int. Solid-State Circuits Conf. (ISSCC) Dig. Tech.
Papers, pp. 432-433, Feb. 2018.
15. 3GPP TS 36.101, 3GPP TS 38.521-3, and 3GPP TS 38.101-1 and -2

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Key References (4/5)
16. J.-S. Paek et al., “An 88%-Efficiency Supply Modulator Achieving 1.08μs/V
Fast Transition and 100MHz Envelope-Tracking Bandwidth for 5G New Radio
RF Power Amplifier,” in IEEE Int. Solid-State Circuits Conf. (ISSCC) Dig. Tech.
Papers, pp. 238-239, Feb. 2019.
17. T. Nomiyama et al., “A 2TX Supply Modulator for Envelope-Tracking Power
Amplifier Supporting Intra- and Inter-Band Uplink Carrier Aggregation and
Power Class-2 High-Power User Equipment,” in IEEE Int. Solid-State Circuits
Conf. (ISSCC) Dig. Tech. Papers, pp. 434-435, Feb. 2018.
18. J.-S. Paek et al., “Efficient RF-PA Two-Chip Supply Modulator Architecture for
4G LTE and 5G NR Dual Connectivity RF Front-End,” Symposium on VLSI
Circuits; Dig. Tech. Papers, pp. 1-2, June. 2021.
19. J.-S. Paek et al., “A 5G New Radio SAW-less RF Transmitter with a 100MHz
Envelope Tracking HPUE n77 Power Amplifier Module,” Symposium on VLSI
Circuits; Dig. Tech. Papers, pp. 1-2, June. 2021.

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Key References (5/5)
20. J.-S. Paek et al., “A 90ns/V Fast-Transition Symbol-Power-Tracking Buck
Converter for 5G mm-Wave Phased-Array Transceiver,” in IEEE Int. Solid-
State Circuits Conf. (ISSCC) Dig. Tech. Papers, pp. 240-241, Feb. 2019.
21. J. Baek et al., “A Voltage-Tolerant Three-Level Buck-Boost DC-DC Converter
with Continuous Transfer Current and Flying Capacitor Soft Achieving 96.8%
Power Efficiency and 0.87μs/V DVS Rate,” in IEEE Int. Solid-State Circuits
Conf. (ISSCC) Dig. Tech. Papers, pp. 202-203, Feb. 2020.
22. D. Kim et al., “A Hybrid Switching Supply Modulator Achieving 130MHz
Envelope-Tracking Bandwidth and 10W Output Power for 2G/3G/LTE/NR RF
Power Amplifiers,” in IEEE Int. Solid-State Circuits Conf. (ISSCC) Dig. Tech.
Papers, pp. 476-477, Feb. 2021.
23. J-S. Bang et al., “2-Tx Digital Envelope-Tracking Supply Modulator Achieving
200MHz Channel Bandwidth and 93.6% Efficiency for 2G/3G/LTE/NR RF
Power Amplifiers,” IEEE Int. Solid-State Circuits Conference (ISSCC) Dig.
Tech. Papers, Feb. 2022.
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 Thank you for listening my tutorial.

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