Unit I: Computer Organization and Architecture

5-1 Instruction Codes

An Instruction code is a group of bits that instructs the computer to perform a specific
operation (sequence of micro operations).

Instruction is divided into two parts (basic part is the operation part)

The operation code of an instruction is a group of bits that defines certain operations such
as add, subtract, shift, and complement

The number of bits required for the operation code depends on the total number of
operations available in the computer

2n (or little less) distinct operations à n bit operation code

Stored Program Organization

The simplest way to organize a computer is to have one processor register (accumulator
AC) and an instruction code format with two parts (opcode and address)

The address tells the control where to find an operand in memory

This memory address is used to take data from that location and along with the data
stored in the processor register

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From the above picture

The instruction is stored in one location of the memory and operands are stored in
another location of the memory
For the capacity of 4096 words, the instruction format must have 16 bits
Out of this 16 bits 4 bits are given to store opcode(operation code) remaining 12 bits are
used to store address of an operand
The computer with single processor register is named as accumulator and labeld as AC
The operation is performed with the memory operand and the content of AC

Indirect Address

Instruction format has 16 bits

 3 bits for opcode

 12 bits for address

o 1 bit for mode: One bit of the instruction code can be used to distinguish between
direct & indirect addresses. When this bit contain 0 - it is direct mode, When this
bit contain 1 – it is indirect mode

There are three Addressing Modes used for address portion of the instruction code:

 Immediate address: the operand is given in the address portion (constant)

 Direct Address: the address points to the operand stored in the memory

 Indirect address: the address points to the pointer (another address) stored in the
memory that references the operand in memory

 Effective address: the address of the operand in a computation-type instruction

or the target address in a branch-type instruction

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5-2 Computer Registers
Computer instructions are normally stored in consecutive memory locations and
executed sequentially one at a time

The instruction are read from a specific address in memory and executed sequentially

This type of sequencing needs a counter to calculate the address of the next instruction
after execution of the current instruction is completed

It is also necessary to provide a register in the control unit for storing the instruction code
after it is read from memory

The computer needs processor registers for manipulating data and a register for holding a
memory address

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Computer Registers Common Bus System

S2S1S0: This input Selects the register/memory that would use the bus

LD (load): When enabled, the particular register receives the data from the bus during the
next clock pulse transition

E (extended AC bit): flip-flop holds the carry

DR, AC, IR, and TR: have 16 bits each

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 AR and PC: have 12 bits each since they hold a memory address

When the contents of AR or PC are applied to the 16-bit common bus, the four most
significant bits are set to zeros

When AR or PC receives information from the bus, only the 12 least significant bits are
transferred into the register

INPR and OUTR: communicate with the eight least significant bits in the bus

INPR: Receives a character from the input device (keyboard,…etc) which is then
transferred to AC

OUTR: Receives a character from AC and delivers it to an output device (say a Monitor)

Five registers have three control inputs: LD (load), INR (increment), and CLR (clear)

The input data and output data of the memory are connected to the common bus

The AR has its own address bus exclusively to send address

Therefore, AR must always be used to specify a memory address

Register à Memory: Write operation

Memory à Register: Read operation (note that AC cannot directly read from memory!!)

the content of any register can be applied onto the bus and an operation can be performed
in the adder and logic circuit during the same clock cycle

5.3 Computer Instructions

Basic Computer Instruction code format

Memory-Reference Instructions (OP-code = 0
15 14
12 11 0
IOpcodeAddress

Register-Reference Instructions (OP-code =

15 12 11 0
0 1 Register
1 1 operation

Input-Output Instructions (OP-code =1

15 12 11 0
1 1 1 I/O
1 operation

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Memory referenced Instruction:

A memory referenced instruction uses 12 bit to specify an address and one bit to specify
the addressing mode I.
The I is equal to 0 for direct address and to 1 for indirect address.

Register referenced Instruction:

The Register referenced instruction are organized by the operation code 111 with 0 in the
left most bit of the instruction.
A register referenced instruction specifies an operation on or a test of the AC Register.
An operand from memory is not needed; therefore other 12 bits are used to specify the
operation or test to be executed.

Input Output Instruction:

An input output instruction does not need a reference to memory and is organized by a
operation code 111 with a 1 in the leftmost bit of the instruction.
The remaining 12 bits are used to specify the type of input-output operation or test
performed.

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Computer Instruction Set completeness

A computer should have a set of instructions so that the user can construct machine
language programs to evaluate any function that is known to computable.

The set of instructions are said to be complete if the computer includes a sufficient
number of instructions in each of the following categories:

 Arithmetic, logical, and shift instructions

 Instructions for moving information to and from memory and processor registers

 Program control instructions together with instructions that check status

conditions

 Input & output instructions

5-4 Timing & Control

The timing for all registers in the basic computer is controlled by a master clock
generator.

The clock pulses are applied to all flip-flops and registers in the system, including the
flip-flops and registers in the control unit

The clock pulses do not change the state of a register unless the register is enabled by a
control signal (i.e., Load)

The control signals are generated in the control unit and provide control inputs for the
multiplexers in the common bus, control inputs in processor registers, and micro-
operations for the accumulator

There are two major types of control organization:

1. Hardwired control

2. Micro-programmed control

Hardwired control

In the hardwired organization, the control logic is implemented with gates, flip-flops,
decoders, and other digital circuits.

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 D3T4: SC←0

Generated by 4-bit sequence counter and 4x16 decoder

The SC can be incremented or cleared.

Example: T0, T1, T2, T3, T4, T0, T1, . . .

Assume: At time T4, SC is cleared to 0 if decoder output D3 is active.

T0 T1 T2 T3 T4 T0
Clock

T0

T1

T2

T3

T4

D3

CLR
SC

• A memory read or write cycle will be initiated with the rising edge of a timing signal

• Assume: memory cycle time < clock cycle time!

• So, a memory read or write cycle initiated by a timing signal will be completed by the
time the next clock goes through its positive edge
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 • The clock transition will then be used to load the memory word into a register

• The memory cycle time is usually longer than the processor clock cycle à wait cycles

• T0: AR←PC

• Transfers the content of PC into AR if timing signal T0 is active

• T0 is active during an entire clock cycle interval

• During this time, the content of PC is placed onto the bus (with S 2S1S0=010) and
the LD (load) input of AR is enabled

• The actual transfer does not occur until the end of the clock cycle when the clock
goes through a positive transition

Micro-Programmed control

In the micro-programmed organization, the control information is stored in a control

memory (if the design is modified, the micro-program in control memory has to be
updated)

5-5 Instruction Cycle

A program is a sequence of instructions stored in memory

The program is executed in the computer by going through a cycle for each instruction.

Each instruction in turn is subdivided into a sequence of sub-cycles or phases

Instruction Cycle Phases:

 1- Fetch an instruction from memory

 2- Decode the instruction

 3- Read the effective address from memory if the instruction has an indirect
address

 4- Execute the instruction

This cycle repeats indefinitely unless a HALT instruction is encountered

Initially, the Program Counter (PC) is loaded with the address of the first instruction in
the program

The sequence counter SC is cleared to 0, providing a decoded timing signal T0

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 After each clock pulse, SC is incremented by one, so that the timing signals go through a
sequence T0, T1, T2, and so on

T0: AR←PC (this is essential!!)

The address of the instruction is moved to AR.

T1: IR←M[AR], PC←PC+1

The instruction is fetched from the memory to IR ,and the PC is incremented.

T2: D0,…, D7←Decode IR(12-14), AR←IR(0-11), I←IR(15)

Memory referenced Instruction:

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The IN Instruction

The OUT Instruction

The SKI and SKO Instruction

The SKI and SKO Instruction check the status of the flag and cause a skip of next
instruction if the flag is 1.

The ION and IOF Instruction

The ION and IOF Instruction set and clear an Interrupt Enabled Flip-flop IEF.

Interrupt

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