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DESIGN AND APPLICATION OF RISC

PROCESSOR
Mohammad Zaid, Prof. Pervez Mustajab

Department of Electronics Engineering

Zakir Hussain College of Engineering & Technology
Aligarh Muslim University,
Aligarh. U.P. India

Abstract— This paper presents the design of multi-cycle 32-bit times and the length of the instruction vary widely. The
Reduced Instruction Set Computer (RISC) processor for better approach of CISC is quite complex and therefore it is being
performance and higher speed of operation. The processor is replaced by the Reduced Instruction Set Computer (RISC).
capable of executing more number of instructions with simple [4]
design and less critical path delay. The designed processor was
simulated and synthesized using Xilinx 14.7 ISE design suite.
RISC doesn’t mean that the number of instructions are
The processor executes each and every instruction in more less it only implies that all the instructions have the same
than one cycle that’s why the term multi-cycle. Each instruction simple and fixed instruction format. Variations in instruction
is divided into three main states namely the Fetch state, the length is the main factor behind inefficient processors. Along
Decode state and the Execution state. The first two sates remain with fixed-length instruction size, RISC designs also use a
the same for all the instruction the last state, however depends simple instruction format. The boundaries of various fields in
on the type of operation performed in that instruction an instruction such as opcode and source operands are fixed.
This allows for efficient decoding and scheduling of
Index Terms— Reduced Instruction Set Computer (RISC), instructions[3].
Microprocessor without Interlocked Pipeline Stages (MIPS),
Apart from this the RISC has other added advantages like
Complex Instruction Set Computer (CISC), Hardware
description languages (HDL), Verilog. simple addressing modes, register-to-register operations
(except for load and store instructions), fixed length of
registers, simple operations and a large register set.
I. INTRODUCTION The MIPS is a RISC based microprocessor architecture
that was developed by MIPS Computer Systems Inc.
There are different view points from which one can view
Architecture of MIPS RISC microprocessor includes, fixed-
a computer system depending on how they interact with the
computer system. The concept of abstraction is important to length instructions, simple decoded instruction format,
explore the details that are necessary from a particular memory accesses limited to load and store instructions,
viewpoint. Computer systems can be viewed from different hardwired control unit, a large general purpose register file,
perspective depending on the user. and operations executing within the registers of the
Programmers uses the instruction set architecture (ISA) is microprocessor[1].
as a useful abstraction to understand the processor’s internal From the literature available on the RISC based
details. ISA defines the processor at a logic level, it defines processors, the problem was to make a processor capable of
the personality of a processor. ISA includes the type of performing fast and executing even more number of
instructions and the meaning of those instructions. If the instructions with the simplest of architectures and the
meaning conveyed to those instructions are correct then it simplest of instruction sets. The RISC topology that would
becomes easy for the chip manufacturer to complete the solve this problem was a special type of RISC architecture
physical design implementation of the processor. There are i.e. the MIPS architecture. So, in this paper single-cycle
two categories of processors defined at the ISA level: RISC MIPS architecture was chosen and the design was modified
and CISC[3]. to provide better performance without compromising the
The approach of CISC machines is to do more with each number of instructions[11].
and every instruction which leads to its complexity. As a The performance of any processor depends on the time it
result, there are a large number of addressing modes takes to execute an instruction (here execution means from
associated with CISC machines. As a result the execution fetching the opcode, then decoding of the opcode, then

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fetching the data, then performing the necessary operation store instructions then read or write data from another part of
and finally storing the result in the registers). Now, the memory. Thus, the overall memory is partitioned into two
execution time of a processor is given by the following smaller memories, one containing instructions and the other
expression: containing data. Figure 1 shows a block diagram with the four
state elements: the program counter, register file, and
Execution time = (# instructions) (Cycles per instruction and data memories.[2]

instructions) (Critical path delay) (1)

The product of the number of instructions, the Cycle per

instruction and the critical path delay commutatively decide
the performance of the processor. Now, if any one of the
parameter on the right hand side of the above expression goes
up the other has to go done so that the execution time does
not exceeds to such values that the processor becomes
redundant. Out of all these three variables the critical path
delay is the most important of all the parameters as it decides
the frequency of operation of the processor[2].
So, the idea was to execute more number of instructions at
less critical path delay but at the expense of increased cycle Figure 1. State elements of MIPS processor
per instruction (CPI). MIPS single-cycle RISC processor was
chosen and the design was modified to give rise to the multi- The Dashed lines indicate 32-bit data busses and 5-bit
cycle MIPS. address busses on the register file.
The program counter is a very simple 32-bit register. The
II. MICROPROCESSOR WITHOUT output of program counter, PC, points to the current
INTERLOCKED PIPELINE instruction whereas the input, PC’, indicates the address of
STAGE (MIPS) the next instruction[2].
MIPS is a RISC based processor which consists of 32
III. SINGLE-CYCLE MIPS AND ITS
register each of 32-bits and the instructions are also 32-bit
DRAWBACK
long .The first 6-bits represent the opcode value. The opcode
value decides which type of instruction is to be executed.[5] The Single-cycle MIPS consists of all the basic elements
There are three type of instructions formats that are supported which are shown in figure 1. This processor executes each
by the MIPS depending on the value of the opcode namely: instruction in one clock cycle. Figure 2 shows the processor
datapath.
• R-type Instructions
• J-type Instructions
• Immediate type Instructions

Another important field is the Funct field of the

instruction which is depicted by the last 6-bits of the
instruction. The Funct field decides which type of operation
is to be executed in the ALU[1].
All the instructions take more than one clock cycle to
execute. The advantage of using reduced number of
instructions is the simplification in decoding. However, three
instruction formats and a single addressing mode mean that
complicated operations and addressing modes will have to be
synthesized by the compiler. If these operations and
addressing modes are less frequently used, then there is not
much penalty to be paid.[1] Figure 2. Complete single-cycle MIPS processor
How does one design a complex system? One method of
doing this is starting with state elements involved in the The blue lines represent the various control signals
hardware. The state elements are generally the memories and involved in the execution of instructions .The value of these
the architectural state (the program counter and registers). control signals depend on the type of instruction to be
The next step is to have combinational blocks to connect executed. The Single-cycle MIPS execute instruction but with
these elements to have a relation between the current and next certain drawbacks which are as follows:
state.. The instruction is read from part of memory; load and


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• There are many adders present in the datapath which

are costly and slow in executing operations. Thus, the The Multi-cycle MIPS executes each instruction by
presence of these adders degrades the performance of dividing into various steps. These steps are shown in the form
the MIPS by increasing the critical path delay of the of a flowchart in figure 4.
processor and in turn increasing the execution time of
the instructions.

• The slowest instruction in the MIPS is the load word

instruction. Thus, the clock cycle of the MIPS should
be chosen so as to fit the load word instruction in the
clock cycle otherwise it will result in the improper
functioning of the processor.

• The third disadvantage is that the single-cycle MIPS

have separate data and instruction memories which is
not a realistic approach for processor design. A much Figure 4. Flowchart showing the multi-cycle MIPS operations
more realistic approach is to use separate data and
instruction memories one holding the data and the The first two steps i.e. the fetching of instruction and the
holding all the instructions. decoding of instructions remains the same for all type of
Due to these drawbacks the design of the single-cycle instructions. After the decoding step the execution takes place
MIPS need to be modified so that more number of according to the opcode value. The processor has been
instructions but with reduced delay. This modification leads designed for a total of 18 instructions.
to the Multi-cycle MIPS in which the cycle per instruction is
more than 1 but the critical path delay is considerably V. Critical Path Delay
reduced[5][8].
The critical path delay is very important in determining
IV. MULTI-CYCLE MIPS
the frequency of operation of any Microprocessor. The
The multi-cycle MIPS datapath is very similar to the critical path is the longest path or the slowest path in terms of
single-cycle MIPS datapath with a few additions which are time. The execution time of an instruction depends on the
shown by green colour in the figure 3. These additions are critical path delay. So, it is wise to choose the critical path
registers which will be used in order to store data during each delay as small as possible .Figure 5 shows the critical path of
cycle so that the data can be used for further operations in the the Multi-cycle MIPS. The critical path of the MIPS depends
next cycle. on the longest instruction in terms of time i.e. the load word
The addition of registers is a very important modification instruction of the multi-cycle MIPS. Now, in case of multi-
as it allows the MIPS to execute an instruction by dividing it cycle MIPS one ALU operation can take place in one cycle.
in various cycle as discussed earlier. The registers are used in So, figure 5 shows one cycle of the instruction.
order to store data so that it can be used for further
processing. Another important modification as can be seen in
the figure 3, as compared to the single-cycle MIPS is the
elimination of adders which are slow and occupy a considerable
amount of space. So, the elimination of adders reduce the critical
path delay and also reduce the area thus leading to better
processor design[2][11].

Figure 5. Critical path for multi-cycle MIPS

Figure 3. Complete Multi-cycle MIPS datapath


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Tcritical = Tpc + Tmux + max (Tmux+Talu,Tmem)+Tmux. Figure 6 shows the RTL schematic of the multi-cycle
MIPS.As can be seen from the figure 5 that the processor is
Tcritical = Tpc + 2Tmux + max (Tmux+Talu,Tmem).
divided into two parts the datapath and the controller.
Critical path delay reduced by Tmux+Tmem
Where,
Tpc = time for pc to load address
Tmux = delay of the multiplexer
Tmem = time to access memory
Talu = time taken for an ALU operation
This is a theoretical calculation of the critical path delay
of the multi-cycle MIPS which is reduced by (Tmux+Tmem)
compared to the single-cycle MIPS. Now, this is a
considerable amount looking into the fact that these delay Figure 8. FSM of multi-cycle MIPS controller
values are generally given in units of nanoseconds. So, for
Table 1 shows the states, which are a part of the FSM of
almost the same topology we have reduced the critical path the controller which is shown in figure 8. The most important
delay[2]. part is the controller or the control unit. The FSM controller
discussed in the previous section tells us about the working of
VI. RESULTS the various MIPS operations along with the changes in the
The RTL schematic or the register transfer schematic is control signals at every state. The definition of the control
generated post HDL synthesis phase of the synthesis process. signals ate every state ensures the correct flow of data in the
It represents the pre-optimized design in terms of generic data path.
symbols, such as multipliers, adders, counters, AND gates
etc, that are independent of the targeted Xilinx device. TABLE 1. STATE TABLE FOR FIGURE 7.

State Operations Next State

S0 Fetch instruction S1
S1 Decode S2
S1 Decode S5
S1 Decode S7
S1 Decode S9
Calculation of
S1 S11
branching address
Calculate address for
S2 S3
loading word
Load word from data
S3 S4
memory
Figure 6. RTL schematic of multi-cycle MIPS Store word into
S4 S0
register file
Calculate address for
S5 S6
storing data
Store data into data
S6 S0
memory
Execution of register
S7 S8
type instruction(add)
Write the result into
S8 S0
register file
Execution of
S9 immediate S10
instructions (SUI)
Write the result into
S10 S0
register file
Branch to calculated
S11 S0
address

Figure 7. Complete multi-cycle MIPS datapath


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Figure 9 shows the simulation result of the controller of

the processor for the add instruction. All the states are marked
in the figure and when compared with table 1and figure 8 it
can be inferred that Multi-cycle MIPS add register type
instruction is executed and the control signals are as given in
the figure 8.

Figure 11. Simulation of controller for beq instruction

VII. CONCLUSION
Figure 9. Simulation of controller for add instruction In the paper we have been able to design and simulate a
32-bit RISC processor for a particular instruction set by
The next simulation result is the control path for the load
modifying the datapath of the single-cycle MIPS by using
word instruction of the multi-cycle MIPS. Figure 10 shows
Xilinx 14.7 ISE design suite. . The processor executes more
the control signals and all the state as mentioned table 1 and
number of instructions with less critical path delay. The
figure 8 and the control path is according to the FSM
developed in figure 8. reduction in critical path delay also led to the reduction in the
execution time thus leading to a better processor.

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[4] Sivarama P. Dandamudi, “Porcessor Design Issues” in Guide to
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