Experiment No.
Aim: To interface LPC2148 using UART (Universal Asynchronous Receiver Transmitter).
Requirements: 1) LPC2148 Educational Board
2) Computer with TeraTerminal installed on it..
3) FlashMagic Software for Program Burning
4) Connecting wires
Theory:
Communication is an important tool in our day to day life. It is basically done in two
ways namely: Serial Communication & Parallel Communication.
Serial Communication is transmitting single bit at a time. It can be achieved Synchronously or
Asynchronously. Hence, there is corresponding module for each mode. i.e. USART or UART.
UART:
It stands for Universal Asynchronous Receiver Transmitter.
In case of LPC2148 (ARM7 microcontroller), there are two UART’s present on chip UART0 &
UART1.In addition to standard Transmit & Receive Data lines, UART1 also supports “Full
Modem Control Handshake Interface.”
Features of UART in LPC2148:
1) 16 B Receive & Transmit FIFO’s.
2) Built-in Fractional Baud Rate Generator with Auto Bauding capabilities.
3) Software Flow Control in both UART’s in Transmission FIFO control.
4) Complete Modem support in UART1 (hardware & software)
UART0:
It has only two pins: Serial Transmit Data (TxD0) as output pin & Serial Receive Data
(TxD0) as input pin. The pins are on Port0.0 & P0.1 respectively included as second
functionality on pins along with GPIO functionality as 1st .
TxD0 => P0.0 2nd Functionality
RxD0 => P0.1 2nd Functionality
The registers included in UART0 are as follows:
U0RBR (Receiver Buffer Register): 8-bit Read data
U0THR (Transmit Holding Register): 8-bit Write data
U0DLL (Divisor Latch LSB): 8-bit data
U0DLM (Divisor Latch MSB): 8-bit data
U0FCR (FIFO Control Register): 8-bit
U0LCR (Line Control Register): 8-bit
U0LSR (Line Status Register): 8-bit
U0SCR (Scratch Pad Register): 8-bit
U0ACR (Auto Baud Rate Control Register): 32-bit
U0FDR (Fractional Divider Register): 32-bit
UOIER (Interrupt Enable Register): 32-bit
U0IIR (Interrupt ID Register): 32-bit
U0TER (Transmitter Enable Register): 8-bit
1) U0RBR & U0THR are registers used for holding data on which operations are to be
performed.
2) U0DLL & U0DLM are used to determine the Baud Rate of the Transmission.
3) U0FDR bits 7:0 are used for fractional generator enabling. (AddDivVal & MulVal)
4) UOLSR is used to check the status of UORBR & UOTHR registers. i.e. if they contain
valid data or not.
5) UOFCR bit 0 = 1 => Enable UART0
= 0 => Disable UART0
6) UOLCR is used to give access to U0DLL & U0DLM registers for Baud Rate setting by
configuring bit 7. U0LCR is also used to set the word length with help of bits 1:0.
7) U0TER bit 7 = 1 => Data in U0THR is sent to TxD pin
= 0 => Data is not transmitted.
Baud Rate Calculation: The Baud Rate can be calculated using the following formula:
PCLK
UART0baud rate = 16∗( 256∗UODLM +UODLL )∗ 1+ ( DivAddVal
MulVal )
Where PCLK = Peripheral Clock;
UODLL & UODLM = Standard Baud Rate Registers;
DivAddVal & MulVal = Fractional Baud Rate Generator Parameters;
DivAddVal = FDR bits 3:0 => If ‘0’, Fractional Generator is disabled
MulVal = FDR bits 7:4 => Greater or equal to 1 for proper operation of UART0
Configuration of Various Registers (in our case) :
1) U0FDR = 0x00000000; // Not using Fractional Generator
2) U0LCR = 0b10000011; // Word Length = 8, DLAB = 1
3) U0FCR = 0b00000111; // Enable UART0, Reset Rx & Tx FIFO
4) PINSEL0 = 0x00000005; // P0.0 & P0.1 2nd Functionality
NB.: Check the U0LSR register for status of U0THR & U0RBR. If it is empty, then transfer the
data. Else, wait till it becomes empty.
UART1:
It is same as UART0 but has additional Pins for MODEM Interfacing. The additional
pins include CTS, DCD, DSR, DTR, RI, RTS.
Interfacing Diagram:
INTERFACING UART0 OF LPC 2148 & TERATERMINAL OF PC
WITH HELP OF SERIAL COMMUNICATION
TxD0
MA
11 X2 14
P0.0
UAR 32 HyperTerminal
Or
T0 P0.1 TeraTerminal
12 13
LPC2148 RxD0
LPC2148
LLPP C
C22 11 4488
Conclusion:
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Additional Calculations: (For those who want to refer)
Baudrate Calculation:
Equation 1:
Taking Baudrate of 115200;
if(BaudRate >=115200 && BaudRate < 460800 )
{
U0FDR |= (1<<0); // DIVADDVAL
U0FDR |= (12<<4); // MULVAL
}
FDR (Fractional Divisor Register) is used to eliminate fractional clock error
Rearranging Eq.1
PCLK = FOSC = 12 MHz
(256 x U0DLM + U0DLL)x(1+ (DivAddVal/MulVal)) = PCLK/ (16 x UART0_baudrate)
=12MHz/(16 x 115200)
=6.5104
Lets consider if no fractional divisor error (1+ (DivAddVal/MulVal)) = 1
(256 x U0DLM + U0DLL) = 6.5104 // U0DLMx256 shifts byte to MSB byte 0xFF00
U0DLL = 6
U0DLM = 0
Now let’s calculate FDR (Rearranging Equation 1):
(1+ (DivAddVal/MulVal)) = PCLK/ (16 x((256 x U0DLM) + U0DLL) x UART0_baudrate)
= 12MHz/(16 x 6 x 115200)
(1+ (DivAddVal/MulVal))= 1.0850
DivAddVal/MulVal = 0.0850
For no error we need FDR = 1 so, MulVal = 1/0.0850 = 11.764 = 12 (avg)
So MulVal = 12 and therefore DivAddVal = 1
if(BaudRate >=115200 && BaudRate < 460800 )
{
U0FDR |= (1<<0); // DIVADDVAL = 1
U0FDR |= (12<<4); // MULVAL = 12
}
Note: The Table 167 on Pg. 152 of LPC2148 user manual is for PCLK = 20MHz (But in our
case we have 12 MHz so values of MulVal and DivAddVal is different and have to
manually calculate)
