Chapter 9

Precision Voltage Sensing in Deep

Sub-micron and Its Challenges

Ivan O’Connell, Subhash Chevella, Gerardo Molina Salgado,

and Daniel O’Hare

Abstract Realising high precision Analog to Digital Converters (ADCs) in 28 nm

and below is a significant challenge. Traditional Sigma Delta architectures are
not compatible with reduced voltage rails and transistor gain. While Successive
Approximation Register (SAR) ADCs have scaled well with technology nodes,
they have struggled to consistently and reliably achieve 12+ bit performance. A
new emerging architecture, the Noise-Shaped SAR ADC, leverages the advantages
of both architectures. However, it is the author’s view that there are still many
challenges that need to be addressed which are discussed here to realise a high
precision converter in these deep sub-micron nodes.

With the advent of the Internet of Things (IoT), sensors have become ubiquitous
in all aspects of our lives, whether it’s at home, work, car or socially. The mobile
phone and smart watch are now a key aspect of all our lives and contain a vast array
of sensors. The iPhone 12 has a comprehensive list of sensors including Face ID,
LiDAR scanner, Barometer, Three-axis gyroscope, Proximity Sensor and Ambient
Light Sensors. Similarly, the Apple watch counts an ECG (electrocardiogram),
Gyroscope, Accelerometer and Optical Heart Sensor among its many sensors.
In 2019, the global sensor market size was valued at $166.69 billion and is
projected to reach $345.77 billion by 2028 [1]. This demonstrates the proliferation
of sensors across all aspects of our lives, while also highlighting the need for
low cost ways to integrate and interface to those sensors. This chapter is focused
on addressing the challenges associated with interfacing to such sensors in deep
sub-micron CMOS technology nodes. 28 nm CMOS and below for high volume
consumer applications, including mobile phones. However, while these technologies
bring many advantages, particularly around the scale and cost, there are many
challenges including reduced transistor gain which have to be addressed when trying

I. O’Connell () · S. Chevella · G. M. Salgado · D. O’Hare

Microelectronics Circuits Centre Ireland, Tyndall National Institute, Cork, Ireland
e-mail: [email protected]

© The Author(s), under exclusive license to Springer Nature Switzerland AG 2022 137
P. Harpe et al. (eds.), Analog Circuits for Machine Learning,
Current/Voltage/Temperature Sensors, and High-speed Communication,
https://doi.org/10.1007/978-3-030-91741-8_9
138 I. ÒConnell et al.

to realise 12+ Bit Analog to Digital Converters (ADCs). This chapter will address
many of these challenges.
This chapter is organised as follows. First, we will provide a brief overview
of ADCs. Then is a recap on the current state of the art, with a focus on ADC
architectures. Finally, a design example is discussed in detail.

1 ADC Overview

All sensors produce a change in either voltage, resistance, capacitance, current or

magnetic field in the presence of a physical change. The output of these is analogue
in nature in that the output signal is continuously varying both in time and magnitude
as illustrated here in Fig. 9.1. The continuously varying nature of signal means that
the output signal of the sensor can have any value at any point in time.
However, all modern electronic systems are digital in nature and therefore they
are not suited for processing the analogue signals shown below. Instead, an Analog
to Digital Converter (ADC) is required convert the continuously varying input signal
into a signal which is restricted to a limit finite set of magnitudes at fixed points
in time. To achieve this, the input signal needs to be sampled and quantised by
the ADC. Note that the ADC has three input signals: (a) the input, (b) the clock
and (c) a reference. Note that all ADCs operate on the principle of comparing an
unknown input signal against a known and stable reference signal, which is typically
a voltage produced by a Bandgap Reference [2]. Hence, any variation or uncertainty
in relation to the reference signal ultimately limits the accuracy that the system can
achieve. Similarly, the clock is used to provide the fixed points in time at when
to measure the input signal. The value in knowing the magnitude of the applied

Fig. 9.1 Continuously varying signals both in magnitude and time on the left are sampled and
quantised by the ADC to produce the discrete time digital representation on the right
9 Precision Voltage Sensing in Deep Sub-micron and Its Challenges 139

Fig. 9.2 The act of sampling a continuously varying signal on the left reduces the signal to having
a value at specific points in time

input signal (from the sensor) is significantly diminished, unless we know when
that magnitude occurred. This is especially the case in safety monitoring systems
irrespective of whether they are in the car, home or office.

1.1 Sampling

Typically, the ADC first samples the input signal at discrete points in time, separated
by a period, Ts. The process of sampling limits or restricts the ADC to only consider
the applied input from the sensor at these specific points in time as illustrated in
Fig. 9.2. The act of sampling means that a significant amount of information can
potentially be lost. However, provided that the Nyquist theorem is observed, there
is no loss in information [3]. The Nyquist theorem states that:
The input signal can be regenerated with no loss of information provided
that it is sampled at a frequency greater or equal to twice the bandwidth of the
signal.

1.2 Quantisation

Quantising the input signal, as illustrated in Fig. 9.3, is the process of restricting
the magnitude of the signal to a finite set of values, which is typically given by 2N ,
where N is the number of bits within the ADC. The act of quantising the input signal
introduces a quantisation error, which can be modelled as having a flat spectrum
from 0 to fs /2, where fs is the sampling frequency [3]. fs /2 is the Nyquist frequency,
which is the largest frequency that can be sampled without loss of information. The
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Fig. 9.3 Quantising the sampled signal in Fig. 9.2 restricts its magnitude to a limit set of values;
this rounding error is called a quantisation error and reduces as the set of available magnitudes
increases

quantisation noise power is VLSB 2 /12 where VLSB is the voltage difference between
two adjacent magnitude levels and is often referred to as the LSB (Least Significant
Bit). The resultant Signal to Quantisation Noise Ratio (SQNR) is given by [4]:

SNQR = 6.02N + 1.76 (dB) .

Hence, each additional bit (or doubling of the available set of magnitudes)
increases the resolution by 6 dB.

1.3 Other Noise Sources

While sampling and quantisation are the primary functions of an ADC and can
be modelled by an appropriate noise source, the realisation of an ADC in CMOS
introduces a significant number of other errors [4] that will be briefly addressed in
this section.

1.3.1 Aperture Error

As mentioned earlier, an important aspect of sampling the input signal is having

certainty as to when the input signal is sampled [4]. However, in a real world
implementation, the clock will have an associated uncertainty or jitter resulting in a
deviation in the value sampled compared to target. The results in an aperture error,
as illustrated in Fig. 9.4, can become significant at higher frequencies.
9 Precision Voltage Sensing in Deep Sub-micron and Its Challenges 141

Fig. 9.4 Uncertainty in the sampling instance is called Aperture error. Deviating from the desired
sampling instance results in the wrong value being sampled by the system

Fig. 9.5 Sampling the input voltage onto a capacitor introduces thermal (KT/C) noise which can
only be reduced by increasing the sampling capacitor size

1.3.2 Thermal Noise

In addition to sampling process introducing an aperture error, the input signal is

typically sampled onto a capacitor using a switch (transistor) which has a finite on-
resistance (Fig. 9.5). This resistance adds thermal noise which has a power spectral
density given by:

V2n = 4KTR.

where K is Boltzmanns constant (1.38 × 10–23 m2 kg s−2 K−1 ), T is the absolute

temperature in Kelvin and R is the resistance. However, irrespective of the total
resistance, the thermal noise power is given by [5]:
2
VnTH = KT/C
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Fig. 9.6 ADC Signal to Noise Ratio highlighting the Signal Power and noise sources including
Sampling Jitter/ Aperture Error, Thermal (KT/C) noise and quantisation noise given by VLSB 2 /12

where C is the sampling capacitor. Therefore, to reduce the resultant thermal noise
voltage by a factor of 2x, a 4x increase in the sampling capacitor is required, which
can quickly become limiting at higher resolutions.

1.4 ADC Signal to Noise

The resultant Signal to Noise Ratio (SNR) of the ADC is given by:

SNR = Signal Power/Noise Power

where the Noise Power is the sum of all the noise sources in the bandwidth of
interest, as illustrated in Fig. 9.6. These error sources include Clock Jitter, KT/C
Noise and Quantisation to name a few.

1.5 Figure of Merits

ADC can come in all shapes and sizes, which makes it difficult to do a fair
comparison between the different designs. To address this, two Figures of Merit
(FoMs) have been developed, namely, the Walden [6] and Schreier FoMs [7].

1.5.1 Walden FoM

The Walden FoM is given by:

FoMW = Power/2ENOB 2BW.

9 Precision Voltage Sensing in Deep Sub-micron and Its Challenges 143

Fig. 9.7 Walden Figure of Merit versus Nyquist Frequency [7]

where Power is the power consumed by the ADC, ENOB is the Effective Number of
Bits and BW is the Bandwidth of the ADC. FoMW is typically expressed as fJ/conv-
step. Illustrated below is the latest ADC survey from Prof. Boris Murmann [7]. Note
that when considering the Walden Figure of Merit, it is important to be aware that
it is more suited to compare data converters that are quantisation noise-limited, i.e.
ADCs where quantisation noise is the dominant noise source. In these cases, the
quantisation noise can be reduced by a linearly increase in the power consumed, i.e.
an additional bit of resolution only requires a 2x increase in the power consumed.
It is clear from Fig. 9.7 above that there can be significant variation in the FoM
across the published ADCs. Hence, it can be extremely difficult to extract any
meaningful information.

1.5.2 Schreier FoM

While the Walden FoM is more suited for comparing low and medium resolution
ADCs (less than 12–14 bits), a more appropriate FoM is required to fairly compare
high resolution data converters which are typically thermally noise-limited. Thus,
any increase in the resolution typically requires a 4x increase in the associated power
consumption. The Schreier FoM is given by:

FoMS = 10 log (SNR × BW/Power)

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Fig. 9.8 Schreier FoM versus Nyquist Frequency [7]

Illustrated in Fig. 9.8 is the Schreier FoM versus Nyquist Frequency for the
various ISSCC and VLSI publications over the last 25 years [7]. It is clearly evident
that the achievable Figure of Merit starts to roll off at higher frequencies.

1.6 Architecture Comparison

In addition to the Figure of Merits providing us with a mechanism to compare a

variety of ADC designs, it also compares and contrasts the different architectures.
This enables us to gather a number of useful insights.
Figure 9.9 shows the Signal to Noise and Distortion Ratio (SNDR) for the ADCs
published over at the IEEE ISSCC and VLSI conferences. The ADCs are grouped
by architecture with Flash ADCs being the architecture of choice for high speed and
low resolution (6–8 bits). Sigma Delta is the dominant architecture at the opposite
end of the spectrum for high resolution low speed applications. However, SAR-
based architectures have the upper hand in the mid-range frequencies. Note that this
plot excludes hybrid architectures including Time Interleaving so that the underling
core ADC architecture performance is highlighted. It is also important to note that
to achieve an SNDR of greater than 80 dB, it typically requires Noise Shaping in
the form of a Sigma Delta-based architecture.
Figure 9.10 below illustrates the SNDR for the same ADCs as in Fig. 9.9 below,
but now grouped by CMOS technology node. When looking at the data in this form,
it quickly becomes apparent that to achieve an SNDR of 80 dB or greater tends to
restrict the ADC Bandwidth to 10 MHz or less and is typically only achieved in very
mature CMOS technology nodes such as 180 nm.
9 Precision Voltage Sensing in Deep Sub-micron and Its Challenges 145

Fig. 9.9 SNDR versus Nyquist Frequency for different ADC architectures

Fig. 9.10 SNDR versus Nyquist Frequency for published ADCs grouped by CMOS technology
node

Illustrated in Fig. 9.11 is the SNDR versus the Schreier Figure of Merit, where it
is clearly evident that there is a strong correlation between SNDR and the Schreier
Figure of Merit.
Figure 9.12 below shows the SNDR versus Nyquist Frequency for Sigma Delta-
based ADCs from which we can make a number of interesting observations. First,
Continuous Time (CT)-based implementations dominate the higher Bandwidth
applications, while the Switched Capacitor (SC) discrete time-based implementa-
tions dominate the lower bandwidth and higher resolution designs.
146 I. ÒConnell et al.

Fig. 9.11 SNDR versus Schreier FoM

Fig. 9.12 SNDR versus Nyquist Frequency for Sigma Delta-based Architectures, divided into
continuous time (CT)-based architectures and discrete time/switched capacitor (SC)-based archi-
tectures

It is clear from Fig. 9.13 that the SNDR of published SARs is centred around an
SNDR of 60 dB, or 10 bits across most of the frequency range. Another significant
observation from this plot is the lack of any correlation with CMOS technology
node. This demonstrates and highlights the popularity of the SAR architecture in
recent years and also the fact that the architecture scales well CMOS technology
node.

1.7 Architecture Selection

So when we examine the observations from these graphs, we quickly form a

number of conclusions in relation to the SAR and noise-shaped Delta Sigma ADC
architectures. In the case of the SAR-based ADC, the observations are:
9 Precision Voltage Sensing in Deep Sub-micron and Its Challenges 147

Fig. 9.13 SNDR versus Nyquist Frequency for SAR ADCs grouped by CMOS technology node

• The resolution is typically limited to around 14 bits. While there a few exceptions
to this [8–11], SAR ADCs typically achieve resolutions of 10–12 bits without
requiring calibration.
• The SAR architecture is almost process technology agnostic, in that it is prevalent
across all CMOS process technologies. In fact, it is becoming more dominant at
lower geometries, reinforcing the fact that the architecture readily scales with
technology.
• At higher resolutions beyond 12 bits, the SAR architecture starts to become
limited by Thermal Noise (KT/C), where each additional bit of resolution
requires a 4x larger DAC capacitance with a corresponding increase in power
and area.
On the other hand, the Sigma Delta architecture has its own limitations or
constraints:
• It’s more suited to higher resolution applications, where it is typically associated
with achieving 14+ bit resolution.
• Noise shaping requires a significant amount of open loop gain to sufficiently
suppress the quantisation within the band of interest. Therefore, it is more suited
to larger CMOS geometries, where the native transistors typically have larger
inherent gain.
• Noise shaping architectures are oversampled, as the process of shaping the
quantisation noise out of the band of interest to some other frequencies requires
an oversampled system. Hence, the thermal noise, which is typically set by the
first stage, benefits from the inherent oversampling within the system, reducing
the in-band thermal noise.
• The noise-shaping architecture leverages the inherent property that many of the
error sources are shaped by the loop, which makes them very tolerant of any
circuit imperfections [3].
148 I. ÒConnell et al.

2 SAR ADC Architecture

Illustrated in Fig. 9.14 below is a single-ended SAR ADC (for simplicity of

illustration) consisting of the Capacitive Digital to Analog Converter (CDAC),
SAR logic and Comparator [12]; the associated linear model of the SAR ADC is
illustrated below in Fig. 9.15, where the Quantisation noise, Qe, and the comparator
noise, ncomp, are added to the applied input signal, Vin, to realise the digital output
code, Dout. However, an important aspect of the SAR architecture is that at the end
of the bit trials, a residue voltage remains on the top-plate of the DAC capacitor,
VDAC, which corresponds to Qe + ncomp.
When the SAR architecture is analysed in terms of its constitutient power
elements as illustrated in Fig. 9.16, there are a few key takeaways from this:

Fig. 9.14 Single-end SAR ADC with CDAC, SAR logic and clocked comparator

Fig. 9.15 Linear model of a

SAR ADC, highlighting the
Quantisation noise, Qe, and
comparator noise, ncomp, with
input signal Vin and Digital
output Dout . The error sources
are added by the comparator
in the top half of the model.
However, the negative
feedback associated with the
SAR operation results in Qe
and ncomp, resulting in the
residue voltage
9 Precision Voltage Sensing in Deep Sub-micron and Its Challenges 149

Fig. 9.16 Predicted power consumption bounds for both noise-limited and mismatch-limited SAR
ADCs together with their individual components [13]

• At lower resolutions (4–6 bits), the power is dominated by the digital SAR logic
power. This can be explained by the fact that the target resolution is readily
achievable.
• At higher resolutions (12+ bits), the power is dominated by the DAC, namely
thermal noise and mismatch. At these resolutions, the KT/C noise requires a 4x
increase in the DAC capacitor for each additional bit in resolution.
• For medium resolution, there is a transition between these two regions of
operation.

3 Noise-Shaped SAR ADC

A number of years ago, Prof. Mike Flynn et al. observed that the residue voltage,
which resides in the SAR CDAC at the end of the conversion, is a measure of the
Quantisation noise or error relating to the conversion as discussed in the previous
section [14]. Hence, taking that error and adding it to the next input sample results
in an Error Feedback modulator, who’s linear model is given by Fig. 9.17 [15],
whereby the reside voltage is filtered by the loop filter, L(z), and added to the
sampled input [16].
To realise this structure, the implementation shown in Fig. 9.18 below results.
The resultant implementation requires that this “residue” voltage is sampled and
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Fig. 9.17 Linear model of an

error feedback noise-shaped
SAR ADC

Fig. 9.18 Circuit implementation of an error feedback-based noise-shaped SAR. A single-ended

representation is shown for simplicity

added to the next input sample as illustrated above, where an additional amplifier
is required to amplify the “residue” voltage prior to sampling it onto a capacitor.
The resultant amplified residue voltage is then added to the next sampled input, Vin ,
prior to undertaking the next set of bit trials.
This approach has the impact of realising a noise-shaped architecture, where the
quantisation error associated with any individual output is effectively averaged out
over a series of samples [17]. This is the objective of all noise-shaped architectures.
Today, there are several architectures used to realise a Noise-Shaped SAR
architecture, whereby the architecture refers to residue voltage which is available
9 Precision Voltage Sensing in Deep Sub-micron and Its Challenges 151

Fig. 9.19 An error feedforward-based architecture, where the residue voltage is sampled, process
for the loop filter, H(z), before being added at the comparator input

Fig. 9.20 Linear model of an

error feedforward-based
noise-shaped SAR ADC, with
loop filter, H(z)

at the end of a conversion. One of the earliest realisations is what was originally
proposed by Fredenburg and Flynn [14], where the residue voltage was sampled and
filtered before being added at the input of the comparator as illustrated in Fig. 9.19
above.
This architecture can be easily described when we look at the linear model
illustrated in Fig. 9.20 above, where the previous residue voltage is sampled and
filtered prior to being added at the input to the quantiser for the next set of bit trails.
Noise-Shaped SAR ADCs offer a number of inherent advantages over the
standard SAR architecture:
152 I. ÒConnell et al.

• First, noise-shaped architectures are inherently oversampled, which reduces the

in-band KT/C noise. This ensures that the CDAC can be made smaller, while
simultaneously reducing the in-band thermal noise.
• Second, unlike traditional Sigma Delta architectures, whereby the loop filter is
often required to suppress the quantisation noise by 14–16 bits in the case of
a single bit quantiser, in a Noise-Shaped SAR, the loop filter is typically only
required to suppress the quantisation noise by 5–7 bits [15]. This significantly
reduces the gain requirements within the loop filter making the architecture very
compatible with deep sub-micron CMOS technologies.
• Finally, the comparator noise is now shaped. As illustrated in Fig. 9.16, the
comparator noise is a significant contributor to the overall noise performance
of a standard SAR. Hence, the opportunity to significantly reduce the design
specifications around the comparator reduces its design complexity and effort.
While the Noise-Shaped SAR offers a number of advantages, there are also
a number of disadvantages which have to be addressed when realising a high
resolution ADC:
• Mismatch within the DAC capacitor [18] is not shaped [15, 19] and ultimately
limits the achievable resolution that can be achieved. A number of options are
available to address this, including a recently proposed technique by Nan Sun
[20]. These options can be best summarised under the following headings:
– Calibration: This requires background calibration whereby the non-ideal
capacitor weights are determined through measurement and digitally cor-
rected [21].
– Dynamic Element Matching: This is a well-established technique for multi-bit
Sigma Delta ADCs, where the error associated with individual capacitors is
averaged out over time [22, 23].
– Dither: Similar to DEM, Dither breaks the relationship between a specific dig-
ital code and a DAC error. This has the impact of distributing the power/energy
associated with the error across the whole spectrum, significantly reducing the
impact of any individual error [24].
• Loop Filter: to realise the noise-shaping, a loop filter is required to introduce the
poles or zeros into the system to suppress the quantisation noise within the band
of interest. However, the loop filter itself introduces its own noise, both thermal
and flicker, which needs to be included in the system calculations. At higher
resolutions, chopping or autozeroing is required to suppress the low-frequency
flicker noise [25].
• While passive loop filters can be used [26, 27], at higher resolutions an active
loop filter is required, which requires active components namely an amplifier. To
ensure stable and robust performance, it’s necessary to ensure that the amplifiers
have stable gain [15].
• Increased clock frequency: as previously stated, noise-shaped systems are inher-
ently oversampled, which means that the core circuitry is now required to run
significantly faster than the Nyquist frequency of the input signal.
9 Precision Voltage Sensing in Deep Sub-micron and Its Challenges 153

4 Error Feedback Design Example

A first-order Noise-Shaped SAR ADC is illustrated in Fig. 9.21 below, where

an error feedback topology is selected, with a single feedback capacitor. This
error feedback topology was selected for implementation as it offers the following
advantages:
• The architecture utilises charge summation to combine the amplified residue
voltage to the sampled input signal.
• By leveraging standard CMOS capacitor matching ensures that the loop filter is
stable.
• The amplifier gain can be realised using a Dynamic amplifier, which confers a
number of inherent advantages:
– Due to the dynamic nature, the Dynamic Amplifier is only consuming power
when amplifying the residue voltage and is not consuming power during the
normal SAR operation.
– Dynamic Amplifiers can be optimised to reduce the noise.
– Dynamic Amplifiers can operate from limited supply voltages.
However, this approach has a number of disadvantages:
• The noise introduced by the loop filter (KT/C noise sampled onto CFB , noise
added by the Dynamic Amplifier) is not shaped and adds directly to the ADC
output. Hence, the gain needs to be realised with low noise.
• The Amplifier needs to be linear to ensure that there is no distortion introduced.
• The Amplifier needs to have a stable gain.

Fig. 9.21 Proposed error feedback-based architecture

154 I. ÒConnell et al.

Fig. 9.22 Linear model of the proposed first-order error feedback noise-shaped SAR, with error
sources included

• In the absence of DAC calibration, the achievable resolution is ultimately limited

by the inherent matching that can be achieved on the process. Hence, to achieve
a resolution of greater than 12 bits will require either calibration, DEM or dither
to increase the raw capacitor matching within the DAC.
A linear model of the proposed error feedback modulator is illustrated in
Fig. 9.22 above, with the various noise sources included. Hence at the input, there is
sampling jitter, njit, and sampled thermal noise denoted by ns . The loop filter noise
is given by nlfilt , the quantisation noise is denoted by Qe , while the comparator noise
is given by ncomp .
When the different noise sources are analysed, it quickly becomes evident that:
• The quantisation error and quantisation noise are shaped by the loop filter.
• The amplifier thermal noise and sampled KT/C are flat and not shaped.
• At lower frequencies, amplifier flicker noise will extend above the noise floor.
• Capacitor mismatch, which for the purpose of this simulation is slightly exag-
gerated at 0.5%, results in high frequency quantisation noise being modulated
in-band, reducing the achievable resolution.
Hence, the presence of these real noise sources results in the ideal SNDR of
121 dB being reduced to a mere 73 dB for the proposed circuit in Fig. 9.23,
when considering the second-order implementation. This circuit consists of a 10
bit fully differential SAR, with the input being sampled onto the bottom plates of
the switched capacitor DAC. The operation of the Noise-shaped SAR can be best
explained as follows:
• At the start of a conversion, the charge in the switched capacitor DAC is reset to
zero, during a single 1.5 GHz clock cycle, R.
• The input signal is then sampled during S/H , which is allocated 2 clock cycles
to ensure that the input signal is fully settled.
9 Precision Voltage Sensing in Deep Sub-micron and Its Challenges 155

-50 Amplifier's CDAC mismatch (0.5%)

Flicker noise

-100
PSD, dB

-150
Sampled kT/CDAC noise
+Amplifier's thermal noise

-200
Ideal: SNDR = 121 dB
With noise sources:
SNDR = 73 dB
-250
4 6
10 10
Frequency, Hz

Fig. 9.23 Simulated noise performance based on the linear model

• At the same time, the residue voltage, which is amplified by 16, is sampled onto a
16C capacitor. Amplifying the residue by 16 has the equivalent effect of sampling
it onto a 256C capacitor, which is the same size as the DAC. Therefore, the
residue voltage is transferred to the next sample without any attenuation. A gain
of 16x is deemed manageable, while the KTC noise charge associated with the
16C feedback capacitors is not deemed excessive.
• Then during the normal synchronous SAR operation during SAR , the residue
voltage is combined with the input signal using charge sharing.
• After the bit trials have been completed, the residue voltage, Vres , is sampled and
amplified by the 2 stage Dynamic Amplifier, during res .
• After which the process repeats itself.
The layout of the capacitor DAC is completed using a segmented, common
centroid approach as illustrated in Fig. 9.24. The MSB capacitors are realised using a
16C segmented column approach with dummy capacitors at either end for matching.
This improves the matching, while also simplifying the layout effort. The 16C
columns are then selected in a common centroid manner to realise the MSBs. The
unit capacitor, Cu , is 16 fF, resulting in the total differential DAC capacitance being
4 pF.
This design targeted first-order Noise shaping; however, to enable an accurate
performance comparison, second-order noise shaping was also enabled.
Illustrated in Fig. 9.25a is the first-order noise shaping where the 20 dB/dec
quantisation noise shaping is clearly visible. But Fig. 9.25b demonstrates the
second-order noise-shaping, with the associated 40 dB/dec noise shaping. Closer
156 I. ÒConnell et al.

Fig. 9.24 Segmented Capacitor DAC layout in 28 nm CMOS

Fig. 9.25 Simulated transistor noise for (a) first-order error feedback noise-shaped SAR and (b)
second-order error feedback noise-shaped SAR

observation highlights that the second-order implementation achieves 0.5 ENOB

less performance compared to the first-order implementation. This can be readily
9 Precision Voltage Sensing in Deep Sub-micron and Its Challenges 157

Table 9.1 Thermal noise calculations for the proposed first-order error feedback noise-shaped
SAR
Noise sources Noise power % of total noise
Sampling noise 2kT/Cs oversampled 6.5E-11 26.4
Jitter 1 ps 1.0E-12 0.4
Quantisation noise 100 dB 2.0E-11 8.2
Mismatch noise (W) 2.0E-11 8.2
Oversampled op-amp thermal noise (W) 7.8E-11 31.9
op-amp flicker noise (W) 5.625E-11 22.9
Reference noise (W) 4.7E-12 1.9
Total noise (W) 2.5E-10
SNR(dB) 91.2

explained by the fact that the second-order implementation requires additional

feedback capacitors and amplification stages, increasing the thermal noise floor.
Hence, to achieve higher resolution, it is recommended to use a first-order noise
shaping. In addition to this, SNDR degradation due to mismatch is higher in the
second order noise-shaped SAR than in a first order one.
Illustrated in Table 9.1 above are the thermal noise calculations for the proposed
first-order error feedback noise-shaped SAR. It quickly becomes evident that
amplifier thermal noise and flicker noise account for over 50% of the total noise
budget. Hence, to minimise the amplifier noise requires a significant effort and
ultimately consumes a significant amount of the overall power budget.

5 Dynamic Amplifier

The Amplifier is implemented using a two-stage Dynamic Amplifier as illustrated in

Fig. 9.26 below. Proposed Dynamic Amplifier implementation features a two-stage
approach. The output shows the additional capacitors required to support second-
order noise shaping.
A two-stage design was selected to ensure that the individual stages had reduced
gain requirements. In addition, the first stage is only required to drive CG1 , which
can be made smaller easing the specifications for the first amplifier. However, while
the second stage is required to drive the larger feedback capacitors, CFB , its noise
spec can be slightly relaxed as its noise is attenuated by the gain of the first stage
when input referred.
Illustrated in Fig. 9.27 below are the trade-offs associated with the Dynamic
Amplifier, where the input referred noise rapidly reduces, when the Dynamic
Amplifier is allocated additional time. However, this reduces the throughput, further
necessitating a two-stage approach.
Illustrated in Fig. 9.28 below is the schematic associated with the two-stage
dynamic amplifier, with the first stage illustrated in Fig. 9.28a and the second
158 I. ÒConnell et al.

Fig. 9.26 Proposed Dynamic Amplifier implementation, featuring a two-stage approach. The
output shows the additional capacitors required to support second-order noise shaping

Fig. 9.27 Dynamic Amplifier Design Trade-offs

stage illustrated in Fig. 9.28b. However, the presence of 1/f noise necessitated
the introduction of chopping; hence, when chopping is introduced, Fig. 9.28a is
replaced with Fig. 9.29.
Note, chopping is not required in the second Dynamic amplifier, as there is
sufficient gain to suppress the 1/f noise when input referred by the first stage.
Illustrated in Fig. 9.30 below is the simulated output results associated with the
design. The presence of 1/f noise is clearly evident in Fig. 9.30a when the chopping
within the first stage of the dynamic amplifier is disabled. However, when the
chopping is enabled, the SNR increases significantly, along with an improvement
in SFDR of 3.7 dB.
The design was fabricated in a 28 nm CMOS bulk process. A die photograph is
illustrated in Fig. 9.31 below.
Illustrated in Fig. 9.32a below are the measured silicon results, clearly showing
the impact of 1/f noise in the absence of chopping. Figure 9.32b shows the simulated
results, showing good correlation with the measured results.
9 Precision Voltage Sensing in Deep Sub-micron and Its Challenges 159

Fig. 9.28 Proposed schematics of the two-stage Dynamic Amplifier (a) illustrates the first stage
and (b) illustrates the second stage with capacitive degeneration

avdd

reset
out1n out1p
φ1 φ2 φ2
en φ1

φ1 φ1
vinp vinn
φ2 φ2
vinn vinp

Fig. 9.29 First-stage Dynamic Amplifier with chopping added to reduce the in-band flicker noise

The measured results are summarised in Fig. 9.33 below, where the presence
flicker noise significantly increases the noise floor at lower frequencies. At higher
frequencies, there are a number of harmonics present. These result from capacitor
mismatch within the SAR DAC and ultimately result in high frequency noise
being modulated down into the baseband increasing the noise floor. In this specific
160 I. ÒConnell et al.

Fig. 9.30 Transistor noise simulations (a) shows the first-order error feedback modulator with
no-chopping in the Dynamic Amplifier. The presence of 1/f noise is clearly evident at the lower
frequencies and (b) with chopping enabled in the first stage of the Dynamic Amplifier, with a small
tone at 30 kHz being an artefact of chopping

Fig. 9.31 Die photo of the fabricated design in 28 nm bulk CMOS

9 Precision Voltage Sensing in Deep Sub-micron and Its Challenges 161

Fig. 9.32 (a) Measured silicon results illustrating the impact of capacitor mismatch and the
presence of 1/f noise and (b) the transistor simulation results which compare well with the
measured results

Fig. 9.33 Summary of Measured Results for the proposed first-order noise-shaped SAR

example, the brute force calibration algorithm we implemented was such that it only
targeted the reduction of distortion in the signal band. The out of band distortion was
never considered in the algorithm, and in fact the out of band distortion can be higher
in the calibrated spectrum than in the non-calibrated one.
162 I. ÒConnell et al.

6 Conclusion

The noise-shaped SAR offers a viable architecture for realising high precision for
voltage sensing in deep sub-micron CMOS process nodes. However, the first stage
ultimately limits the achievable accuracy where:
• Thermal Noise: in the form sampled KT/C in the SAR DAC, amplifier thermal
noise in design employing active loop filter and the loop filter sampled KT/C
noise need to be considered in the resultant performance.
• 1/f Noise: in architectures employing active loop filters, the 1/f noise of the
amplifier needs to be included in the noise calculation. At higher resolutions,
12+ bit, chopping or autozeroing needs to be added to the design to reduce the
in-band 1/f noise.
• Capacitor Mismatch: Capacitor mismatch within the SAR DAC ultimately limits
the achievable resolution. Hence, techniques such as DEM, Dither or calibration
need to be considered.
• While a single higher order loop is desirable to supress the in-band quantisation
noise, the additional thermal noise overhead associated with these designs
actually degrades the achievable performance. Hence, first-order single loops are
preferable.
• However, early research into cascaded/MASH based Noise-Shaped SARs is
offering interesting possibilities.
Considering this, noise-shaped SARs are enabling precision converters to be
realised in deep submicron CMOS technology nodes. In addition, while noise-
shaped SARs have gained popularity in recent years, especially in the research and
academic community, there are still many exciting research vectors to be explored.
One of these vectors is the area of hybrid architectures where noise-shaped SARs
are combined with other architectures. This is an exciting area with a lot of future
potential.

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