VLSI Physical Design Automation

Prof. G.K.Sharma

ABV-IIITM, Gwalior

August 3, 2015

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Introduction

Today’s complexity is billions (109 ) of transistors on a single chip.

I Examples:
1. The Intel 80x86 series of microprocessors has over 1 × 105
transistors (80186 = 5.5 × 104 , 80286 = 1.34 × 105 ,
80386 = 2.75 × 105 , and 80486 = 1.18 × 106 ).
2. The Pentium (Px) series processors has over 3 × 106 transistors
(P1 = 3.1 × 106 , P2 = 7.5 × 106 , P3 = 9.5 × 106 , and
P4 = 4.2 × 107 ).
3. Year 2012: the highest transistor count in a commercially
available CPU (Intel’s 10-core Xeon Westmere-EX) is 2.6
billion transistors (2.6 × 109 ).
4. Xilinx currently holds the world-record for an FPGA containing
billions of transistors.

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Introduction (Contd...)

ICs of such complexity (109 ) would not have been possible without
computer programs which automate most design tasks.
I Designing a VLSI chip with the help of computer programs is
known as Computer-Aided Design (CAD).
I Design Automation (DA) refers to entirely computerized
design process with no or very little human intervention.
I Electronic Design Automation (EDA or ECAD) provides a set
of software tools for designing electronic systems such as
PCBs and ICs.
I CAD and DA research has a long history (1960) and near to
mature since last two decades.

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Technology Transition vs. DA Research

I The demand for DA has escalated.

I The types of DA tools have multiplied due to changing needs.
Example: It is important to simulate the behavior of a circuit
before the circuit has been manufactured; this is because it is
impractical to breadboard a circuit of VLSI complexity.
I There has been a radical change in design issues.
Example: It is not very important to save on transistors; it is
important to save on interconnection costs, since wires are far
more expensive in VLSI than transistors.
I Due to sustained research by a number of groups,
sophisticated tools are available for designing ICs, and we are
briskly moving towards complete DA.

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VLSI Design Process

In order to reduce the complexity of design process, several

intermediate levels of abstractions are introduced.

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VLSI Design Process (Contd...)

I More and more details are introduced as the design progresses

from highest to lowest levels of abstractions.
I The design is taken from specifications to fabrication step by
step with the help of CAD tools.

Note: It is not possible for a human engineer to sit down with

paper and pencil to design a billion-transistor IC.
Rather it is easy to think in terms of larger circuit modules such as
ALUs, memory units (RAM/ROM), interconnection networks, and
controllers.
Designing a circuit at this level (modules) of abstractions is known
as architectural design.

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Architectural Design

I Job of expert human engineers.

I Decisions (instruction set, addressing modes, memory size,
pipelining, interface etc.) made at this stage affect the cost
and performance of the design significantly.
I Architectural design cannot be done entirely by a computer
program.
I Computer programs can aid the system architect in making
important decisions and tuning parameters through
simulation.
I Simulators and performance prediction tools are useful to a
computer architect for experimenting with innovative ideas.

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Architectural Design (Contd...)

I Once the system architecture is defined, we need to carry out

the following:

(a) Data Path Design: Detailed logic design of individual circuit

modules.
(b) Control Path Design: Derive the control signals necessary to
activate and deactivate the circuit modules.
I Data path of a circuit includes the various functional blocks
(adder, multipliers, ALU), storage elements (registers,
RAM/ROM, buffers), and hardware components to allow
transfer of data.
I Control path of a circuit generates the various control signals
(initialize storage elements, initiate data transfers, and so on)
necessary to operate the circuit.

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Example: An 8-Bit Adder Design

The two operands are stored in two 8-bit shift registers A and B.
At the end of the addition operation, the sum must be stored in A.
The contents of B must not be destroyed. The design must be as
economical as possible in terms of hardware.

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Solution

Numerous ways:
I Use an 8-bit carry look-ahead adder.
I Use an 8-bit ripple-carry adder.
I Use two 4-bit carry look-ahead adders and ripple the carry
between stages.
I Use a 1-bit carry adder and perform the addition serially in 8
clock cycles.
Last option, i.e. serial adder is perhaps the best since the
requirement is the minimum hardware cost.

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Hardware Synthesis

I Designing a circuit involves a trade-off between cost,

performance, and testability. There are many more design
aspects, such as power dissipation, fault tolerance, ease of
design, and ease of making changes to the design.
I All the different ways that we can think of to design a circuit
(such as 8-bit adder) constitute what is known as the design
space (at that particular level of abstraction).
I Each method of implementation is called a point in the design
space. There are advantages and disadvantages associated
with each design point.
I When we try optimizing the hardware cost, we usually lose
out on performance, and vice versa.

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Hardware Synthesis (Contd...)

I A circuit specification may pose constraints on one or more

aspects of the final design.
Example: When the specification says that the circuit must
operate at a minimum of 15 MHz, we have a constraint on
the timing performance.
I The objective is to arrive at a design which meets all the
constraints posed by the specification, and optimization of one
or more of the design aspects is known as hardware synthesis.
I Computer programs have been developed for data path
synthesis as well as control path synthesis.
I The automatic generation of data path and control path is
known as high-level synthesis.

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Logic Design

I The data path and control path will have components such as
adders, multipliers, ALUs, registers, RAM/ROM, buffers, and
hardware components to allow transfer of control and data
signals.
I Design steps depend on the following two factors:

1. How is the circuit to be implemented, on a PCB or as a VLSI

chip?
2. Are all the components available as off-the-shelf ICs circuits or
as predesigned modules?
I If the circuit must be implemented on a PCB using
off-the-shelf components, then the next stage in design is to
select the components to minimize the total cost and
maximize the performance.

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Logic Design (Contd...)

I Further, the ICs are placed on one or more boards and the
necessary interconnections are established using one or more
layers of metal deposits.

I A similar procedure may be used in case the circuit is

implemented on a VLSI chip using predesigned components
from a module library.

I These predesigned modules are also known as macro-cells.

I The cells must be placed on the layout surface and wired

together using metal and polysilicon (poly) interconnections.

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Physical Design

I Physical design of a circuit is the phase that precedes the

fabrication of a circuit.
I In most general terms it refers to all synthesis steps
succeeding logic design and preceding fabrication.
I These include all or some of the following steps:
1. Circuit Partitioning
2. Floorplanning
3. Placement
4. Routing,

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Physical Design (Contd...)

I The performance, area, yield, and reliability of the circuit

depend on the physical layout.
I There are two components to the area of an IC - functional
area (active elements), and the wiring area (metal and poly
lines used for interconnect).
I Wires (metal and poly lines), contacts, and vias introduce a
significant amount of impedance and affect the performance
(slowing down of signals) and area of the circuit.
I The area of a circuit also has a direct influence on the yield
(no. of defect-free chips) of the manufacturing process.
I A good layout should have strongly connected modules placed
closely together, so that long wires and number of vias are
avoided as much as possible.

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Layout Styles

I Layout styles differ mainly in the structural constraints they

impose on the layout elements and the layout surface.
I They belong to two general classes:
(a) The full-custom layout approach (no constraints imposed).
(b) The semi-custom approaches (impose some structure to reduce
complexity).
I Current layout styles are:
1. Full-Custom,
2. Gate-Array,
3. Standard-Cell,
4. Macro-Cell (Building Block Layout),
5. PLA (Programmable Logic Array), and
6. FPGA (Field Programmable Gate-Array).

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Full-Custom Layout

I Full-custom layout refers to manual layout design, where an

expert artwork designer uses a layout editor to generate a
physical layout.
I Advantages:
1. Gives full control to the artwork designer in placing and
interconnecting circuit blocks.
2. A high degree of optimization in both the area and
performance is possible.
I Disadvantages:
1. Full-custom design is a time-consuming and difficult task. It
takes several months to layout a VLSI chip manually.
2. Full-custom approach is used only for circuits that are mass
produced, e.g., microprocessors.

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Full-Custom Layout (Contd...)

I Designers productivity is increased with the help of a good

layout editor, e.g., a layout editor can perform on-line Design
Rule Check (DRC).
I Design rules are a set of precautions that must be taken while
drawing a layout.
I There are two types of design rules:
1. Width rule: specifies the minimum width of a feature i.e.
technology, e.g., 180µm, 90nm, 45nm .
2. Spacing rule: specifies the minimum distance that must be
allowed between two features.
I Full-custom design is prohibitively expensive for circuits which
are unlikely to be manufactured in large numbers (such as
Application-Specific Integrated Circuits (ASICs)).

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Gate-Array Layout

I A gate-array (Mask Programmable Gate Arrays (MPGAs))

consists of transistors prefabricated on a wafer in the form of
a regular 2-D array.
I Initially the transistors in an array are not connected to one
another.
I In order to realize a circuit on a gate-array, metal connections
must be placed using the usual process of masking known as
personalizing.
I Personalization involves two types of interconnections -
intra-cell wiring and inter-cell wiring.
I After personalization, the wafer can be diced and individual
gate-arrays can be separated, packaged, and tested.

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Gate-Array Layout (Contd...)

I The floorplan of the gate-array chip can be likened to that of

a township which has a number of buildings (cells) and streets
(channels) to carry traffic (wires) from one building to
another.
I Properties of Gate-Array:
(a) Short fabrication time (only four processing steps).
(b) Low cost of production due to high yield.
(c) Limited wiring space, therefore present difficulties to automatic
layout generator.
I A special case of the gate-array architecture is when routing
channels are very narrow, or virtually absent is called
Sea of Gates (Channel-less Gate-Arrays).

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Basic Gate-Array Cell

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Gate-Array Floorplan

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