Digital Circuit Design

CHAPTER-1
Number Systems and Codes

2.1 Motivation:
This chapter provides a review of the different number system formats used in digital world and
the conversions between these number systems. It also focuses on the basic arithmetic in binary
form. It also includes the different codes present in digital world. The main motivation of this
chapter is to deliver the knowledge, motivate and train students in basics of Digital Logic Design.

1.2. Syllabus: -
Sr. No Topic Fine Detailing No of Week Self
Hours Study

01 Number Review of Number System, Binary Code, 6 2 15

Systems and Binary Coded Decimal, Octal Code,
Codes Hexadecimal Code and their conversions,
Binary Arithmetic: One's and two's
complements,Excess-3 Code, Gray Code,
Weighted code, Parity Code: Hamming Code
1.3. Books Recommended:
1. Morris Mano, Digital Design, Pearson Education, Asia 2002.
2. R.P.Jain, Modern Digital Electronics, Tata McGraw Hill Education, Third Edition 2003.
3. John F. Wakerly, Digital Design Principles and Practices, Pearson Education, Fourth
Edition, 2008.

1.4. Weightage in University Examination: 15-25 Marks

1.5. Objectives:
• To list the different number systems
• To calculate ones and twos complement of a givne number
• To convert a particular given number into a different number system format
• To calculate excess 3 code for a given binary number

1.6 Key Notations:

BCD – Binary Coded Decimal

1.7 Key Definitions:

Binary Numbers - A binary number is a sequence of the digits 0 and 1

Bits - Each of the digits is called a bit

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Bytes - A byte is a group of 8 bits

1.8.1 Introduction:
The decimal number system is fine for calculations done by humans, but it is not the easiest system
for a computer to use. A digital computer contains elements that can be in either of two states: on
or off, magnetized or not magnetized, and so on. For such devices, calculations are most
conveniently done using binary numbers. In this chapter we learn what binary numbers are and how
to convert between binary and decimal numbers. Binary numbers are useful in a computer, where
each binary digit (bit) can be represented by one state of a “binary switch” that is either on or off.
However, binary numbers are hard to read, partly because of their great length. To represent a nine-
digit Social Security number, for example, requires a binary number 29 bits long. So, in addition to
binary numbers, we also study other ways in which numbers can be represented. Hexadecimal,
octal, and binary-coded decimal systems allow us to express binary numbers more compactly, and
they make the transfer of data between computers and people much easier. Here we learn how to
convert numbers between each of these systems, and between decimal and binary as well.

1.8.1.1 The Binary Number System

Binary Numbers - A binary number is a sequence of the digits 0 and 1, such as 1101001 The number
shown has no fractional part and so is called a binary integer. A binary number having a fractional
part contains a binary point (also called a radix point), as in the number 1001.01

Base or Radix - The base of a number system (also called the radix) is equal to the number of digits
used in the system.

Example 1:

(a) The decimal system uses the ten digits

0 1 2 3 4 5 6 7 8 9
and has a base of 10.

(b) The binary system uses two digits

0 1
and has a base of 2.

Bits, Bytes, and Words

Each of the digits is called a bit, from binary digit. A byte is a group of 8 bits, and a word is the largest
string of bits that a computer can handle in one operation. The number of bits in a word is called the
word length. Different computers have dif-ferent word lengths, with 8, 16, or 32 bits being common
for desktop or personal computers. The longer words are often broken down into bytes for easier
handling. Half a byte (4 bits) is called a nibble.
A kilobyte (Kbyte or KB) is 1024 (210) bytes, and a megabyte (Mbyte or MB) is 1,048,575 (220)
bytes.

1.8.1.2 The Hexadecimal Number System

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Hexadecimal Numbers Hexadecimal numbers (or hex for short) are obtained by grouping the bits in
a binary number into sets of four and representing each such set by a single number or letter. A hex
number one-fourth the length of the binary number is thus obtained.

Base 16

Since a 4-bit group of binary digits can have a value between 0 and 15, we need 16 symbols to
represent all of these values. The base of hexadecimal numbers is thus 16. We use the digits from 0
to 9 and the capital letters A to F, as shown in Table 1.

TABLE 1 Hexadecimal and octal number systems.

Decimal Binary Hexadecimal Octal

0 0000 0 0

1 0001 1 1

2 0010 2 2

3 0011 3 3

4 0100 4 4

5 0101 5 5

6 0110 6 6

7 0111 7 7

8 1000 8 10

9 1001 9 11

10 1010 A 12

11 1011 B 13

12 1100 C 14

13 1101 D 15

14 1110 E 16

15 1111 F 17
1.8.1.3 The Octal Number System

The octal number system uses eight digits, 0 to 7, and hence has a base of eight. A comparison of the
decimal, binary, hex, and octal digits is given in Table 1.

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1.8.2 Number System Conversion

1.8.2.1 Converting Binary Numbers to Decimal

1. Write down the binary number.
2. List the powers of two from right to left.
3. Write the digits of the binary number below their corresponding powers.
4. Write down the final value of each power of two.
5. Connect the digits in the binary number with their corresponding powers.
6. Add the final values.
7. Write the answer along with its base subscript.

Example: Find the decimal value of 1110012:

binary number: 1 1 1 0 0 1
power of 2: 25 24 23 22 21 20

1110012 = 1⋅25 + 1⋅24 + 1⋅23 + 0⋅22 + 0⋅21 + 1⋅20 = 5710

Here are some examples of converting binary directly into decimal. We simply add up the place
values of each 1 digit in the binary number.

1001012 = 3710:
Exponents 25 24 23 22 21 20
Place Values 32 16 8 4 2 1
Bits 1 0 0 1 0 1
Value 32 + 4 + 1 = 37

100011102 = 14210:

Exponents 27 26 25 24 23 22 21 20
Place Values 128 64 32 16 8 4 2 1
Bits 1 0 0 0 1 1 1 0
Value 128 + 8 + 4 + 2 = 142

1111010002 = 48810:

Exponents 28 27 26 25 24 23 22 21 20
Place Values 256 128 64 32 16 8 4 2 1
Bits 1 1 1 1 0 1 0 0 0
Value 256 + 128 + 64 + 32 + 8 = 488

101101012 = 18110:

Exponents 27 26 25 24 23 22 21 20
Place Values 128 64 32 16 8 4 2 1
Bits 1 0 1 1 0 1 0 1
Value 128 + 32 + 16 + 4 + 1 = 181
1.8.2.2. Binary To Hex Conversions

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Conversion between hex and binary is easy. Simply substitute four-bit groups for the hex digit of the
same value. Specifically:

Hex Digit: 0 1 2 3 4 5 6 7
Bit Group: 0000 0001 0010 0011 0100 0101 0110 0111
Hex Digit: 8 9 a b c d e f
Bit Group: 1000 1001 1010 1011 1100 1101 1110 1111

For conversion from hex to binary, simply string together the bits for each hex digit. For instance,
0x509d7a is binary 10100001001110101111010.

Hex Number: 5 0 9 d 7 a
Binary Number: 0101 0000 1001 1101 0111 1010

To convert the other way, break the binary number into groups of four, and then replace each one
with its hex digit. Group the digits starting from the right. If you don't have a complete group of four
when you reach the left, pad with zero bits on the left to fill the last group. For instance, binary
111011011111110001 is 0x3b7f1:

Binary Groups: 0011 1011 0111 1111 0001

Hex Digits: 3 b 7 f 1

Because this conversion is so easy, the easiest way to convert between binary and decimal is usually
to go through hex. It generally requires fewer operations, and hex numbers are easier to work with
because they are shorter Also, it's easier to remember where you are when scanning a hex number,
since the digits differ more.

1.8.2.3 Binary to Octal

An easy way to convert from binary to octal is to group binary digits into sets of three, starting with
the least significant (rightmost) digits.

Binary: 11100101 = 11 100 101

011 100 101 Pad the most significant digits with zeros if necessary to
complete a group of three.

Then, look up each group in a table:

Binary: 000 001 010 011 100 101 110 111
Octal: 0 1 2 3 4 5 6 7

Binary = 011 100 101

Octal = 3 4 5 = 345 oct

1.8.2.4 Hex To Decimal Conversions

Here are some examples of converting hexadecimal into decimal. For each place, we multiply the
digit value by the place value, and total the products.

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5a816 = 144810:

Exponent: 162 161 160

Place Value: 256 16 1
Digit Value: 5 10 8
Product: 1280 + 160 + 8 = 1448

2c0316 = 1126710:

16
Exponent: 163 162 161 0

Place Value: 4096 256 16 1

Digit Value: 2 12 0 3
Product: 8192 + 3072 + 0 + 3 = 11267

9516 = 14910:

Exponent: 161 160

Place Value: 16 1
Digit Value: 9 5
Product: 144 + 5 = 149

b1716 = 283910:

16
Exponent: 162 161 0

Place Value: 256 16 1

Digit Value: 11 1 7
Product: 2816 + 16 + 7 = 2839

1.8.2.5 Hexadecimal to Binary

Converting from hexadecimal to binary is as easy as converting from binary to hexadecimal. Simply
look up each hexadecimal digit to obtain the equivalent group of four binary digits.

Hexadecimal: 0 1 2 3 4 5 6 7
Binary: 0000 0001 0010 0011 0100 0101 0110 0111
Hexadecimal: 8 9 A B C D E F
Binary: 1000 1001 1010 1011 1100 1101 1110 1111

Hexadecimal = A 2 D E
Binary = 1010 0010 1101 1110 = 1010001011011110 binary

1.8.2.5 Hexadecimal to Octal

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When converting from hexadecimal to octal, it is often easier to first convert the hexadecimal
number into binary and then from binary into octal. For example, to convert A2DE hex into octal:

(from the previous example)

Hexadecimal = A 2 D E
Binary = 1010 0010 1101 1110 = 1010001011011110 binary

Add leading zeros or remove leading zeros to group into sets of three binary digits.

Binary: 1010001011011110 = 001 010 001 011 011 110

Then, look up each group in a table:

Binary: 000 001 010 011 100 101 110 111
Octal: 0 1 2 3 4 5 6 7

Binary = 001 010 001 011 011 110

Octal = 1 2 1 3 3 6 = 121336 octal

Therefore, through a two-step conversion process, hexadecimal A2DE equals binary

1010001011011110 equals octal 121336.

1.8.2.6 Octal to Binary

Converting from octal to binary is as easy as converting from binary to octal. Simply look up each
octal digit to obtain the equivalent group of three binary digits.

Octal: 0 1 2 3 4 5 6 7
Binary: 000 001 010 011 100 101 110 111

Octal = 3 4 5
Binary = 011 100 101 = 011100101 binary

1.8.2.7 Octal to Hexadecimal

When converting from octal to hexadecimal, it is often easier to first convert the octal number into
binary and then from binary into hexadecimal. For example, to convert 345 octal into hex:

(from the previous example)

Octal = 3 4 5
Binary = 011 100 101 = 011100101 binary

Drop any leading zeros or pad with leading zeros to get groups of four binary digits (bits):
Binary 011100101 = 1110 0101

Then, look up the groups in a table to convert to hexadecimal digits.

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Binary: 0000 0001 0010 0011 0100 0101 0110 0111

Hexadecimal: 0 1 2 3 4 5 6 7
Binary: 1000 1001 1010 1011 1100 1101 1110 1111
Hexadecimal: 8 9 A B C D E F

Binary = 1110 0101

Hexadecimal = E 5 = E5 hex

Therefore, through a two-step conversion process, octal 345 equals binary 011100101 equals
hexadecimal E5.

1.8.2.8 Octal to Decimal Conversion

The method is quite similar to the transformation of any binary number to decimal number, the only
difference is that in this case the 2 s will be replaced by 8 and everything else i.e. the methods will
remain same. So it is quite clear if we want to change any octal number into decimal number we
have to start multiplying the digits of the number from right hand side with increasing powers of 8
staring from 0 and finally summing up all the products. The method will be clearer with an example.
Suppose we want to convert 1238 into decimal number, so we have to follow the procedure as
shown below
1238 = 1×82 + 2×81 + 3×80 = 64 + 16 + 3 = 73
So, the decimal equivalent of the number 1238 is 7310

1.8.2.9 Converting Decimal Numbers to Binary

A quick way to convert decimal numbers into their binary counterparts is to repeatedly divide the
decimal number by two. The remainders of each division (always a 1 or 0) will be the binary
number. As an example, we will convert 102 into decimal. In Table 2, we repeatedly divide the left
number by 2 and insert the remainder in the right column. We do this until we get zero in all
columns.
Table 2. Algorithm for decimal to binary conversion.

The result is that (102)10 = (1100110)2.

Number conversion Without fractions Fractions

Decimal to binary ,octal Divide by 2 for binary, divide by 8 for Multiply fractional part by 2 in
,hexadecimal octal and divide by 16 for hexadecimal binary.

By 8 for octal and by 16 for

hexadecimal

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Binary to decimal Add the weighted value to the decimal Add the weighted value to the
number ( base 2) where place holder is decimal number ( base 2) where
0 to n fractional placeholder is 2-1, 2-
2
………
2 2 , 2 1 ,2 0

Same applies for octal and Base 8 and 16 respectively

hexadecimal
Base 8 and 16 respectively

Binary to octal Create a group of 3 bits ,add trailing Create a group of 3 bits and add
bits to the left with 0, and assign the trailing bits to the right with
corresponding value 0,assign the corresponding value
Binary to hexadecimal Create a group of 4 bits ,add trailing Create a group of 4bits and add
bits to the left with 0 trailing bits to the right with 0
Octal and hexadecimal to Write binary equivalent of each digit Write binary equivalent of each
binary towards left. (For octal form group digit after decimal point towards
of3bits and for hexadecimal in 4bits) right
Octal to hexadecimal First convert octal to binary then Same as for integers
binary to hexadecimal
Hexadecimal to octal First convert hexadecimal to binary Same as for integers
then binary to octal

1.8.3 BCD Codes

With a BCD or binary-coded-decimal code, a decimal number is not converted as a whole to

binary, but rather digit by digit. For example, the 1 in the decimal number 17 is 0001 in 4-bit binary,
and the 7 is equal to 0111. Thus
17 = 10001 in straight binary

and

17 = 0001 0111 in BCD

When we converted the digits in the decimal number 17, we used the same 4- bit binary equivalents
as in Table 2. The bits have the place values 8, 4, 2, and 1, and BCD numbers written in this manner
are said to be in 8421 code. The 8421 code and its decimal equivalents are listed in Table 3

TABLE 3 Binary-coded-decimal numbers.

Decimal 8421 2421 5211

0 0000 0000 0000

1 0001 0001 0001

2 0010 0010 0011

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3 0011 0011 0101

4 0100 0100 0111

5 0101 1011 1000

6 0110 1100 1010

7 0111 1101 1100

8 1000 1110 1110

9 1001 1111 1111

1.8.3.1 Converting Decimal Numbers to BCD

To convert decimal numbers to BCD, simply convert each decimal digit to its equivalent 4-bit code.

Example 1: Convert the decimal number 25.3 to 8421 BCD code.

Solution: We find the BCD equivalent of each decimal digit from Table 3.
2 5 . 3
0010 0101 . 0011
or 0010 0101.0011.

1.8.3.2 Converting from BCD to Decimal

To convert from BCD to decimal, separate the BCD number into 4-bit groups, and write the decimal
equivalent of each group.
Example 22: Convert the 8421 BCD number 1 0011.0101 to decimal.
Solution: We have
0001 0011 . 0101
From Table 3, we have
1 3 . 5
or 13.5.

1.8.3.3 Other BCD Codes

Other BCD codes are in use which represent each decimal digit by a 6-bit binary number or an 8-bit
binary number, and other 4-bit codes in which the place values are other than 8421. Some of these
are shown in Table 3. Each is used in the same way as shown for the 8421 code.

Example : Convert the decimal number 825 to 2421 BCD code.

Solution: We convert each decimal digit separately,
8 2 5

1110 0010 1011

1.8.4 Other Computer Codes

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In addition to the binary, hexadecimal, octal, and BCD codes we have discussed, many other codes
are used in the computer industry. Numbers can be represented by the excess-3 code or the Gray
code. There are error-detecting and parity checking codes. Other codes are used to represent letters
of the alphabet and special symbols, as well as numbers. Some of these are Morse code, the
American Standard Code for Information Interchange or ASCII (pronounced “as-key”) code, the
Extended Binary-Coded-Decimal Interchange Code or EBCDIC (pronounced “eb-si-dik”) code, and the
Hollerith code used for punched cards.

1.8.5 Binary Arithmetic: One's and two's complements

Complements are used in the digital computers in order to simplify the subtraction operation and
for the logical manipulations. For each radix-r system (radix r represents base of number system)
there are two types of complements.

S.N. Complement Description

1 Radix Complement The radix complement is referred to as the r's

complement

2 Diminished Radix Complement The diminished radix complement is referred to as

the (r-1)'s complement

Binary system complements

As the binary system has base r = 2. So the two types of complements for the binary system are 2's

complement and 1's complement.

1.8.5.1 1's complement

The 1's complement of a number is found by changing all 1's to 0's and all 0's to 1's. This is called as

taking complement or 1's complement. Example of 1's Complement is as follows.

1.8.5.2 2's complement

The 2's complement of binary number is obtained by adding 1 to the Least Significant Bit (LSB) of
1's complement of the number.

2's complement = 1's complement + 1

Example of 2's Complement is as follows.

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What is -65d in binary?

Two’s complement allows us to represent signed negative values in binary, so here is an introductory

demonstration on how to convert a negative decimal value to its negative equivalent in binary using

two’s complement.

Step 1: Convert 65d to binary. Ignore the sign for now. Use the absolute value. The absolute value of

-65d is 65d.
65d --> 01000001b

Step 2: Convert 01000001 to its one’s complement.

01000001 --> 10111110

Step 3: Convert 10111110b to its two’s complement by adding 1 to the one’s complement.
10111110
+ 1
---------
10111111 <--- Two's complement

10111111b is -65d in binary.

In the coding, when numbers, letters or words are represented by a specific group of symbols, it is

said that the number, letter or word is being encoded. The group of symbols is called as a code. The

digital data is represented, stored and transmitted as group of binary bits. This group is also called

as binary code. The binary code is represented by the number as well as alphanumeric letter.

1.8.6 Advantages of Binary Code

Following is the list of advantages that binary code offers.

• Binary codes are suitable for the computer applications.

• Binary codes are suitable for the digital communications.

• Binary codes make the analysis and designing of digital circuits if we use the binary codes.

• Since only 0 & 1 are being used, implementation becomes easy.

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1.8.7 Classification of binary codes

The codes are broadly categorized into following four categories.

• Weighted Codes

• Non-Weighted Codes

• Binary Coded Decimal Code

• Alphanumeric Codes

• Error Detecting Codes

• Error Correcting Codes

1.8.7.1 Weighted Codes

Weighted binary codes are those binary codes which obey the positional weight principle. Each

position of the number represents a specific weight. Several systems of the codes are used to

express the decimal digits 0 through 9. In these codes each decimal digit is represented by a group

of four bits.

1.8.7.2 Non-Weighted Codes

In this type of binary codes, the positional weights are not assigned. The examples of non-weighted

codes are Excess-3 code and Gray code.

Excess-3 code

The Excess-3 code is also called as XS-3 code. It is non-weighted code used to express decimal

numbers. The Excess-3 code words are derived from the 8421 BCD code words adding (0011)2 or

(3)10 to each code word in 8421. The excess-3 codes are obtained as follows −

Example

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Gray Code

It is the non-weighted code and it is not arithmetic codes. That means there are no specific weights

assigned to the bit position. It has a very special feature that, only one bit will change each time the

decimal number is incremented as shown in fig. As only one bit changes at a time, the gray code is

called as a unit distance code. The gray code is a cyclic code. Gray code cannot be used for

arithmetic operation.

Application of Gray code

• Gray code is popularly used in the shaft position encoders.

• A shaft position encoder produces a code word which represents the angular position of the

shaft.

1.8.7.2.1 Conversion from Gray Code to Binary Code

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Let Gray Code be g3 g2 g1 g0. Then the respective Binary Code can be obtained as follows:

i.e. b3 = g3

b2 = b3 ⊕ g2

b1 = b2 ⊕ g1

b0 = b1 ⊕ g0

Example:

Gray Code: g3 g2 g1 g0 = 1 0 0 1 then Binary Code: b3 b2 b1 b0

b3 = g3 = 1

b2 = b3 ⊕ g2 = 1 ⊕ 0 = 1

b1 = b2 ⊕ g1 = 1 ⊕ 0 = 1

b0 = b1 ⊕ g0 =1 ⊕ 1 = 0

∴ Final Binary Code: 1 1 1 0

1.8.7.2.2 Conversion from Binary code to Gray Code

Let Binary code be b3 b2 b1 b0. Then the respective Gray Code can be obtained is as follows

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i.e. g3 = b3

g2 = b3 ⊕ b2

g1 = b2 ⊕ b1

g0 = b1 ⊕ b0

Example:

Binary Code: b3 b2 b1 b0 = 1 1 1 0 Gray Code: g3 g2 g1 g0

g3 = b3 = 1

g2 = b3 ⊕ b2 = 1 ⊕ 1 = 0

g1 = b2 ⊕ b1 = 1 ⊕ 1 = 0

g0 = b1 ⊕ b0 =1 ⊕ 0 = 1

∴ Final Gray code: 1 0 0 1

1.8.7.3 Parity Code : Hamming Code

Richard Hamming found a beautiful binary code that will correct any single error and will detect any
double error (two separate errors). The Hamming code has been used for computer RAM, and is a
good choice for randomly occurring errors. (If errors come in bursts, there are other good codes.)
Unlike most other error-correcting codes, this one is simple to understand.

The code uses extra redundant bits to check for errors, and performs the checks with special check
equations. A parity check equation of a sequence of bits just adds the bits of the sequence and
insists that the sum be even (for even parity) or odd (for odd parity). This section uses even parity.
Alternatively, one says that the sum is taken modulo 2 (divide by 2 and take the remainder), or one
says that the sum is taken over the integers mod 2, Z2.

A simple parity check will detect if there has been an error in one bit position, since even parity will
change to odd parity. (Any odd number of errors will show up as if there were just 1 error, and any
even number of errors will look the same as no error.)

One has to force even parity by adding an extra parity bit and setting it either to 1 or to 0 to make
the overall parity come out even. It is important to realize that the extra parity check bit participates
in the check and is itself checked for errors, along with the other bits.

The Hamming code uses parity checks over a portion of the positions in a block. Suppose there are
bits in consecutive positions from 1 to n-1. The positions whose position number is a power of 2 are

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used as check bits, whose value must be determined from the data bits. Thus the check bits are in
positions 1, 2, 4, 8, 16, ..., up to the largest power of 2 that is less than or equal to the largest bit
position. The remaining positions are reserved for data bits.

1.9 Objective Questions

1. Define Bit.
2. What do you mean by BCD.
3. How to obtain Excess 3 Code from BCD code?
4. List the different number systems.
5. List the different binary weighted codes.

1.10 ShortQuestions
1. Convert a binary number (1001011) to a decimal number.
2. Convert a Hexadecimal number (F7#4) to octal number.
3. Find ones and twos complement of (1001011).

1.11 Long Questions

1. How to convert a binary code to a gray code.
2. Why do we require ones and twos complement.

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CHAPTER-2
Logic Gates and Boolean Algebra

2.1 Motivation:
This chapter teaches the basic design techniques for logic circuits. It emphasizes the synthesis of
circuits and explains how circuits are implemented using logical gates. The main motivation of
this chapter is to deliver the knowledge, motivate and train students in basics of Digital Logic
Design.

2.2. Syllabus: -
Sr. No Topic Fine Detailing No of Week Self
Hours Study

02 Logic Gates Digital logic gates, Realization using NAND, 08 02 20

and Boolean NOR gates, Boolean Algebra, De Morgan’s
Algebra Theorem, SOP and POS representation, K Map
up to four variables and Quine-McClusky
method upto four variables

2.3. Books Recommended:

1. Morris Mano, Digital Design, Pearson Education, Asia 2002.
2. R.P.Jain, Modern Digital Electronics, Tata McGraw Hill Education, Third Edition 2003.
3. John F. Wakerly, Digital Design Principles and Practices, Pearson Education, Fourth
Edition, 2008.

2.4. Weightage in University Examination: 20-30 Marks

2.5. Objectives:
• To understand basic terminology, types of logic gates (AND, OR, NOT, NAND, NOR,
XOR,XNOR)
• To understand the basic operations used in computers and other digital systems
• To introduce the students basic rules of Boolean algebra, De Morgan’s laws
• To study universality of NAND and NOR gates
• To study Karnaugh maps for circuit minimization

2.6 Key Notations:

SOP-Sum of Product

POS-Product of Sum

K-Map- Karnough Map

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2.7 Key Definitions:

De Morgan's Laws: These laws are very useful in simplifying Boolean expressions. According to
De Morgan's theorem:

2.8.1 Introduction:

Boolean Algebra and Logic Gates

Boolean algebra:
Boolean algebra (due to George Boole) is the mathematics of digital logic and is useful in dealing
with binary system of numbers. Boolean algebra is used in the analysis and synthesis of logical
expressions.
Logical expressions are constructed using logical-variables and -operators. The value of any
logical expression boils down to any one of the two logical constants listed below:
- True
- False
In Boolean algebra, a variable x may take any one of the two possible values 1 and 0.
x = 1 and x = 0 which may represent respectively
- Truth or Falsehood of a statement
- On or Off states of a switch
- High (5V) or low (0V) of a voltage level

Fig.2.1:Logic waveform And True-False Representation

Electrical circuits designed to represent logical expressions are popularly known as logic circuits.
Such circuits are extensively used in industrial processes, household appliances, computers,
communication devices, traffic signals and microprocessors to make important logical decisions.
Logic circuits are usually represented by logic operations involving boolean variables.
There are three basic logic operations as listed below:
- OR operation

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- AND operation
- NOT operation

Logic Gates: logic gates are the basic building blocks of any digital system.it is an electronic
circuit having one or more than one inputs and only one output. The relationship between
the input and the output is based on a certain logic .based on this logic the gates are named
as NOT gate, AND gate, OR, NAND, NOR etc. AND , OR and NOR GATE are considered to be
the basic gate. Truth Tables are used to help show the function of a logic gate.

Digital systems are said to be constructed by using logic gates. These gates are the AND, OR,
NOT, NAND, NOR, EXOR and EXNOR gates. The basic operations are described below with the
aid of Truth Tables
1] AND gate:
The AND gate is an electronic circuit that gives a high output (1) only if all its inputs are high. A
dot (.) is used to show the AND operation i.e. A.B. Bear in mind that this dot is sometimes
omitted i.e. AB

Fig.2.2: AND Gate and Its Truth Table

The following relationships can be easily derived from this circuit:

A.A = A
1.A = A
0.A = 0
A.Ā = 0
A.B = B.AA.(B.C) = (A.B).C = A.B.C

Note: The • sign can be omitted when indicating an AND operation. Thus, C=A•B and C=AB
mean the same operation.
2] OR gate:
The OR gate is an electronic circuit that gives a high output (1) if one or more of its inputs are
high. A plus (+) is used to show the OR operation.

Fig.2.3: OR Gate and Its Truth Table

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 Digital Circuit Design

The following relationships can be easily derived from this circuit:

A+Ā = 1
A+A = A
0+A = A
1+A = 1
(A+B)+C=A+(B+C)=A+B+C

3] NOT gate :

The NOT gate is an electronic circuit that produces an inverted version of the input at its output.
It is also known as an inverter. If the input variable is A, the inverted output is known as NOT A.
This is also shown as A', or A with a bar over the top, as shown at the outputs. The diagrams
below show two ways that the NAND logic gate can be configured to produce a NOT gate

Fig.2.4: NOT Gate and Its Truth Table

It can also be done using NAND logic gates in the same way.

Fig.2.5: NOT Gate using NAND

4] NAND gate:

This is a NOT-AND gate which is equal to an AND gate followed by a NOT gate. The outputs of
all NAND gates are high if any of the inputs are low. The symbol is an AND gate with a small
circle on the output. The small circle represents inversion.

Fig.2.6: NAND Gate and Its Truth Table

5] NOR gate:

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 Digital Circuit Design

NOT-OR gate which is equal to an OR gate followed by a NOT gate. The outputs of all NOR gates
are low if any of the inputs are high. The symbol is an OR gate with a small circle on the output.
The small circle represents inversion

Fig.2.7: NOR Gate and Its Truth Table

6] EXOR gate:
The 'Exclusive-OR' gate is a circuit which will give a high output if either, but not both, of its two
inputs are high. An encircled plus sign ( ) is used to show the EOR operation.

Fig.2.8: EXOR Gate and Its Truth Table

7] EXNOR gate:
The 'Exclusive-NOR' gate circuit does the opposite to the EOR gate. It will give a low output if
either, but not both, of its two inputs are high. The symbol is an EXOR gate with a small circle on
the output. The small circle represents inversion.

Fig.2.9: EXNOR Gate and Its Truth Table

The NAND and NOR gates are called universal functions since with either one the AND and OR
functions and NOT can be generated.

2.8.2 Realization using NAND gates

NOT

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 Digital Circuit Design

OR The following statements are called DeMorgan's Theorems and can be easily verified and
extended for more than two variables.

In general:

Thus :

Now it is easy to see that , which can be checked from the truth table easily.
The resulting realization of OR gate is shown in fig.

AND gate

X-OR gate

Clearly, this can be implemented using AND, NOT and OR gates, and hence can be implemented
using universal gates.

X-NOR gate

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 Digital Circuit Design

Again, this can be implemented using AND, NOT and OR gates, and hence can be implemented
using universal gates, i.e., NAND or NOR gates.

2.8.3 Realization using NOR gates

A NOR gate is a universal gate, meaning that any other gate can be represented as a
combination of NOR gates.
NOT[edit]
This is made by joining the inputs of a NOR gate. As a NOR gate is equivalent to an OR gate
leading to NOT gate, this automatically sees to the "OR" part of the NOR gate, eliminating it
from consideration and leaving only the NOT part.
output= NOT(A+A)
Desired Gate NOR Construction

Truth Table
Input A Output Q
0 1
1 0
OR
The OR gate is simply one NOR gate followed by a second whose inputs are joined.
Output= NOT[NOT(A+B)+NOT(A+B)]
Desired Gate NOR Construction

Truth Table
Input A Input B Output Q
0 0 0
0 1 1
1 0 1
1 1 1

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 Digital Circuit Design

AND
An AND gate gives a 1 output when both inputs are 1; a NOR gate gives a 1 output only when
both inputs are 0. Therefore, an AND gate is made by inverting the inputs of a NOR gate.
Desired Gate NOR Construction

Truth Table
Input A Input B Output Q
0 0 0
0 1 0
1 0 0
1 1 1
NAND
A NAND gate is made using an AND gate in series with a NOT gate:
Desired Gate NOR Construction

Truth Table
Input A Input B Output Q
0 0 1
0 1 1
1 0 1
1 1 0
XOR
An XOR gate is made by connecting the output of 3 NOR gates (connected as an AND gate) and
the output of a NOR gate to the respective inputs of a NOR gate. This expresses the logical
formula (A AND B) NOR (A NOR B). This construction entails a propagation delay three times
that of a single NOR gate.

Desired Gate NOR Construction

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 Digital Circuit Design

Truth Table
Input A Input B Output Q
0 0 0
0 1 1
1 0 1
1 1 0
XNOR
An XNOR gate can be constructed from four NOR gates implementing the expression "(A NOR N)
NOR (B NOR N) where N = A NOR B".This construction has a propagation delay three times that
of a single NOR gate, and uses more gates.
Desired XNOR Gate NOR Construction

Truth Table
Input A Input B Output Q
0 0 1
0 1 0
1 0 0
1 1 1

Logic gates representation using the Truth table:

Fig.2.10: Logic Gate Representation using the Truth Table

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 Digital Circuit Design

2.8.4 Elements of Boolean Algebra:

A symbolic binary logic expression consists of binary variables and the operators AND, OR and
NOT (e.g.A +B•C ). The possible values for any Boolean expression can be tabulated in a truth
table.

Boolean algebra expressions can be implemented by interconnection of AND gates, OR gates,

and inverters.

Fig.2.11: Implementation by AND –OR gate

As can be seen, the number of simple gates needed to implement an expression is equal to the
number of operations in the Boolean expression. We could use the rules of Boolean Algebra or
Karnaugh Maps to simplify a given Boolean expression. This would allow the given expression to
be implemented using less number of gates.
Basic Laws of Boolean Algebra:
Some of the basic rules of Boolean algebra that may be used to simplify the Boolean expressions
are shown below.
These rules may be proved using the truth tables. Essentially, we consider all combinations of
inputs and show that in all cases the LHS expression and RHS expression lead to the same result.
Such a method of proving logi cal equations is known as proof by perfect induction.

Fig.2.12: Rules of Boolean Algebra

De Morgan's Laws:

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 Digital Circuit Design

These laws are very useful in simplifying Boolean expressions. According to De Morgan's
theorem:

Notice that the De Morgan's Laws give the link between the OR operation and the AND
operation. Application of De Morgan's theorem makes it easy to design logic circuits using NAND
and NOR logic gates which we will soon
see.

Because of the above relationships, any logical function can be implemented by using only
1)AND and NOT gatesor 2)OR and NOT gates.
Thus an OR gate can be implemented with AND and NOT gates as shown below

Fig.2.13:De Morgan’s Law

Universality of NAND and NOR Gates:

Universality of NAND Gates:

NAND gates can be used to implement the functions of both a NOT gate and an AND gate

Fig.2.14: Universality of NAND Gates

Thus, any given logic function can be implemented by using NAND gates alone. For this reason,
NAND gate is said to be logically complete.

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 Digital Circuit Design

Universality of NOR Gates

Likewise, it can be shown that any logic function can be implemented using NOR gates alone.
This is so because NOR gates can be used to implement the functions of both a NOT gate and an
OR gate.

Fig. 2.15: Universality of NOR Gates

A NOR gate is functionally complete because AND, OR, and NOT gates can be implemented
using NOR gates alone.

2.8.5 Designing Logic Circuits:

In designing digital circuits, the designer often begins with a truth table describing what the
circuit should do. The design task is to determine what type of circuit will perform the function
described in the truth table. Although, it may not always be obvious what kind of logic circuit
would satisfy the truth table, two simple methods for designing such a circuit are found in
standard form of Boolean expression called the Sum-Of-Products (or SOP) form and Product-Of-
Sums (or POS) forms. Based on the description of the problem, natural language is first
translated into a truth table and Boolean expressions are found methodically using one of these
two methods. The Boolean expression is then simplified using rules of Boolean algebra or
Karnaugh Maps (which we will study later), so that it can be implemented using minimum
number of logic gates for practical implementation.

Sum-of-Products Implementation:
As you might suspect, a Sum-Of-Products Boolean expression is literally a set of Boolean terms
added (summed) together, each term being a multiplicative (product) combination of Boolean
variables.
(Sum-of-products-expression) = (term) + (term) ... + (term)

Product terms that include all of the input variables (or their inverses) are called minterms. In a
sum-of-products expression, we form a product of all the input variables (or their inverses) for
each row of the truth table for which the result is logic 1. The output is the logical “sum” of
these minterms

Sum-Of-Products expressions are easy to generate from truth tables as shown in the example
below, by determining which rows of the table have an output of 1, writing one product term

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 Digital Circuit Design

for each row, and finally summing all the product terms. This creates a Boolean expression
representing the truth table as a whole.
Sum-Of-Products expressions lend themselves well to implementation as a set of AND gates
(products) feeding into a single OR gate (sum).
Example : Obtain W from the truth table in the Sum Of Products (SOP) form. Draw the logical
circuit to implement it.

Using this method, the resulting Boolean expression and its circuit implementation are shown
below.

Fig.2.16: Sum Of Products (SOP) form.

Product-of-Sums Implementation:
An alternative to generating a Sum-Of-Products expression to account for all the "high" (1)
output conditions in the truth table is to generate a Product-Of-Sums, or POS, expression, to
account for all the "low" (0) output conditions instead. POS Boolean expressions can be
generated from truth tables quite easily, by determining which rows of the table have an output
of 0, writing one sum term for each row, and finally multiplying all the sum terms. This creates a

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 Digital Circuit Design

Boolean expression representing the truth table as a whole. These “sum” terms that include all
of the input variables (or their inverses) are called maxterms. For POS implementation, the
output variable is the logical product of maxterms.
Product-Of-Sums expressions lend themselves well to implementation as a set of OR gates
(sums) feeding into a single AND gate (product).
Example: Find Z in terms of A, B and C in product-of-sum (POS) form from the following truth
table.

.
To begin, we identify which rows in the last truth table column have "low" (0) outputs, and write
a Boolean sum term that would equal 0 for that row's input conditions. For instance, in the fifth
row of the truth table, where A=1,B=0, and C=0, the sum term would be (Ā + B + C), since that
term would have a value of 0 if and only if Ā =0,B=0, and C=0. Similarly, max terms for the 6th
and 7th row can be found. The completed Product-Of-Sums expression, of course, is the
multiplicative combination of these three sum terms

Whereas a Sum-Of-Products expression could be implemented in the form of a set of AND gates
with their outputs connecting to a single OR gate, a Product-Of-Sums expression can be
implemented as a set of OR gates feeding into a single AND gate.

2.8.6 Karnaugh Maps:

From the previous examples we can see that rules of Boolean algebra can be applied in order to
simplify expressions. Apart from being laborious (and requiring us to remember all the laws) this
method can lead to solutions which, though they appear minimal, are not. The Karnaugh map
provides a simple and straight-forward method of minimizing Boolean expressions. With the
Karnaugh map Boolean expressions having up to four and even six variables can be simplified

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 Digital Circuit Design

easily. The simplified logical expression is then used so that minimum hardware is employed in
the implementation of logical circuits.
A Karnaugh map provides a pictorial method of grouping together expressions with common
factors and therefore eliminating unwanted variables. The values inside the squares are copied
from the output column of the truth table, therefore there is one square in the map for every
row in the truth table. Around the edge of the Karnaugh map are the values of the two input
variable, A is along the top and B is down the left hand side. The diagram below explains this.
Karnaugh maps: Complete Simplification Process
1. Draw out the pattern of output 1’s and 0’s in a matrix of input values
2. Construct the K map and place 1s and 0s in the squares according to the truth table.
3. Group the isolated 1s which are not adjacent to any other 1s. (single loops)
4. Group any pair which contains a 1 adjacent to only one other 1. (double loops)
5. Group any quad that contains one or more 1s that have not already been grouped, making
sure to use the minimum number of groups.
6. Group any pairs necessary to include any 1s that have not yet been grouped, making sure to
use the minimum number of groups.
7. Form the OR sum of all the terms generated by each group.
Compared to the algebraic method, the K-map process is a more orderly process requiring fewer
steps and always producing a minimum expression. It must be noted that the minimum
expression is generally NOT unique.
Boolean Expressions in Two Variables:
Consider the following truth table.

The logical expression X is given by

The Karnaugh map of the above truth table is shown in the following figure Fig 1.31. The values
inside the squares are copied from the output column of the truth table, therefore there is one
square in the map for every row in the truth table. Around the edge of the Karnaugh map are
the values of the two input variable A and B and their inverses.
In other words, we may say that Karnaugh map is a graphical representation of the truth table

. Fig.2.17: K Map of Two Variables

Consider the logical expression

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 Digital Circuit Design

Its Karnaugh map is shown below. The two adjacent squares may be combined together as
shown by the loop

Fig.2.18: K Map of Two Variables

Referring to the map above, the two adjacent 1's are grouped together. Through inspection it
can be seen that variable A has its true and false form within the group. This eliminates variable
A leaving only variable B which only has its true form. The minimized answer therefore is Y = B.
It simply means that we are combining the two terms of the above expression Y as shown

below:

Boolean Expressions in Three Variables:

Consider the following truth table.

The corresponding Boolean expression using SOP is

Figure below shows the Karnaugh map of the above truth table. The expression X may be
simplified by combining two adjacent squares as shown

Fig.2.19: K Map of Three Variables

The simplified expression of X is:

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 Digital Circuit Design

Now, consider another expression Y given below:

The Karnaugh map of Y is shown below. In this case, we are able to combine four adjacent
squares. Note that

Fig.2.20: K Map of Three Variables

Y can also be obtained as

Therefore, we can conclude that combining four

adjacent squares in Karnaugh map eliminates two variables from the resulting Boolean
expression of the corresponding squares.

Boolean Expressions in Four Variables:

Knowing how to generate Gray code should allow us to build larger maps. Actually, all we need
to do is look at the left to right sequence across the top of the 3-variable map, follow a similar
sequence for the other two variables and write it down on the left side of the 4-variable map.
Karnaugh map of four variables A, B, C and D is shown in the following figure. As we have shown
in the previous
examples, we may easily prove that:
Combining eight adjacent squares in Karnaugh map eliminates three variables from the
resulting Boolean expression of the corresponding squares.

Fig.2.21: K Map of Four Variables

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 Digital Circuit Design

Example: Simplify the Boolean expression:

Karnaugh map of X is shown in Figure 1.35. As we could combine 4 adjacent squares as shown
below, the simplified expression should be independent of two variables. Adjacent squares in a
row suggest that the resultant expression should be independent of B. Similarly, adjacent
squares in a column suggest that it should also be independent of C. Hence, the simplified
expression of X is given by:

Fig.2.22: K Map of Four Variables

Example: Simplify the following Boolean expression using Karnaugh map.

Solution: Karnaugh map of Y is shown below. There are four loops enclosing 4-adjacent squares.
First, consider the loop 1. The resulting expression for these squares should be independent of C
and D. Next, consider loop 2. The resulting expression of these squares should be independent
of B and D. Thirdly, consider loop 3. The resulting expression of these squares should be
independent of B and C. Finally, consider loop 4.

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 Digital Circuit Design

Fig.2.23: K Map of Four Variables

The resulting expression of these squares should be independent of A and B. Hence, we get

Note: Reductions could be done with Boolean algebra. However, the Karnaugh map is faster
and easier, especially if there are many logic reductions to do.
Elimination of the redundant group:
If all the 1’s in a group are already involved in some other groups then that group is called as a
redundant group.
A redundant group has to be eliminated ,because it increases the number of gates required.

2.8.7 Quine Mc Cluskey Method

The tabular method which is also known as the Quine-McCluskey method is particularly useful
when minimising functions having a large number of variables, e.g. The six-variable functions.
Computer programs have been developed employing this algorithm. The method reduces a
function in standard sum of products form to a set of prime implicants from which as many
variables are eliminated as possible. These prime implicantsare then examined to see if some
are redundant.
The tabular method makes repeated use of the law A + = 1. Note that Binary notation is used
for the function, although decimal notation is also used for the functions. As usual a variable in
true form is denoted by 1, in inverted form by 0, and the abscence of a variable by a dash ( - ).

Rules of Tabular Method

Consider a function of three variables f(A, B, C):

Consider the function:

Listing the two minterms shows they can be

combined
Now consider the following:

Note that these variables cannot be

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 Digital Circuit Design

combined
This is because the FIRST RULE of the Tabular method for two terms to combine, and thus
eliminate one variable, is that they must differ in only one digit position.

Bear in mind that when two terms are combined, one of the combined terms has one digit more
at logic 1 than the other combined term. This indicates that the number of 1's in a term is
significant and is referred to as its index.

For example: f(A, B, C, D)

0000...................Index 0
0010, 1000.............Index 1
1010, 0011, 1001.......Index 2
1110, 1011.............Index 3
1111...................Index 4

The necessary condition for combining two terms is that the indices of the two terms must differ
by one logic variable which must also be the same.

Example 1:

Consider the function: Z = f(A,B,C) = + C+A +A C

To make things easier, change the function into binary notation with index value and decimal
value.

Tabulate the index groups in a colunm and insert the decimal value alongside.

From the first list, we combine terms that differ by 1 digit only from one index group to the next.
These terms from the first list are then seperated into groups in the second list. Note that the

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 Digital Circuit Design

ticks are just there to show that one term has been combined with another term. From the
second list we can see that the expression is now reduced to: Z = + + C+A

From the second list note that the term having an index of 0 can be combined with the terms of
index 1. Bear in mind that the dash indicates a missing variable and must line up in order to get
a third list. The final simplified expression is: Z =

Bear in mind that any unticked terms in any list must be included in the final expression (none
occured here except from the last list). Note that the only prime implicant here is Z = .

The tabular method reduces the function to a set of prime implicants.

Note that the above solution can be derived algebracially. Attempt this in your notes.

Example 2:

Consider the function f(A, B, C, D) = (0,1,2,3,5,7,8,10,12,13,15), note that this is in decimal

form.

(0000,0001,0010,0011,0101,0111,1000,1010,1100,1101,1111) in binary form.

(0,1,1,2,2,3,1,2,2,3,4) in the index form.

The prime implicants are: + + D + BD + A + AB

The chart is used to remove redundant prime implicants. A grid is prepared having all the prime
implicants listed at the left and all the minterms of the function along the top. Each minterm
covered by a given prime implicant is marked in the appropriate position.

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 Digital Circuit Design

From the above chart, BD is an essential prime implicant. It is the only prime implicant that
covers the minterm decimal 15 and it also includes 5, 7 and 13. is also an essential prime
implicant. It is the only prime implicant that covers the minterm denoted by decimal 10 and it
also includes the terms 0, 2 and 8. The other minterms of the function are 1, 3 and 12. Minterm
1 is present in and D. Similarly for minterm 3. We can therefore use either of these prime
implicants for these minterms. Minterm 12 is present in A and AB , so again either can be
used.Thus, one minimal solution is: Z = + BD + +A

2.9 Objective Questions

1. State De Morgans Law.
2. List the different Basic, universal and Derived gates.
3. State the different Boolean Laws.

2.10 Short Questions

1. Draw the logic diagram for Boolean expression
A] Y=A’B’+B(A+C) B]Y=BC+AC’ C]Y=A+CD D]Y=(A+B)(C’+D)
2. K map for simplification
a]F(w,x,y,z)=∑m(0,2,4,6,7,8,10,13,15) b]F(A,B,C,D)=∑m(0,2,3,5,7,8,10,11,14,15)
c]F(A,B,C,D)=∑m(1,3,4,5,10,11,12,13,14,15)
3. Demonstrate the Digital logic gates with their algebraic function &truth table ;state the use of
positive logic and negative logic

2.11 Long Questions

1. Show that the dual of Ex-OR gate is equal to its complement
2. Draw the logic diagram using only two input NAND gate to implement the following expression
(AB+A’B’)(CD’+C’D)
3. Simplify the following function with three variable maps
[a]xy+x’y’z’+x’yz’
[b]x’y’+yz+x’yz’
[c]A’B+BC’+B’C’
4. Implement following Boolean function F together with don’t care condition `d’ using no more than
two NOR gate F(A,B,C,D)=∑m(0,1,2,9,11) d=(A,B,C,D)=∑(8,10,14,15)

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 Digital Circuit Design

CHAPTER-3
Combinational Logic Circuits and Hazards

2.1 Motivation:
This chapter deals with combinational circuits. It also deals with combinational logic design using
MSI circuits, which is important for the design of digital digital systems considering the simplicity in
design, cost, space, power requirement and other factors.

3.2. Syllabus: -
Sr. No Topic Fine Detailing No of Week Self
Hours Study

03 Combinational Arithmetic Circuits: Adders/Subtractors:Half 12 3 25

Logic Circuits adder, Full adder, Half Subtractor, Full
and Hazards Subtractor, Ripple carry adder, Carry Look
ahead adder and BCD adder, Magnitude
Comparator
Multiplexer and De-multiplexer:
Multiplexer, cascading of Multiplexer,
Boolean Function implementation using
single multiplexer and basic gates, De-
multiplexer, encoder and decoder, Parity
Circuits, ALU
Hazards: Timing hazards static and dynamic
3.3. Books Recommended:
1. Morris Mano, Digital Design, Pearson Education, Asia 2002.
2. R.P.Jain, Modern Digital Electronics, Tata McGraw Hill Education, Third Edition 2003.
3. John F. Wakerly, Digital Design Principles and Practices, Pearson Education, Fourth
Edition, 2008.

3.4. Weightage in University Examination: 30-40 Marks

3.5. Objectives:
• To list the different conmbinational circuits.
• To teach the working of combinational circuits and their applications.

3.6 Key Notations:

MUX – Multiplexer

DEMUX - Demultiplexer

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 Digital Circuit Design

3.7 Key Definitions:

Combinational Circuit - A circuit whose output depends on present input

Multiplexer: A device that selects one of several analog or digital input signals and forwards the
selected input into a single line.
Demultiplexer : A device that takes a single input line and routes it to one of several digital output
lines

3.8.1 Introduction:
Combinational logic circuits (circuits without a memory): Combinational switching networks whose
outputs depend only on the current inputs.
A combinational circuit consists of input variables, logic gates and output variables. The logic gates
accept signals from the input variables and generate output signals. This process transforms binary
information from the given input data to the required output data. Figure 3.1 shows the block
diagram of a combinational circuit. As shown in the figure the combinational circuit accepts n input
binary variables and generates m output variables depending on the logical combination of gates

Fig. 3.1 Combinational logic circuits

Most important standard combinational circuits are:
• Adders
• Subtractors
• Comparators
• Decoders
• Encoders
• Multiplexers
Available in IC’s as MSI and used as standard cells in complex VLSI (ASIC)

Classification of Combinational Logic shown in fig.3.2

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 Digital Circuit Design

Fig.3.2 Classification of Combinational Logic

One of the most common uses of combinational logic is in Multiplexer and De-multiplexer type
circuits. Here, multiple inputs or outputs are connected to a common signal line and logic gates
are used to decode an address to select a single data input or output switch. A multiplexer
consist of two separate components, a logic decoder and some solid state switches, but before
we can discuss multiplexers, decoders and de-multiplexers in more detail we first need to
understand how these devices use these "solid state switches" in their design

DESIGN OF COMBINATIONAL LOGIC

1. From the specifications of the circuit, determine the number of inputs and outputs
2. Derive the truth table that defines the relationship between the input and the output.
3. Obtain the simplified Boolean function using x-variable K-Map.
4. Draw the logic diagram and verify the correctness of the design

Half Adder
Half adder is a combinational logic circuit which is used to add two bits at a time and gives two
Outputs sum(s) and carry (c) Let A and B are two input variables.
Half adder is a logic circuit that finds the arithmetic sum of two binary digits at a time. Its logic
circuit is shown in Figure 3.3

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 Digital Circuit Design

Fig.3.3 Half Adder

The outputs of the XOR and AND gates produces the sum and carry respectively

Fig.3.4: (a)K Map for Sum S (b)K Map for Carry C

The input variables of half adder are augend and addend. The output variables are sum and
carry. It is necessary to specify two output variables, because the sum of 1+1=10. Let A & B
be input variables SUM and CARRY be output variables.
The output ‘CARRY’ represents an AND function. The output SUM represents exclusive OR
function. The Boolean functions of the two outputs are
SUM = A B and CARRY = A . B

Full Adder
When two binary numbers are added a carry may be generated onto the subsequent bit
positions. Hence, it is required to add three bits for the subsequent additions. A
combinational circuit that finds the arithmetic sum of three bits is called a Full adder. A Full
adder can be constructed using two half adders and an OR gate as shown in the Figure 3.5.

Fig.3.5 Full Adder

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 Digital Circuit Design

Thus a full-adder is a combinational circuit that performs the arithmetic sum of three input bits.
It consists of three inputs and two outputs. Two of the input variables denoted by A, B
represents the two significant bits to be added. The third input C represents the carry from the
lower significant position. The two outputs are denoted by SUM and CARRY. The Boolean
expressions for SUM and CARRY outputs are given below

Half Subtractor:
A Half subtractor is a combinational logic circuit which is used to find the difference between
two binary digits. Its logic circuit is shown in Figure 3.6
A half-subtractor has two inputs and two outputs. Let the input variables minuend and
subtrahend be designated as A and B respectively, and output functions be designated as D for
difference and B for borrow. The truth table of the functions is as follows

Fig. 3.6 Half Subtractor & Truth Table

Map for DIFFERENCE Map for BORROW

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 Digital Circuit Design

DIFFERENCE = A'B + AB' BORROW = A'B

= A B
Fig. 3.7 Half Subtractor K map for Difference &Borrow
A half subtractor consists of two input variables A and B (minuend and subtrahend) and two
output variables DIFFERENCE and BORROW. The DIFFERENCE output is obtained by a 2-
input XOR gate. The BORROW output is obtained by the expression A'B
Hence DIFFERENCE = A B BORROW = A'B

Full Subtractor:
A full subtractor Figure 3.8 is a combinational circuit that performs a subtraction between
two bits taking into account that a 1 may have been borrowed by a lower significant stage.
A combinational circuit of full-subtractor performs the operation of subtraction of three bits—
the minuend, subtrahend, and borrow generated from the subtraction operation of previous
significant digits and produces the outputs difference and borrow.

Fig.3.8 Full Subtractor

This circuit has three inputs and two outputs. The three inputs A, B and C denote the
minuend, subtrahend and previous borrow respectively. The two outputs DIFFERENCE and
BORROW represent the difference and borrow, respectively. The truth table for the circuit is
as follows.

6
 Digital Circuit Design

A B C D BOROUT
BORIN

0 0 0 0 0
0 0 1 1 1
0 1 0 1 0
0 1 1 0 0
1 0 0 1 1
1 0 1 0 1
1 1 0 0 0
1 1 1 1 1

Fig. 3.9 Full Subtractor Truth Table

The Boolean functions for the two outputs of the full subtractor are derived in the K-map
as shown below.

Map for BORROW Map for DIFFERENCE

BORROW = A'C + A'B + B

Fig.3.10 Full Subtractor K Map for Borrow & Difference

7
 Digital Circuit Design

The Multiplexer:
A data selector, more commonly called a Multiplexer, shortened to "Mux" or "MPX", are
combinational logic switching devices that operate like a very fast acting multiple position rotary
switch. They connect or control, multiple input lines called "channels" consisting of either 2, 4, 8
or 16 individual inputs, one at a time to an output.

Then the job of a "multiplexer" is to allow multiple signals to share a single common output. For
example, a single 8-channel multiplexer would connect one of its eight inputs to the single data
output. Multiplexers are used as one method of reducing the number of logic gates required in a
circuit or when a single data line is required to carry two or more different digital signals.

Digital Multiplexers are constructed from individual analogue switches encased in a single IC
package as opposed to the "mechanical" type selectors such as normal conventional switches
and relays. Generally, multiplexers have an even number of data inputs, usually an even power
of two, n2 , a number of "control" inputs that correspond with the number of data inputs and
according to the binary condition of these control inputs, the appropriate data input is
connected directly to the output. An example of a Multiplexer configuration is shown below.

Fig.3.11 [a]4-to-1 Channel Multiplexer[b]4 Channel Multiplexer using Logic Gates

[c]Multiplexer Symbol

8
 Digital Circuit Design

Fig.3.12 [d]4-to-2 Channel Multiplexer

Here in this example the 4 input channels are switched to 2 individual output lines but larger
arrangements are also possible. This simple 4 to 2 configuration could be used for example, to
switch audio signals for stereo pre-amplifiers or mixers.

The Multiplexer is a very useful combinational device that has its uses in many different
applications such as signal routing, data communications and data bus control. When used with
a demultiplexer, parallel data can be transmitted in serial form via a single data link such as a
fibre-optic cable or telephone line. They can also be used to switch either analogue, digital or
video signals, with the switching current in analogue power circuits limited to below 10mA to
20mA per channel in order to reduce heat dissipation.
It is possible to make simple multiplexer circuits from standard AND and OR gates as we have
seen above, but commonly multiplexers/data selectors are available as standard I.C. packages
such as the common TTL 74LS151 8-input to 1 line multiplexer or the TTL 74LS153 Dual 4-input
to 1 line multiplexer. Multiplexer circuits with much higher number of inputs can be obtained by
cascading together two or more smaller devices.

Digital multiplexers are sometimes also referred to as "Data Selectors" as they select the data to
be sent to the output line and are commonly used in communications or high speed network
switching circuits such as LAN´s and Ethernet applications. Some multiplexer IC´s have a single
inverting buffer (NOT Gate) connected to the output to give a positive logic output (logic "1",
HIGH) on one terminal and a complimentary negative logic output (logic "0", LOW) on another
different terminal.
MUX IC:

9
 Digital Circuit Design

Fig.3.13: MSI -IC-74151(8:1)MUX

A strobe control ‘ E’ ’ acts as an enable signal. The function table specifies the value of output ‘Y’
as function of the selection lines. Output ‘ Y’ ’ is the complement of ‘Y’. for proper operation, the
strobe input ‘ E’ ’ must be connected to ground.

.
Fig.3.14:MSI -IC-74151(8:1)MUX-Functional Table

Multiplexer is a combinational ckt. that is one of the most widely used in digital design. The
multiplexer is a data selector which gates one out of several i/ps to a single o/p. It has n data
i/ps & one o/p line & m select lines where 2m = n. Depending upon the digital code applied
at the select inputs one out of n data input is selected & transmitted to a single o/p channel.
Normally strobe(G) input is incorporated which is generally active low which enables the
multiplexer when it is LOW. Strobe i/p helps in cascading no. of ICs that are available such as
74157, 74158(Quad 2:1 mux), 74352, 74153 (dual 4:1 Mux.), 74151A, 74152 (8:1 Mux.),
74150 (16:1 Mux). IC 74151A is a 8 : 1 multiplexer which provides two complementary o/ps
Y & Y´. The o/p Y is same as the selected i/p & Y´ is its complement. Then any multiplexer
can be used to realize any m variable function. (2m= n, m is no. of select inputs).

The Demultiplexer:

The data distributor, known more commonly as a Demultiplexer or "Demux", is the exact
opposite of the Multiplexer. The demultiplexer takes one single input data line and then

10
 Digital Circuit Design

switches it to any one of a number of individual output lines one at a time. The
demultiplexer converts a serial data signal at the input to a parallel data at its output lines
as shown below.

Fig.3.15: [a]1-to-4 Channel De-multiplexer[b] 4 Channel Demultiplexer using Logic Gate [c]
Demultiplexer Symbol

Standard Demultiplexer IC packages available are the TTL 74LS138 1 to 8-output demultiplexer,
the TTL 74LS139 Dual 1-to-4 output demultiplexer or the CMOS CD4514 1-to-16 output
demultiplexer. Another type of demultiplexer is the 24-pin, 74LS154 which is a 4-bit to 16-line
demultiplexer/decoder. Here the individual output positions are selected using a 4-bit binary
coded input. Like multiplexers, demultiplexers can also be cascaded together to form higher
order demultiplexers.

Unlike multiplexers which convert data from a single data line to multiple lines and
demultiplexers which convert multiple lines to a single data line, there are devices available
which convert data to and from multiple lines and in the next tutorial about combinational logic
devices, we will look at Encoders which convert multiple input lines into multiple output lines,
converting the data from one form to another.

Demultiplex means one into many. Input and many outputs. By applying control signals, we can
steer the input signal to one of the output lines. The block diagram of a simple is as shown below:

11
 Digital Circuit Design

A0–A2 Address Inputs, E1–E2 Enable Inputs,E3 Enable Input,O0–O7(Y0-Y-7) Outputs

Fig.3.16:MSI -IC-74138(1:8)DE-MUX

Functional Table:

Fig.3.17:MSI -IC-74138(1:8)DE-MUX-Functional Table

Demux takes single i/p & distributes it over several o/ps. It has one data line, n o/p lines & m
select lines where 2 m = n. MSI ICs available in TTL family for demux. are 74138(3 line to 8
line decoder/demux.), 74139(dual 2 to 4 line decoder/driver.), 74154(4 to 16 line decoder/
demux), 74155(dual 2 to 4 line decoder) etc. IC 74155 is a dual 2 to 4 line decoder. It has
two sets of active low outputs1Y0 to 1Y3 & 2Y0 to 2Y3. A & B are the select terminals
common for both the demux. C1, C2 & G1, G2 are the data lines& strobe (enable) inputs for
the two demux. C1 is active high, C2,G1, G2 are active low. The two 2 line to 4 line demux.
can be combined to implement 3 line to 8 line demux.

The Magnitude Comparator:

Magnitude Comparator compares two binary data signals A & B and generates the results of
comparison in form of three output signals A>B, A=B, A<B. IC 7485 is a 4-bit comparator.
The cascade inputs A>B, A=B, A<B can be used to construct a comparator comparing more
than 4 bits. The compare outputs depend on both compare i/ps as well as cascade i/ps.

12
 Digital Circuit Design

Fig.3.18 : (a)Comparator using Ex-OR gate(b)7485 TTL 4-bit comparator Pin Diagram

Fig.3.19: IC7485 TTL 4-bit comparator logic symbols

The truth table :- The action of the entries A > B, A < B and A = B.

13
 Digital Circuit Design

Fig.3.20: IC7485 TTL 4-bit comparator truth table

1. If it is wished that the exit A = B pass to state 1 each time the two binary numbers are
equal, it is enough to carry the entry A = B to state 1, the state of entries A < B and A > B
not having then importance.
2. If it is wished that the exit A > B also pass to state 1 if the two binary numbers are equal,
it is enough to carry the entry A > B to state 1 and to carry the entries A < B and A = B to
state 0.
3. In this configuration of the state of the entries A > B, A < B and A = B, exit A > B is with
state 1 when binary number A is higher than the binary number B or when these two
numbers are equal. It thus indicates if A > B.
4. In the same way, while carrying entry A < B with state 1 and entries A > B and A = B with
state 0, the exit A < B indicates binary number A is lower or equal to the binary number
B.

Decoders:
A decoder is a logic circuit that reads a binary value represented on a set of inputs and
activates one of the outputs that corresponds to the binary value. For N inputs there will be
2N outputs. Only one output can be active at any given time
Decoder vs. DEMUX
3-8 decoder: 3 data inputs, 8 outputs
1-8 DEMUX: 1 data input, 3 control inputs, 8 outputs
Add enable control bit to decoder:
e = 0: all outputs are 0
e = 1: behaves like regular decoder

14
 Digital Circuit Design

Data inputs of a decoder correspond to the control bits of a DEMUX

Enable input of a decoder corresponds to the data bit of a DEMUX

Fig.3.21: IC74138 as Decoder

Fig.3.22: IC74138 as Decoder- Internal Diagram &Truth Table

Features:

1. Demultiplexing capability
2. Multiple input enable for easy expansion
3. Complies with JEDEC standard no. 7A
4. ideal for memory chip select decoding
5. Active LOW mutually exclusive outputs
6. ESD protection:
HBM EIA/JESD22-A114F exceeds 2000 V
MM EIA/JESD22-A115-A exceeds 200 V
7. Multiple package options
8. Specified from −40 C to +85 C and from −40 C to +125 C

Encoders:
An encoder is a logic circuit that produces a binary value output based upon the active input
(s). For 2N inputs there will be N outputs. A standard encoder circuit allows one input to be
active at a time. Priority encoders allow multiple inputs to be activated and will generate an
output code based upon the highest numbered input.

15
 Digital Circuit Design
for example. Here, we could use an 8-to-3 Encoder. The 74HC148 encoder is one chip that will do
the trick

Fig.3.23:IC74148 as Encoder
Here, inputs 0-7 are the input signals -- again, these are Active-LOW. The chip encodes the input
into a 3digit output, A0 (1's bit), A1 (2's bit), and A3 (4's bit).
EI enables the inputs. When it is LOW, the chip works properly. When it's HIGH, all outputs
are set to HIGH regardless of the input. EO and GS are outputs that we can ignore for now.
The encoder and decoder chips allow us to maximize the use of inputs and outputs. Since
the RCX has only 3 of each, it's handy to be able to get more than 3 pieces of information
back and forth at any one time.

3.9 Objective Questions

Q.1] Implement following function using 4:1MUX with active low strobe (E=0) in put
F(A,B,C,D)=∑M(2,3,5,7,9,12,13,14,15)
Q.2 ] Implement Full Subtractor using decoder IC 74138 and 2 input NAND gate IC7400
Q.3] Compare MUX and DEMUX w.r.to parameters ;write applications of MUX and DEMUX
Q.4] Design 8 bit comparator using IC 7485
Q.5] Implement Full Adder using IC74151(8:1MUX)
Q.6] Compare Encoder and Decoder w.r.to parameters ;write applications of Encoder and
Decoder
3.10 Short Questions
Q.1] What is the difference between a Half Adder & a Full Adder? Implement Full Adder using
Half Adder
Q.2] Implement the following function Using 4:1MUX with active low strobe in put
[1]F(A,B,C,D)=∑(2,3,5,7,8,9,12,13,14,15) [2]implement Full Adder using two 4:1 MUX
Q.3] What is the difference between Half Subtractor &Full Subtractor? Implement Full Subtractor
using Half Subtractor
Q.4] Design the circuit for 4 bit combinational incrementer [circuit adds 4 one to 4 bit binary
number) using 4 Half Adders
Q.5] Design &Explain 8 bit binary Adder Using IC 7483
Q.6] Explain comparator chip IC7485 &working of IC 7485
Q.7] Explain the feature of IC 74138(1:8DE-MUX); Implement the full subtractor using 1:8
DEMUX

16
 Digital Circuit Design

3.11 Long Questions

Q.1] What is the difference between Half Adder & A Full Adder? Implement Full Adder using Half
Adder
Q.2] Implement the following function Using 4:1MUX with active low strobe in put
[1]F(A,B,C,D)=∑(2,3,5,7,8,9,12,13,14,15) [2]implement Full Adder using two 4:1 MUX
Q.3] What is the difference between Half Subtractor &Full Subtractor? Implement Full Subtractor
using Half Subtractor
Q.4] Design the circuit for 4 bit combinational incrementer [circuit adds 4 one to 4 bit binary
number) using 4 Half Adders
Q.5] Design &Explain 8 bit binary Adder Using IC 7483
Q.6] Explain comparator chip IC7485 &working of IC 7485
Q.11] Explain the feature of IC 74138(1:8DE-MUX);Implement the full subtractor using 1:8
DEMUX

17
 Unit III – Combinational Logic Circuits
✓ Standard Boolean representation: Sum of Product (SOP) &
Product of Sum (POS), Maxterm and Minterm , Conversion
between SOP and POS forms, realization using NAND/NOR gates.

✓ K-map reduction technique for the Boolean expression:

Minimization of Boolean functions up to 4 variables (SOP & POS
form)

✓ Design of Airthmetic circuits and code converter using K-map:

Half and Full Adder, Half and Full Subtractor, Gray to Binary Code
Converter and Binary to Gray Code Converter (up to 4 bit).

Module-3 10/17/2024 1
 Design of Gray to Binary Code Converter
Block Diagram:

G3 B3
G2 Gray to Binary B2 Binary
Gray
Inputs G1
Code B1
Outputs
converter B0
G0

Module-3 10/17/2024 2
Design of Gray to Binary Code Converter
Truth Table :
Gray Inputs Binary Outputs Gray Inputs Binary Outputs

G3 G2 G1 G0 B3 B2 B1 B0 G3 G2 G1 G0 B3 B2 B1 B0
0 0 0 0 0 0 0 0 1 0 0 0 1 1 0 0
0 0 0 1 0 0 0 1 1 0 0 1 1 1 0 1

0 0 1 0 0 0 1 1 1 0 1 0 1 1 1 1

0 0 1 1 0 0 1 0 1 0 1 1 1 1 1 0

0 1 0 0 0 1 1 0 1 1 0 0 1 0 1 0

0 1 0 1 0 1 1 1 1 1 0 1 1 0 1 1

0 1 1 0 0 1 0 1 1 1 1 0 1 0 0 1

0 1 1 1 0 1 0 0 1 1 1 1 1 0 0 0
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Design of Gray to Binary Code Converter
K-map for B0: G1G0 G1G0 G1G0 G1G0 G1G0
G 3G 2 00 01 11 10
0 1 3 2
G3G2 00 0 1 0 1
4 5 7 6
GG23 01 1 0 1 0
12 13 15 14
G3G2 11 0 1 0 1
8 9 11 10
G3G2 10 1 0 1 0

B0 = G3G2G1G0 + G3G2G1G0 + G3G2G1G0 + G3G2G1G0

+G3G2G1G0 + G3G2G1G0 + G3G2G1G0 + G3G2G1G0
B0 = G3  G2  G1  G0

Module-3 10/17/2024
Design of Gray to Binary Code Converter
K-map for B1: G1G0 G1G0 G1G0 G1G0 G1G0
G 3G 2 00 01 11 10
0 1 3 2
G3G2 00 0 0 1 1
4 5 7 6
GG23 01 1 1 0 0
12 13 15 14
G3G2 11 0 0 1 1
8 9 11 10
G3G2 10 1 1 0 0

B1 = G3G2G1 + G3G2G1 + G 3 G 2 G 1 + G 3 G 2 G 1

B1 = G 3  G 2  G1

Module-3 10/17/2024
Design of Gray to Binary Code Converter
K-map for B2: G1G0 G1G0 G1G0 G1G0 G1G0
G 3G 2 00 01 11 10
0 1 3 2
G3G2 00 0 0 0 0
4 5 7 6
GG23 01 1 1 1 1
12 13 15 14
G3G2 11 0 0 0 0
8 9 11 10
G3G2 10 1 1 1 1

B2 = G3G2 + G3G2

B1 = G 3  G 2

Module-3 10/17/2024
Design of Gray to Binary Code Converter

K-map for B3: G1G0 G1G0 G1G0 G1G0 G1G0

G 3G 2 00 01 11 10
0 1 3 2
G3G2 00 0 0 0 0
4 5 7 6
GG23 01 0 0 0 0
12 13 15 14
G3G2 11 1 1 1 1
8 9 11 10
G3G2 10 1 1 1 1

B3 = G3

Module-3 10/17/2024
Design of Gray to Binary Code Converter

Logic Diagram:
G3 G2 G1 G0

B3

B2 = G 3  G 2

B1 = G1  G2  G3

B0 = G0  G1  G2  G3

Module-3 10/17/2024
 Unit III – Combinational Logic Circuits
✓ Standard Boolean representation: Sum of Product (SOP) &
Product of Sum (POS), Maxterm and Minterm , Conversion
between SOP and POS forms, realization using NAND/NOR gates.

✓ K-map reduction technique for the Boolean expression:

Minimization of Boolean functions up to 4 variables (SOP & POS
form)

✓ Design of Airthmetic circuits and code converter using K-map:

Half and Full Adder, Half and Full Subtractor, Gray to Binary and
Binary to Gray Code Converter (up to 4 bit).

Module-3 10/17/2024
 Design of Binary to Gray Code Converter

Block Diagram:

B3 G3
B2 Binary to Gray G2
Binary Code Gray
Inputs B1 G1 Outputs
converter
B0 G0

Module-3 10/17/2024
 Design of Binary to Gray Code Converter
Truth Table :
Binary Inputs Gray Outputs Binary Inputs Gray Outputs

B3 B2 B1 B0 G3 G2 G1 G0 B3 B2 B1 B0 G3 G2 G1 G0

0 0 0 0 0 0 0 0 1 0 0 0 1 1 0 0

0 0 0 1 0 0 0 1 1 0 0 1 1 1 0 1

0 0 1 0 0 0 1 1 1 0 1 0 1 1 1 1

0 0 1 1 0 0 1 0 1 0 1 1 1 1 1 0

0 1 0 0 0 1 1 0 1 1 0 0 1 0 1 0

0 1 0 1 0 1 1 1 1 1 0 1 1 0 1 1

0 1 1 0 0 1 0 1 1 1 1 0 1 0 0 1

0 /10/1201
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 Design of Binary to Gray Code Converter

K-map for G0:

B1B0 B1B0 B1B0 B1B0 B1B0

B3B2 00 01 11 10
0 1 3 2
B3B2 00 0 1 0 1
4 5 7 6
B B23 01 0 1 0 1 G0 = B1B0 + B1B0
12 13 15 14
B3B2 11 0 1 0 1 G0 = B0  B1
8 9 11 10
B3B2 10 0 1 0 1

B1B0 B1B0

Module-3 10/17/2024
Design of Binary to Gray Code Converter

K-map for G1:

B1B0 B1B0 B1B0 B1B0 B1B0

B3B2 00 01 11 10
0 1 3 2
B3B2 00 0 0 1 1
4 5 7 6
B B23 01 1 1 0 0 G1 = B2B1 + B2 B1
12 13 15 14
B3B2 11 1 1 0 0 G1 = B2  B1
8 9 11 10
B3B2 10 0 0 1 1

B2B1 B2B1

Module-3 10/17/2024
Design of Binary to Gray Code Converter

K-map for G2:

B1B0 B1B0 B1B0 B1B0 B1B0

B3B2 00 01 11 10
0 1 3 2
B3B2 00 0 0 0 0

G2 = B3B2 + B3B2
4 5 7 6
B B23 01 1 1 1 1
12 13 15 14
B3B2 11 0 0 0 0 G2 = B3  B2
8 9 11 10
B3B2 10 1 1 1 1

B3B2 B3B2

Module-3 10/17/2024
Design of Binary to Gray Code Converter

K-map for G3:

B1B0 B1B0 B1B0 B1B0 B1B0

B3B2 00 01 11 10
0 1 3 2
B3B2 00 0 0 0 0

B B23 01 0
4
0
5
0
7
0
6
G 3 = B3
12 13 15 14
B3B2 11 1 1 1 1
8 9 11 10
B3B2 10 1 1 1 1

B3

Module-3 10/17/2024
Design of Binary to Gray Code Converter

Logic Diagram:
B3 B2 B1 B0

G3

G 2 = B3  B 2

G1 = B2  B1

G0 = B1  B0

Module-3 10/17/2024
IC 7483 4 – Bit Binary Parallel Adder

A Binary number B Binary number

A 3 A 2 A1 A 0 B 3 B 2 B1 B 0

IC 7483 Cin
C0
Carry
Carry
Input
Output

S3 S 2 S1 S0
Sum Output
Module-3 10/17/2024
 Cascading of IC 7483

✓ If we want to add two 8 bit binary numbers using 4 bit binary parallel adder IC 7483,
then we have to cascade the two ICs in following way

Lower nibble of Lower nibble of

Higher nibble of Higher nibble of
A Binary number B Binary number
A Binary number B Binary number
A7 A6 A5 A4 B7 B6 B5 B4 A 3 A 2 A1 A 0 B 3 B 2 B1 B 0

C in C0
C0 IC 7483-II IC 7483-I C in

Carry Carry
Output Input
S7 S6 S5 S4 S3 S 2 S1 S0

Sum Output

Module-3 10/17/2024
Design of 1 Digit BCD Adder
Block Diagram: A BCD no. B BCD no.

C0 IC 7483-I
S 3 S 2 S1 S 0 C in

Logic
Circuit

Add 0110 Command

IC 7483-II
C0 C in

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Design of 1 Digit BCD Adder

As we know BCD addition rules, we understand that the 4

bit BCD adder should consists of following:

✓ A 4 bit binary adder to add the given two (4 bit

numbers).

✓ A combinational logic circuit to check if sum is greater

than 9 or carry 1.

✓ One more 4 bit binary adder to add 0110 to the invalid

BCD sum or if carry is 1
Module-3 10/17/2024
Design of 1 Digit BCD Adder
Logic Table for design of Logic circuit:
Inputs Y Inputs Y

S3 S2 S1 S0 S3 S2 S1 S0

0 0 0 0 0 1 0 0 0 0

0 0 0 1 0 1 0 0 1 0

0 0 1 0 0 1 0 1 0 1

0 0 1 1 0 1 0 1 1 1
Sum is
0 1 0 0 0 1 1 0 0 1 invalid
BCD
0 1 0 1 0 1 1 0 1 1 Number
Y=1
0 1 1 0 0 1 1 1 0 1

0 1 1 1 0 1 1 1 1 1

Module-3 10/17/2024
Design of 1 Digit BCD Adder

K-map for Logic circuit:

S1S0 S1S0 S1S0 S1S0 S1S0

S3s2 00 01 11 10
0 1 3 2
S3S2 00 0 0 0 0
4 5 7 6
S3S2 01 0 0 0 0
12 13 15 14 Y = S 3S 2 + S 3S1
S3S2 11 1 1 1 1
8 9 11 10
S3S2 10 0 0 1 1

S3S2 S1S3

Module-3 10/17/2024
Design of 1 Digit BCD Adder
A BCD no. B BCD no.

Combinational
Logic Circuit
C0 IC 7483-I
S 3 S 2 S1 S 0 C in

Y' Y

C0
IC 7483-II
Not used C in
S3 S 2 S1 S0

Carry output
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BCD Output Sum
4 Bit Binary Parallel Subtractor using IC 7483

A Binary number B Binary number

A 3 A 2 A1 A 0 B 3 B 2 B1 B 0
NOT gates for 1’s
complement of B

Vcc +5V

C0
Carry IC 7483 Cin = 1
Output S3 S 2 S1 S0 It adds 1 to 1’s
complement of B

Difference Output

Module-3 10/17/2024
 IC 7483 as Parallel Adder/Subtractor
B Binary number
B3 B2 B1 B0
A Binary number
M
A 3 A 2 A1 A 0 Mode
Select

C0
Carry IC 7483
C in
Output S3 S 2 S1 S0

Sum or Difference Output Mode Select

M=0 Addition
M=1 Subtraction
Module-3 10/17/2024
 Unit III – Combinational Logic Circuits

✓ Airthmetic Circuits: (IC 7483) Adder & Subtractor, BCD Adder

✓ Encoder/Decoder: Basics of Encoder, decoder, comparison, (IC
7447) BCD to 7- Segment decoder/driver.

✓ Multiplexer and Demultiplexer: Working, truth table and

applications of Multiplexers and Demultiplexers, MUX tree, IC
74151 as MUX, DEMUX tree, DEMUX as decoder, IC 74155 as
DEMUX

✓ Buffer: Tristate logic, Unidirectional and Bidirectional buffer (IC

74LS244 and IC 74LS245)

Module-3 10/17/2024
Multiplexers

✓Multiplexer is a circuit which has a number of

inputs but only one output.

✓Multiplexer is a circuit which transmits large

number of information signals over a single line.

✓Multiplexer is also known as “Data Selector” or

MUX.

Module-3 10/17/2024
Necessity of Multiplexers
✓ In most of the electronic systems, the digital data is
available on more than one lines. It is necessary to route
this data over a single line.
✓ Under such circumstances we require a circuit which
select one of the many inputs at a time.
✓ This circuit is nothing but a multiplexer. Which has many
inputs, one output and some select lines.
✓ Multiplexer improves the reliability of the digital system
because it reduces the number of external wired
connections.
Module-3 10/17/2024
Advantages of Multiplexers

✓It reduces the number of wires.

✓So it reduces the circuit complexity and cost.

✓We can implement many combinational circuits
using Mux.

✓It simplifies the logic design.

✓It does not need the k-map and simplification.

Module-3 10/17/2024
Applications of Multiplexers

✓It is used as a data selector to select one out of

many data inputs.

✓It is used for simplification of logic design.

✓It is used in data acquisition system.

✓In designing the combinational circuits.

✓In D to A converters.

✓To minimize the number of connections.

Module-3 10/17/2024
 Block Diagram of Multiplexer

D0 D0
D1 D1
Data D2 D2
Inputs D3 Y
D3
. n:1 .
. .
. Mux Output .
. . Output
. .
Dn-1 Dn-1
E
Enable Input
. . .. . . ..

Sm-1 S2 S1 s0 Sm-1 S2 S1 s0
Select Lines

Fig. General Block Diagram Fig. Equivalent Circuit

Module-3 10/17/2024
Relation between Data Input Lines & Select Lines

✓In general multiplexer contains , n data lines,

one output line and m select lines.

✓To select n inputs we need m select lines such

that 2m=n.

Module-3 10/17/2024
Types of Multiplexers

✓2:1 Multiplexer

✓4:1 Multiplexer

✓8:1 Multiplexer

✓16:1 Multiplexer

✓32:1 Multiplexer

✓64:1 Multiplexer

and so on…………
Module-3 10/17/2024
 2:1 Multiplexer

Data D0
Inputs 2:1 Y
D1 Block Diagram
Mux
Output
E
Enable Input
s
Select Lines
Enable i/p Select i/p Output
(E) (S) (Y)

0 X 0

Truth Table 1 0 D0

1 1 D1

Module-3 10/17/2024
Realization of 2:1 Mux using gates

S D1 D0
S

SD0
Y

Output
SD 1
E
Enable Input

Module-3 10/17/2024
 4:1 Multiplexer

Block Diagram Truth Table

Output
Enable i/p Select i/p
D0
D1 E S1 S0 Y
Data
Y
Inputs D2 4:1
Mux 0 X X 0
D3 Output
D0
1 0 0
E
1 0 1 D1
Enable Input
S1 S0
1 1 0 D2
Select Lines
D3
1 1 1

Module-3 10/17/2024
Realization of 4:1 Mux using gates

S1 S0

S1S 0D0
D0
S1S 0 D 1
D1 Y

Output
D2
S1S 0D2
E
D3 S1S 0 D3 Enable Input

Module-3 10/17/2024
 8:1 Multiplexer
Block Diagram
Truth Table

D0
Outp
D1 Enable
Select i/p ut
i/p
D2
D3 E S2 S1 S0 Y
Data
Y
Inputs D4 8:1 0 X X X 0
Mux Output 1 0 0 0 D0
D5
1 0 0 1 D1
D6
1 0 1 0 D2
D7
1 0 1 1 D3
1 1 0 0 D4
E
1 1 0 1 D5
Enable Input
1 1 1 0 D6
S2 S1 S0 1 1 1 1 D7
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16:1 Multiplexer
Block Diagram
D0
D1
D2
D3
D4
D5
Data D6 Y
Inputs D7 16:1
D8 Mux
D9 Output
D10
D11
D12
D13
D14
D15

E
Enable Input

S3 S2 S1 S0
Select Lines
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 Enable Select Lines Output
16:1 Multiplexer
E S3 S2 S1 S0 Y
0 X X X X 0
1 0 0 0 0 D0
1 0 0 0 1 D1
1 0 0 1 0 D2
1 0 0 1 1 D3
1 0 1 0 0 D4
1 0 1 0 1 D5
Truth Table 1 0 1 1 0 D6
1 0 1 1 1 D7
1 1 0 0 0 D8
1 1 0 0 1 D9
1 1 0 1 0 D10
1 1 0 1 1 D11
1 1 1 0 0 D12
1 1 1 0 1 D13
1 1 1 1 0 D14
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10/17/2024 213
1 1 1 1 1 D
Mux Tree

✓The multiplexers having more number of inputs

can be obtained by cascading two or more
multiplexers with less number of inputs. This is
called as Multiplexer Tree.

✓For example, 32:1 mux can be realized using two

16:1 mux and one 2:1 mux.

Module-3 10/17/2024
 8:1 Multiplexer using 4:1 Multiplexer

D0
D1
Y1
D2 4:1
Mux
D3

S2 E S1 S0 Y
Select
Lines S1
S0 Output
S1 S0
D4
D5
4:1
D6 Mux
Y2
D7

E
Module-3 10/17/2024
8:1 Multiplexer using 4:1 Multiplexer

D0
D1
Y1
D2 4:1
Mux
D3

D0
E S1 S0 2:1 Y
D1
S1 Mux
S0 Output
E
S1 S0
D4
D5 S2
4:1
D6 Mux
Y2
D7

E
Module-3 10/17/2024
 D0
4:1 Y1
16:1 Mux using 4:1 Mux
D1
D2 Mux
D3
S1 S0
S1
S0
D4 S1 S0
D5 4:1 Y2
D6 Mux
D7
D0
4:1 Y
D1
D2 Mux
D3 S S0 Output
D8 1

D9 4:1 Y3
D10 Mux
D11
S1 S0 S3 S2

D12 S1 S0
D13 4:1 Y4
D14 Mux
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 Thank You

Module-3 10/17/2024
Realization of Boolean expression using Mux

✓We can implement any Boolean expression

using Multiplexers.

✓It reduces circuit complexity.

✓It does not require any simplification

Module-3 10/17/2024
Example 1

Implement following Boolean expression using multiplexer

f ( A, B , C ) =  m ( 0 , 3, 5, 6 )

✓Since there are three variables, therefore a

multiplexer with three select input is required
i.e. 8:1 multiplexer is required
✓The 8:1 multiplexer is configured as below to
implement given Boolean expression
Module-3 10/17/2024
Example 1 continue…..

+Vcc f ( A, B , C ) =  m ( 0 , 3, 5, 6 )

D0
D1
D2
D3
Y
D4 8:1
Mux
Output
D5
D6
D7

E S2 S1 S0

A B C
Module-3 10/17/2024
Example 2

Implement following Boolean expression using multiplexer

f ( A, B , C , D ) =  m ( 0 , 2, 3, 6 , 8 , 9 , 1 2 , 14)

✓Since there are four variables, therefore a

multiplexer with four select input is required
i.e. 16:1 multiplexer is required
✓The 16:1 multiplexer is configured as below to
implement given Boolean expression
Module-3 10/17/2024
Example 2 continue…..

+Vcc
f ( A, B , C , D ) =  m ( 0 , 2, 3, 6 , 8 , 9 , 1 2 , 1 4 )
D0
D1
D2
D3
D4
D5
D6 Y
D7 16:1
D8 Mux
D9 Output
D10
D11
D12
D13
D14
D15
S3 S2 S1 S0
E

A B C D
Module-3 10/17/2024
 Unit III – Combinational Logic Circuits

✓ Airthmetic Circuits: (IC 7483) Adder & Subtractor, BCD Adder

✓ Encoder/Decoder: Basics of Encoder, decoder, comparison, (IC
7447) BCD to 7- Segment decoder/driver.

✓ Multiplexer and Demultiplexer: Working, truth table and

applications of Multiplexers and Demultiplexers, MUX tree, IC
74151 as MUX, DEMUX tree, DEMUX as decoder, IC 74155 as
DEMUX

✓ Buffer: Tristate logic, Unidirectional and Bidirectional buffer (IC

74LS244 and IC 74LS245)

Module-3 10/17/2024
De-multiplexer

✓A de-multiplexer performs the reverse

operation of a multiplexer i.e. it receives one
input and distributes it over several outputs.
✓At a time only one output line is selected by the
select lines and the input is transmitted to the
selected output line.
✓It has only one input line, n number of output
lines and m number of select lines.
Module-3 10/17/2024
 Block Diagram of De-multiplexer

Y0 Y0
Y1 Y1
Y2 Y2
Data Y3 Y3
Input 1:n . Data .
. .
De-mux .
Outputs Input .
Output
. .
. .
Yn-1 Yn-1
E
Enable
Input . . .. . . ..

Sm-1 S2 S1 s0 Sm-1 S2 S1 s0
Select Lines

Fig. General Block Diagram Fig. Equivalent Circuit

Module-3 10/17/2024
Relation between Data Output Lines & Select Lines

✓In general de-multiplexer contains , n output

lines, one input line and m select lines.

✓To select n outputs we need m select lines such

that n=2m.

Module-3 10/17/2024
Types of De-multiplexers

✓1:2 De-multiplexer
✓1:4 De-multiplexer
✓1:8 De-multiplexer
✓1:16 De-multiplexer
✓1:32 De-multiplexer
✓1:64 De-multiplexer
and so on…………
Module-3 10/17/2024
1: 2 De-multiplexer

Y0
Data Din 1:2
Block Diagram
Input De-mux
Y1
E
Enable
Input S
Select Lines

Enable i/p Select i/p Outputs

E S Y0 Y1

Truth Table 0 X 0 0

1 0 Din 0

1 1 0 Din

Module-3 10/17/2024
1:2 De-mux using basic gates

E Din S
S

Y0

Y1

Module-3 10/17/2024
 1: 4 De-multiplexer
Y0
Data Din 1:4 Y1
Block Diagram
Input De-mux Y2
Y3
E
Enable
Input Enable
S1 S0 Select i/p Outputs
Select Lines i/p

E S1 S0 Y0 Y1 Y2 Y3

0 X X 0 0 0 0

1 0 0 Din 0 0 0

Truth Table 1 0 1 0 Din 0 0

1 1 0 0 0 Din 0

1 1 1 0 0 0 Din
Module-3 10/17/2024
1:4 De-mux using basic gates
E Din S 1 S0
S1 S0

Y0

Y1

Y2

Y3

Module-3 10/17/2024
1: 8 De-multiplexer

Block Diagram

Y0
Y1
Data Din Y2
1:8 Y3
Input Y4
De-mux
Y5
Y6
E Y7
Enable
Input
S2 S1 S0
Select Lines

Module-3 10/17/2024
 1: 8 De-multiplexer
Truth Table

Enabl
Select i/p Outputs
e i/p

E S2 S1 S0 Y7 Y6 Y5 Y4 Y3 Y2 Y1 Y0

0 X X X 0 0 0 0 0 0 0 0

1 0 0 0 0 0 0 0 0 0 0 Din
1 0 0 1 0 0 0 0 0 0 Din 0

1 0 1 0 0 0 0 0 0 Din 0 0

1 0 1 1 0 0 0 0 Din 0 0 0

1 1 0 0 0 0 0 Din 0 0 0 0

1 1 0 1 0 0 Din 0 0 0 0 0

1 1 1 0 0 Din 0 0 0 0 0 0

1 9/10 /2011
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Amit N evase0 0 0 0 0 233
1: 16 De-multiplexer
Y0
Block Diagram
Y1
Y2
Y3
Y4
Y5
Y6
Din
Data Y7
Input Y8
1:16
Y9
De-mux
Y10
Y11
Y12
Y13
Y14
E Y15
Enable
Input
S3 S2 S1 S0

Module-3 10/17/2024
De-mux Tree

✓Similar to multiplexer we can construct the de-

multiplexer with more number of lines using de-

multiplexer having less number of lines. This is

call as “De-mux Tree”.

Module-3 10/17/2024
1:4 De-mux using 1:2 De-mux

Data Y0 Y0
1:2
Input Din De-mux
Y1 Y1
S1 E S0
Select
Lines
S0

S0
Y0 Y2
Din 1:2
De-mux
Y1 Y3
E

Module-3 10/17/2024
1:16 De-mux using 1:4 De- Y0
1:4 Y1
mux Din De-mux Y2
Y3
S1 S0

S1 S0 Y4
1:4 Y5
Din Y6
Data Y0 De-mux
Din 1:4 Y7
Input Y1
De-mux Y2
Y3
S1 S0
Y8
1:4 Y9
Din De-mux
Y10
S3 S2 S1 S0 Y11

S1 S0 Y12
Din 1:4 Y13
De-mux Y14 S1 S0
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Amit Nevase Y15 237
Decoder

✓Decoder is a combinational circuit.

✓It converts n bit binary information at its input

into a maximum of 2n output lines.

✓For example, if n=2 then we can design upto 2:4

decoder

Module-3 10/17/2024
 2:4 Decoder
Y0
A
2:4 Y1
Inputs Block Diagram
B Decoder Y2
Y3

E Enable
Input Enable
Data Inputs Outputs
i/p

E A B Y0 Y1 Y2 Y3

0 X X 0 0 0 0

1 0 0 1 0 0 0
Truth Table

1 0 1 0 1 0 0

1 1 0 0 0 1 0

1 1 1 0 0 0 1
Module-3 10/17/2024
De-multiplexer as Decoder

✓It is possible to operate a de-multiplexer as a

decoder.

✓Let us consider an example of 1:4 de-mux can

be used as 2:4 decoder

Module-3 10/17/2024
 1:4 De-multiplexer as 2:4 Decoder

Vcc

Y0 Din Y0
A S1
Data Din 1:4 Y1
Inputs
1:4 Y1
Input De-mux Y2 De-mux Y2
B S0
Y3 Y3
E
Enable E Enable
Input S1 S0 Input
Select Lines

1: 4 De-multiplexer 1: 4 De-multiplexer as 2:4 Decoder

Module-3 10/17/2024
Realization of Boolean expression using De-mux

✓We can implement any Boolean expression

using de-multiplexers.

✓It reduces circuit complexity.

✓It does not require any simplification

Module-3 10/17/2024
Example 1

Implement following Boolean expression using de-multiplexer

f ( A, B , C ) =  m ( 0 , 3, 5, 6 )

✓ Since there are three variables, therefore a de-

multiplexer with three select input is required i.e.
1:8 de-multiplexer is required

✓ The 1:8 de-multiplexer is configured as below to

implement given Boolean expression
Module-3 10/17/2024
Example 1 continue…..

f ( A, B , C ) =  m ( 0 , 3, 5, 6 )

+Vcc Y0
Y1
Data Y2
Din 1:8 Y3 Y
Input
De-mux Y4
Y5
Y6
E S2 S1 S0 Y7
Enable
Input
A B C

Module-3 10/17/2024
Example 2

Implement following Boolean expression using de-multiplexer

f ( A, B , C , D ) =  m ( 0 , 2, 3, 6 , 8 , 9 , 1 2 , 1 4 )

✓ Since there are four variables, therefore a de-

multiplexer with four select input is required i.e.
1:16 de-multiplexer is required
✓ The 1:16 de-multiplexer is configured as below to
implement given Boolean expression

Module-3 10/17/2024
Example 2 continue…..

Y0
Y1
Y2
+Vcc Y3
Y4
Y5
Y6
Data 1:16 Y7 Y
Input De-mux Y8
Din
Y9
Y10
Y11
Y12
Y13
Y14
E S3 S2 S1 SY0 15
Enable
Input f ( A, B , C , D ) =  m ( 0 , 2, 3, 6 , 8 , 9 , 1 2 , 1 4)
A B C D
Module-3 10/17/2024
References
✓ Digital Principles by Malvino
Leach
✓ Modern Digital Electronics
by R.P. Jain
✓ Digital Electronics, Principles
and Integrated Circuits by
Anil K. Maini
✓ Digital Techniques by A.
Anand Kumar
Module-3 10/17/2024
Online Tutorials

✓ http://nptel.ac.in/video.php
?subjectId=117106086
✓ http://www.electronics-
tutorials.ws/combination/co
mb_1.html
✓ http://www.electronics-
tutorials.ws/combination/co
mb_2.html
Module-3 10/17/2024
 Thank You

Module-3 10/17/2024
 Digital Circuit Design

CHAPTER 5
Sequential Logic Principles

5.1 Motivation: Students will be able to design most complex high-speed digital circuits using Flip-
Flops.

5.2. Syllabus: -

Sr. No Topic Fine Detailing No of Week Self

Hours Study

05 Sequential Latches and Flip flops: Difference between 8 2 20

Logic Principles latches and flip flops, RS, JK, Master slave flip
flops, T & D flip flops with various triggering
methods, Conversion of flip flops,
Applications of latches and flip flops in
switch debouncing, bus holder circuits, Flip
flops timing considerations and Metastability

5.3. Books Recommended: .

1. William I. Fletcher, ‘An Engineering Approach to Digital Design’, PHI.
2. B. Holdsworth and R. C. Woods, ‘Digital Logic Design’, Newnes, 4th Edition
3. Morris Mano, Digital Design, Pearson Education, Asia 2002.
4. John F. Wakerley, Digital Design Principles And Practices, third Edition Updated, Pearson
Education, Singapore, 2002
5. Anil K. Maini, Digital Electronics, Principles, Devices and Applications, Wiley
6. Stephen Brown and Zvonko Vranesic, Fundamentals of digital logic design with VHDL,
McGraw Hill, 2nd Edition.

5.4. Weight age in University Examination: 20-30 Marks

5.5. Objective :
• To understand design goals and tradeoffs in Latches and Flip-flops and how they are
measured.
• To be able to describe operation of a wide range of flips and recognize how the individual
transistors determine operation

• To teach students to analyze, understand and design sequential circuits.

5.6 Key Notations :

SR –Set-Reset

1
 Digital Circuit Design

Q- Previous State
Q+- Present State.

5.7 Key Definitions:

1] Bistable element- Two cross coupled inverters form bistable element.

5.8. Introduction

Simple Circuits with Feedback:

Simple memory elements created from cascaded gates

Simplest gate component: inverter

Basis for commercial static RAM designs

Cross-coupled NOR gates and NAND gates also possible

These two types of memory elements form the basic building blocks of the latch and flip-flop
memory elements

1] In sequential logic, the outputs depend not only on the inputs, but also on the preceding
input values... it has memory.

2] Memory can be implemented in 2 ways:

Positive feedback or regeneration (static):

One or more output signals are connected back to the inputs via storage elements. These
circuits are called multivibrator.

Bistable elements such as flip-flops are most common but monostable and astable circuits are
also used.

Charge storage (dynamic): As we know, a periodic refresh is necessary here.

The bistable element can be either static or dynamic and is an essential library element called a
register.

Astable multivibrator acts as an oscillator (clock generator) while a monostable multivibrator

can be used as a pulse generator.

Static Sequential Circuits

If the gain of the inverter in the transient region is greater than 1, there are only two stable
operating points.

2
 Digital Circuit Design

Storing a new value usually involves applying a trigger pulse for a duration equal to the
propagation delay through the two inverters. The trigger pulse takes either Vi1 or Vi2
temporarily out of the region where the gain, G, is less than 1 to the unstable region where
G > 1.

Fig.5.1: Cascaded Inverters: Static Memory Cell

Sequential Action: Sequential action means (i) to remember what steps are to be done next,
and (ii) to recall which step has just been finished

3] Sequential Circuit:

Definition A sequential circuit is a circuit made up by combining logic gates such that the
required logic at the output(s) depends not only on the current input logic conditions but also
on the past inputs, outputs and sequences

Sequential circuit Consist of a combinational circuit to which storage elements are connected to
form a feedback path

! State: The state of the memory devices now, also called current state

! Next states and outputs are functions of inputs and present states of storage elements

Features: 1] Sequential circuit has a feedback of the output(s) from a stage to the input of
either that stage or any previous stage

2] An output depends on the current input state and past input state (thus past output state)

3] An output(s) can remain stable (constant) even after the input conditions change

4]An output(s) at each stage appears after a delay of few tens or hundred ns depending upon
the gate type or family of used to implement the circuit

5]A sequential circuit may have a clock (gate) input to control the instance or time interval in
which the output gets affected as per the inputs to the sequential circuit and in which the
output undergoes transition to next state

Clock Input: Input after which the state at output(s) of sequential circuit undergoes transition to
next state

Asynchronous input (Level clocking)—A time interval defined by clock input during which input
changes reflect on the output

Level means 1 for a time interval or 0 for a time interval

3
 Digital Circuit Design

Synchronous input — (i) Edge +ve or –ve defines the instance at which input affects the output
and transition is to next state (ii) Master slave —at +ve edge at master section of circuit, there is
transition at master’s output and at – ve edge, the slave output undergoes transition as per
master output.

+ ve edge and -ve edge:

+ edge means transition at input from 0 to 1

- edge means transition at input from 0 to 1

Sequential Circuit State Table: Sequential circuit has a state table (like truth table in a
combinational circuit) Sequences are specified by a table called state table. State table gives the
past, current and future states at the output.

A sequential circuit consists of a feedback path, and employs some memory elements

Sequential circuit = Combinational logic + Memory Elements

▪ Bistable logic devices: latches and flip-flops.

▪ Latches and flip-flops differ in the method used for changing their state.

Fig.5.2:Elements of sequential circuit

Two Types of Sequential Circuits

1] Asynchronous sequential circuit-Depends upon the input signals at any instant of time and
their change order, May have better performance but hard to design

2] Synchronous sequential circuit Defined from the knowledge of its signals at discrete instants
of time, Much easier to design (preferred design style), Synchronized by a periodic train of clock
pulses

4
 Digital Circuit Design

Fig.5.3(a): Sequential circuit with Flip-Flop

Memory Elements: Allow sequential logic design
Memory element: a device which can remember value indefinitely, or change value on
command from its inputs.

Fig.5.3(b): Sequential circuit with Flip-Flop

a] Latch . a level-sensitive memory element

SR latches
D latches
b] Flip-Flop .an edge-triggered memory element
Master-slave flip-flop
Edge-triggered flip-flop
c] RAM and ROM. a mass memory element
Command Q(t) Q(t+1)
Characteristic table: (at time t)
Set X 1
Reset X 0
Memorise / 0 0
Q(t): current state No Change 1 1
Q(t+1) or Q+: next state

5.8.2 Sequential Logic: Latches and Flip-Flops (Conversions, timing considerations and meta
stability are not expected)

Latches:

• The most basic types of flip-flops operate with signal levels

• The basic circuits from which all flip-flops are constructed &Useful for storing binary
information and for the design of asynchronous sequential circuits

5
 Digital Circuit Design

• Not practical for use in synchronous sequential circuits Avoid to use latches as possible in
synchronous sequential circuits to avoid design problems

• A circuit with two cross-coupled NOR gates or two cross-coupled NAND gates

A] SR Latch using NOR gates The SR latches constructed with two cross-coupled NOR gates are
active-high

Two useful states:

1] S=1, R=0 " set state (Q will become to 1)
2] S=0, R=1 " reset state (Q will become to 0)
3] When S=0 and R=0 " keep the current value

Fig.5.4: S-R Latch using NOR gate

Undefined State in SR Latch:

Fig.5.5: Undefined state in S-R Latch

Fig.5.6: Logic Simulation of S-R Latch behavior

B] SR Latch with NAND Gates The SR latches constructed with two cross-coupled NAND gates
are active-low

6
 Digital Circuit Design

1] S=1, R=0 " reset state (Q will become to 0)

2] S=0, R=1 " set state (Q will become to 1)

3] S=1, R=1 " unchanged

Fig.5.7: S-R Latch using NAND gate

SR Latch with Control Input: Add an additional control input to determine when the state of
the latch can be changed

1] C=0: S and R are disabled (no change at outputs)

2] C=1: S and R are active-high

Fig.5.8: S-R Latch with control input

C] D Latch: D latch has only two inputs: D(data) and C(control)

1] Use the value of D to set the output value

2] Eliminate the indeterminate state in the SR latches

3] The D input goes directly to the S input and its complement is applied to the R input

D =1 Q=1 S=1, R=0

7
 Digital Circuit Design

Fig.5.9: D- Latch

Fig.5.10: Graphic symbols for Latches

Flip-Flops:
Unlike Combinational Logic circuits that change state depending upon the actual signals being
applied to their inputs at that time, Sequential Logic circuits have some form of inherent
"Memory" built in to them as they are able to take into account their previous input state as
well as those actually present, a sort of "before" and "after" is involved with sequential circuits.
In other words, the output state of a "sequential logic circuit" is a function of the following three
states, the "present input", the "past input" and/or the "past output". Sequential Logic circuits
remember these conditions and stay fixed in their current state until the next clock signal
changes one of the states, giving sequential logic circuits "Memory".
Sequential logic circuits are generally termed as two state or Bistable devices which can have
their output or outputs set in one of two basic states, a logic level "1" or a logic level "0" and will
remain "latched" (hence the name latch) indefinitely in this current state or condition until some
other input trigger pulse or signal is applied which will cause the bistable to change its state
once again.

1] Sequential Logic Representation:

The word "Sequential" means that things happen in a "sequence", one after another and in
Sequential Logic circuits, the actual clock signal determines when things will happen next.
Simple sequential logic circuits can be constructed from standard Bistable circuits such as Flip-
flops, Latches and Counters and which themselves can be made by simply connecting together
universal NAND Gates and/or NOR Gates in a particular combinational way to produce the
required sequential circuit.

8
 Digital Circuit Design

Fig.5.11 Sequential logic circuit representation

2] Classification of Sequential Logic:
As standard logic gates are the building blocks of combinational circuits, bistable latches and
flip-flops are the building blocks of Sequential Logic Circuits. Sequential logic circuits can be
constructed to produce either simple edge-triggered flip-flops or more complex sequential
circuits such as storage registers, shift registers, memory devices or counters. Either way
sequential logic circuits can be divided into the following three main categories:
1. Event Driven - asynchronous circuits that change state immediately when enabled.
2. Clock Driven - synchronous circuits that are synchronised to a specific clock signal.
3. Pulse Driven - which is a combination of the two that responds to triggering pulses?

Fig.5.12Sequential logic circuit classification

As well as the two logic states mentioned above logic level "1" and logic level "0", a third
element is introduced that separates sequential logic circuits from their combinational logic
counterparts, namely TIME. Sequential logic circuits that return back to their original state once
reset, i.e. circuits with loops or feedback paths are said to be "cyclic" in nature. We now know
that in sequential circuits changes occur only on the application of a clock signal making it
synchronous, otherwise the circuit is asynchronous and depends upon an external input. To
retain their current state, sequential circuits rely on feedback and this occurs when a fraction of
the output is fed back to the input and this is demonstrated as:

3] Sequential Feedback Loop:

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 Digital Circuit Design

Fig.5.13Sequential Feed back loop

The two inverters or NOT gates are connected in series with the output at Q fed back to the
input. Unfortunately, this configuration never changes state because the output will always be
the same, either a "1" or a "0", it is permanently set. However, we can see how feedback works
by examining the most basic sequential logic components, called the SR flip-flop

4] SR Flip-Flop:
The SR flip-flop, also known as a SR Latch, can be considered as one of the most basic sequential
logic circuit possible. This simple flip-flop is basically a one-bit memory bistable device that has
two inputs, one which will "SET" the device (meaning the output = "1"), and is labelled S and
another which will "RESET" the device (meaning the output = "0"), labelled R.
Then the SR description stands for "Set-Reset". The reset input resets the flip-flop back to its
original state with an output Q that will be either at a logic level "1" or logic "0" depending upon
this set/reset condition.
A basic NAND gate SR flip-flop circuit provides feedback from both of its outputs back to its
opposing inputs and is commonly used in memory circuits to store a single data bit. Then the SR
flip-flop actually has three inputs, Set, Reset and its current output Q relating to it's current
state or history. The term "Flip-flop" relates to the actual operation of the device, as it can be
"flipped" into one logic Set state or "flopped" back into the opposing logic Reset state.

5] The NAND Gate SR Flip-Flop:

The simplest way to make any basic single bit set-reset SR flip-flop is to connect together a pair
of cross-coupled 2-input NAND gates as shown, to form a Set-Reset Bistable also known as an
active LOW SR NAND Gate Latch, so that there is feedback from each output to one of the other
NAND gate inputs. This device consists of two inputs, one called the Set, S and the other called
the Reset, R with two corresponding outputs Q and its inverse or complement Q (not-Q) as
shown below.
The Basic SR Flip-flop

Fig 5.14 The Basic SR Flip-flop

The Set State
Consider the circuit shown above. If the input R is at logic level "0" (R = 0) and input S is at logic
level "1" (S = 1), the NAND gate Y has at least one of its inputs at logic "0" therefore, its output Q
must be at a logic level "1" (NAND Gate principles). Output Q is also fed back to input "A" and so

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 Digital Circuit Design

both inputs to NAND gate X are at logic level "1", and therefore its output Q must be at logic
level "0".
Again NAND gate principals. If the reset input R changes state, and goes HIGH to logic "1" with S
remaining HIGH also at logic level "1", NAND gate Y inputs are now R = "1" and B = "0". Since
one of its inputs is still at logic level "0" the output at Q still remains HIGH at logic level "1" and
there is no change of state. Therefore, the flip-flop circuit is said to be "Latched" or "Set" with Q
= "1" and Q = "0".
Reset State
In this second stable state, Q is at logic level "0", (not Q = "0") its inverse output at Q is at logic
level "1", (Q = "1"), and is given by R = "1" and S = "0". As gate X has one of its inputs at logic "0"
its output Q must equal logic level "1" (again NAND gate principles). Output Q is fed back to
input "B", so both inputs to NAND gate Y are at logic "1", therefore, Q = "0".
If the set input, S now changes state to logic "1" with input R remaining at logic "1", output Q
still remains LOW at logic level "0" and there is no change of state. Therefore, the flip-flop
circuits "Reset" state has also been latched and we can define this "set/reset" action in the
following truth table.
Truth Table for this Set-Reset Function:
State S R Q Q Description
1 0 0 1 Set Q » 1
Set
1 1 0 1 no change
0 1 1 0 Reset Q » 0
Reset
1 1 1 0 no change
Invalid 0 0 1 1 Invalid Condition

It can be seen that when both inputs S = "1" and R = "1" the outputs Q and Q can be at either
logic level "1" or "0", depending upon the state of the inputs S or R BEFORE this input condition
existed. Therefore the condition of S = R = "1" does not change the state of the outputs Q and Q.
However, the input state of S = "0" and R = "0" is an undesirable or invalid condition and must
be avoided. The condition of S = R = "0" causes both outputs Q and Q to be HIGH together at
logic level "1" when we would normally want Q to be the inverse of Q. The result is that the flip-
flop looses control of Q and Q, and if the two inputs are now switched "HIGH" again after this
condition to logic "1", the flip-flop becomes unstable and switches to an unknown data state
based upon the unbalance as shown in the following switching diagram.

S-R Flip-flop Switching Diagram

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 Digital Circuit Design

Fig.5.15 S-R Flip-flop Switching Diagram

This unbalance can cause one of the outputs to switch faster than the other resulting in the flip-
flop switching to one state or the other which may not be the required state and data
corruption will exist. This unstable condition is generally known as its Meta-stable state.
Then, a bistable SR flip-flop or SR latch is activated or set by a logic "1" applied to its S input and
deactivated or reset by a logic "1" applied to its R. The SR flip-flop is said to be in an "invalid"
condition (Meta-stable) if both the set and reset inputs are activated simultaneously.
As well as using NAND gates, it is also possible to construct simple one-bit SR Flip-flops using
two cross-coupled NOR gates connected in the same configuration. The circuit will work in a
similar way to the NAND gate circuit above, except that the inputs are active HIGH and the
invalid condition exists when both its inputs are at logic level "1", and this is shown below.
6] The NOR Gate SR Flip-flop:

Fig.5.16 The NOR Gate S-R Flip-flop

7] Switch Debounce Circuits:

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 Digital Circuit Design

Edge-triggered flip-flops require a nice clean signal transition, and one practical use of this type
of set-reset circuit is as a latch used to help eliminate mechanical switch "bounce". As its name
implies, switch bounce occurs when the contacts of any mechanically operated switch, push-
button or keypad are operated and the internal switch contacts do not fully close cleanly, but
bounce together first before closing (or opening) when the switch is pressed.
This gives rise to a series of individual pulses which can be as long as tens of milliseconds that an
electronic system or circuit such as a digital counter may see as a series of logic pulses instead of
one long single pulse and behave incorrectly. For example, during this bounce period the output
voltage can fluctuate wildly and may register multiple input counts instead of one single count.
Then set-reset SR Flip-flops or Bistable Latch circuits can be used to eliminate this kind of
problem and this is demonstrated below.

SR Bistable Switch Debounce Circuit:

Fig.5.17 SR Bistable Switch Debounce Circuit

Depending upon the current state of the output, if the set or reset buttons are depressed the
output will change over in the manner described above and any additional unwanted inputs
(bounces) from the mechanical action of the switch will have no effect on the output at Q.

When the other button is pressed, the very first contact will cause the latch to change state, but
any additional mechanical switch bounces will also have no effect. The SR flip-flop can then be
RESET automatically after a short period of time, for example 0.5 seconds, so as to register any
additional and intentional repeat inputs from the same switch contacts, such as multiple inputs
from a keyboards "RETURN" key.

Commonly available IC's specifically made to overcome the problem of switch bounce are the
MAX6816, single input, MAX6817, dual input and the MAX6818 octal input switch debouncer

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 Digital Circuit Design

IC's. These chips contain the necessary flip-flop circuitry to provide clean interfacing of
mechanical switches to digital systems.

Set-Reset bistable latches can also be used as Monostable (one-shot) pulse generators to
generate a single output pulse, either high or low, of some specified width or time period for
timing or control purposes. The 74LS279 is a Quad SR Bistable Latch IC, which contains four
individual NAND type bistable's within a single chip enabling switch debounce or
monostable/astable clock circuits to be easily constructed.

Quad SR Bistable Latch 74LS279

Fig.5.18 Quad SR Bistable Latch 74LS279

8] Gated or Clocked SR Flip-Flop:

It is sometimes desirable in sequential logic circuits to have a bistable SR flip-flop that only
changes state when certain conditions are met regardless of the condition of either the Set or
the Reset inputs. By connecting a 2-input AND gate in series with each input terminal of the SR
Flip-flop a Gated SR Flip-flop can be created. This extra conditional input is called an "Enable"
input and is given the prefix of "EN". The addition of this input means that the output at Q only
changes state when it is HIGH and can therefore be used as a clock (CLK) input making it level-
sensitive as shown below.
Gated SR Flip-flop

Fig.5.19.Gated SR Flip-flop
When the Enable input "EN" is at logic level "0", the outputs of the two AND gates are also at
logic level "0", (AND Gate principles) regardless of the condition of the two inputs S and R,
latching the two outputs Q and Q into their last known state. When the enable input "EN"

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 Digital Circuit Design

changes to logic level "1" the circuit responds as a normal SR bistable flip-flop with the two
ANDgates becoming transparent to the Set and Reset signals.
This additional enable input can also be connected to a clock timing signal (CLK) adding clock
synchronization to the flip-flop creating what is sometimes called a "Clocked SR Flip-flop". So a
Gated Bistable SR Flip-flop operates as a standard bistable latch but the outputs are only
activated when a logic "1" is applied to its EN input and deactivated by a logic "0".
In the next tutorial about Sequential Logic Circuits, we will look at another type of simple edge-
triggered flip-flop which is very similar to the RS flip-flop called a JK Flip-flop named after its
inventor, Jack Kilby. The JK flip-flop is the most widely used of all the flip-flop designs as it is
considered to be a universal device.

9] The JK Flip-flop:
From the previous tutorial we now know that the basic gated SR NAND flip-flop suffers from two
basic problems: number one, the S = 0 and R = 0 condition or S = R = 0 must always be avoided,
and number two, if S or R change state while the enable input is high the correct latching action
may not occur. Then to overcome these two fundamental design problems with the SR flip-flop,
the JK flip-Flop was developed.
This simple JK flip-Flop is the most widely used of all the flip-flop designs and is considered to be
a universal flip-flop circuit. The sequential operation of the JK flip-flop is exactly the same as for
the previous SR flip-flop with the same "Set" and "Reset" inputs. The difference this time is that
the JK flip-flop has no invalid or forbidden input states of the SR Latch (when S and R are both 1).
The JK flip-flop is basically a gated SR flip-flop with the addition of a clock input circuitry that
prevents the illegal or invalid output condition that can occur when both inputs S and R are
equal to logic level "1". Due to this additional clocked input, a JK flip-flop has four possible input
combinations, "logic 1", "logic 0", "no change" and "toggle". The symbol for a JK flip-flop is
similar to that of an SR Bistable Latch as seen in the previous tutorial except for the addition of
a clock input.
The Basic JK Flip-flop

Fig.5.20 (A) The Basic JK Flip-flop

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 Digital Circuit Design

Fig.5.20(B) JK Flip-Flop IC7476

Both the S and the R inputs of the previous SR bistable have now been replaced by two inputs
called the J and K inputs, respectively after its inventor Jack Kilby. Then this equates to: J = S and
K = R.
The two 2-input AND gates of the gated SR bistable have now been replaced by two 3-input
NAND gates with the third input of each gate connected to the outputs at Q and Q. This cross
coupling of the SR flip-flop allows the previously invalid condition of S = "1" and R = "1" state to
be used to produce a "toggle action" as the two inputs are now interlocked.
If the circuit is now "SET" the J input is inhibited by the "0" status of Q through the lower NAND
gate. If the circuit is "RESET" the K input is inhibited by the "0" status of Q through the upper
NAND gate. As Q and Q are always different we can use them to control the input. When both
inputs J and K are equal to logic "1", the JK flip-flop toggles as shown in the following truth table.

The Truth Table for the JK Function

Input Output
Description
J K Q Q
0 0 0 0 Memory
same as no change
0 0 0 1
for the
SR Latch 0 1 1 0
Reset Q » 0
0 1 0 1
1 0 0 1
Set Q » 1
1 0 1 0
toggle 1 1 0 1
Toggle
action 1 1 1 0

Then the JK flip-flop is basically an SR flip-flop with feedback which enables only one of its two
input terminals, either SET or RESET to be active at any one time thereby eliminating the invalid
condition seen previously in the SR flip-flop circuit. Also when both the J and the K inputs are at
logic level "1" at the same time, and the clock input is pulsed either "HIGH", the circuit will
"toggle" from its SET state to a RESET state, or visa-versa. This results in the JK flip-flop acting
more like a T-type toggle flip-flop when both terminals are "HIGH".

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 Digital Circuit Design

Although this circuit is an improvement on the clocked SR flip-flop it still suffers from timing
problems called "race" if the output Q changes state before the timing pulse of the clock input
has time to go "OFF". To avoid this the timing pulse period ( T ) must be kept as short as possible
(high frequency). As this is sometimes not possible with modern TTL IC's the much improved
Master-Slave JK Flip-flop was developed.
The master-slave flip-flop eliminates all the timing problems by using two SR flip-flops
connected together in a series configuration. One flip-flop acts as the "Master" circuit, which
triggers on the leading edge of the clock pulse while the other acts as the "Slave" circuit, which
triggers on the falling edge of the clock pulse. This results in the two sections, the master section
and the slave section being enabled during opposite half-cycles of the clock signal.
The 74LS73 is a Dual JK flip-flop IC, which contains two individual JK type bistable's within a
single chip enabling single or master-slave toggle flip-flops to be made. Other JK flip-flop IC's
include the 74LS107 Dual JK flip-flop with clear, the 74LS109 Dual positive-edge triggered JK flip-
flop and the 74LS112 Dual negative-edge triggered flip-flop with both preset and clear inputs.
Dual JK Flip-flop 74LS73

Fig.5.21 Dual JK Flip-flop74LS73

10] The Master-Slave JK Flip-flop:
The Master-Slave Flip-Flop is basically two gated SR flip-flops connected together in a series
configuration with the slave having an inverted clock pulse. The outputs from Q and Q from the
"Slave" flip-flop are fed back to the inputs of the "Master" with the outputs of the "Master" flip-
flop being connected to the two inputs of the "Slave" flip-flop. This feedback configuration from
the slave's output to the master's input gives the characteristic toggle of the JK flip-flop as
shown below.

Fig.5.22 The Master-Slave JK Flip-Flop

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 Digital Circuit Design

The input signals J and K are connected to the gated "master" SR flip-flop which "locks" the
input condition while the clock (Clk) input is "HIGH" at logic level "1". As the clock input of the
"slave" flip-flop is the inverse (complement) of the "master" clock input, the "slave" SR flip-flop
does not toggle. The outputs from the "master" flip-flop are only "seen" by the gated "slave"
flip-flop when the clock input goes "LOW" to logic level "0".

When the clock is "LOW", the outputs from the "master" flip-flop are latched and any additional
changes to its inputs are ignored. The gated "slave" flip-flop now responds to the state of its
inputs passed over by the "master" section. Then on the "Low-to-High" transition of the clock
pulse the inputs of the "master" flip-flop are fed through to the gated inputs of the "slave" flip-
flop and on the "High-to-Low" transition the same inputs are reflected on the output of the
"slave" making this type of flip-flop edge or pulse-triggered.

Then, the circuit accepts input data when the clock signal is "HIGH", and passes the data to the
output on the falling-edge of the clock signal. In other words, the Master-Slave JK Flip-flop is a
"Synchronous" device as it only passes data with the timing of the clock signal.

11] The D flip-flop:

One of the main disadvantages of the basic SR NAND Gate bistable circuit is that the
indeterminate input condition of "SET" = logic "0" and "RESET" = logic "0" is forbidden. This state
will force both outputs to be at logic "1", over-riding the feedback latching action and whichever
input goes to logic level "1" first will lose control, while the other input still at logic "0" controls
the resulting state of the latch.

But in order to prevent this from happening an inverter can be connected between the "SET"
and the "RESET" inputs to produce another type of flip-flop circuit called a Data Latch, Delay
flip-flop, D-type Bistable or simply a D-type flip-flop as it is more generally called.

The D flip-flop is by far the most important of the clocked flip-flops as it ensures that ensures
that inputs S and R are never equal to one at the same time. D-type flip-flops are constructed
from a gated SR flip-flop with an inverter added between the S and the R inputs to allow for a
single D (data) input. This single data input D is used in place of the "set" signal, and the inverter
is used to generate the complementary "reset" input thereby making a level-sensitive D-type
flip-flop from a level-sensitive RS-latch as now S = D and R = not D as shown.
D flip-flop Circuit

Fig.5.23 D flip-flop Circuit

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 Digital Circuit Design

We remember that a simple SR flip-flop requires two inputs, one to "SET" the output and one to
"RESET" the output. By connecting an inverter (NOT gate) to the SR flip-flop we can "SET" and
"RESET" the flip-flop using just one input as now the two input signals are complements of each
other. This complement avoids the ambiguity inherent in the SR latch when both inputs are
LOW, since that state is no longer possible.

Thus the single input is called the "DATA" input. If this data input is HIGH the flip-flop would be
"SET" and when it is LOW the flip-flop would be "RESET". However, this would be rather
pointless since the flip-flop's output would always change on every data input. To avoid this an
additional input called the "CLOCK" or "ENABLE" input is used to isolate the data input from the
flip-flop after the desired data has been stored. The effect is that D is only copied to the output
Q when the clock is active. This then forms the basis of a D flip-flop.

The D flip-flop will store and output whatever logic level is applied to its data terminal so long as
the clock input is HIGH. Once the clock input goes LOW the "set" and "reset" inputs of the flip-
flop are both held at logic level "1" so it will not change state and store whatever data was
present on its output before the clock transition occurred. In other words the output is
"latched" at either logic "0" or logic "1".
Truth Table for the D Flip-flop
Clk D Q Q Description
Memory
↓»0 X Q Q
no change
↑»1 0 0 1 Reset Q » 0
↑»1 1 1 0 Set Q » 1
Note: ↓ and ↑ indicates direction of clock pulse as it is assumed D flip-flops are edge triggered
The Master-Slave JK Flip-flop
The basic D flip-flop can be improved further by adding a second SR flip-flop to its output that is
activated on the complementary clock signal to produce a "Master-Slave D flip-flop". On the
leading edge of the clock signal (LOW-to-HIGH) the first stage, the "master" latches the input
condition at D, while the output stage is deactivated.
On the trailing edge of the clock signal (HIGH-to-LOW) the second "slave" stage is now activated,
latching on to the output from the first master circuit. Then the output stage appears to be
triggered on the negative edge of the clock pulse. "Master-Slave D flip-flops" can be constructed
by the cascading together of two latches with opposite clock phases as shown.
Master-Slave D flip-flop Circuit

Fig.5.24 Master-Slave D flip-flop Circuit

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 Digital Circuit Design

We can see from above that on the leading edge of the clock pulse the master flip-flop will be
loading data from the data D input, therefore the master is "ON". With the trailing edge of the
clock pulse the slave flip-flop is loading data, i.e. the slave is "ON". Then there will always be one
flip-flop "ON" and the other "OFF" but never both the master and slave "ON" at the same time.
Therefore, the output Q acquires the value of D, only when one complete pulse, i.e. 0-1-0 is
applied to the clock input.

There are many different D flip-flop IC's available in both TTL and CMOS packages with the more
common being the 74LS74 which is a Dual D flip-flop IC, which contains two individual D type
bistable's within a single chip enabling single or master-slave toggle flip-flops to be made. Other
D flip-flop IC's include the 74LS174 HEX D flip-flop with direct clear input, the 74LS175 Quad D
flip-flop with complementary outputs and the 74LS273 Octal D flip-flop containing eight D flip-
flops with a clear input in one single package.

Dual D flip-flop 74LS74

Fig.5.25 Dual D flip-flop 74LS74

Application of Dflip flop:

1. As a delay element.
2. In the digital latches
D latches are also referred to as transparent latch because the output follows the
changes in D input
2.8.3 Counters: Asynchronous, Synchronous Counters, Up Down Counters, Mod
Counters, Ring Counters Shift Registers, Universal Shift Register
Frequency Division:
One main use of a D flip-flop is as a Frequency Divider. If the Q output on a D-type flip-flop is
connected directly to the D input giving the device closed loop "feedback", successive clock
pulses will make the bistable "toggle" once every two clock cycles.
In the counters tutorials we saw how the Data Latch can be used as a "Binary Divider", or a
"Frequency Divider" to produce a "divide-by-2" counter circuit, that is, the output has half the
frequency of the clock pulses. By placing a feedback loop around the D flip-flop another type of
flip-flop circuit can be constructed called a T-type flip-flop or more commonly a T-type bistable,
that can be used as a divide-by-two circuit in binary counters as shown below.

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 Digital Circuit Design

Divide-by-2 Counter

Fig.5.26 Divide-by-2 Counter

It can be seen from the frequency waveforms above, that by "feeding back" the output from Q
to the input terminal D, the output pulses at Q have a frequency that are exactly one half ( ƒ/2 )
that of the input clock frequency, ( ƒIN ). In other words the circuit produces frequency division
as it now divides the input frequency by a factor of two (an octave) as Q = 1 once every two
clock cycles.
Data Latches
Another useful application of the Data Latch is to hold or remember the data present on its data
input, thereby acting as a single bit memory device and IC's such as the TTL 74LS74 or the CMOS
4042 are available in Quad format for this purpose. By connecting together four, 1-bit data
latches so that all their clock terminals are connected at the same time a simple "4-bit" Data
latch can be made as shown below.
4-bit Data Latch

Fig. 5.27 4-bit Data Latch

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 Digital Circuit Design

Transparent Data Latch

The Data Latch is a very useful device in electronic and computer circuits. They can be designed
to have very high output impedance at both outputs Q and its inverse or complement output Q
to reduce the impedance effect on the connecting circuit when used as a buffer, I/O port, bi-
directional bus driver or even a display driver. But a single "1-bit" data latch is not very practical
to use on its own and instead commercially available IC's incorporate 4, 8, 10, 16 or even 32
individual data latches into one single IC package, and one such IC device is the 74LS373 Octal D-
type transparent latch.

The eight individual data latches or bistables of the 74LS373 are "transparent" D-type flip-flops,
meaning that when the clock (CLK) input is HIGH at logic level "1", (but can also be active low)
the outputs at Q follows the data D inputs. In this configuration the latch is said to be "open"
and the path from D input to Q output appears to be "transparent" as the data flows through it
unimpeded, hence the name transparent latch. When the clock signal is LOW at logic level "0",
the latch "closes" and the output at Q is latched at the last value of the data that was present
before the clock signal changed and no longer changes in response to D.

8-bit Data Latch

Fig.5.28 Functional diagram of the 74LS373 Octal Transparent Latch

D flip-flop Summary:
The data or D flip-flop can be built from a pair of back-to-back latches by connecting an inverter
between the S and the R inputs to allow for a single D (data) input. The basic D-type flip-flop
circuit can be improved further by adding a second SR flip-flop to its output that is activated on
the complementary clock signal to produce a "Master-Slave D flip-flop".
The difference between a D-type latch and a D-type flip-flop is that a latch does not have a clock
-signal to change state whereas a flip-flop always does. The D flip-flop is an edge triggered
device which transfers input data to Q on clock rising or falling edge. Data Latches are level
sensitive devices such as the data latch and the transparent latch.
In the next tutorial about Sequential Logic Circuits, we will look at connecting together data
latches to produce another type of sequential logic circuit called a Shift Register that are used to
convert parallel data into serial data and vice versa.

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 Digital Circuit Design

5.9 Questions:
5.9.1 Objective Questions:

Que.1] Explain the difference between the combinational circuit and sequential circuits ?List the
features of Sequential circuit over combinational circuit

Que.2] Explain single bit NOR cell and its uses in clocked JK Flip flop

Que.3] Derive the characteristics equation of SR flip Flop

Que.4] Draw SR NAND latch ,give its operation

Que.5] Draw circuit of JK using NAND ,explain wave forms of various modes of latch

Que.6] Explain the TRUTH table of positive edge triggered JKFF & characteristics of JK Flip flop

Que.7] Explan the necessity of Master Slave Flip Flop? Explain the working ,using NAND gates

Que.8] what is flip flop?show how to construct SET-RESET Flip Flop from NOT gate ?Can Flip
Flop be used as memory ?if so how many Bits can be stored by RS-Flip Flop?

5.9.2 Short Questions:

Que.1] How basic NOR or NAND gate could be used to construct a Set –Reset Flip –Flop?
Explain the working of circuit with the help of TRUTH Table of NOR or NAND gate ?Can Flip –
Flop constructed using OR or AND gate ?How /why?

Que.2]What is clock RS flip Flop ? show that the states of the flip flop changes only when the
clock pulse arrives &thus explain the working of clocked RS flip flop ,what modification required
so that the flip flop can respond only in the absence of clock pulse?

Que.3] Show how the Rs flip flop can be converted to a JK flip flop show the TRUTH table
&Explain each line in detail

Que.4] What is RACE around condition? Explain how RACE around condition can be avoided in
Master Slave Flip Flop?

Que.5] What is Edge Triggered Flip flop ?Show the logic symbol of positive Edge triggered and
Negative Edge triggered flip flop .Why edge triggered flip flops are preferred in digital systems

5.9.3 Long Questions:

Que.1] What is a Latch? Show how a D type flip flop can be constructed ?Explain its working?
How D flip flop can be converted to a T flip flop .can JK FF can be converted to a D type Flip Flop.

23
 Digital Circuit Design

Que.2] Show the circuit of Master Slave Flip –flop and Explain its working? Explain RACE –around
condition is avoided in a Master Slave flip flop

Que.3] Give the Description of data latch ,What are the uses of latch ?Explain 4 bit latch using
IC7475

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 Digital Circuit Design

CHAPTER 6
Counters and Registers

6.1 Motivation: Students will be able to design most complex digital circuits using counters.

6.2. Syllabus: -

Sr. No Topic Fine Detailing No of Week Self

Hours Study

06 Counters and Asynchronous and Synchronous, Up/Down, 8 2 20

Registers Johnson Counter, MOD N, BCD counter using
Decade counter, Ring counters, Shift
registers, Universal Shift Register

6.3. Books Recommended: .

1. William I. Fletcher, ‘An Engineering Approach to Digital Design’, PHI.
2. B. Holdsworth and R. C. Woods, ‘Digital Logic Design’, Newnes, 4th Edition
3. Morris Mano, Digital Design, Pearson Education, Asia 2002.
4. John F. Wakerley, Digital Design Principles And Practices, third Edition Updated, Pearson
Education, Singapore, 2002
5. Anil K. Maini, Digital Electronics, Principles, Devices and Applications, Wiley
6. Stephen Brown and Zvonko Vranesic, Fundamentals of digital logic design with VHDL,
McGraw Hill, 2nd Edition.

6.4. Weight age in University Examination: 20-30 Marks

6.5. Objective :

• To teach students to analyze, understand and design sequential circuits.

6.6 Key Notations :

Q- Previous State
Q+- Present State.

6.7 Key Definitions:

1] Asynchronous sequential circuit-Depends upon the input signals at any instant of time and
their change order, May have better performance but hard to design

1
 Digital Circuit Design

2] Synchronous sequential circuit Defined from the knowledge of its signals at discrete instants
of time, Much easier to design (preferred design style), Synchronized by a periodic train of clock
pulses

6.8. Introduction
Counters: Asynchronous, Synchronous Counters, Up Down Counters, Mod
Counters, Ring Counters Shift Registers, Universal Shift Register
Frequency Division:
One main use of a D flip-flop is as a Frequency Divider. If the Q output on a D-type flip-flop is
connected directly to the D input giving the device closed loop "feedback", successive clock
pulses will make the bistable "toggle" once every two clock cycles.
In the counters tutorials we saw how the Data Latch can be used as a "Binary Divider", or a
"Frequency Divider" to produce a "divide-by-2" counter circuit, that is, the output has half the
frequency of the clock pulses. By placing a feedback loop around the D flip-flop another type of
flip-flop circuit can be constructed called a T-type flip-flop or more commonly a T-type bistable,
that can be used as a divide-by-two circuit in binary counters as shown below.

Divide-by-2 Counter

Fig.6.1 Divide-by-2 Counter

It can be seen from the frequency waveforms above, that by "feeding back" the output from Q
to the input terminal D, the output pulses at Q have a frequency that are exactly one half ( ƒ/2 )
that of the input clock frequency, ( ƒIN ). In other words the circuit produces frequency division
as it now divides the input frequency by a factor of two (an octave) as Q = 1 once every two
clock cycles.

The Shift Register:

2
 Digital Circuit Design

The Shift Register is another type of sequential logic circuit that is used for the storage or
transfer of data in the form of binary numbers and then "shifts" the data out once every clock
cycle, hence the name "shift register". It basically consists of several single bit "D-Type Data
Latches", one for each bit (0 or 1) connected together in a serial or daisy-chain arrangement so
that the output from one data latch becomes the input of the next latch and so on.
The data bits may be fed in or out of the register serially, i.e. one after the other from either the
left or the right direction, or in parallel, i.e. all together. The number of individual data latches
required to make up a single Shift Register is determined by the number of bits to be stored
with the most common being 8-bits (one byte) wide, i.e. eight individual data latches.
The Shift Register is used for data storage or data movement and are used in calculators or
computers to store data such as two binary numbers before they are added together, or to
convert the data from either a serial to parallel or parallel to serial format. The individual data
latches that make up a single shift register are all driven by a common clock ( Clk ) signal making
them synchronous devices.
Shift register IC's are generally provided with a clear or reset connection so that they can be
"SET" or "RESET" as required. Generally, shift registers operate in one of four different modes
with the basic movement of data through a shift register being:
• Serial-in to Parallel-out (SIPO) - the register is loaded with serial data, one bit at a
time, with the stored data being available in parallel form.
• Serial-in to Serial-out (SISO) - the data is shifted serially "IN" and "OUT" of the register,
one bit at a time in either a left or right direction under clock control.
• Parallel-in to Serial-out (PISO) - the parallel data is loaded into the register
simultaneously and is shifted out of the register serially one bit at a time under clock
control.
• Parallel-in to Parallel-out (PIPO) - the parallel data is loaded simultaneously into the
register, and transferred together to their respective outputs by the same clock pulse.
The effect of data movement from left to right through a shift register can be presented
graphically as:

Fig.6.2 The Shift Register

Also, the directional movement of the data through a shift register can be either to the left, (left
shifting) to the right, (right shifting) left-in but right-out, (rotation) or both left and right shifting
within the same register thereby making it bidirectional. In this tutorial it is assumed that all the
data shifts to the right, (right shifting).
Serial-in to Parallel-out (SIPO)
4-bit Serial-in to Parallel-out Shift Register

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 Digital Circuit Design

Fig.6.3 4bit Serial-in to Parallel-out Shift Register

The operation is as follows. Lets assume that all the flip-flops ( FFA to FFD ) have just been RESET
( CLEAR input ) and that all the outputs QA to QD are at logic level "0" i.e, no parallel data output.
If a logic "1" is connected to the DATA input pin of FFA then on the first clock pulse the output of
FFA and therefore the resulting QA will be set HIGH to logic "1" with all the other outputs still
remaining LOW at logic "0". Assume now that the DATA input pin of FFA has returned LOW
again to logic "0" giving us one data pulse or 0-1-0.
The second clock pulse will change the output of FFA to logic "0" and the output of FFB and Q B
HIGH to logic "1" as its input D has the logic "1" level on it from Q A. The logic "1" has now moved
or been "shifted" one place along the register to the right as it is now at Q A. When the third
clock pulse arrives this logic "1" value moves to the output of FFC ( QC ) and so on until the
arrival of the fifth clock pulse which sets all the outputs Q A to QD back again to logic level "0"
because the input to FFA has remained constant at logic level "0".
The effect of each clock pulse is to shift the data contents of each stage one place to the right,
and this is shown in the following table until the complete data value of 0-0-0-1 is stored in the
register. This data value can now be read directly from the outputs of Q A to QD. Then the data
has been converted from a serial data input signal to a parallel data output. The truth table and
following waveforms show the propagation of the logic "1" through the register from left to
right as follows.

Basic Movement of Data through a Shift Register

Clock Pulse No QA QB QC QD
0 0 0 0 0
1 1 0 0 0
2 0 1 0 0
3 0 0 1 0
4 0 0 0 1
5 0 0 0 0

4
 Digital Circuit Design

Fig 6.4 Basic Movement of Data through a Shift Register

Note that after the fourth clock pulse has ended the 4-bits of data ( 0-0-0-1 ) are stored in the
register and will remain there provided clocking of the register has stopped. In practice the
input data to the register may consist of various combinations of logic "1" and "0". Commonly
available SIPO IC's include the standard 8-bit 74LS164 or the 74LS594.

Serial-in to Serial-out (SISO)

This shift register is very similar to the SIPO above, except were before the data was read
directly in a parallel form from the outputs QA to QD, this time the data is allowed to flow
straight through the register and out of the other end. Since there is only one output, the DATA
leaves the shift register one bit at a time in a serial pattern, hence the name Serial-in to Serial-
Out Shift Register or SISO.

The SISO shift register is one of the simplest of the four configurations as it has only three
connections, the serial input (SI) which determines what enters the left hand flip-flop, the serial
output (SO) which is taken from the output of the right hand flip-flop and the sequencing clock
signal (Clk). The logic circuit diagram below shows a generalized serial-in serial-out shift register.

4-bit Serial-in to Serial-out Shift Register

Fig.6.5 -4-bit Serial-in to Serial-out Shift Register

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 Digital Circuit Design

You may think what's the point of a SISO shift register if the output data is exactly the same as
the input data. Well this type of Shift Register also acts as a temporary storage device or as a
time delay device for the data, with the amount of time delay being controlled by the number of
stages in the register, 4, 8, 16 etc or by varying the application of the clock pulses. Commonly
available IC's include the 74HC595 8-bit Serial-in/Serial-out Shift Register all with 3-state
outputs.

Parallel-in to Serial-out (PISO)

The Parallel-in to Serial-out shift register acts in the opposite way to the serial-in to parallel-out
one above. The data is loaded into the register in a parallel format i.e. all the data bits enter
their inputs simultaneously, to the parallel input pins PA to PD of the register. The data is then
read out sequentially in the normal shift-right mode from the register at Q representing the data
present at PA to PD.
This data is outputted one bit at a time on each clock cycle in a serial format. It is important to
note that with this system a clock pulse is not required to parallel load the register as it is
already present, but four clock pulses are required to unload the data.
4-bit Parallel-in to Serial-out Shift Register

Fig.6.6 -4-bit Parallel -in to Serial-out Shift Register

As this type of shift register converts parallel data, such as an 8-bit data word into serial format,
it can be used to multiplex many different input lines into a single serial DATA stream which can
be sent directly to a computer or transmitted over a communications line. Commonly available
IC's include the 74HC166 8-bit Parallel-in/Serial-out Shift Registers.

Parallel-in to Parallel-out (PIPO)

The final mode of operation is the Parallel-in to Parallel-out Shift Register. This type of register
also acts as a temporary storage device or as a time delay device similar to the SISO
configuration above. The data is presented in a parallel format to the parallel input pins P A to PD
and then transferred together directly to their respective output pins QA to QA by the same clock
pulse. Then one clock pulse loads and unloads the register. This arrangement for parallel loading
and unloading is shown below.

6
 Digital Circuit Design

4-bit Parallel-in to Parallel-out Shift Register

Fig.6.7 4-bit Parallel-in to Parallel-out Shift Register

The PIPO shift register is the simplest of the four configurations as it has only three connections,
the parallel input (PI) which determines what enters the flip-flop, the parallel output (PO) and
the sequencing clock signal (Clk).

Similar to the Serial-in to Serial-out shift register, this type of register also acts as a temporary
storage device or as a time delay device, with the amount of time delay being varied by the
frequency of the clock pulses. Also, in this type of register there are no interconnections
between the individual flip-flops since no serial shifting of the data is required.

Universal Shift Register:

Today, high speed bi-directional "universal" type Shift Registers such as the TTL 74LS194,
74LS195 or the CMOS 4035 are available as a 4-bit multi-function devices that can be used in
either serial-to-serial, left shifting, right shifting, serial-to-parallel, parallel-to-serial, and as a
parallel-to-parallel multifunction data register, hence the name "Universal". These devices can
perform any combination of parallel and serial input to output operations but require additional
inputs to specify desired function and to pre-load and reset the device.

4-bit Universal Shift Register 74LS194

Fig.6.8 4-bit Universal Shift Register 74LS194

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 Digital Circuit Design

Universal shift registers are very useful digital devices. They can be configured to respond to
operations that require some form of temporary memory, delay information such as the SISO or
PIPO configuration modes or transfer data from one point to another in either a serial or parallel
format. Universal shift registers are frequently used in arithmetic operations to shift data to the
left or right for multiplication or division.

Summary of Shift Registers

o A simple Shift Register can be made using only D-type flip-Flops, one flip-Flop for each data
bit.
o The output from each flip-Flop is connected to the D input of the flip-flop at its right.
o Shift registers hold the data in their memory which is moved or "shifted" to their required
positions on each clock pulse.
o Each clock pulse shifts the contents of the register one bit position to either the left or the
right.
o The data bits can be loaded one bit at a time in a series input (SI) configuration or be loaded
simultaneously in a parallel configuration (PI).
o Data may be removed from the register one bit at a time for a series output (SO) or removed
all at the same time from a parallel output (PO).
o One application of shift registers is converting between serial and parallel data.
o Shift registers are identified as SIPO, SISO, PISO, PIPO, and universal shift registers.
The Ring Counter:
In the previous Shift Register tutorial we saw that if we apply a serial data signal to the input of
a serial-in to serial-out shift register, the same sequence of data will exit from the last flip-flip in
the register chain after a preset number of clock cycles thereby acting as a sort of time delay
circuit to the original signal.
But what if we were to connect the output of this shift register back to its input so that the
output from the last flip-flop, QD becomes the input of the first flip-flop, DA. We would then
have a closed loop circuit that "recirculates" the DATA around a continuous loop for every state
of its sequence, and this is the principal operation of a Ring Counter. Then by looping the output
back to the input, we can convert a standard shift register into a ring counter. Consider the
circuit below.
4-bit Ring Counter

Fig.6.9 4-bit Ring Counter

8
 Digital Circuit Design

The synchronous Ring Counter example above, is preset so that exactly one data bit in the
register is set to logic "1" with all the other bits reset to "0". To achieve this, a "CLEAR" signal
is firstly applied to all the flip-flops together in order to "RESET" their outputs to a logic "0"
level and then a "PRESET" pulse is applied to the input of the first flip-flop ( FFA ) before the
clock pulses are applied. This then places a single logic "1" value into the circuit of the ring
counter.

So on each successive clock pulse, the counter circulates the same data bit between the four
flip-flops over and over again around the "ring" every fourth clock cycle. But in order to cycle
the data correctly around the counter we must first "load" the counter with a suitable data
pattern as all logic "0's" or all logic "1's" outputted at each clock cycle would make the ring
counter invalid.

This type of data movement is called "rotation", and like the previous shift register, the
effect of the movement of the data bit from left to right through a ring counter can be
presented graphically as follows along with its timing diagram:

Rotational Movement of a Ring Counter

Fig.6.10(A) Rotational Movement of a Ring Counter

Fig.6.10(B) Rotational Movement of a Ring Counter

Since the ring counter example shown above has four distinct states, it is also known as a
"modulo-4" or "mod-4" counter with each flip-flop output having a frequency value equal to
one-fourth or a quarter (1/4) that of the main clock frequency.

9
 Digital Circuit Design

The "MODULO" or "MODULUS" of a counter is the number of states the counter counts or
sequences through before repeating itself and a ring counter can be made to output any
modulo number. A "mod-n" ring counter will require "n" number of flip-flops connected
together to circulate a single data bit providing "n" different output states.

For example, a mod-8 ring counter requires eight flip-flops and a mod-16 ring counter would
require sixteen flip-flops. However, as in our example above, only four of the possible sixteen
states are used, making ring counters very inefficient in terms of their output state usage.

Johnson Ring Counter:

The Johnson Ring Counter or "Twisted Ring Counters", is another shift register with feedback
exactly the same as the standard Ring Counter above, except that this time the inverted output
Q of the last flip-flop is now connected back to the input D of the first flip-flop as shown below.
The main advantage of this type of ring counter is that it only needs half the number of flip-flops
compared to the standard ring counter then its modulo number is halved. So a "n-stage"
Johnson counter will circulate a single data bit giving sequence of 2n different states and can
therefore be considered as a "mod-2n counter".
4-bit Johnson Ring Counter

Fig.6.11 4-bit Johnson Ring Counter

This inversion of Q before it is fed back to input D causes the counter to "count" in a
different way. Instead of counting through a fixed set of patterns like the normal ring
counter such as for a 4-bit counter, "0001"(1), "0010"(2), "0100"(4), "1000"(8) and repeat,
the Johnson counter counts up and then down as the initial logic "1" passes through it to the
right replacing the preceding logic "0".

A 4-bit Johnson ring counter passes blocks of four logic "0" and then four logic "1" thereby
producing an 8-bit pattern. As the inverted output Q is connected to the input D this 8-bit
pattern continually repeats. For example, "1000", "1100", "1110", "1111", "0111", "0011",
"0001", "0000" and this is demonstrated in the following table below.

As well as counting or rotating data around a continuous loop, ring counters can also be
used to detect or recognise various patterns or number values within a set of data. By
connecting simple logic gates such as the AND or the OR gates to the outputs of the flip-

10
 Digital Circuit Design

flops the circuit can be made to detect a set number or value. Standard 2, 3 or 4-stage
Johnson ring counters can also be used to divide the frequency of the clock signal by varying
their feedback connections and divide-by-3 or divide-by-5 outputs are also available
Truth Table for a 4-bit Johnson Ring Counter
Clock Pulse No FFA FFB FFC FFD
0 0 0 0 0
1 1 0 0 0
2 1 1 0 0
3 1 1 1 0
4 1 1 1 1
5 0 1 1 1
6 0 0 1 1
7 0 0 0 1
.
A 3-stage Johnson Ring Counter can also be used as a 3-phase, 120 degree phase shift square
wave generator by connecting to the data outputs at A, B and NOT-B. The standard 5-stage
Johnson counter such as the commonly available CD4017 is generally used as a synchronous
decade counter/divider circuit. The smaller 2-stage circuit is also called a "Quadrature"
(sine/cosine) Oscillator/Generator and is used to produce four individual outputs that are each
"phase shifted" by 90 degrees with respect to each other, and this is shown below.
2-bit Quadrature Generator

Fig6.12 2-bit Quadrature Generator

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 Digital Circuit Design

Output A B C D
QA+QB 1 0 0 0
QA+QB 0 1 0 0
QA+QB 0 0 1 0
QA+QB 0 0 0 1
2-bit Quadrature Oscillator, Count
Sequence

As the four outputs, A to D are phase shifted by 90 degrees with regards to each other, they
can be used with additional circuitry, to drive a 2-phase full-step stepper motor for position
control or the ability to rotate a motor to a particular location as shown below.

Stepper Motor Control

2-phase (unipolar) Full-Step Stepper Motor Circuit

Fig.6.13 Stepper Motor Control

The speed of rotation of the Stepper Motor will depend mainly upon the clock frequency
and additional circuitry would be require to drive the "power" requirements of the motor.
As this section is only intended to give the reader a basic understanding of Johnson Ring
Counters and its applications, other good websites explain in more detail the types and
drive requirements of stepper motors.

Johnson Ring Counters are available in standard TTL or CMOS IC form, such as the CD4017
5-Stage, decade Johnson ring counter with 10 active HIGH decoded outputs or the CD4022
4-stage, divide-by-8 Johnson counter with 8 active HIGH decoded outputs.

12
 Digital Circuit Design

Example on Design of Counters:

This example is taken from T. L. Floyd, Digital Fundamentals, Fourth Edition, Macmillan
Publishing, 1990, p.395.

Example: A counter is first described by a state diagram, which is shows the sequence of
states through which the counter advances when it is clocked. Figure 2.40 shows a state
diagram of a 3-bit binary counter.

Fig.6.14 State diagram of a 3-bit Binary

counter.

The circuit has no inputs other than the clock pulse and no outputs other than its internal
state (outputs are taken off each flip-flop in the counter). The next state of the counter
depends entirely on its present state, and the state transition occurs every time the clock
pulse occurs. Figure 2.41 shows the sequences of count after each clock pulse.

Once the sequential circuit is defined by the state diagram, the next step is to obtain the
next-state table, which is derived from the state diagram in Figure 2.40 and is shown in
Table1.

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 Digital Circuit Design

Table 1:State table

Present State Next State

Q2 Q1 Q0 Q2 Q1 Q0

0 0 0 0 0 1
0 0 1 0 1 0
0 1 0 0 1 1
0 1 1 1 0 0
1 0 0 1 0 1
1 0 1 1 1 0
1 1 0 1 1 1
1 1 1 0 0 0

Since there are eight states, the number of flip-flops required would be three. Now we want
to implement the counter design using JK flip-flops.

Next step is to develop an excitation table from the state table, which is shown in Table2.

Table2:. Excitation table

Output State Transitions Flip-flop inputs

Present State Next State
Q2 Q1 Q0 Q2 Q1 Q0 J2 K2 J1 K1 J0 K0

0 0 0 0 0 1 0X 0X 1X
0 0 1 0 1 0 0X 1X X1
0 1 0 0 1 1 0X X0 1X
0 1 1 1 0 0 1X X1 X1
1 0 0 1 0 1 X0 0X 1X
1 0 1 1 1 0 X0 1X X1
1 1 0 1 1 1 X0 X0 1X
1 1 1 0 0 0 X1 X1 X1
S

14
 Digital Circuit Design

Fig.6.15 Kmap

Now transfer the JK states of the flip-flop inputs from the excitation table to Karnaugh maps
to derive a simplified Boolean expression for each flip-flop input. This is shown in Figure 2.41

The 1s in the Karnaugh maps of Figure 2.41 are grouped with "don't cares" and the following
expressions for the J and K inputs of each flip-flop are obtained:

J0 = K0 = 1
J1 = K1 = Q0
J2 = K2 = Q1*Q0

The final step is to implement the combinational logic from the equations and connect the
flip-flops to form the sequential circuit. The complete logic of a 3-bit binary counter is shown
in Figure 2.42.

Fig.6.16 Logic diagram of a 3-bit binary counter

This example is taken from M. M. Mano, Digital Design, Prentice Hall, 1984, p.243.

Example Design a counter specified by the state diagram in using T flip-flops. The state diagram
is shown here again in Figure 6.17.

15
 Digital Circuit Design

Fig. 6.17. State diagram of a 3-bit binary counter.

The state table will be the same as in Example 6.17.

Now derive the excitation table from the state table, which is shown in Table 3.

Table 3. Excitation table.

Output State Transitions Flip-flop inputs
Present State Next State
Q2 Q1 Q0 Q2 Q1 Q0 T2 T1 T0

0 0 0 0 0 1 0 0 1
0 0 1 0 1 0 0 1 1
0 1 0 0 1 1 0 0 1
0 1 1 1 0 0 1 1 1
1 0 0 1 0 1 0 0 1
1 0 1 1 1 0 0 1 1
1 1 0 1 1 1 0 0 1
1 1 1 0 0 0 1 1 1

Next step is to transfer the flip-flop input functions to Karnaugh maps to derive a simplified
Boolean expressions, which is shown in Figure 2.44.

Fig.6.18 K-Maps

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 Digital Circuit Design

The following expressions are obtained:

T0 = 1; T1 = Q0; T2 = Q1*Q0

Finally, draw the logic diagram of the circuit from the expressions obtained. The complete logic
diagram of the counter is shown in Figure 6.19.

Fig.6.19. Logic diagram of 3-bit binary counter.

6.9 Questions:
6.9.1 Objective Questions:

Que.1] With neat diagram explain the 4 bit Parallel in Parallel out (PIPO) register draw timing
diagram and wave form and its Truth Table

Que.2] With neat diagram explain the 4 bit Serial in Serial out (SISO) register draw timing
diagram and wave form and its Truth Table

Que.3] Define bi-directional Shift register ?Draw the 3 bit bi-Directional shift Register using D-
type Flip Flop

6.9.2 Short Questions:

Que1] Design 4 bit Twisted Ring counter (Johnson’s counter)using Flip Flop of your choice

Que.2] What is the function shift Register? give its applications

Que.3] With neat diagram explain the 4 bit serial in parallel out (SIPO) register draw timing
diagram and wave form and its Truth Table

Que.4] With neat diagram explain the 4 bit Parallel in Serial out (PISO) register draw timing
diagram and wave form and its Truth Table

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 Digital Circuit Design

6.9.3 Long Questions:

Que.1] What do mean by Universal Shift Register ?List one of IC used shift register give pin
configuration with specifications

Que.2] Explain glitch problem along with wave forms

Que.3] Design MOD13 counter using T flip flop

Que.4] Design 4 bit sync universal up/down counter

Que.5] Design 4 bit ripple counter using T flip-flop with suitable circuit diagram and timing
diagram

Que.6] What are the application of counters ?state the procedure to design MOD counter from
N bit ripple counter

Que.7] What is Synchronous counter ,Explain working 4 bit ripple counter

Q8. Design a sequential circuit specified by Table Q.1, using JK flip-flops.

Table Q.1

Present State Next State Output

Q0 Q1 x=0 x=1 x=0 x=1

00 00 01 0 0
01 00 10 0 0
10 11 10 0 0
11 00 01 0 1
Q9 Design the sequential circuit in question1, using T flip-flops.

Q10. Design a mod-5 counter which has the following binary sequence: 0, 1, 2, 3, 4. Use JK flip-
flops.

Q11. Design a counter that has the following repeated binary sequence: 0, 1, 2, 3, 4, 5, 6, 7. Use
RS flip-flops.

Q12. Design a counter with the following binary sequence: 1, 2, 5, 7 and repeat. Use JK flip-
flops.

Q13. Design a counter with the following repeated binary sequence: 0, 4, 2, 1, 6. Use T flip-flops.

Q14. Design a counter that counts in the sequence 0, 1, 3, 6, 10, 15, using four a) D, b) SR, c) JK
and d) T flip-flops.

18