UNIT-2

DELAY
 The delay of a logic circuit defines how quickly it responds to a
change at its input(s).
 Delay expresses the delay experienced by a signal when passing
through a gate.
 The delay determines the input to output signal dealy during high-
to-low and low-to-high transitions of the output.
 The delay of each gate is controlled by its driving resistance and
load capacitance.
 It is measured between the 50% transition points of the input and
output waveforms. This is called propagation delay of logic gates.
Timing analysis
 The nodes are classified as inputs, outputs, and internal nodes. The
user must specify the arrival time of inputs and the time data is
required at the outputs. The arrival time ai at internal node i
depends on the propagation delay of the gate driving i and the
arrival times of the inputs to the gate:

 The timing analyzer computes the arrival times at each node and
checks that the outputs arrive by their required time. The slack is
the difference between the required and arrival times. Positive
slack means that the circuit meets timing. Negative slack means
that the cir- cuit is not fast enough.
 TRANSIENT RESPONSE
 The most fundamental way to compute delay is to develop a
physical model of the circuit of interest, write a differential
equation describing the output voltage as a function of input
voltage and time, and solve the equation. The solution of the
differential equation is called the transient response, and the delay
is the time when the output reaches VDD /2.
 The differential equation is based on charging or discharging of the
capacitances in the circuit. The circuit takes time to switch because
the capacitance cannot change its voltage instantaneously. If
capacitance C is charged with a current I, the voltage on the
capacitor varies as:
I = C dv/dt
Unit Transistor
Second order system
 R1 and R2 might model the two series nMOS transistors in a NAND gate
or an inverter driving a long wire with non-negligible
 resistance. The transfer function is

Equation is so complicated that it

defeats the purpose of simplifying a
CMOS circuit into an equivalent RC
network. However, it can be further
approximated as a firstorder
system with a single time constant:
 Approximation

 This approximation works best when one time constant is significantly bigger than the other.
 For example, if R1 = R2 = R and C1 = C2 = C, then τ1= 2.6 RC,
 τ2 = 0.4 RC, τ = 3 RC and the second-order response and its first-order approximation are shown in
Figure below.

 The error in estimated propagation delay from the first-order approximation is less than 7%. Even in
the worst case, where the two time constants are equal, the error is less than 15%
 Simple single time constant approximation for general RC tree circuits
 using the Elmore delay model.
UNIT-2 Elmore Delay Model, Asst. Prof. Anup Kumar, ECE Department AKGEC, Ghaziabad
UNIT-2 Elmore Delay Model, Asst. Prof. Anup Kumar, ECE Department AKGEC, Ghaziabad
 Linear delay model
 The RC delay model showed that delay is a linear function of the
fanout of a gate. Based on this observation, designers further
simplify delay analysis by characterizing a gate by the slope and
y-intercept of this function. In general, the normalized delay of a
gate can be expressed in units of as
 d=f+p
 p is the parasitic delay inherent to the gate when no load is
attached. f is the effort delay or stage effort that depends on the
complexity and fanout of the gate:
 f = gh
 Logical effort
 Delay of a logic gate is composed of the delay due to
parasitic delay p(no load delay) and the delay due to
load(effort delay or stage effort f).
 A template circuit is chosen as the basis upon which other
gates are scaled. The scaling factor is 𝛼.
 Ct is the input cap of the template.
 Rt is the Pull-up or Pull-down resistance of the template.
 Cpt is the parasitic capacitance of the template.
 Cin = 𝛼Ct Input capacitance scales up
 Ri = Rui = Rdi = Rt/ 𝛼 Channel resistance scaled down
 Cpi = 𝛼Cpt Parasitic scale up
 Dabs = k Ri(Cout + Cpi)
 = k (Rt/ 𝛼) Cin (𝛼 Cout/Cin) + k (Rt/ 𝛼)(𝛼Cpt)
 = (k Rt Ct) (Cout/Cin) + kRtCpt
Multiply and divide by RinvCinv
(k Rt Ct) (Cout/Cin) + kRtCpt
Dabs = Rinv Cinv
Rinv Cinv
RtCt Cout RtCpt
Dabs = k RinvCinv +k
RinvCinv Cin RinvCinv
Dabs = 𝜏 ( g h + p )
 Logical effort of a gate is defined as the ratio of the input
capacitance of the gate to the input capacitance of an inverter that
can deliver the same output current.
 Logical effort indicates how much worse a gate is at producing
output current as compared to an inverter, given that each input of
the gate may only present as much input capacitance as the inverter.
 Logical effort can be measured in simulation from delay vs. fanout
plots as the ratio of the slope of the delay of the gate to the slope of
the delay of an inverter.
 The parasitic delay of a gate is the delay of the gate when it drives
zero load. It can be estimated with RC delay models.
Logical effort for Multi input
The effort tends to increase with the number of inputs. NAND
gates are better than NOR gates because the series transistors
are nMOS rather than pMOS.
The parasitic delay of a gate is the delay of the gate when it
drives zero load. It can be estimated with RC delay models.
A crude method good for hand calculations is to count only
diffusion capacitance on the output node.
https://www.youtube.com/watch?v=hFjcWBjL-
wc
Delay in Multistage Logic Networks
 The path logical effort G can be expressed as the products
of the logical efforts of each stage along the path.
 G = ς 𝑔𝑖
 The path electrical effort H can be given as the ratio of the
output capacitance the path must drive divided by the
input capacitance presented by the path
Cout(path)
H =
Cin(path)
 The path effort F is the product of the stage efforts of each
stage. Recall that the stage effort of a single stage is f = gh.
 F = ς fi = ς 𝑔𝑖 ℎi
 Branch Effort
 If branch occurs in the path then F = GH is no longer
valid. Consider a path from the primary input to one of
the outputs. The path logical effort is G = 1 × 1 = 1. The
path electrical effort is H = 90/5 = 18. Thus, GH = 18.
 But F= f1f2 = g1h1g2h2 =1×6×1×6=36. In other words, F=2GH
in this path on account of the two-way branch.
 This branching effort b is the ratio of the total capacitance
seen by a stage to the capacitance on the path
Conpath+Coffpath
 b=
Conpath
 The path branching effort B is the product of the
branching efforts between stages.
 B = ς 𝑏𝑖
 We can define the path effort F as the product of the
logical, electrical, and branching efforts of the path. Note
that the product of the electrical efforts of the stages is
actually BH, not just H.
 F = GBH
 We can now compute the delay of a multistage network. The path
delay D is the sum of the delays of each stage. It can also be written
as the sum of the path effort delay DF and path parasitic delay P:
 D = σ 𝑑𝑖 = 𝐷𝐹 + 𝑃
 DF = σ 𝑓𝑖
 P = σ 𝑝𝑖
 The product of the stage efforts is F, independent of gate sizes. The
path effort delay is the sum of the stage efforts. the path delay is
minimized when each stage bears the same effort. If a path has N
stages and each bears the same effort, that effort must be
ˆ

 𝑓መ = gi hi = F 1/N
 Thus, the minimum possible delay of an N-stage path with
path effort F and path parasitic delay P is
 D = NF1/N + P
 It shows that the minimum delay of the path can be
estimated knowing only the number of stages, path effort,
and parasitic delays without the need to assign transistor
sizes.
 The capacitance transformation formula to find the best
input capacitance for a gate given the output capacitance
it drives.
 f=gh
𝐶𝑜𝑢𝑡
h =
𝐶𝑖𝑛
𝐶𝑜𝑢𝑡
f = g
𝐶𝑖𝑛
𝐶𝑜𝑢𝑡 𝑔𝑖
 Cin =
𝑓መ
 Starting with the load at the end of the path, work backward
applying the capacitance transformation to determine the
size of each stage. Check the arithmetic by verifying that the
size of the initial stage matches the specification.
 Estimate the minimum delay of the path from A to B in following Figure
and choose transistor sizes to achieve this delay. The initial NAND2 gate
may present a load of 8 of transistor width on the input and the output
load is equivalent to 45 of transistor width.
 The path logical effort is G = (4/3) × (5/3) × (5/3) = 100/ 27.
 The path electrical effort is H = 45/8.
 The path branching effort is B = 3 × 2 = 6.
 The path effort is F = GBH = 125.
 As there are three stages, the best stage effort is f = 125 = 5 .
 The path para- sitic delay is P = 2 + 3 + 2 = 7.
 Hence, the minimum path delay is D = 3 × 5 + 7 = 22 unit
 The gate sizes are computed with the capacitance transformation
from equqtion working backward along the path:
 y = 45 × (5/3)/5 = 15.
 x = (15 + 15) × (5/3)/5 = 10.
 We verify that the initial 2-input NAND gate has the specified
size of (10 + 10 + 10) × (4/3)/5 = 8.
 If the total input capacitance is 15, the pMOS width must be 12
and the nMOS width must be 3 to achieve that ratio.
 Example of Minimizing delay: Consider the path from A to B involving
three two input NAND gates. The input capacitance of first gate is C and
the load capacitance is also C . Find the least delay in this path and how
should the transistors be sized to achieve least delay?