EE Department DSD
EE-421 Digital System Design
Laboratory Manual
For
B.E. Electrical Engineering
Group Members
Degree Syndicate
Instructor:
Dr. Usman Ali
CEME (NUST), Rawalpindi 1
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Standard Equipments and Components;
Software:
1) Xilinx ISE, Intel Quartus
2) Modelsim
Hardware:
FPGA kit
Desktop PC
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EE-421 Digital System Design
List of Experiments
S.NO. EXPERIMENT
01 Introduction To Modelsim &Xilinx
02 Design of Half Adder, Full Adder, 4 bit Ripple Carry Adder at
various abstraction levels
03 Implementation of sequential circuits
04 Introduction and use of Xilinx cores and Simulation of math
functions & memories
05 Design and Simulation of Arithmetic Logic Unit
06 Simulation of a FIR and IIR filters on fully dedicated
architecture
07 Implementation of Fast Adders
08 Implementation of Parallel Barrel Shift and Multiplier
09 Introduction to FPGA, Implementation of a Clock divider circuit
on FPGA kit
10 ASM (Algorithmic State Machine ) design of binary pattern
detection in binary data stream
11 Simulation of a Shift-and-Add Multiplier Circuit using
Algorithmic State Machine
12 Simulation of an Enhanced Divider Circuit using Algorithmic
State Machine
13 Micro-coded FSM design of four 1s detection in binary stream
14 Project lab: Design of Micro Programmed State Machine with
ALU and register file
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Lab#1: Introduction to ModelSim/Xilinx ISE
GROUP MEMBERS 1.
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3.
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INSTRUCTOR
Step 1
Find the Xilinx ISE 12.1 shortcut on desktop and run the program. This opens the
following window on your screen.
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There are 3 main panes, SOURCES, PROCESSES and TRANSCRIPT. SOURCES pane
lists all your source files in proper hierarchy (as long as files are instantiated properly)
and for different purposes of simulation and synthesis. PROCESSES pane lists all the
processes that can be run on the files and TRANSCRIPT pane gives a log of all the
commands run. The errors/warnings in code can also be looked at in the TRANSCRIPT
pane.
Step 2
Create a new project in Xilinx ISE 12.1 as described below.
a.Click on FILE >> NEW PROJECT. A window pops-up.
b. Type Lab01 as project name (You can give the project any name you want to). Set the
work-directory for project and select HDL for Top-Level Source Type field.
c. Click on NEXT.
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d. On the next screen, you can select your target device. Set the options as per the picture
below and then click on NEXT. (This will be covered later in the course)
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e.Create New Source:click on the NEW SCREEN button to create a new source file
automatically where the tool writes the first few lines of code automatically mentioning
the ports, their size and direction.
f. Select VERILOG MODULE from different file types on the left-hand menu. In the file
name field, type the name of Verilog file e.g. Lab01. Click on NEXT.
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g. Type the names of the input/output ports and select their type from the Direction
dropdown
list.
Input ports for this module are
A, B, C and D which are all 1-bit inputs
Outputs for this module are E and F which are also a1-bit signals.
Then click on NEXT.
h. On the next screen, click on FINISH. Xilinx will ask for permission to create the target
work-directory for the project (if not already there).
When the file is created/added, it is listed in the SOURCES pane.
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The PROCESSES pane lists the processes that can be performed on this file.
Since, we are only interested in simulation at this stage, change the
SYNTHESIS/IMPLEMENTATION option to SIMULATION.
Since, we are only interested in simulation at this stage, change the
SYNTHESIS/IMPLEMENTATION option to SIMULATION.Note the list of processes
in the PROCESSES pane changed by changing the option to SIMULATION
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Write the following code in a new source-file.
To test the functionality of the written code, we’ll write another code which provides test
signals for the inputs in our circuit. In the SOURCES pane, right-click and select NEW
SOURCE.New Source Wizard window pops up. Create the testbenchfile.Remember that
the testbench does not have any ports. The code for testbench is as follows.
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Note the hierarchy changing in the SOURCES pane. Since, testbench is ‘calling’
“combo_boolean”, it is shown as the top-level file in hierarchy.
In Verilog HDL, the process of calling another module is called “Instantiation”.
In the SOURCES pane, select the testbench file and see the available processes for it.
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Click on SIMULATE BEHAVIORAL MODEL to start the simulation.
After clicking on SIMULATE BEHAVIORAL MODEL, ModelSim SE 6.5 is launched
which simulates the circuit. It opens a number of windows which are briefly explained by
their window title.
Task 1:
Design a 4 to 1 multiplexer circuit and implement it in modelsim. Make a test bench for
simulation.
Task 2:
Design a 4 to 1 multiplexer circuit and implement it in Xilinx. Make a test bench for
simulation.
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Lab#2: Design of Half Adder, Full Adder, 4 bit Adders at various
abstraction levels
GROUP MEMBERS 1.
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INSTRUCTOR
Objective;
In this lab you will learn:
• modeling at Gate level
• modeling at Dataflow level
• modeling at Behavioral level
Part (A);
Write Verilog code/module in Gate level, Data flow level and Behavioral level for
Half and Full Adder.
Background;
The simplest form of adder is called a Half-Adder (HA). The HA performs bit-wise
addition between two input bits. Depending on the result of the operation, the HA either
sets or clears its Sum and Carry bit. A HA can be expanded to include the logic for
carry—in, and the modified unit is called the Full Adder (FA).
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1) Gate level Design;
At gate level, the circuit is described in terms of gates (e.g; and, or, xor). Hardware
design at this level is intuitive for a user with a basic knowledge of digital logic design because it
is possible to see a one-to-one correspondence between the logic circuit diagram and the
Verilog description.
2) Dataflow level Design;
Dataflow modeling provides a powerful way to implement a design. Verilog allows a
circuit to be designed in terms of the data flow between registers and how a design processes
data rather than instantiation of individual gates.
3) Behavioral level Design
With the increasing complexity of digital design, it has become vitally important to make
wise design decisions early in a project. Designers need to be able to evaluate the trade-offs of
various architectures and algorithms before they decide on the optimum architecture and
algorithm to implement in hardware. Thus, architectural evaluation takes place at an algorithmic
level where the designers do not necessarily think in terms of logic gates or data flow but in
terms of the algorithm they wish to implement in hardware. They are more concerned about
the behavior of the algorithm and its performance. Only after the high-level architecture and
algorithm are finalized, do designers start focusing on building the digital circuit to implement
the algorithm. Verilog provides designers the ability to describe design functionality in an
algorithmic manner. In other words, the designer describes the behavior of the circuit. Thus,
behavioral modeling represents the circuit at a very high level of abstraction.
Tasks :
1) Write a Verilog code for Half adder, Full adder and 4-bit adder at various
abstraction level.
2) Verify the arithmetic, logical and relational operators by coding at Data flow
level.
3) Write a test bench for verifying the functionality.
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Lab#3: Implementation of sequential circuits
GROUP MEMBERS 1.
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INSTRUCTOR
Objective
In this lab, you will build:
1) implementation of 4-bit Up/Down loaded Counter.
2) implementation of universal shift register
Task 1:
Design a 4-bit up/down counter and write a Verilog code for it on
modelsim/Xilinx. Write a test bench code.
en out[3]
clk out[2]
up/down Counter out[1]
out[0]
LV
LE
Task 2:
Design a 4-bit universal shift register and write a Verilog code for it on
modelsim/Xilinx. Write a test bench code.
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Lab#4: Introduction and use of Xilinx cores and Simulation of math
functions & memories
GROUP MEMBERS 1.
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INSTRUCTOR
Task 1:
(a) Use Xilinx IP Core to simulate a 4-bit adder ,Multiplier And Divider.
(b) Vary the Latency and observe the response.
Task 2:
(a) Design a memory named MEM containing 256 words of 64 bits each.
(b) Write a code for RAM in write First mode.
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Lab#5: Design and Simulation of Arithmetic Logic Unit
GROUP MEMBERS 1.
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Task :
(a) Design an ALU as shown in the figure below performing the desired set of
functions, i.e., (A+B), (A-B), (A*B), (A>B)
(b) Make a ROM for storing the information of select pins of multiplexers,
demultiplexers, ALU.
(c) On reset store values in register 0, and register1.
(d) Execute following sequence
a. R2=R1+R0;
b. R3=R1*R0;
c. R0=R2-R3;
d. R1=(R2>R3)
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Lab#06: Simulation of a FIR and IIR filters on fully dedicated
architecture
GROUP MEMBERS 1.
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INSTRUCTOR
An IIR filter response can be described by following difference equations:
The above system can be converted to FIR if b1, b2,… coefficients become zero.
The block diagram of the system is given below:
The objective of this lab is to implement both filters in RTL verilog and study their RTL
diagram and resource utilization on FPGA.
Task1:
a. Write parameterized code to design a fixed point second order IIR filter.
b. Note down the resource utilization and synthesis frequency from the synthesis
report.
c. Show computer generated schematic diagram of the circuit.
Task2:
a. Write parameterized code to design a fixed point 8-tap FIR filter.
b. Note down the resource utilization and synthesis frequency from the synthesis
report.
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c. Show computer generated schematic diagram of the circuit.
Resource Comparison Table:
IIR Filter FIR filter
Synthesis frequency
Number of Slices
Number of Slice
FFs
Number of LUTs
Number of 18x18
multiplier
RTL block diagrams generated by software:
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Lab#7: Implementation of Fast Adders
GROUP MEMBERS 1.
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INSTRUCTOR
Carry Look Ahead adder
A simple consideration of full adder logic identifies that a carry c(i+1) is generated if
a(i) = b(i) = 1, and a carry is propagated if either a(i) or b(i) is 1. This can be written as:
Task1:
d. Write parameterized code to design a 16-bit Carry Look Ahead Adder.
e. Note down the resource utilization and synthesis frequency from the synthesis
report.
f. Show computer generated schematic diagram of the circuit.
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Carry Select Adder with uniform grouping:
Task2:
a. Write parameterized code to design a 16-bit Carry Select Adder.
b. Note down the resource utilization and synthesis frequency from the synthesis
report.
c. Show computer generated schematic diagram of the circuit.
Resource Comparison Table:
Carry Look Ahead Carry Select Ripple Carry
Adder Adder Adder
Synthesis frequency
Number of Slices
Number of Slice
FFs
Number of LUTs
Number of 18x18
multiplier
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Lab#8: Implementation of Parallel Barrel Shift and multiplier
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INSTRUCTOR
Parallel Multiplier without compression tree
Task1:
g. Write parameterized code to design a 16-bit Parallel without any compression
tree.
h. Note down the resource utilization and synthesis frequency from the synthesis
report.
i. Show computer generated schematic diagram of the circuit.
j. Compare results with dedicated 18x18 multiplier.
k. Resource Table:
Resource Table:
Parallel multiplier Dedicated Multiplier
Synthesis frequency
Number of Slices
Number of Slice FFs
Number of LUTs
Number of 18x18 mul.
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Barrel Shift:
Task2:
d. Write parameterized code to design a 8-bit Barrel shift circuit.
e. Note down the resource utilization and synthesis frequency from the synthesis
report.
f. Show computer generated schematic diagram of the circuit.
Resource Table:
Barrel shift
Synthesis frequency
Number of Slices
Number of Slice FFs
Number of LUTs
Number of 18x18 mul.
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Lab#9: Introduction to FPGA ,Implementation of Clock divider on
FPGA
GROUP MEMBERS 1.
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INSTRUCTOR
Task1:
Implement a two bit adder taking input from the onboard slider switches and
display the result on FPGA.
Step 1: Writing Verilog code of the circuit we want to implement
Step 2: Simulating the Verilog code using a simulator (ModelSim/Xilinx) to check
if the intended functionality has been achieved
Step 3: Use Xilinx PlanAhead tool to assign input and output ports to the input
out variables so it can generate a user constraint file (.ucf).
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Step 4: Synthesizing the Verilog code using a tool form Xilinx called ISE so that it
can be programmed onto an FPGA
Step 5: Program the Verilog code on the FPGA.
Step 6: Applying inputs to and observing outputs from our circuit using the
peripherals (like switches, buttons, LEDs, etc) on the FPGA board
Button 1 Button 2 Button 3 Button 4
L14 L13 N17 H18
Task 2:
Use the 50 MHz clock extracted from C9 pin of Spartan 3E in the FPGA board
design a counter which needs to increment in every second using this clock.
Output the most significant bit through LED .
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Lab#10: ASM representations of four 1s detected problem
GROUP MEMBERS 1.
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INSTRUCTOR
Introduction to ASM
ASM is a flowchart like graphical notation that describes the cycle by cycle behavior of
an algorithm. Each step transitioning from one state to another or to the same state takes
one clock cycle. The ASM is composed of three basic building blocks: rectangles,
diamonds and ovals. Arrows are used to interconnect these building blocks. Each
rectangle represents a state and the state output is written inside the rectangle. The state
output is always an unconditional output, which is asserted when the FSM transitions to a
state represented by the respective rectangle. A diamond is used for specifying a
condition. Based on whether the condition is TRUE or FALSE, the next state or
conditional output is decided. An oval is used to represent a conditional output. As Moore
machines only have state outputs, Moore FSM implementations do not have ovals, but
Mealy machines may contain ovals in their ASM representations. Figure 9.13 shows the
relationship of three basic components in an ASM representation. For TRUE or FALSE,
T and F are written on respective branches. The condition may terminate in an Oval,
which lists conditional output.
Figure 1
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Task 1:
Write Verilog code for 4-entry FIFO system by Mealy and Moore State Machines.
Simulate the code and demonstrate the results. ASM chart is shown in the figure
Figure 1 (a) Mealy Machine (b) Moore Machine
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Lab#11: Simulation of a Shift-and-Add Multiplier Circuit using
Algorithmic State Machine
GROUP MEMBERS 1.
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INSTRUCTOR
A binary multiplier can be implemented on hardware in various ways. Previously, we used
dedicated 18x18 multiplier primitive of Spartan 3E architecture. Secondly we designed
parallel multiplier using LUT resources by generating partial products and adding those using
RCAs. Both were fully dedicated architectures.
Now the objective is to implement multiplier based on time shared architecture. Each
partial product will be added in consecutive clock cycles using a single adder. The partial
products generation and addition will be controlled by Finite State Machine controller. The
Pseudo Code, ASM chart and Data Path are shown below:
Fig-1. Pseudo-code
Fig-2. Data-path
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Fig-3. ASM Chart for Multiplier
Task:
Write a Verilog code for the design shown above. Multiply two 4-bit numbers and
demonstrate the output using simulation results.
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Lab#12: Simulation of an Enhanced Divider Circuit using Algorithmic
State Machine
GROUP MEMBERS 1.
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INSTRUCTOR
The objective is to write and simulate the Verilog code for the division of two binary
numbers using state machine. The Pseudo Code, ASM chart and Data Path are shown below
(a) Pseudo-code
(b) Data Path Circuit for Enhanced Divider
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(b) ASM Chart
Task: Write Verilog code for the design shown above. Divide two 4-bit numbers and
demonstrate the output using simulation results.
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Lab#13: Micro-coded FSM design of four 1s detection in binary stream
GROUP MEMBERS 1.
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In time-shared architecture, computational units are shared to execute different
operations of the algorithm in different cycles. As described in Chapter 9, time-shared
architecture consists of a datapath and a control unit. In each clock cycle the control unit
generates appropriate control signals for the datapath. In hardwired state machine-
based designs, the controller is implemented as a Mealy or Moore finite state machine
(FSM).
However, in many applications the algorithms are so complex that a hardwired
FSM design is not feasible. In other applications, either several algorithms need to be
implemented on the same datapath or the designer wants to keep the flexibility of
modifying the controller without repeating the entire design cycle, so a flexible
controller is implemented to use the same datapath for different algorithms. The
controller is made programmable using a program memory. This type of FSM is known
as Micro-coded State Machine.
Fig. 13-1 Micro-programmed state machine design showing program memory and state register
A micro-programmed state machine stores the entire output sequence of control
signals along with the associated next state in program memory. The address of the
contents in the memory is determined by the current state and input to the FSM.
This experiment designs a state machine that implements the four 1s detection
problem of Experiment 10, where the same was realized as hardwired Mealy and Moore
state machines.
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Fig. 13-2 ASMchart for four 1s detected problem and equivalent micro-programmed state machine
design
Task:
Write a Verilog code for the design FSM shown in fig. 13-2. Demonstrate the inputs and
outputs of the FSM using simulation results.
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Lab#14: Micro Programmed State Machine Design
GROUP MEMBERS 1.
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INSTRUCTOR
The objective is to design, simulate and implement a micro-coded state machine as
shown in the figure:
Figure 1
The design supports a program that uses the following set of micro codes:
R1=8; R2=5;
R3=R1+R2;
R1=R3*R2;
+,-,AND,OR
if(N) jump label
if(!N) jump label
if(Z) jump label
if(!Z) jump label
jump label
Register = value
The following diagrams show Non-overlapping fields and Overlapping fields (to
reduce the width of the PM) in the micro code of programmable state machine ,
respectively
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Task 1: Design the micro programmed state machine and execute the following set of
instructions
label0 : R0 = 50
R1 = -7
R2 = R0+R1
label1: R2 = R2+R1
if(!N)
jump label1
Note: Add extra logic for writing data to the registers R7…R0
Registers R7…R0 are 8-bit registers
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