Brac University ID: Name:
Semester: Summer 2024
Course Code: CSE460
VLSI Design Set
Section: ■ Assessment: Assignment 2
Faculty: KFP Full Marks: 50
✓ No washroom breaks. Phones must be turned off. Using/carrying any notes during the exam is not allowed.
✓ At the end of the exam, both the answer script and the question paper must be returned to invigilator.
✓ All 5 questions are compulsory. Marks allotted for each question are mentioned beside each question.
✓ Write your answers inside the indicated boxes where applicable.
✓ Symbols have their usual meanings.
■ Question 1 of 5 [CO2] [10 marks]
Here the fill boxes are metal and the circles are obstacles
CSE460 Summer 2024 Assignment 2 ▶ Set Page 2 of 6
i. Find the shortest path for each target using Lee’s maze routing. [7 Marks]
ii. If the maximum memory is set to 120 bytes, then calculate the bit number [3 marks]
CSE460 Summer 2024 Assignment 2 ▶ Set Page 3 of 6
■ Question 2 of 5 [CO2] [10 marks]
(a)Draw the corresponding graph representation of the above circuit.
(b)Perform the KL algorithm on the graphical representation. Perform pass as many as needed to get the optimum
circuit.
CSE460 Summer 2024 Assignment 2 ▶ Set Page 4 of 6
■ Question 3 of 5 [CO2] [10 marks]
3. A digital system-on-a-chip in a 1V 65 nm process (with 50 nm drawn channel lengths and λ=25 nm) has 2.1
billion transistors, of which 100 million are used for building logic gates and the rest are used in memory arrays. The
average logic transistor width is 14λ and the average memory transistor width is 6λ. The memory arrays are divided
into banks and only the necessary bank is activated, so the memory activity factor is 0.03. The static CMOS logic
gates have an average activity factor of 0.15. Assume each transistor contributes 1.01 fF/µm of gate capacitance and
0.84 fF/µm of diffusion capacitance. Neglect the wire capacitance.
(a) i) What are the capacitance values of total logic gates and memory arrays?
(b) ii) What is the switching power when the operating frequency is 1 GHz?
CSE460 Summer 2024 Assignment 2 ▶ Set Page 5 of 6
■ Question 4 of 5 [CO2] [10 marks]
Consider the following logic circuit, driven by a system frequency of 1 GHz and a supply voltage of 3.2 V. The inputs
to the circuit are A, B, C, and D, while the output node is Y. N1 and N2 are intermediate nodes. The activity factors
of nodes N1, N2, and Y concerning the system frequency are given in Table 1. The input and output capacitances of
the individual logic gates are listed in Table 2.
a. Find out the total capacitances at nodes N1, N2, and Y.
b. Compute the total switching power of the logic circuit, assuming no power is being consumed at nodes A, B, C,
and D.
CSE460 Summer 2024 Assignment 2 ▶ Set Page 6 of 6
■ Question 5 of 5 [CO2] [10 marks]
The switching probabilities of nodes A, B, C, D and basic logic gates along with the node capacitances of E, F,
and G are given below:
Explanation of the second table: Say, an AND gate has two input nodes with switching probabilities of P1 and P2
The switching probability of the output node will be P1*P2. Now, if Pi is the switching probability of any node i,
the activity factor of that node can be calculated using the following equation:
For the nodes E, F and G: (a) Calculate the switching probabilities.
(b) Determine the activity factors.
(c) Calculate the switching power losses.
