ST93CS66

ST93CS67

4K (256 x 16) SERIAL MICROWIRE EEPROM

NOT FOR NEW DESIGN

1 MILLION ERASE/WRITE CYCLES, with

40 YEARS DATA RETENTION
SELF-TIMED PROGRAMMING CYCLE with
AUTO-ERASE
READY/BUSY SIGNAL DURING
PROGRAMMING
SINGLE SUPPLY VOLTAGE 8 14
– 3V to 5.5V for the ST93CS66
– 2.5V to 5.5V for the ST93CS67 1 1
USER DEFINED WRITE PROTECTED AREA PSDIP8 (B) SO14 (ML)
PAGE WRITE MODE (4 WORDS) 0.25mm Frame 150mil Width
SEQUENTIAL READ OPERATION
5ms TYPICAL PROGRAMMING TIME
ST93CS66 and ST93CS67 are replaced by
the M93S66
Figure 1. Logic Diagram

DESCRIPTION
The ST93CS66 and ST93CS67 are 4K bit Electri-
cally Erasable Programmable Memory (EEPROM)
fabricated with SGS-THOMSON’s High Endurance
Single Polysilicon CMOS technology. The memory
is accessed through a serial input D and output Q. VCC
The 4K bit memory is organized as 256 x 16 bit
words.The memory is accessed by a set of instruc-
tions which include Read, Write, Page Write, Write D
All and instructions used to set the memory protec-
tion. A Read instruction loads the address of the C Q
first word to be read into an internal address
pointer. ST93CS66
S ST93CS67

Table 1. Signal Names PRE

S Chip Select Input W

D Serial Data Input

Q Serial Data Output

VSS
C Serial Clock AI00906B

PRE Protect Enable

W Write Enable

VCC Supply Voltage

VSS Ground

June 1997 1/16

This is information on a product still in production bu t not recommended for new de signs.
ST93CS66, ST93CS67

Figure 2A. DIP Pin Connections Figure 2B. SO Pin Connections

ST93CS66
ST93CS67
ST93CS66
ST93CS67 NC 1 14 NC
S 2 13 VCC
S 1 8 VCC
C 3 12 PRE
C 2 7 PRE
NC 4 11 NC
D 3 6 W
D 5 10 W
Q 4 5 VSS
AI00907B
Q 6 9 VSS
NC 7 8 NC
AI00908C

Warning: NC = Not Connected.

Table 2. Absolute Maximum Ratings (1)
Symbol Parameter Value Unit

TA Ambient Operating Temperature –40 to 85 °C

TSTG Storage Temperature –65 to 150 °C

TLEAD Lead Temperature, Soldering (SO14 package) 40 sec 215

°C
(PSDIP8 package) 10 sec 260

VIO Input or Output Voltages (Q = VOH or Hi-Z) –0.3 to VCC +0.5 V

VCC Supply Voltage –0.3 to 6.5 V

(2)
Electrostatic Discharge Voltage (Human Body model) 2000 V
VESD
(3)
Electrostatic Discharge Voltage (Machine model) 500 V
Notes: 1. Except for the rating ”Operating Temperature Range”, stresses above those listed in the Table ”Absolute Maximum Ratings”
may cause permanent damage to the device. These are stress ratings only and operation of the device at these or any other
conditions above those indicated in the Operating sections of this specification is not implied. Exposure to Absolute Maximum
Rating conditions for extended periods may affect device reliability. Refer also to the SGS-THOMSON SURE Program and other
relevant quality documents.
2. MIL-STD-883C, 3015.7 (100pF, 1500 Ω).
3. EIAJ IC-121 (Condition C) (200pF, 0 Ω).

DESCRIPTION (cont’d) size of this area is defined by the content of a

Protect Register, located outside of the memory
The data is then clocked out serially. The address array. As a final protection step, data may be per-
pointer is automatically incremented after the data manently protected by programming a One Time
is output and, if the Chip Select input (S) is held Programing bit (OTP bit) which locks the Protect
High, the ST93CS66/67 can output a sequential Register content.
stream of data words. In this way, the memory can Programming is internally self-timed (the external
be read as a data stream of 16 to 4096 bits, or clock signal on C input may be disconnected or left
continuously as the address counter automatically running after the start of a Write cycle) and does
rolls over to 00 when the highest address is not require an erase cycle prior to the Write instruc-
reached. tion. The Write instruction writes 16 bits at one time
Within the time required by a programming cycle into one of the 256 words, the Page Write instruc-
(tW), up to 4 words may be written with the help of tion writes up to 4 words of 16 bits to sequential
the Page Write instruction; the whole memory may locations, assuming in both cases that all ad-
also be erased, or set to a predetermined pattern, dresses are outside the Write Protected area. After
by using the Write All instruction. the start of the programming cycle, a Ready/Busy
signal is available on the Data output (Q) when the
Within the memory, an user defined area may be Chip Select (S) input pin is driven High.
protected against further Write instructions. The

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 ST93CS66, ST93CS67

AC MEASUREMENT CONDITIONS Figure 3. AC Testing Input Output Waveforms

Input Rise and Fall Times ≤ 20ns
Input Pulse Voltages 0.2V CC to 0.8VCC 0.8VCC
0.7VCC
Input and Output Timing
0.3V CC to 0.7VCC 0.3VCC
Reference Voltages
0.2VCC

AI00825
Note that Output Hi-Z is defined as the point where data
is no longer driven.

Table 3. Capacitance (1)

(TA = 25 °C, f = 1 MHz )
Symbol Parameter Test Condition Min Max Unit
C IN Input Capacitance VIN = 0V 5 pF
COUT Output Capacitance VOUT = 0V 5 pF
Note: 1. Sampled only, not 100% tested.

Table 4. DC Characteristics (TA = 0 to 70°C or –40 to 85°C; VCC = 3V to 5.5V for ST93CS66 and
VCC = 2.5V to 5.5V for ST93CS67)
Symbol Parameter Test Condition Min Max Unit
ILI Input Leakage Current 0V ≤ VIN ≤ VCC ±2.5 µA
0V ≤ VOUT ≤ VCC,
ILO Output Leakage Current ±2.5 µA
Q in Hi-Z
ICC Supply Current (TTL Inputs) S = VIH, f = 1 MHz 3 mA
Supply Current (CMOS Inputs) S = VIH, f = 1 MHz 2 mA
ICC1 Supply Current (Standby) S = VSS, C = VSS 50 µA
Input Low Voltage (ST93CS66,67) 4.5V ≤ VCC ≤ 5.5V –0.1 0.8 V
VIL
Input Low Voltage (ST93CS66) 3V ≤ VCC ≤ 5.5V –0.1 0.2 VCC V
Input Low Voltage (ST93CS67) 2.5V ≤ VCC ≤ 5.5V –0.1 0.2 VCC V
Input High Voltage (ST93CS66,67) 4.5V ≤ VCC ≤ 5.5V 2 VCC + 1 V
VIH
Input High Voltage (ST93CS66) 3V ≤ VCC ≤ 5.5V 0.8 VCC VCC + 1 V
Input High Voltage (ST93CS67) 2.5V ≤ VCC ≤ 5.5V 0.8 VCC VCC + 1 V
IOL = 2.1mA 0.4 V
VOL Output Low Voltage
IOL = 10 µA 0.2 V
IOH = –400µA 2.4 V
VOH Output High Voltage
IOH = –10µA VCC – 0.2 V

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ST93CS66, ST93CS67

Table 5. AC Characteristics (TA = 0 to 70° or, –40 to 85°C; VCC = 3V to 5.5V for ST93CS66 and
VCC = 2.5V to 5.5V for ST93CS67)
Symbol Alt Parameter Test Condition Min Max Unit
tPRVCH tPRES Protect Enable Valid to Clock High 50 ns
tWVCH tPES Write Enable Valid to Clock High 50 ns
tSHCH tCSS Chip Select High to Clock High 50 ns
tDVCH tDIS Input Valid to Clock High 100 ns
tCHDX tDIH Clock High to Input Transition 100 ns
tCHQL tPD0 Clock High to Output Low 500 ns
tCHQV tPD1 Clock High to Output Valid 500 ns
tCLPRX tPREH Clock Low to Protect Enable Transition 0 ns
tSLWX tPEH Chip Select Low to Write Enable Transition 250 ns
tCLSL tCSH Clock Low to Chip Select Transition 0 ns
tSLSH tCS Chip Select Low to Chip Select High Note 1 250 ns
tSHQV tSV Chip Select High to Output Valid 500 ns
tSLQZ tDF Chip Select Low to Output Hi-Z 300 ns
tCHCL tSKH Clock High to Clock Low Note 2 250 ns
tCLCH tSKL Clock Low to Clock High Note 2 250 ns
tW tWP Erase/Write Cycle time 10 ms
fC fSK Clock Frequency 0 1 MHz
Notes: 1. Chip Select must be brought low for a minimum of 250 ns (tSLSH) between consecutive instruction cycles.
2. The Clock frequency specification calls for a minimum clock period of 1 µs, therefore the sum of the timings tCHCL + tCLCH
must be greater or equal to 1 µs. For example, if tCHCL is 250 ns, then tCLCH must be at least 750 ns.

Figure 4. Synchronous Timing, Start and Op-Code Input

PRE

tPRVCH

tWVCH tCHCL

tSHCH tCLCH

tDVCH tCHDX

D START OP CODE OP CODE

OP CODE INPUT
START
AI00887

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 ST93CS66, ST93CS67

Figure 5. Synchronous Timing, Read or Write

tCLSL

tDVCH tCHDX tCHQV tSLSH

D An A0

tCHQL tSLQZ
Hi-Z
Q Q15/Q7 Q0

ADDRESS INPUT DATA OUTPUT

AI00820C

PRE

tCLPRX

tSLWX

tCLSL

tSLSH

tDVCH tCHDX

D An A0/D0

tSHQV tSLQZ
Hi-Z
Q BUSY READY

tW

ADDRESS/DATA INPUT WRITE CYCLE

AI00888B

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ST93CS66, ST93CS67

POWER-ON DATA PROTECTION applied on the Chip Select (S) input (assuming that
the Clock C is low). The data input D is then
In order to prevent data corruption and inadvertent
sampled upon the following rising edges of the
write operations during power up, a Power On clock C until a ’1’ is sampled and decoded by the
Reset (POR) circuit resets all internal programming ST93CS66/67 as a Start bit.
circuitry and sets the device in the Write Disable
mode. When VCC reaches its functional value, the The ST93CS66/67 is fabricated in CMOS technol-
device is properlyreset (in the Write Disable mode) ogy and is therefore able to run from zero Hz (static
and is ready to decode and execute an incoming input signals) up to the maximum ratings (specified
instruction. A stable VCC must be applied before in Table 5).
any logic signal. Read
The Read instruction (READ) outputs serial data
on the Data Output (Q). When a READ instruction
INSTRUCTIONS is received, the instruction and address are de-
The ST93CS66/67 has eleven instructions, as coded and the data from the memory is transferred
shown in Table 6. Each instruction is composed of into an output shiftregister. A dummy ’0’ bit is output
a 2 bit op-code and an 8 bit address. Each instruc- first followed by the 16 bit word with the MSB first.
tion is preceded by the rising edge of the signal

Table 6. Instruction Set

W PRE Op (1) Additional
Instruction Description Address Data
pin (1) pin Code Information

READ Read Data from Memory X ’0’ 10 A7-A0 Q15-Q0

Write is executed if
the address is not
WRITE Write Data to Memory ’1’ ’0’ 01 A7-A0 D15-D0
inside the
Protected area

Write is executed if
all the addresses
PAWRITE Page Write to Memory ’1’ ’0’ 11 A7-A0 D15-D0
are not inside the
Protected area

Write all data if the

WRALL Write All Memory ’1’ ’0’ 00 01XX XXXX D15-D0 Protect Register is
cleared

WEN Write Enable ’1’ ’0’ 00 11XX XXXX

WDS Write Disable X ’0’ 00 00XX XXXX

Data Output =
Protect Register
PRREAD Protect Register Read X ’1’ 10 XXXX XXXX Q8-Q0
content + Protect
Flag bit

Data above
specified address
PRWRITE Protect Register Write ’1’ ’1’ 01 A7-A0
A7-A0 are
protected

Protect Flag is also

PRCLEAR Protect Register Clear ’1’ ’1’ 11 1111 1111 cleared (cleared
Flag = 1)
PREN Protect Register Enable ’1’ ’1’ 00 11XX XXXX

OTP bit is set

PRDS Protect Register Disable ’1’ ’1’ 00 0000 0000
permanently
Note: 1. X = don’t care bit.

6/16
 ST93CS66, ST93CS67

Output data changes are triggered by the Low to After the LSB of the last data word, Chip Select (S)
High transition of the Clock (C). The ST93CS66/67 must be brought Low before the next rising edge of
will automatically increment the address and will the Clock (C). The falling edge of Chip Select (S)
clock out the next word as long as the Chip Select initiates the internal, self-timed write cycle. The
input (S) is held High. In this case the dummy ’0’ bit Page Write operation will not be performed if any
is NOT output between words and a continuous of the 4 words is addressing the protected area. If
stream of data can be read. the ST93CS66/67 is still performing the program-
Write Enable and Write Disable ming cycle, the Busy signal (Q = 0) will be returned
if the Chip Select input (S) is driven high, and the
The Write Enable instruction (WEN) authorizes the ST93CS66/67 will ignore any data on the bus.
following Write instructions to be executed, the When the write cycle is completed, the Ready
Write Disable instruction (WDS) disables the exe- signal (Q = 1) will indicate (if S is driven high) that
cution of the following Erase/Write instructions. the ST93CS66/67is ready to receive a new instruc-
When power is first applied, the ST93CS66/67 tion.
enters the Disable mode. When the Write Enable
Write All
instruction (WEN) is executed, Write instructions
remain enabled until a Write Disable instruction The Write All instruction (WRALL) is valid only after
(WDS) is executed or if the Power-on reset circuit the Protect Register has been cleared by executing
becomes active due to a reduced VCC. To protect a PRCLEAR (Protect Register Clear) instruction.
the memory contents from accidental corruption, it The Write All instruction simultaneously writes the
is advisable to issue the WDS instruction after whole memory with the same data word included
every write cycle. in the instruction. The Write Enable signal (W)
must be held High before and during the Write
The READ instruction is not affected by the WEN instruction. Input address and data are read on the
or WDS instructions. Low to High transition of the clock. If the
Write ST93CS66/67 is still performing the programming
The Write instruction (WRITE) is followed by the cycle, the Busy signal (Q = 0) will be returned if the
address and the word to be written. The Write Chip Select input (S) is driven high, and the
Enable signal (W) must be held high during the ST93CS66/67 will ignore any data on the bus.
WRITE instruction. Data input D is sampled on the When the write cycle is completed, the Ready
Low to High transition of the clock. After the last signal (Q = 1) will indicate (if S is driven high) that
data bit has been sampled, Chip Select (S) must the ST93CS66/67is ready to receive a new instruc-
be brought Low before the next rising edge of the tion.
clock (C), in order to start the self-timed program-
ming cycle, providing that the address is NOT in the MEMORY WRITE PROTECTION AND PROTECT
protected area. If the ST93CS66/67 is still per- REGISTER
forming the programming cycle, the Busy signal (Q The ST93CS66/67 offers a Protect Register con-
= 0) will be returned if the Chip Select input (S) is taining the bottom address of the memory area
driven high, and the ST93CS66/67 will ignore any which has to be protected against write instruc-
data on the bus. When the write cycle is completed, tions. In addition to this Protect Register, two flag
the Ready signal (Q = 1) will indicate (if S is driven bits are used to indicate the Protect Register status:
high) that the ST93CS66/67 is ready to receive a the Protect Flag enabling/disabling the protection
new instruction. of theProtect Register and the OTP bit which, when
Page Write set, disables access to the Protect Register and
A Page Write instruction (PAWRITE) contains the thus prevents any further modifications of this Pro-
first address to be written followed by up to 4 data tect Register value. The content of the Protect
words. The Write Enable signal (W) must be held Register is defined when using the PRWRITE in-
High duringthe Write instruction. Input address and struction, it may be read when using the PRREAD
data are read on the Low to High transition of the instruction. A specific instruction PREN (Protect
clock. After the receipt of each data word, bits Register Enable) allows the user to execute the
A1-A0 of the internal address register are incre- protect instructions PRCLEAR, PRWRITE and
mented, the high order bits A7-A2 remaining un- PRDS; this PREN instruction being used together
changed. Users must take care by software to with the signals applied on the input pins PRE
ensure that the last word address has the same six (Protect Register Enable pin) and W (Write En-
upper order address bits as the initial address able).
transmitted to avoid address roll-over.

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ST93CS66, ST93CS67

Figure 6. READ, WRITE, WEN, WDS Sequences

READ PRE

D 1 1 0 An A0

Q Qn Q0

ADDR DATA OUT

OP
CODE

WRITE PRE

CHECK
STATUS
D 1 0 1 An A0 Dn D0

ADDR DATA IN BUSY READY

OP
CODE

WRITE PRE WRITE PRE

ENABLE DISABLE

W S

S D 1 0 0 0 0 Xn X0

D 1 0 0 1 1 Xn X0 OP
CODE

OP
CODE
AI00889D

8/16
 ST93CS66, ST93CS67

Figure 7. PAWRITE, WRALL Sequences

PAGE PRE
WRITE

CHECK
STATUS
D 1 1 1 An A0 Dn D0

ADDR DATA IN BUSY READY

OP
CODE

WRITE PRE
ALL

CHECK
STATUS
D 1 0 0 0 1 Xn X0 Dn D0

ADDR DATA IN BUSY READY

OP
CODE

AI00890C

9/16
ST93CS66, ST93CS67

MEMORY WRITE PROTECTION (cont’d) protected from writing. The Protect Flag bit is set to
’0’, it can be read with Protect Register Read
Accessing the Protect Register is done by execut- instruction. Both the Protect Enable (PRE) and
ing the following sequence: Write Enable (W) input pins must be driven High
– WEN: execute the Write Enable instruction, during the instruction execution.
– PREN: execute the PREN instruction, Note: A PREN instruction must immediately pre-
– PRWRITE, PRCLEAR or PRDS: the protection cede the PRWRITE instruction, but it is not neces-
then may be defined, in terms of size of the sary to execute first a PRCLEAR.
protected area (PRWRITE, PRCLEAR) and Protect Register Disable
may be set permanently (PRDS instruction). The Protect Register Disable instruction sets the
Protect Register Read One Time Programmable bit (OTP bit). The Protect
The Protect Register Read instruction (PRREAD) Register Disable instruction (PRDS) is a ONE TIME
outputs on the Data Output Q the content of the ONLY instruction which latches the Protect Regis-
Protect Register, followed by the Protect Flag bit. ter content, this content is therefore unalterable in
The Protect Register Enable pin (PRE) must be the future. Both the Protect Enable(PRE) and Write
driven High before and during the instruction. As in Enable (W) input pins must be driven High during
the Read instruction a dummy ’0’ bit is output first. the instruction execution. The OTP bit cannot be
Since it is not possible to distinguish if the Protect directly read, it can be checked by reading the
Register is cleared (all 1’s) or if it is written with all content of the Protect Register (PRREAD instruc-
1’s, user must check the Protect Flag status (and tion), then by writing this same value into the Pro-
not the Protect Register content) to ascertain the tect Register (PRWRITE instruction): when the
setting of the memory protection. OTP bit is set, the Ready/Busy status cannot ap-
pear on the Data output (Q); when the OTP bit is
Protect Register Enable not set, the Busy status appear on the Data output
The Protect Register Enable instruction (PREN) is (Q).
used to authorize the use of further PRCLEAR, A PREN instruction must immediately precede the
PRWRITE and PRDS instructions. The PREN PRDS instruction.
insruction does not modify the Protect Flag bit
value.
Note: A Write Enable (WEN) instruction must be READY/BUSY Status
executed before the Protect Enable instruction. When the ST93CS66/67 is performing the write
Both the Protect Enable (PRE) and Write Enable cycle, the Busy signal (Q = 0) is returned if S is
(W) input pins must be held High during the instruc- driven high, and the ST93CS66/67 will ignore any
tion execution. data on the bus. When the write cycle is completed,
Protect Register Clear the Ready signal (Q = 1) will indicate, if S is driven
The Protect Register Clear instruction (PRCLEAR) high, that the ST93CS66/67 is ready to receive a
clears the address stored in the Protect Register to new instruction. Once the ST93CS66/67 is Ready,
all 1’s, and thus enables the execution of WRITE the Data Output Q is set to ’1’ until a new Start bit
and WRALL instructions. The Protect Register is decoded or the Chip Select is brought Low.
Clear execution clears the Protect Flag to ’1’. Both
the Protect Enable (PRE) and Write Enable (W) COMMON I/O OPERATION
input pins must be driven High during the instruc-
tion execution. The Data Output (Q) and Data Input (D) signals can
Note: A PREN instruction must immediately pre- be connected together, through a current limiting
cede the PRCLEAR instruction. resistor, to form a common, one wire data bus.
Some precautions must be taken when operating
Protect Register Write the memory with this connection, mostly to prevent
The Protect Register Write instruction (PRWRITE) a short circuit between the last entered address bit
is used to write into the Protect Register the ad- (A0) and the first data bit output by Q. The reader
dress of the first word to be protected. After the should refer to the SGS-THOMSON application
PRWRITE instruction execution, all memory loca- note ”MICROWIRE EEPROM Common I/O Opera-
tions equal to and above the specified address, are tion”.

10/16
 ST93CS66, ST93CS67

Figure 8. PRREAD, PRWRITE, PREN Sequences

Protect PRE
Register
READ

D 1 1 0 Xn X0

Q An A0 F

ADDR DATA F = Protect Flag

OP OUT
CODE

Protect PRE
Register
WRITE

CHECK
STATUS
D 1 0 1 An A0

ADDR BUSY READY

OP
CODE

Protect PRE
Register
ENABLE

D 1 0 0 1 1 Xn X0

OP
CODE AI00891D

11/16
ST93CS66, ST93CS67

Figure 9. PRCLEAR, PRDS Sequences

Protect PRE
Register
CLEAR

CHECK
STATUS
D 111 111

ADDR BUSY READY

OP
CODE

Protect PRE
Register
DISABLE

CHECK
STATUS
D 100 000

ADDR BUSY READY

OP
CODE

AI00892C

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 ST93CS66, ST93CS67

ORDERING INFORMATION SCHEME

Example: ST93CS66 M 1 013TR

Operating Voltage Package Temp. Range Option

66 3V to 5.5V B PSDIP8 1 0 to 70 °C 013TR Tape & Reel
0.25mm Packing
67 2.5V to 5.5V Frame 6 –40 to 85 °C

ML SO14 3 (1)
–40 to 125 °C
150mil Width

Note: 1. Temperature range on request only.

Devices are shipped from the factory with the memory content set at all ”1’s” (FFFFh).

For a list of available options (Operating Voltage, Package, etc...) or for further information on any aspect
of this device, please contact the SGS-THOMSON Sales Office nearest to you.

13/16
ST93CS66, ST93CS67

PSDIP8 - 8 pin Plastic Skinny DIP, 0.25mm lead frame

mm inches
Symb
Typ Min Max Typ Min Max
A 3.90 5.90 0.154 0.232
A1 0.49 – 0.019 –
A2 3.30 5.30 0.130 0.209
B 0.36 0.56 0.014 0.022
B1 1.15 1.65 0.045 0.065
C 0.20 0.36 0.008 0.014
D 9.20 9.90 0.362 0.390

E 7.62 – – 0.300 – –
E1 6.00 6.70 0.236 0.264

e1 2.54 – – 0.100 – –
eA 7.80 – 0.307 –

eB 10.00 0.394
L 3.00 3.80 0.118 0.150

N 8 8
CP 0.10 0.004
PSDIP8

A2 A

A1 L
B e1 C
B1 eA
D eB

E1 E

1
PSDIP-a

Drawing is not to scale

14/16
 ST93CS66, ST93CS67

SO14 - 14 lead Plastic Small Outline, 150 mils body width

mm inches
Symb
Typ Min Max Typ Min Max
A 1.35 1.75 0.053 0.069
A1 0.10 0.25 0.004 0.010
B 0.33 0.51 0.013 0.020
C 0.19 0.25 0.007 0.010
D 8.55 8.75 0.337 0.344
E 3.80 4.00 0.150 0.157
e 1.27 – – 0.050 – –

H 5.80 6.20 0.228 0.244

h 0.25 0.50 0.010 0.020

L 0.40 0.80 0.016 0.031

α 0° 8° 0° 8°

N 14 14
CP 0.10 0.004
SO14

h x 45°

A
C
B
e CP

E H
1

A1 α L

SO-a

Drawing is not to scale

15/16
ST93CS66, ST93CS67

Information furnished is believed to be accurate and reliable. However, SGS-THOMSON Microelectronics assumes no responsibility for the
consequences of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. No
license is granted by implication or otherwise under any patent or patent rights of SGS-THOMSON Microelectronics. Specifications mentioned
in this publication are subject to change without notice. This publication supersedes and replaces all information previously supplied.
SGS-THOMSON Microelectronics products are not authorized for use as critical components in life support devices or systems without express
written approval of SGS-THOMSON Microelectronics.

 1997 SGS-THOMSON Microelectronics - All Rights Reserved

 MICROWIRE is a registered trademark of National Semiconductor Corp.

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