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Vlsi Design

Verilog hdl by Samir paniker

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26 views20 pages

Vlsi Design

Verilog hdl by Samir paniker

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upparbearth
Copyright
© © All Rights Reserved
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= visidesign using Verilog HDL —— ae a) Vector Part Select « For the vector declarations shown above, it is possible to address bits or parts of vectors. busA[7] // bit #7 of vector busA bus{20] // Three least significant bits of vector bus, bus[0:2] /*lllegal because the significant bit should always be on the left of a range specification*/ 2.11.5. Integer, Real, and Time Register Data Types Integer, real, and time register data types are supported in Verilog. a) Integer + Aninteger is a general purpose register data type used for manipulating quantities. * Integers are declared by the keyword integer. * Although it is possible to use reg as a general-purpose variable, it is more convenient to declare an integer variable for purposes such as counting. * The default width for an integer is the host-machine word size, which is implementation-specific but is at least 32 bits. ens integer counter; // general purpose variable used as a counter ial counter = // A negative one is stored in the counter b) Real * Real number constants and real register data types are declared with the keyword real. © They can be specified in decimal notation or in scientific notation. * Real numbers cannot have a range declaration, and their default value is 0. * When a real value is assigned to an integer, the real number is rounded off to the nearest integer. real delta; 7/ Define a real variable called delta ] initial begin delta = 4e10; // delta is assigned in scientific notation delta = 2.13; // delta is assigned a value 2.13 end Se OO M.G.B Publications Digital Circuit Design through VERILOG HDL Iauanieme, A spec! time regis nee i ¢ to simul i Verilog simulation , fan Mei Nation tenes data type is used in ° tat ‘ a fic but is at least ¢ « Atime variable is declan ‘ ister data types ‘th for time regis implementation-speci © The wic a i time. : Fe system function Sime is invoked fo get the current simulation time save_sim_time; 7] Define a time variable save_sim_time initial ; beveleion tine Stites f/f Seve the carrent simulation fie 2.11.6. Arrays «mays ate allowed in Verilog for reg, integer, time, real, realtime and vec register data types. arra «Arrays are accessed by []. For multi-dimensional indexes need to be provided for each dimension. integer count{0:7]; 7/ Anartay of 8 count variables reg boolf3-0); // Axray of 32 one-bit boolean register variables wire [7:0] w_array? [5:0]; // Declare an array of 8 bit vector wire wire w_array1{7:0][5: // Declare an array of single bit wires 2.11.7, Memories * Memories are modeled in Verik Each element of the array is kno. single array index, ‘+ Each word can be one or more bits registers and one n-bit desta oh * A particular word in me subscript. Verilog simply as a one-dimensional array of y is known as an element or word and is addresse. tis important to differentiate between n 1 mory is ol i Pear ted by Using thelkddress as a memory a reg, mem|bit{01023} ” 7 11 Me reg [7:0] membyte[0:1023}, _nory memlbit with 1K 1-bit wor , hiki4 membyte(511] HM Mersory menibytewith kono yte bit words(bytes) / Fetches 1 by _——e te wor MGB Publications Word whose address is 511 Digital Ci “aa Hreuit Design through VERILOG HOL vyistdesign using Verilog HOL mz 223 2.11.8. Strings ‘ Strings can be stored in reg. The width of the register variables must be large enough to hold the string. Each character in the string takes up 8 bits (1 byte) « Ifthe width of the register is greater than the size of the string. Verilog fills bits to Meciineszingwith zeros tn a If the register width is smaller than the string width, Verilog truncales the leftmost bits of the string, It is always safe to declare a string that is slightly wider than necessary. eg [8*18:1] string_value; 7/ Declare a variable that is 18 bytes wide initial value = "Hello Verilog World’; // String, can be stored in variable | Special characters serve a special purpose in displaying strings and are listed in table 2.11.3. Table 2.11.3 Special Characters Escaped Characters _| Character Displayed \n Newline \t Tab % % % \\ i‘ Vr i \oo0 Character written in 1-3 octal digits B Special characters can be displayed in strings only when they are preceded by escape characters. 2.12. Parameters Verilog, allows constants to be defined in a module by the keyword parameter. Parameters cannot be used as variables. Parameter values for each module instance can Be overridden indiv idually at compile time. This allows the module instances to be ‘customized. Module definitions may be written in terms of parameters, Hlardcoded numbers Should be avoided. eee M.G.B Publications Digital Circuit Design through VERILOG HDL. jing Verilog HDL 204 ttement aram Sta ee a dtp cnt on i nce can ae name of the module insta! «The hie! values. design with tt instance in the module instanc be used to override param mber = 0 ‘module hello_world; parameter dma =0/ tay the module identificatos initial coups é saisplay (Displaying pello_world id number = ‘6d, id_nam) endmodule module identification nu! Ng yn number / [define top-level module module top; //cvange parameter values in the instantiated modules use defparam statement defparam w!.id_num = 1, w2id_num = 2; / finstantiate two hello_world modules hello_world w1(); hello_world w2(); endmodule In example, the module hello_world we However, when the module instances w their id_num values are modified with above design, we would get the following as defined with a default id_num 1 and w2 of the type hello_world are the defparam statement. If we simulate output: Displaying hello_world id number = 1 Displaying hello world id - n = b) localparam ie * The localparam be changed, Keyword is used to define p arameters w! ‘ameters when their values should * The state encod ing cannot be ch. Parameter redefiniti oe hi Provides protectio: ion against inadv vist design using Verilog HOL 2-25 4b0001, 4’b0010, 4’b0100, 4’b1000; stated —S 2.13. System Tasks and Compiler Directives 2.13.1. System Tasks * Verilog provides standard system tasks for certain routine operations. All system tasks appear in the form $. * Operations such as displaying on the screen, monitoring values of nets, stopping, and finishing are done by system tasks a) Displaying information * Sdisplay is the main system task for displaying values of variables or strings or expressions. This is one of the most useful tasks in Verilog. * Usage: Sdisplay(p1, p2, p3..., pn); pl, p2, p3...., pn can be quoted strings or variables or expressions. The format of Sdisplay is very similar to printf in C. A Sdisplay inserts a newline at the end of the string by default. A Sdisplay without any arguments produces a newline. Strings Table 2.13.1: String Format Specifications Format Display ed or %D Display variable in decimal eb or %B Display variable in binary %s or %S Display %h or %H Display variable in hex %e or %C fm or %M. tov or %V %0 or %O Yt or %T %e or %E Display real Vktorur (| D al number in decimal format %g or %G 1 = vated rr M.G.B Publications Digital Circuit Design through VERILOG HDL 1st design using Verilog HOL ee 2:26 Aj aonorng nermAHON nit signa when vue hanes * Verilog provides a | faci igprnided by the Smonitor task. M es, or quoted strings. Usage: Smonitor(pl, P2, PS: -~ ‘The parameters pl, p2, pn can be variables, signal nam‘ i itor task. $monit . Peay task i# used in, the Srmonil f format similar to the SHSPAH MF the variables or signals specitiod in th continuously monitor a arameter list and displays all arameters in the list. . Only ‘monitoring list can be active at a time. If there is more than on: me lation, the last $monitor statement will be th: Smonitor statement in your simul $ rt active statement, The earlier Smonitor statements will be overridden. «Two tasks are used to switch monitoring on and off. Usage: $monitoron; ‘$monitoroff; ‘The Smonitoron tasks enables monitoring, and the Smonitor monitoring during a simulation Monitor Statement 7/Monitor time and value of the signals clock and reset / {Clock toggles every 5 time units and reset goes down at 10 time units Initial begin off task disable | Smonitor(Stime," Value of signals clock = %b reset = %b", clock,reset); end ‘ f Partial output of the monitor statement 0 Value of signals clock = 5 Value of signals clock 10 Value of signals clock = 0 reset = 0 2.13.2. Compiler Directives ¥ Compiler directives are i i provided in Vi by using the ‘ construct. We directives. a) ‘define + The ‘define directive is used to define The Verilog, compiler substitutes the *. ete All compiler directives are defin. leal with the two most useful compil text macros in Verilog (see Example 2.1 text of\the macro wher xample 2 rever it encounters © This is similar to the #define constr uct in C, The defined const, are used in the Verilog code by prece ants or text macr “ling them with a ° (back tick), M.G.B Publications Digital . ‘sHal Clreuit Design through VERILOG HOL 227 visi design using Verilog HDL —— BEMMIPERERE ievine Directive //define a text macro that defines default word size ‘define WORD. SIZE 32 pb) ‘include ¢ The ‘include directive allows you to include entire contents of a Verilog source file in another Verilog file during compilation. + This works similarly to the #include in the C programming language. This directive is typically used to include header files, which typically contain global or commonly used definitions. BEMOPRERS ‘include Directive // Include the file header.v, which contains declarations in the J/ main verilog file design.v. ‘include header.v ZA4 Expressions, Operators, and Operands Dataflow modeling describes the design in terms of expressions instead of Primitive gates. Expressions, operators, and operands form the basis of dataflow modeling. 2.14.1. Expressions gre constructs that combine operators and operands to produce a Expressions result. Examples of expressions: Combine operands and operators arb addrl [20 : 17] + addr? [20:17] 2.14.2. Operands -onstructs will take only certain types of operands. Operands can be 4 Oe ce | numbers, nets, registers, times, bit-select (one bit of vector net or tarts integer cartaclect (elected Bits of the vector net or register vector), and vector register), P* memories or function ©! M.G.B Publications Digital Circuit Design through VERILOG HDL .B Pul mem VLSI design using Verilog HDL 2.28 integer count, final_count; 4 ; feat count = count + 1; //count is an integer operand 1a, b,c: i cn : /Jaand bare real operands reg [154 reg [3:0] reg_out; reg. out = regi[30] *reg203:0};//regi[0] and reg2[3:0] are //part-select register operands reg ret_value; i ret value = calculate_parity(A, B); //calculate_parity is a function type. operand 2.14.3. Operators * Anoperator is a symbol that tells the compiler to perform certain mathematical or logical manipulations. regl, reg; Operators are used in program to manipulate data and variables. ‘+ Operators provide a means to construct expressions. * Verilog consists of about two dozen operators. 2.15 Operator Types Verilog HDL includes following kinds of operators: * Boolean logical + Unary reduction logical * Bitwise logical Relational * Binary arithmetic + Unary arithmetic © Other 2.15.1. Boolean Logical Operators Logical operators operate on logic: 7 gical operands and ret (1) or FALSE (0). Used typically in if and while statements. Dy operators Bs ie Boolean operators. For example, | isa le aa NOT on Ss bitwise NOT. The first megates, e.g. 1(5=- 6) is TRUE, The second pears Se oie te l complements the bit turn a logic value, i.e., TRL :B Publications é oer Digital Circuit Design through VERILOG HOL —<—— 2-29 © yustdesign using Verilog HOL Operator Name } Logical negation && Logical AND ii} Logical OR | Lesicah ON ae aera 2.15.2. Unary Reduction Logical Operators Unary reduction operators operate on a single operand. | result from applying the operator to all of the bits of the oper They produce a single bit and. For example, in statement B=&A, if A=1101, then B=(1&1&0&1)=0. Operator Name or & AND reduction | OR reduction a XOR reduction ae NAND reduction a NOR reduction — ~A XINOR reduction 2.15.3. Bitwise Logical Operators Bitwise operators operate on the bits of the operand or operands. The result of A and B is AND of cach corresponding bit of A with B. For example, if A=1011 and B=0101, then C= A and B gives C=0001. Except for bitwise negation these operators operate on two operands. Operator Name Bitwise negative e AND OR Bitwit RUE a Bitwise XOR Bitwise NA Bitwise NOR Equivalence bitwise NOT XOR $$$ Digital Circuit Design through VERILOG HDL. M.G.B Publications Apt zt 3 1 design using Verilog HOL a e, TRUE 54. Relational Operators Pe earre beret value te 1 aa a vcempare two operands and OT statement if (A=B) Relational operat Az0100 and B=0100, result is , ‘ * i d the (1) or FALSE Oe a wn, the relation is ambiguous an‘ results True (1). If am i unknown (X)- oo canes ‘Operator mae a Greater than tet Greater than or equal | Greater than or eq0?" _| Less than <= Less than or equal eee Logical equality 2.15.5. Binary Arithmetic Operators Binary arithmetic operators operate on two operands. Register and net, i.e. wits operands are treated as unsigned. However, real and integer operands may be signed. I any bit of an operand is unknown ('x’) then the result is unknown. [Operator Name Comments * Addition i ‘Subtraction * Multiplication / Division Divide by zero produces an x, ie, unknown. % Modulus 2.15.6. Unary Arithmetic Operators Operator Name Coms ts ] . ment Unary minus : | Changes sign of it operand M.G.B Publications Dioit sMal Circuit Design through VERILOG HOL 2:31 2.15.7. Other Operators The conditional operator operators much like in the language C- Operator Name Comments Case equality |The bitwise comparison includes comparison of x and z values. All bits must match’ for equality. Returns TRUE oF FALSE, Case inequality |The bitwise, comparison, includes comparison of x and z values. Any bit difference produces inequality. Returns TRUE or FALSE. {} Concatenation joins bits together with 2 or more comma-separated expressions, ©.g- {alo} Bll:7]} concatenates the zero bit of A to bits 1 to 7 of B. << Shift left Vacated bit positions are filled with zeros, eg. A=A> Shift right Vacated bit positions are filled with zeros. 2 Conditional ‘Assigns one of two values depending on the conditional expression e.g. A=C>D2B+3:B-2 means if C greater than D, the value of A is B+3 otherwise B-2 2.15.8. Operator Precedence ‘The precedence of operators is shown in table. The top of the table is the highest precedence and the bottom is the lowest. Operators on the same line have the same precedence and associate left to right in an expression, Parentheses can be used to Khange the precedence or clarify the situation. We strongly urge you to use parentheses toimprove readability. eo Operators Ricyoperstors ree aoe Multiplying operators | * / . | Sign operators +r ra EN Relational operators >> [Relational operators .G.B Publications Digital Circuit Design through VERILOG HDL emus VISI design using Verilog HDL 232 Logical operators E Conditional operators 2: (Lowest Precedence) | Table 2.12.1 Operator Precedence in Verilog HDL B Additional Information Verilog provides many different operator types. Operators can be arithmetic, logical, relational, equality, bitwise, reduction, shift, concatenation, or conditional. Some ES of these operators are similar to the operators used in the C programming language. Each operator type is denoted by a symbol. Table shows the complete listing of operator symbols classified by category. Table: Operator Types and Symbols R Operator Type | Operator Symbol Operation Number of Performed a Multiply Two / Divide Two Arithmetic ane Two vi Subtract Two st * Modulus Te. Bs Power (exponent) | Two a | Logical negation One ks i ee Logical and Two MN Logical or ao e Greater than Two 1. < Less th, Relational Pe lan EWo Bi Greater than or | Two = sls A Lu. - than or equal | Two D M.G.B Publications a 'gital Circuit Design through VERILOG HDL ee using Verilog HO z_—_ Equality Inequality Case equality Case inequality Bitwise negative Bitwise and Bitwise or Bitwise xor Bitwise xnor Two Reduction and One Reduction nand One Reduction or One Reduction nor One Reduction xor One Reduction xnor One Right shift Two Left shift Two Arithmetic right | Two shift Arithmetic left shift | Two Concatenation Any number Replication Any number Conditional three |. Arithmetic Operators . ‘There are two types of arithmetic operators: binary and unary. Binary operators e ors are multiply (*), divide (/), add (+), subtract (), power (*), operators take two operand: nary arithmetic operate d modulus (%). Binary 5 = 4b0100; // Aand Bare register vectors // Dand E are integers // Multiply A.and B, Evaluates to 4'b1100 B Enilicatione Digital Circuit Design through VERILOG HDL “_ ames VISI design using Ver yg HOL = 7] Divide D by E. Evaluates fo 1. Truncates any fractional part Re // ddd A and B. Evaluates to4’b01 tt en // Subtract A from B. Evaluates to 4'0001 é ce F, //E to the power F, yields 16 o fhe entire expression is x. This t of t TFany operand bit has a value x, then the result of St iu elt shouldbe seems intuitive because if an operand value is not known precis anunknown. a inl = 4b101x; in2= 4'b1010; sum = inl + in2; // sum will be evaluated to the value 4'bx Modulus operators produce the remainder from the division of two numbers. ‘They operate similarly to the modulus operator in the C programming language. 13%3 7/ Evaluates to 1 | 16%4 // Evaluates to 0 T%2 // Ewaluates to -1, takes sign of the first operand 7%2 // Evaluates to +1, takes sign of the first operand 2. Unary operators ‘The operators + and - can also work as unary operators. They are used to speci! the positive or negative sign of the operand. Unary + or ? operators have higher precedence than the binary + or ? operators. 4 71 Negative 4 ee, / | Positive S Negative numbers are represented as 2's complement internally in Verilog, | advisable to use negative numbers only of the type integer or real in expressions Designers should avoid negative numbers of the type ‘ ' // Ws equivalent (2's complement of 10)/5 // where 32 is the defa a Y J1This 10)/5 ult machine word width, St an incorrect and unexpected result M.G.B Publications Pigital Circuit Design through VERILOG HO! gn using Verilog HOL —— 235 cal Operators a ae (&&), logical-or (||) and logical-not ®. s re binar is tor. Logical Biiiswithese Peano operators. Operator ! is a unary opera! tor. Logit ee rators always evaluate to a L-bit value, 0 (false), 1 (true), oF * biguous). e operand is not equal to zero, itis equivalent to a logical 4 (true condition), If it is Dlequal to zero, it is equivalent to a logical 0 (false condition). If any operand bit Bor 2, it is equivalent to x (ambiguous condition) and is normally treated by llators as a false condition. ical operators take variables or expressions as operands. Use of parentheses to 1p logical operations is highly recommended to improve readability. Also, the does not have to remember the precedence of operators. 7/ Logical operations // Evaluates to 0. Equivalent to (logical-] && logical-0) /// Evaluates to 1. Equivalent to (logical! || logical-0) Evaluates to 0. Equivalent to not(logical-?) 7// Evaluates t 1. Equivalent to not(logical) // Unknowns ; B= 2'b10; 1// Evaluates to x. Equivalent to ( && logical 1) // Expressions 3) // Evaluates to 1 if both a = and b ==3are true. // Evaluates to 0if either is false © Relational operators are greater-than (>), less-than (9), greaterthan-or-equal-to eat Tess than-or-equal-to (<°)- It “elational operators are used in an expression, the Deceeairw logical value of SITE ‘expression is true andi 0 if the expression is Bi cere are any unknown of 2 STE the operands, the expression takes a value x operators function menctly as the corresponding operators in the C programming puage. aes =4,B %=4'b1010, y=a'p1i01, Z bIXXx // Evaluates to a logical 0 // Evaluates to a logical 1 // Evaluates to a logical 1 toanx using Verilog HOL — visi design Tab 2:36. case equality «at inequality (!=), case ed Equality Operators tity (2°), logical ined tors returr al equality i lity operat Eauality operators re OB ein an expression, operands bit by bi ‘compare j===), and case inequality ('=*): (eel Ntve i sth Table lists the operators Jogical value 1 if true, 0 if false, These operators en ists the oper aah zero filling if the operands are of uned ut Sail valor Expression Description a equal to b, result unknown if x or Zin a OF 0,1,x b al=b a not equal tb, result unknown if x or zin a | 0, 1/* orb ‘a equal to b, including x and 2 0,1 =b ‘a not equal to b, including x and z 01 itis important to note the difference between the logical equality operators t=) and case equality operators (===, !==). The logical equality operators (==, =) will jeld an x if either operand has x or z in its bits, However, the case equality operators ( ) compare both operands bit by bit and compare all bits, including x and z. The result is 1 if the operands match exactly, including x and z bits. The result is 0 if th Case equality operators never result in an x. | // Z= Abou, M=4'bbox, N= 4'bbox | A==B // Results in logical 0 Xie // Results in logical 1 ae _ (7 Results inx i // Results in logical 1 (all bits match, including x anci i= / ta patentee ____// Results in togical 1 6. Bitwise Operators Bitwise ope and itwise operators are negation (~), and(), o perators perform a bit-by-bit che i ole FAS, knox (A~, ~»), 5 i" ; Bit rand and perform the On On Wo oper P Perform the operation with the comes nts They take each tit , ne operand is shorter than the othe i Beet length of t longer oper ic abla ey i ln ; E "8 " operand Logic tables forthe big ne : +» an x ina bitwise opefation od her oper With zeros to i computation eption is the Perates on the §.6.B Publications «nan th ital Circuit Desi c Hon through VERILOG mat erator (~), are sh iS | perand unary using Verilog HDL __—~ Bitwise or 0 i x Bitwise xnor 0 a x Bitwise xor x hes of bitwise operators are shown below. =api010, Y = 41101 =4'b10x1 ston // Negation. Result is 4'b0101 Bitwise and, Result is 4’b1000 Publications Digital Circuit Design through VERILOG HDL. ul mums VLSI design using Verilog HOL 2:38 xlY // Bitwise or. Result is 4’b1111 x ; ¥ // Bitwise xor. Result is 4'b0111 xy // Bitwise xnor. Result is 4’b1000 X&Z // Result is 4'b10x0 It is important to distinguish bitwise operator 1, &&, | |-Logical operators always yield a logical value 0, 1, x operators yield a bit-by-bit value. Logical operators perform a logical operation, not » bit-by-bit operation, // X= 4°b1010, Y = 4'b0000 XY // bitwise operation. Result is 4'b1010 XY // logical operation. Equivalent to 1 | | 0. Result is 1 J 7. Reduction Operators Reduction operators are and (&), nand (~&), or (|), nor (~|), xor (*), and xnor (~, ‘~), Reduction operators take only one operand. Reduction operators perform a bitwise operation on a single vector operand and yield a 1-bit result. The logic tables for the operators are the same as in Bitwise Operators. The difference is that bitwise operations are on bits from two different operands, whereas reduction operations are on the bits of the same operand. Reduction operators work bit by bit from right to left. Reduction nand, reduction nor, and reduction xnor are computed by inverting the result of th reduction and, reduction or, and reduction xor, respectively. 15 ~ &, and | from logical operators whereas bitwise 7/X=4b1010 &X //Equivalent to 1 & 0 & 1 & 0. Results in 1'bO. Ix //Equivalent to1 | 0 | 1 | 0. Results in bt “x / [Equivalent to1* 010, Results in 1'b0 //A eduction xor or xnor can be used for even or odd parity Z/generation of a vector. i The use of a similar set of symbols for k , Gee, || reduction operators (8, IL i ee! pe number of operands each o} 8. Shift Operators Shift operators are right shift (>>), let shift (<<) arithmetic left shift (<<<), Repular shift ope the let by a specified number of bits, The eeocn et et 0 ise (~, &, |, %), ) is somewhat confusing initially. The Bey rence lies erator takes and also the value of results computed arithmetic right shift (> @ vector operand to the rit operands are the vecte 4 bits to shift. When the bits are shifted, the Nita i Hac we operations do not wrap around. Arithmetic shift'onmee ee ee ee expression to determine the value with which to fil the caentey oo oe ¢ vacated bits M.G.B Publications Digital Circuit Design through VERILOG HO: op siz op pai design using Verilog HOL X=4'b1100 // is 4100110, Shift right 1 bit. 0 filled in MSB position. //X is 4'b1000. Shift left 1 bit. 0 filled in LSB position. //Y is 40000. Shift left 2 bits. //Signed data types // 00111...10110 binary / [Results in -2 decimal, due to arithmetic shift ¥ Btfloperciors are useful because thay allow |e denotes wmecel Su ations, shiftand- add algorithms for multiplication, and other useful operations "9, Concatenation Operator 7 The concatenation operator ( {, } ) provides a mechanism to append multiple “operands. The operands must be sized. Unsized operands are not allowed because the Me cf cach operand must be known for computation of the size of the result Bi tonations are expressed as operands within braces, with commas separating the operands. Operands can be scalar nets or registers, vector nets or registers, bit-select, " part-select, or sized constants. Pf A=101, B= 2°00, C = 2'b10, D = 3110 B,C} // Result Y is 40010 A,B,C,D,3'b001} _// Result Y is 11’b10010110001 ¥={A_ BIO}, Cli} // Result Y is 3101 40. Replication Operator 4 T Repetitive concatenation of the same number can be expressed by using a Teplication constant. A replication constant specifies how many times to replicate the Mpamber inside the brackets ({})- reg A; Teg [1:0] B,C; // Result Y is 41111 aa) 20)) Rest fa11110000 ay oei.ch _// Result ¥ is 8161111000010 a ee GB Publications Digital Circuit Design through VERILOG HDL. wees VSI design using Verilog HDL oY 11. Conditional Operator ‘The conditional operator(:) takes tee operands. Usage: condition expr ? tue_exPr false expr ‘The condition expression (condition expr) is frst ev t (logical 1), then the true_expr is evaluated. If the result is false (logical 0), then the uated. If the result is x Taaticuoun), ten bor tee and a, bit by bit, to return for each bit aluated. If the result is true position an x i action of a co! compared to the if-else expres false_expr is eval false expr are evaluated and thelr results are co evn bits are different and the value of the Pits if they are the same. The multiplexer. Alternately, it can be rnditional operator is similar to @ ssion. false expr —*0 2404 rmltiploxer true expr —=|1 cond expr expr i Fig, 2x1 multiplexer using conditional operator ers operators are frequently used in dataflow modeling to. mod assignments, The conditional expression acts as a switchiny a a 7 /model functionality of a tristate buffer a assign addr_bus = drive_enable ? addr_out : 36'bz //model functionality of a 2-to-1 mux ' ‘out = control ? in! : ind; Conditional " , operations can be nested. E: conditional operation. In the Pee ca eral ee Hd ea ee SELES TEAMS se oath (0) een wee yourself that (A==3) an a I a RIEL i wy as eae as 1, X as the inputs an, 2 })? (control ? x: y ): (control ? m : n) MG. Publications i igital Cir ult Design through VERILOG HOL

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