Logic Built-In Self-Test (LBIST)

LFSR — Theory and Operation

VLSI System Testing Jiun-Lang Huang, GIEE/ICDA, NTU

 Linear Feedback Shift Register (LFSR)
• Consists of n D-type flip-flops and a selected number of exclusive-OR
(XOR) gates.

• flip-flop: one cycle delay.

• XOR: modulo-2 addition.
• connection: modulo-2 multiplication D1 D2 D3

• Example: 1
1
0
1
0
0
(seed—initial value)

1 1 1
0 1 1
D Q D Q D Q 1 0 1
0 1 0
D2 D3 0 0 1
D1
1 0 0
VLSI System Testing 98 Jiun-Lang Huang, GIEE/ICDA, NTU
 Standard and Modular LFSRs
• Standard LFSR is also called external LFSR.
hn-1 hn-2 h2 h1

D0 D1 Dn-2 Dn-1

• Modular LFSR is also called internal LFSR.

• Faster than standard LFSR.
h1 h2 hn-2 hn-1

D0 D1 Dn-2 Dn-1

VLSI System Testing 99 Jiun-Lang Huang, GIEE/ICDA, NTU

 Characteristic Polynomial
• The internal structure of the n-stage LFSR can be described by specifying a
characteristic polynomial of degree n, f(x).

• f (x) = 1 + h1x + h2x + − + hn⋯1x

2 n⋯1
+x n

• hi is either 1 or 0, depending on the hn-1 hn-2 h2 h1

existence or absence of the feedback
D0 D1 Dn-2 Dn-1
path.

h1 h2 hn-2 hn-1

D0 D1 Dn-2 Dn-1

VLSI System Testing 100 Jiun-Lang Huang, GIEE/ICDA, NTU

 Figure 5.12b, below. The characteristic polynomials, f{x), used to construct both
LFSRs are l-^x'^+x'^ and \-\-x-\-x^, respectively.
Example: 4-Stage Standard and Modular LFSRs
The test sequences generated by each LFSR, when its initial contents, SQ, are set
to [0001] or SQ(X) =X^, are listed in Figures 5.12c and 5.12d, respectively. Because
2 4 4
1+x +x 1+x+x

(a) (b)

0001 0001
1000 1100
0100 0 110
1010 0011
0101 1101
00 10 10 10
0001 0101
1000 1110
0100 0111
1010 1111
0101 1011
0010 1001
0001 1000
1000 0100
0100 0010
1010 0001

(c) (d)

VLSI System Testing • FIGURE 5.12 101 Jiun-Lang Huang, GIEE/ICDA, NTU
 Galois Field GF(2)
x3 + x2 + x + 1
• Operation x2 + x + 1
x3 + x2 + x + 1
• Modulo-2 addition, subtraction, x4 + x3 + x2 + x
multiplication, and division of binary x5 + x4 + x3 + x2
x5 + 0 + x3 + x2 + 0 + 1
values.

• Properties x2 + x + 1 x5 + 0 +
x3
x3
+ x2 + x + 1
+ x2 + 0 + 1

• Modulo-2 addition and subtraction x5 + x4

x4
+
+
x3
0 + x2
are identical.
x4 + x3 + x2
x3 + 0 + 0
• 0 ± 0 = 0, 0 ± 1 = 1, 1 ± 0 = 1, x3 + x2 + x
1±1=0 x2 + x + 1
x2 + x + 1
0 + 0 + 0

VLSI System Testing 102 Jiun-Lang Huang, GIEE/ICDA, NTU

 LFSR Properties
• Maximum-length sequence:
• A sequence generated by an n-stage LFSR is called a maximum-length sequence if it has
a period of 2n-1.

• A maximum-length sequence is called an m-sequence.

• Primitive polynomial
• The characteristic polynomial associated with an m-sequence is called a primitive
polynomial.

VLSI System Testing 103 Jiun-Lang Huang, GIEE/ICDA, NTU

 • Numbers of 1s and 0s
• The number of 1s in an m-sequence differs from the number of 0s by one.
• Pseudo-random sequence
• The sequence generated by an LFSR is a pseudo-random sequence.
• The correlation
• Very close to zero between any two output bits.
• Consecutive run of 1s and 0s
• An m-sequence produces an equal number of runs of 1s and 0s.
• In every m-sequence, one-half of the runs have length 1, one-fourth of the runs have
length 2, one-eighth of the runs have length 3, and so forth.

VLSI System Testing 104 Jiun-Lang Huang, GIEE/ICDA, NTU

 LFSR — Polynomial Division
• LFSR can be configured to perform polynomial division.
M (x) = g (x) × Q (x) + R (x)
• Application:
Compact a test response sequence, M(x), into a fixed-length signature, R(x).

g (x)

M (x) D0 Dn-1 Q (x)

R (x)
VLSI System Testing 105 Jiun-Lang Huang, GIEE/ICDA, NTU
 • Example
8 7 5 4 2 4
M (x) = x + x + x + x + x + x Q (x) = x + x + 1
4 3 3 2
g (x) = x + x + 1 R (x) = x + x + 1

M (x) Q (x)
0 1 1 0 1 1 0 1 1 D0 D1 D2 D3 1 1 0 0 1

1 0 1 1
R (x)
R(x)
M(x) Q(x)
D0 D1 D2 D3
0 1 1 0 1 1 0 1 1 0 0 0 0
0 1 1 0 1 1 0 1 1 0 0 0
0 1 1 0 1 1 0 1 1 0 0
0 1 1 0 1 1 0 1 1 0
0 1 1 0 1 1 0 1 1
0 1 1 0 0 1 0 0 1
0 1 1 0 0 1 0 0 1
0 1 1 0 0 1 0 0 1
0 0 1 0 1 1 0 0 1
1 0 1 1 1 1 0 0 1
1 x2 x3 1 x x4

VLSI System Testing 106 Jiun-Lang Huang, GIEE/ICDA, NTU

 Logic Built-In Self-Test (LBIST)

Test Pattern Generation

VLSI System Testing Jiun-Lang Huang, GIEE/ICDA, NTU

 Overview
• Three forms of testing
stuck-at fault
fault simulation pattern count comments
coverage

exhaustive 100% no 2n long test time

suffer long fault

pseudo-random < 100% yes
simulation time

pseudo-exhaustive 100% maybe can still be large may need DfT

• LFSR-based TPGs are most common for logic BIST applications.

VLSI System Testing 108 Jiun-Lang Huang, GIEE/ICDA, NTU

 • A pseudo-exhaustive testing
example:

• Consider a circuit with two outputs,

y1 and y2, and n primary inputs.

• There are n1 and n2 primary inputs in n1 y1

the fan-in cones of y1 and y2,
n
respectively.

• We can exhaustively test this circuit n2 y2

n1 n2
with at most 2 + 2 test patterns.

VLSI System Testing 109 Jiun-Lang Huang, GIEE/ICDA, NTU

 Pseudo-Random Testing
• Testing of a circuit with pseudo-random patterns.
• Reproducible and with many characteristics of random patterns.
• Not all 2 patterns are generated.
n

• Suffer random-pattern-resistant faults.

• Example: input faults and the output sa0 fault
of an AND gate.

• Non-trivial test quality (fault coverage) evaluation:

• Lengthy fault simulation; fault detection probability analysis; estimation of test length as
a function of fault coverage

VLSI System Testing 110 Jiun-Lang Huang, GIEE/ICDA, NTU

 Weighted Random Pattern Generation
• Adjust the distribution of 0s and 1s to increase the coverage of pseudo-
random-pattern-resistant faults.

• Such a generator can be realized using an LFSR and combinational logic.

• Determine the set of weights in advance. Logic Built-in Self-Test

• Weights for different parts of the

circuit may differ.

• Example:
A 4-stage weighted LFSR with
0.25 0-probability.

VLSI System Testing 111 Jiun-Lang Huang, GIEE/ICDA, NTU

 Signals of Arbitrary Weights

• Decompose the desired probability into a sum of basic weights (2 ⋯n

).

• Use AND and OR gates to realize the weight.

• Example: to realize 1-probability of 5/32.
• 5/32 = 1/8 + 1/32

VLSI System Testing 112 Jiun-Lang Huang, GIEE/ICDA, NTU

 Adaptive Test Generation
• Multiple sets of weights are employed.
• Derived with the help of fault simulation.
• More efficient tests but more
complicated TPG hardware. 4321

• Example:
Programmable weighted
LFSR.

Control Register

VLSI System Testing 113 Jiun-Lang Huang, GIEE/ICDA, NTU

 case we can achieve the same probability of successful en- establishes thz feedback links. Subsequently, in m clock
coding using only an (s+4)-bit LFSR. This is the most cycles it prodiices serially the bits of the test vector which
are shifted into the scan chain. The test vector is then
LFSR Reseeding efficient encoding but the scheme is also computationally
the most complex as it involves solving systems of non- applied to the CUT, the responses are loaded back into the
linear equations. In fact, the process of finding the poly- scan register and shifted out for compaction into the

• The nomials is computationally so complex that it makes this signature register SR.
LFSR can also be used
scheme inapplicable to practical cases.
to generate
deterministic patterns.

I
Therefore we propose to use a scheme based on reseeding
and multiple primitive polynomials. In this scheme the

• LFSR can operate according to one out of many primitive

A seed is computed to generate each
polynomials. The testcube is encoded as the polynomial
deterministic
identifier and pattern
the initial with
seed. We the selected
demonstrate that with
polynomials, which require 4 bits to encode the choice,
16
shift register

LFSR.
this scheme achieves the same probability of finding the v
m
encoding as the scheme with full polynomial programma-
bility. Encoding a given testcube involves solving sys-
• Multiple
tems ofLFSRs are needed
linear equations to ensure
for the polynomials. Although
we have 1 6 polynomials the process stops when we find
successful seed Incomputation.
the first encoding. practice the average number of poly-
nomials that are analyzed is only slightly greater than one.
The paper introduces the schemes, presents the theoretical n
models of their efficiency as well as the experimental vali- Figure 1. The general structure of the BIST scheme.
dation of the models. The organization of the paper will
be as follows. After this introductory section the proposed The main problem addressed in this paper is how to
scheme will be presented in section 2, which also provides encode lhe test cubes into seeds and polynomials to achieve
the notation used throughout this paper and some basic the best encocing efficiency with the least computational
VLSI System Testing 114 Jiun-Lang
complexity. Before we precisely Huang,the
formulate GIEE/ICDA,
problem,NTU
 Logic Built-In Self-Test (LBIST)

Output Response Analysis

VLSI System Testing Jiun-Lang Huang, GIEE/ICDA, NTU

 Need of ORA
• For BIST operations, it is impossible to store all output responses on-chip,
on-board or in-system to perform a bit-by-bit comparison.

• Output responses are compacted into a signature and compared with a

golden signature either embedded on-chip or stored off-chip.

• Compaction vs. compression: the former is lossy, and the latter is lossless.
• Aliasing probability should be kept low.
• The probability that the signature of a faulty response is the same as that of the fault-free
response.

VLSI System Testing 116 Jiun-Lang Huang, GIEE/ICDA, NTU

 cept that the signature is defined as the number of 0-to-l and 1-to-O transitions.
theory behind transition count testing is similar to that for ones count testing,
he transition count test technique [Hayes 1976] simply requires using
ept that the signature is defined as the number of 0-to-l and 1-to-O transitions. a D flip-
Ones and Transition Count Testing
optransition
and an XOR gate connected to a ones counter (see Figure 5.28), to
count test technique [Hayes 1976] simply requires using a D flip- count the
and an XOR gate connected to a ones counter (see Figure 5.28), to count the

/ w
CUT Counter
•
i V
/ w
CUT Counter
•
i V

CLK >
C (L, m) ⋯ 1
— i
L: bitstream length
CLK > P (m) = m: the number of 1s
2L ⋯ 1
— i
FIGURE 5.27
GURE 5.27
es counter as ORA.
counter as ORA.

T - — J CUT D Q ^ Counter 7^-^ Signature

T - — J CUT D Q ^ Counter 7^-^ Signature
2C (L ⋯ 1,m) ⋯ 1
CLK- P (m) =
CLK-
2L ⋯ 1
FIGURE 5.28
GURE 5.28
ansition counter as ORA.
VLSI System Testing 117 Jiun-Lang Huang, GIEE/ICDA, NTU
 responses from a CUT having a single output, and (2) parallel signature analysis
for compacting responses from a CUT having multiple outputs.

Signature Analysis using SISR 5A.3.1 Serial Signature Analysis

Consider the n-stage single-input signature register (SISR) shown in Figure 5.29.
This SISR uses an additional XOR gate at the input for compacting an L-bit

• Single-input signature register (SISR)

• Add an XOR gate at the input of a modular
LFSR to compact an L-bit bitstream. M •©—H

•
FIGURE 5.29

After shifting the L-bit bitstream, M, into the modular LFSR, the contents
An n-stage single-input signature register (SISR).

(remainder) of the SISR, r, satisfy M (x) = q (x) f (x) + r (x).

• M = {m0m1m2−mL⋯1}: M (x) = m0 + m1x + m2x + − + mL⋯1x . (m first)

2 L⋯1
L-1

• { }
2 n⋯1
r = r0r1r2−rn⋯1 : r (x) = r0 + r1x + r2 x + − + rn⋯1x is the signature.

• Aliasing probability: P (n) ≠ 2 ⋯n

if L → n.

VLSI System Testing 118 Jiun-Lang Huang, GIEE/ICDA, NTU

 The remainder [1011] is equal to the signature derived from Figure 5.30a when
SISR is first initialized to a starting pattern (seed) of [0000].
SISR Example Now, assume fault f^ produces an erroneous output stream M' = {11001011

• g (x) = 1 + x + x
we 4
obtain q\x) M-M
=x^ +x^ and H
r\x) = 1 — •
-i-x-\-x^ ^J
M'{x) = l+x-\-x^ ~\-x^-\-x^, as given in Figure 5.30b. Using polynomial divi
—or• R = {1110}. Because the f

signature jR', {1110}, is different from the fault-free signature R, [1011], fault

•
detected.
M ro For fault/2 with
3 M4' ' = {11001101}
6 7 or M''(^) = 1+^+-^^-f-^^ H-^^ as giv
M = {10011011}, M (x) = 1 + x + x + x + x
^1 rz A3 M' To r^ 1-2 Tg M " ^0 r^ ^2 ^
1 0 0 0 0 1 0 0 0 0 1 0 0 0 0

•
1 1 0 0 0 1 1 2 0 30 0 0 1 0 0 0
Using polynomial
0 division,
1 1 0 we 0have q (x) 0 = x
1 + x
1 0 0 and 1 0 1 0 0
2 1 30
r (x) = 1 + x + x . 1 1 0 M-M
1
H
0 1—•
1 —•
0 ^J 1 1 0 1 0
1 1 0 1 1 0 1 0 1 1 0 1 1 0 1
M ro ^1 rz A3 M' To Tg M " ^0

•
0 0 0 0 1 0 0 0 0 r^ 1-2 1 0 r^
1 ^20 ^3 1 0
M' detected; 0 1 11 00 0 0 0 0 1 1
1 0 0 0 0
1 0 0 1
1 0 0 0 0
0 1 0 1
1 1 0 0 0 1 1 0 0 0 0 1 0 0 0
M'' not detected.
1 0 01 11 1 0 0 0 1 0 1 1 1 1 00 00 1 10 1 01 0 1
0 0
R 1 10 01 1 1 1 0 R' 1 1 0 1 1 11 00 1 H- 1 01 10 0 1 1
1 1 0 1 1 0 1 0 1 1 0 1 1 0 1
0
(a) 0 0 0 1 0 0 (b)0 0 1 0 1 0 1(c) 0
0 1 1 0 0 1 1 1 0 0 1 0 1 0 1
1 0 1 1 0 1 1 1 0 0 1 0 1 1 0
• FIGURE 5.30 R 1 0 1 1 R' 1 1 1 0 H- 1 0 1 1

(a) (b) (c)

VLSI System Testing A four-stage SISR: (a) fault-free signature;
119 (b) signature for fault f^; and (c)
Jiun-Lang signature
Huang, GIEE/ICDA, for
NTUf
 CUT. It is possible to reduce the hardware cost by using an m-to-1 mu
this increases the test time m times. Consider the n-stage multiple-i
ture register (MISR) shown in Figure 5.31. The MISR uses n extra X
Multiple-Input Signature Register (MISR) compacting n L-bit output sequences, MQ to M„_i, into the modular L
neously.

• MISR uses n extra XOR gates for compacting

n L-bit output sequences, M0 to Mn-1 into the 0/7i 0/?2 0/7n-2 Q/^n-l
modular LFSR simultaneously. $-H # > r^ m^ -^M''n #H
Mn M, Mn M.'n-2 Mn

FIGURE 5.31

• The n-input MISR can be remodeled as a single-input SISR with effective

An n-stage multiple-input signature register (MISR).

input sequence M(x) as

n⋯2 n⋯1
M (x) = M0 (x) + xM1 (x) + − + x Mn⋯2 (x) + x Mn⋯1 (x).

• Aliasing probability: P (n) ≠ 2 ⋯n

if L → n.

VLSI System Testing 120 Jiun-Lang Huang, GIEE/ICDA, NTU

 If L » n, then PpsA(n) ^ 2-". When n = 20, PpsA{n) < 2-^0 = 0.0001%. The resuh
suggests that PPSA{^) mainly depends on n, when L ^ n. Hence, increasing the
MISR
numberExample
of MISR stages or using the same MISR but with a different f{x) can
substantially reduce the aliasing probability [Hassan 1984] [Williams 1987].
^-N ^-H e-H
Mn Mi Mp Mo

• FIGURE 5.32 ^-N ^-H e-H

A four-stage MISR. Mi Mp Mo
Mn

• FIGURE 5.32
Mo 1 0 0 1 0
A four-stage MISR.
01010
M2 1 1 000
M3 10011
M
Mo 1100001110 0 1 1
01010
FIGURE 5.33 M2 1 1 000
M3 10011
An equivalent M sequence.
M 10011011
VLSI System Testing 121 Jiun-Lang Huang, GIEE/ICDA, NTU
 Logic Built-In Self-Test (LBIST)

LBIST Architecture

VLSI System Testing Jiun-Lang Huang, GIEE/ICDA, NTU

 patterns are shifted in at the same time while test responses are being shifted out.
This BIST architecture is referred to as self-testing using MISR and parallel SRSG
(STUMPS) [Bardell 1982]. Due to the ease of integration with traditional scan
BIST Architectures for Scan Design architecture, the STUMPS architecture is the only BIST architecture widely used
in industry to date. In order to further reduce the lengths of the PRPG and MISR
and improve the randomness of the PRPG, a STUMPS-based architecture that

• Generally, BIST uses the scan architecture, which is called test-per-scan.

includes an optional linear phase shifter and an optional linear phase compactor
is often used in industrial applications [Nadeau-Dostie 2000] [Cheon 2005]. The
linear phase shifter and linear phase compactor typically comprise a network of

• Test-per-clock is possible by redesigning the storage elements to function as pattern

XOR gates. Figure 5.38 shows the STUMPS-based architecture.

generators or signature analyzers 5.5.3

for test purposes.
BIST Architectures Using Register Reconfiguration
A concern with BIST designs is the amount of test time required. One technique

• STUMPS (Self-Testing Using MISR and Parallel SRSG):

for reducing the test time is to make use of the storage elements already in the
design for both test generation and response analysis. The storage elementsLogicare
redesigned so they can function as pattern generators or signature analyzers for
Built-

• The only widely adopted BIST architecture due to its ease of

test purposes. This BIST architecture is generally referred to as a test-per-clock

integration with scan architecture.

BIST system [Bushnell 2000].
PRPG

n Linear Phase Shifter

•
PRPG
Add a linear phase shifter and a linear phase • ••
CUT
^
• ••
compactor to reduce the PRPG and MISR lengths CUT r
• • •
(C)

and improve the PRPG randomness. ^f

(C)

Linear Phase Compactor

i ^ T • • •
T T
MISR
MISR
FIGURE 5.37

VLSI System Testing FIGURE 5.38

123using IVIISR and parallel Jiun-Lang Huang, GIEE/ICDA, NTU
The self-testing (STUMPS) architecture.
 Memory Testing

VLSI System Testing Jiun-Lang Huang, GIEE/ICDA, NTU

 Functional Diagram of a Memory Block

VLSI System Testing 125 Jiun-Lang Huang, GIEE/ICDA, NTU

 Memory Testing Complexity
• Increasing density (the Moore’s law).
• More to test, more test time.
• Addition of logic to memories.
• Random logic or memory testing techniques alone do not achieve high fault coverage for
both.

• Memories are more deeply embedded.

• 40 different memory designs on a single chip!!
• Direct access is simply impossible.

VLSI System Testing 126 Jiun-Lang Huang, GIEE/ICDA, NTU

 • Increasing number of memory types.
• Volatile: DRAM, SRAM, CAM, TCAM, …
• Multi-port, pseudo multi-port.
• Non-volatile: Flash, EEPROM, FeRAM, MRAM, OUM.
• Different process technologies.
• CMOS, SOI, SiGe, …
• Strained silicon, silicon on nothing, …
• Redundancy
• To enhance yield for large memories.
• Involves locating the faults and allocating the redundant elements.
VLSI System Testing 127 Jiun-Lang Huang, GIEE/ICDA, NTU
 Memory Faults
• Classical fault models
• Read disturb fault model
• Pre-charge faults
• False write faults
• Data retention faults
• Decoder faults
• Multi-port memory faults
• Other fault models
VLSI System Testing 128 Jiun-Lang Huang, GIEE/ICDA, NTU
 Classical Memory Fault Models
• Stuck-at fault
• Transition fault
• Coupling fault
• Neighborhood pattern sensitive fault

VLSI System Testing 129 Jiun-Lang Huang, GIEE/ICDA, NTU

 Stuck-At Fault Model
• The most classic and always used.
• Indicates that a cell is locked in one state or another.

VLSI System Testing 130 Jiun-Lang Huang, GIEE/ICDA, NTU

 Transition Fault Model
• In many ways, it looks like a stuck-at fault.
• The cell will retain either state; however, once it is written to one state, it
cannot transit back.

VLSI System Testing 131 Jiun-Lang Huang, GIEE/ICDA, NTU

 Coupling Fault Models
• A coupling fault (CF) between two cells occurs when the logic value of a
cell is influenced by the content of or operation on another cell.

• State Couple Fault (CFst)

Coupled (victim) cell is forced to 0 or 1 if coupling (aggressor) cell is in a
given state.

• Inversion Coupling Fault (CFin)

Transition in coupling cell complements (inverts) coupled cell.

• Idempotent Coupling Fault (CFid)

Coupled cell is forced to 0 or 1 if coupling cell transits from 0 to 1 or 1 to
0.
VLSI System Testing 132 Jiun-Lang Huang, GIEE/ICDA, NTU
 A Coupling Fault Example

VLSI System Testing 133 Jiun-Lang Huang, GIEE/ICDA, NTU

 Neighborhood Pattern Sensitive Fault Model
• A memory cell is dependent upon the cells in the neighborhood.
• Neighboring cells ==> base cell

VLSI System Testing 134 Jiun-Lang Huang, GIEE/ICDA, NTU

 Read Disturb Fault Model
• The defects that cause a cell to lose its data during a read.
• Deceptive Read Disturb
• Some defects cause the read disturb to occur late in the cycle, with the correct data
being placed in the sense amp, but the incorrect data is retained in the cell.

• Aka, deceptive destructive read.

• The cell disturbs, but the memory’s operation does not fail during the first cycle.

VLSI System Testing 135 Jiun-Lang Huang, GIEE/ICDA, NTU

 Data Retention Fault
• A cell fails to retain its logic value after a pre-specified period of time.
• DRAM: The defect discharges the storage capacitor faster
than normal.

• SRAM:
• Highly resistive defect in the pull-down path.
•Open or highly resistive defect along the pull-up path.
• A pause is required to identify that the leakage exceeds the specification.

VLSI System Testing 136 Jiun-Lang Huang, GIEE/ICDA, NTU

 Address Decoder Fault
• The decoder outputs are not observable, and so cannot be tested with logic
patterns.

• The address decoder must be thoroughly tested to ensure that the

appropriate location is accessed.

• Types of decoder faults:

• A certain address can access no cell.
• Multiple cells are accessed simultaneously by a certain address.
• A certain cell is not accessible by any address.
• A certain cell is accessible by multiple addresses.
VLSI System Testing 137 Jiun-Lang Huang, GIEE/ICDA, NTU
 March Patterns
• March C- pattern
• A slight reduction of the March C algorithm.
• The description: { (w0);⇑ (r0,w1);⇑ (r1,w0);⇓ (r0,w1);⇓ (r1,w0); (r0)}
• Ten operations on each cell.
• A € unique address pattern.
two-step

• Two-step: two operations in elements two to five.

• Unique: ensuring that each address is uniquely addressed.

VLSI System Testing 138 Jiun-Lang Huang, GIEE/ICDA, NTU

 • March C- Pattern (cont'd)
• Covers stuck-at faults, many coupling faults, transition faults, and the like.
• Also covers many decoder faults.
• The simplest “unique address” pattern which checks for the four simple decoder faults
described before.

• Example:

VLSI System Testing 139 Jiun-Lang Huang, GIEE/ICDA, NTU

 • Partial Moving Inversion Pattern (PMOVI)
{ ( w0);⇑ ( r0,w1,r1);⇑ ( r1,w0,r0);⇓ ( r0,w1,r1);⇓ ( r1,w0,r0)}
• A three-step unique address pattern.
€ • Reading each cell immediately after it is written ensures it is correctly written.
• This prevents a defective operation from later writing a cell that had failed to be written
correctly.

• If a cell is destabilized during a write, reading the cell immediately after the write allows
detection.

• Otherwise, the unstable cell will recover with the correct data value.

VLSI System Testing 140 Jiun-Lang Huang, GIEE/ICDA, NTU

 • Enhanced March C- Pattern
$ ( w0); (
& &
&⇑ ( r0,w1,r1,w1);⇑ ( r1,w0,r0,w0);&
% )
&⇓ ( r0,w1,r1,w1);⇓ ( r1,w0,r0,w0);&
& r0 &
' ( ) *

• A four-step unique address pattern.

€ • This pattern will catch all defects identified by the March C- and Partial Moving Inversion
patterns but will also detect pre-charge defects.

VLSI System Testing 141 Jiun-Lang Huang, GIEE/ICDA, NTU

 • March LR Pattern
• A combination of marching (March C-) and walking elements.
$ ( w0); (
& &
&⇓ ( r0,w1);⇑ ( r1,w0,r0,w1);&
% )
&⇑ ( r1,w0);⇓ ( r0,w1,r1,w0);&
& r0 &
' ( ) *

VLSI System Testing 142 Jiun-Lang Huang, GIEE/ICDA, NTU

 • March G Pattern
• Includes a “pause” in the sequence to facilitate retention testing.
• Useful for finding stuck-open defects.
$ ( w0); (
& &
&⇑ ( r0,w1,r1,w0,r0,w1);⇑ ( r1,w0,w1);&
& &
%⇓ ( r1,w0,w1,w0);⇓ ( r0,w1,w0); )
& &
& Pause; ( r0,w1,r1); &
&' Pause; ( r1,w0,r0) &*

VLSI System Testing 143 Jiun-Lang Huang, GIEE/ICDA, NTU

 Memory BIST (MBIST)

VLSI System Testing Jiun-Lang Huang, GIEE/ICDA, NTU

 MBIST Functional Diagram

memory
under
test

VLSI System Testing 145 Jiun-Lang Huang, GIEE/ICDA, NTU

 State-Machine BIST

VLSI System Testing 146 Jiun-Lang Huang, GIEE/ICDA, NTU

 Programmable State Machine BIST
• A BIST engine can be programmed to execute modified patterns.
• The latches are properly initialized before the BIST is run.

VLSI System Testing 147 Jiun-Lang Huang, GIEE/ICDA, NTU

 Micro-Code BIST
• Also called a processor-based BIST.
• Still needs a BIST engine in addition to the instruction memory where
pattern definitions are contained.

VLSI System Testing 148 Jiun-Lang Huang, GIEE/ICDA, NTU

 An Instruction Word Example

VLSI System Testing 149 Jiun-Lang Huang, GIEE/ICDA, NTU

 Example Program—March LR

VLSI System Testing 150 Jiun-Lang Huang, GIEE/ICDA, NTU

 Conclusions
• Testing is crucial to the success of IC
products — quality and economy.

• Testing activities spread over the entire

IC design and manufacturing process.

• Gradually over the entire lifecycle!

• With the advance in IC fabrication technologies and the introduction of
new applications, testing keeps evolving to meet the challenges.

VLSI System Testing 151 Jiun-Lang Huang, GIEE/ICDA, NTU