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Unit 4 Asynchronous Sequential Notes

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0% found this document useful (0 votes)
10 views29 pages

Unit 4 Asynchronous Sequential Notes

Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
Available Formats
Download as PDF, TXT or read online on Scribd
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Uni

t-
IVASYNCHRONOUSSEQUENTI
ALLOGI
C
TwoMar
ks

1.Whati
stheobj
ect
iveofr
acef
reest
ateassi
gnment
?
I
nasy
nchr
onousci
rcui
ts,t
heobj
ect
iveofst
ateassi
gnmenti
stoav
oid
cr
it
ical
races.
2.Whati
srace?
Whent
woormor
ebi
nar
yst
atev
ari
abl
eschanget
hei
rval
uei
nresponset
o
achangei
nani
nputv
ari
abl
e,r
acecondi
ti
onoccur
sinanasy
nchr
onous
ci
rcui
t.
3.Whati
scr
it
icalr
ace?
I
fthef
inalst
abl
est
atedependsont
heor
deri
nwhi
cht
hest
atev
ari
abl
e
changes,
ther
acecondi
ti
oni
shar
mful
andi
tiscal
l
edacr
it
ical
race.
4.Whati
snon-
cri
ti
calr
ace?
I
fthef
inalst
abl
est
atet
hatt
heci
rcui
treachesdoesnotdependont
he
or
deri
nwhi
cht
hest
atev
ari
abl
echanges,
ther
acecondi
ti
oni
snothar
mful
andi
tiscal
l
edanon-
cri
ti
cal
race.
5.Whati
sacy
cle?
Acy
cleoccur
swhenanasy
nchr
onousci
rcui
tmakesat
ransi
ti
ont
hrougha
ser
iesofunst
abl
est
ates.Whenast
ateassi
gnmenti
smadesot
hati
t
i
ntr
oduces cy
cles,car
e mustbe t
aken t
o ensur
ethateach cy
cle
t
ermi
nat
esonast
abl
est
ate.I
facy
cledoesnotcont
ainast
abl
est
ate,
the
ci
rcui
twi
l
lgof
rom oneunst
abl
est
atet
oanot
her
,unt
ilt
hei
nput
sar
e
changed.
6.Whatar
ethet
echni
quescommonl
yusedt
omakeacr
it
icalr
acef
ree
assi
gnment
?
 Shar
edr
owassi
gnment
 Mul
ti
pler
owassi
gnment
 Onehotassi
gnment
7.Def
inei
mpl
icat
iont
abl
e.
Thei
mpl
i
cat
iont
abl
eisachar
tthatconsi
stsofsquar
es,onef
orev
ery
possi
blepai
rofst
atest
hatpr
ovi
despacesf
orl
i
sti
nganypossi
blei
mpl
i
ed
st
ates.

8.Di
sti
ngui
sht
hef
undament
almodemodelf
rom pul
semodemodel
.
Fundament
almodeoper
ati
on Pul
semodeoper
ati
on
Ci
rcui
tdesi
gnsassumet
hatt
he Ther
equi
rementl
i
mit
ingi
nputchanges
i
nput
stot
hesy
nchr
onousci
rcui
ttoonl
yonev
ari
abl
eal
soappl
i
edt
opul
se
wi
l
lchangewhent
heci
rcui
tis modeci
rcui
ts
st
abl
e.
I
nput
sar
elev
els I
nput
sar
epul
ses
Lat
chesar
ememor
yel
ement
s Lat
chesar
ememor
yel
ement
s
Pr
imi
ti
vef
lowt
abl
eisder
ived Pr
imi
ti
vef
lowt
abl
eisder
ivedf
rom
f
rom st
atet
abl
e t
imi
ngdi
agr
am

9.Def
inepr
imi
ti
vef
lowt
abl
e.
Apr
imi
ti
vef
lowt
abl
eisaspeci
alcaseoff
lowt
abl
e.I
tisdef
inedasaf
low
t
abl
ewhi
chhasexact
lyonest
abl
est
atef
oreachr
owi
nthet
abl
e
10.
Def
inef
lowt
abl
e.
Dur
ingt
hedesi
gnofsy
nchr
onoussequent
ialci
rcui
t,i
tismor
econv
eni
ent
t
onamet
hest
atesbyl
ett
ersy
mbol
swi
thoutmaki
ngspeci
fi
cref
erencet
o
t
hei
rbi
nar
yval
ues.Suchat
abl
eiscal
l
edaf
lowt
abl
e.
11.
Whatar
ecompat
ibl
eandmaxi
malcompat
ibl
epai
rs?
Twoi
ncompl
etel
yspeci
fi
edst
atest
hatcanbecombi
nedar
esai
dtobe
compat
ibl
e.The maxi
malcompat
ibl
eis a gr
oup ofcompat
ibl
ethat
cont
ainsal
lthepossi
blecombi
nat
ionsofcompat
ibl
est
ates.
12.
Def
inemer
gergr
aph.
Themer
gergr
aphcont
ainst
hesamenumberofv
ert
icesast
hest
atet
abl
e
cont
ains.Themer
gergr
aphi
sat
oolusedt
oident
if
ycompat
ibl
est
ate
pai
rsi
nani
ncompl
etel
yspeci
fi
edst
atemachi
nef
orst
ater
educt
ion.
13.
Whati
smeantbycompat
ibl
est
ate?
Twost
atesar
ecompat
ibl
eifandonl
yiff
orev
eryi
nputsequencet
hat
ef
fect
sthet
wost
ates,
thesameout
putsequenceoccur
swhent
he
i
ncompl
etel
yspeci
fi
edout
put
sar
especi
fi
edr
egar
dlessofwhi
chst
atei
s
t
hest
art
ingst
ate.

14.
Def
inet
het
erm Hazar
d.
Theunwant
edswi
tchi
ngt
ransi
ent
s(gl
i
ches)t
hatmayappearatt
heout
put
ofaci
rcui
tar
ecal
l
edhazar
ds.Themai
ncauseofhazar
dsi
sthedi
ff
erent
pr
opagat
iondel
aysatdi
ff
erentpat
hs.
15.
Whatar
ethet
wot
ypesofhazar
ds?
 St
ati
chazar
ds:
Stat
ic-
0andSt
ati
c-1
 Dy
nami
chazar
ds
16.
Def
ineSt
ati
chazar
ds.
Ast
ati
chazar
dexi
stsi
fasi
gnal
issupposedt
oremai
natpar
ti
cul
arl
ogi
c
v
aluewhenani
nputv
ari
abl
echangesi
tsv
alue,
buti
nst
eadt
hesi
gnal
under
goesamoment
arychangei
nit
srequi
redv
alue.
17.
Def
inest
ati
c-0hazar
d.
I
nacombi
nat
ional
cir
cui
t,i
fout
putgoesmoment
ari
l
y1wheni
tshoul
d
r
emai
na0,
thehazar
disknownasst
ati
c-0hazar
d.
18.
Def
inest
ati
c-1hazar
d.
I
nacombi
nat
ional
cir
cui
t,i
fout
putgoesmoment
ari
l
y0wheni
tshoul
d
r
emai
na1,
thehazar
disknownasst
ati
c-1hazar
d.
19.
Def
ineDy
nami
chazar
d.
I
tisonei
nwhi
chout
putchangest
hreeormor
eti
meswheni
tshoul
d
changef
rom 1t
o0orf
rom 0t
o1.
20.
Whatdoy
oumeanbyessent
ialhazar
ds?
I
toccuri
nasy
nchr
onoussequent
ial
cir
cui
ts.I
tiscausedbyunequal
del
aysal
ongoneormor
epat
hst
hator
igi
nat
efr
om t
hesamei
nput
.These
hazar
dscanbeel
i
minat
edbyadj
ust
ingt
heamountofdel
aysi
nthe
af
fect
edpat
h.Remedi
esofst
ati
canddy
nami
csar
eremov
ed.
UNIT-4

ASYNCHRONOUS SEQUENTIAL CIRCUITS

• Analysis and design of asynchronous sequential circuits

• Reduction of state and Flow tables

• Race-free state assignment

• Hazards

SYNCHRONOUS SEQUENTIAL CIRCUITS ASYNCHRONOUS SEQUENTIAL CIRCUITS

Change of internal states occurs in response to the No clock pulses used, change of internal states occurs
synchronized clock pulses. when there is a change in input variables.

Memory Elements are clocked flipflops Memory Elements are either unclocked or time-delay
elements
Design is easy Design is more difficult because of timing problems
involved in feedback path
Timing problems eliminated by triggering all No clock pulses used, so change of state occurs
flipflops with the pulse edge immediately after input changes

No need to take care to ensure it is in stable state Care must be taken to ensure that each new state
keeps the circuit in stable condition
Fig 1BLOCK DIAGRAM OF ASYNCHRONOUS CIRCUIT

• yi = Yi in steady state (but may be different during transition).

• Simultaneous change in two inputs is prohibited.

Advantages:

Low power

High performance

No need for clock

Disadvantages:

Complexity of design process

MODES OF OPERATION

 FUNDAMENTAL MODE
 PULSE MODE
Fundamental mode:

• No simultaneous changes of two or more variables

• The time between two input changes must be longer than the time it takes the circuit to a
stable state

• The input signals change one at a time and only when the circuit is in a stable condition

Pulse Mode:

• The inputs and outputs are represented by pulses.

• Only one input is allowed to have pulse present at any time.

• Similar to synchronous sequential circuits except without a clock signal.

Analysis and design of asynchronous sequential circuits

Step 1:
STEP 2:
2. An Asynchronous sequential circuit is described by the following excitation and output
function.

STEP 1: LOGIC DIAGRAM


STEP 2: PRESENT STATE,NEXT STATE and OUTPUT

STEP3: TRANSITION TABLE

STEP4: OUTPUT MAP


HAZARDS

• Unwanted switching transients that may appear at the output of a circuit are
called Hazards.

• Hazards cause the circuit to malfunction.

• Main cause of Hazard is the different propagation delays at different paths.

• Hazards occur in the combinational circuits, where they may cause a


temporary false value.

HAZARDS:

 Hazards in combinational circuits

 Hazards in sequential circuits

Types of Hazards:

 Static Hazards

 Dynamic Hazards
RACE FREE STATE ASSIGNMENT:

• In asynchronous circuits, the objective of state assignment is to avoid critical races.

• When two or more binary state variables change their value in response to a change in an
input variable, race condition occurs in an asynchronous sequential circuit.

RACES

NONCRITICAL RACES:

If the final stable state that the circuit reaches does not depend on the order in which the
state variable changes, the race condition is not harmful and it is called a non critical race.

CRITICAL RACES:

If the final stable state depends on the order in which the state variable changes, the race
condition is harmful and it is called a critical race.
CYCLES:

Two techniques are commonly used for making a critical-race free state assignment

 Shared row state assignment

 One hot state assignment


Shared row state assignment:
PROBLEMS ON ASYNCHRONOUS SEQUENTIAL CIRCUITS

1. DESIGN AN ASYNCHRONOUS SEQUENTIAL CIRCUIT WITH TWO INPUTS X


and Y and with OUTPUT Z.
Whenever Y is 1, Input X is transferred to Z. When Y is 0, the Output doesn’t change for
any change in X.
2. Design a circuit with inputs A and B to give an output Z=1, when AB=11 but only if A
becomes 1 before B, by drawing total state diagram, primitive flow table and O/P map in
which transient state is included.

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