THIAGARAJAR COLLEGE OF ENGINEERING, MADURAI-15

(A Govt. Aided Autonomous Institution affiliated to Anna University)

- where quality and ethics matter

Module 5 – Placement
CO4 : Use Optimization algorithms in placement to
determine the best position for each module on the chip.

Dr.(Mrs).D.Gracia Nirmala Rani

Associate Professor
ECE Department
Thiagarajar College of Engineering
Madurai-15
Email : [email protected]
 PLACEMENT
Placement is the problem of automatically assigning correct positions
on the chip to predesigned cells, such that some cost function is
optimized.
․Inputs: A set of fixed cells/modules, a netlist.
․Goal: Find the best position for each cell/module on the chip according
to appropriate cost functions.

 Considerations: routability/channel density, wirelength, cut size, performance, thermal

issues, I/O pads.

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Placement

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5
 Placement Objectives and Constraints
․What does a placement algorithm try to optimize?
 the total area
 the total wire length
 the number of horizontal/vertical wire segments crossing a line
․Constraints:
 the placement should be routable (no cell overlaps; no density overflow).
 timing constraints are met (some wires should always be shorter than a given
length).

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 Types of VLSI Placement

․Different design styles create different placement problems.

➢ building-block,
➢standard-cell,
➢gate-array placement

․Building block: The cells to be placed have arbitrary shapes.

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 VLSI Placement: Standard Cell Placement

Standard cells are designed in such a way that power and clock
connections run horizontally through the cell and other I/O
leaves the cell from the top or bottom sides.
․The cells are placed in rows.
․Sometimes feedthrough cells are added to ease wiring.

feedthrough

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 Consequences of Fabrication Method
․Full-custom fabrication (building block):
 Free selection of aspect ratio (quotient of height and width).
 Height of wiring channels can be adapted to necessity.

▪ Semi-custom fabrication (gate array, standard cell):

 Placement has to deal with fixed carrier dimensions.
 Placement should be able to deal with fixed channel capacities.

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 Relation with Routing

• Ideally, placement and routing should be performed

simultaneously as they depend on each other’s results.
This is, however, too complicated.
⎯ P&R: placement and routing tool

• In practice placement is done prior to routing. The

placement algorithm estimates the wire length of a net
using some metric.

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 Circuit Representation

• The data model proposed here consists of the three structures cell, port
and net.
• A cell is the basic building block of a circuit. A NAND gate is an example of
a cell.
• The point at which a connection between a wire and a cell is established is
called a port. So, a cell has one or more ports.
• The wire that electrically connects two or more ports is a net. So, a set of
ports is associated with each net and a port can only be part of a single net.
• A cell in a circuit is an instance of a master cell. The master contains all
information that all cells of a specific type, e.g. all NAND gates, have in
common. The term instance refers to each occurrence of the cell in the
circuit.
[Note that the information stored in masters originates from a library,
either a library of predesigned cells such as standard cells, or a library of
cells designed by the designer].

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The Representation of the RS Latch using the Cell –port-net Model

The graph will have three distinct sets of vertices: a cell set, a port set and a
net set. There will be two edge sets: one for edges connecting cells with ports
and one for edges connecting nets with ports.

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 All ports can be merged with their
The edges never connect vertices of the associated cell vertices. The result is a
same type and neither do they connect nets bipartite graph consisting of cell and
with cells. One could call such a graph a net vertices and a single edge set that
tripartite graph. links nets with cells.

The model can be simplified even further by omitting

the explicit representation of nets. Only the set of cell
vertices remains in the graph. For each set of cells that
are connected to the same net, edges are created
between each pair of cells in this set. It is known as a
clique in the graph.

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Data Structure definitions in pseudo-code of RS Latch

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 Wirelength Estimation Methods

Rectilinear or Manhatton distance defined as or the

Euclideandistance defined as

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16
 Global Placement

• Partitioning-based algorithms:
− The netlist and the layout are divided into smaller sub-netlists and
sub-regions, respectively
− Process is repeated until each sub-netlist and sub-region is small
enough to be handled optimally
− Detailed placement often performed by optimal solvers, facilitating
a natural transition from global placement to detailed placement
− Example: min-cut placement
• Analytic techniques:
− Model the placement problem using an objective (cost)
function, which can be optimized via numerical analysis
− Examples: quadratic placement and force-directed placement
• Stochastic algorithms:
− Randomized moves that allow hill-climbing are used to
optimize the cost function
− Example: simulated annealing
 Global Placement

Partitioning-based Analytic Stochastic

Min-cut Quadratic Force- Simulated annealing

placement placement directed
placement
 Min-Cut Placement

• Uses partitioning algorithms to divide (1) the netlist and (2) the layout
region into smaller sub-netlists and sub-regions
• Conceptually, each sub-region is assigned a portion of the original
netlist
• Each cut heuristically minimizes the number of cut nets using, for
example,
− Kernighan-Lin (KL) algorithm
− Fiduccia-Mattheyses (FM) algorithm
Min-Cut Placement

Alternating cutline directions Repeating cutline directions

2
4a a 4c 4a 3a 4e
3 3 2
a 4b 4d b a 4b 3b 4f
1 1
4e 4g 4c 3c 4g
3 3 2
c 4f 4h d b 4d 3d 4h

© 2011 Springer Verlag

2
b
 Min-Cut Placement

Input: netlist Netlist, layout area LA, minimum number of cells per region
cells_min
Output: placement P
P=Ø // assign netlist to layout area
regions = ASSIGN(Netlist,LA) // while regions still not placed
while (regions != Ø) // first element in regions
region = // remove first element of
FIRST_ELEMENT(regions) regions
REMOVE(regions, region)
// divide region into two subregions
if (region contains more than cell_min
cells) (sr1,sr2) = BISECT(region) // sr1 and sr2, obtaining the sub-
// netlists and sub-areas
ADD_TO_END(regions,sr1 // add sr1 to the end of regions
) // add sr2 to the end of regions
ADD_TO_END(regions,sr2
) // place region
else // add region to P
PLACE(region
)
ADD(P,region
)
 Min-Cut Placement – Example

Given cut1
1
:
4
2
5 6

Task: 4 x 2 placement with minimum wirelength using

alternative cutline directions and the KL algorithm
 cut1 Min-Cut-Platzierung:
4.3.1
1
Beispiel
4
2
5 6

Vertical cut cut1: L={1,2,3}, R={4,5,6}

1 4 1 4 5

2 5 2 3

3 6 0 6 0

0 0 KL
Algorithmus
cut1 cut1
 1 4 5

2 3

0 6 0

cut1
Horizontal cut cut2L: T={1,4}, B={2,0} Horizontal cut cut2R: T={3,5}, B={6,0}

1 3
cut2L cut2R
4 5

2 0

0 cut3TL cut3TR 61 5
1 4 5 3
4 3
0 2 6 0
cut3BL cut3BR 2 6
 Min-Cut Placement – Terminal Propagation

TR
2
2 2 3 3
4
3
1 1 4 1 4
BR

• Terminal Propagation
− External connections are represented by artificial connection points on
the cutline
− Dummy nodes in hypergraphs

x TR
p‘ 2 4
2 2 4
4

© 2011 Springer Verlag

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1 1 3 1 3
BR
 Min-Cut Placement

• Advantages:
− Reasonable fast
− Objective function and be adjusted, e.g., to perform timing-driven
placement
− Hierarchical strategy applicable to large circuits

• Disadvantages:
− Randomized, chaotic algorithms – small changes in input lead to large
changes in output
− Optimizing one cutline at a time may result in routing congestion
elsewhere
 Iterative Placement Improvement

An iterative placement improvement algorithm takes an existing placement and

tries to improve it by moving the logic cells. There are two parts to the
algorithm:
 The selection criteria that decides which logic cells to try moving.
 The measurement criteria that decides whether to move the selected cells.

There are several interchange or iterative exchange methods that differ in their
selection and measurement criteria:
 Pair wise interchange,
 force-directed interchange,
 force-directed relaxation, and
 force-directed pair wise relaxation.

All of these methods usually consider only pairs of logic cells to be exchanged.
A source logic cell is picked for trial exchange with a destination logic cell

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 Iterative Placement Improvement
(contd.,)
The pair wise-interchange algorithm is similar to the interchange algorithm
used for iterative improvement in the system partitioning step:

 Select the source logic cell at random.

 Try all the other logic cells in turn as the destination logic cell.
 Use any of the measurement methods we have discussed to decide on whether to
accept the interchange.
 The process repeats from step 1, selecting each logic cell in turn as a source logic
cell.

The neighborhood exchange algorithm is a modification to pairwise

interchange that considers only destination logic cells in a neighborhood —cells
within a certain distance, e, of the source logic cell. Limiting the search area for
the destination logic cell to the e -neighborhood reduces the search time.

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 FIGURE 16.26 Interchange.
(a) Swapping the source logic cell with a destination logic cell in pairwise interchange.
(b) Sometimes we have to swap more than two logic cells at a time to reach an optimum
placement, but this is expensive in computation time. Limiting the search to neighborhoods
reduces the search time. Logic cells within a distance e of a logic cell form an e-neighborhood.
(c) A one-neighborhood.
(d) A two-neighborhood.
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Force Directed Approach
 Transform the placement problem to the classical mechanics
problem of a system of objects attached to springs.
 Analogies:
 Module (Block/Cell/Gate) = Object
 Net = Spring
 Net weight = Spring constant.
 Optimal placement = Equilibrium configuration
An Example

Resultant
Force
 Force Calculation

 Hooke’s Law:
 Force = Spring Constant x Distance
 Can consider forces in x- and y-direction seperately:

Distance d ij = ( x j − xi ) 2 + ( y j − yi ) 2
Net Cost cij (xj, yj)

F = cij ( x j − xi ) 2 + ( y j − yi ) 2 F
Fx = cij ( x j − xi ) Fx
Fy = cij ( y j − yi ) (xi, yi)
Fy
 Problem Formulation

 Equilibrium: Sj cij (xj - xi) = 0 for all module i.

 However, trivial solution: xj = xi for all i, j. Everything placed on the
same position!
 Need to have some way to avoid overlapping.
 Several possible ways to avoid overlapping:
 Add some repulsive force which is inversely proportional to distance (or
distance squared).
 Have connections to fixed I/O pins on the boundary of the placement
region.
 Not really move to the equilibrium position, but a nearby position
without introducing overlapping.
Algorithms for Force-Directed Placement

Many variations exist. 2 major categories below.

 Constructive Methods:
 Coordinates of all modules are treated as variables.
 Solving all equations simultaneously.
 Iterative Methods:
 Start with some initial placement, improve placement by moving
modules iteratively.
 Select one module at a time.
 Move that module to the point of zero force.
(assume positions of all other modules are fixed)
Comments on Force-Directed Placement

✓ Use directions of forces to guide the search (compared with

‘blind’ search of simulated annealing).
✓ Usually much faster than simulated annealing.
x Focus on connections, not shapes of blocks.
x Only a heuristic; an equilibrium configuration does not
necessarily give a good placement.
? Successful or not depends on the way to eliminate overlapping
Thank You!