CSC 252/452: Computer Organization

Fall 2024: Lecture 17

Instructor: Yanan Guo

Department of Computer Science

University of Rochester
 Carnegie Mellon

Announcements
• Programming Assignment 4 released
• Due on Nov. 15th
• Cache Simulator + Matrix Transpose

• For midterm
• Come to my office hours tomorrow if TAs cannot solve your problems of
midterm grades
• For Programming Assignment 3
• Contact Mengqi if you did not generate your cookie using NetID
• For final
• December 14th at 8:30am

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General Cache Organization (S, E, B)

E = 2e lines per set

set
line

S=
2s sets

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General Cache Organization (S, E, B)

E = 2e lines per set

set
line

S=
2s sets

v tag 0 1 2 B-1

B = 2b bytes per cache line (the data)

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General Cache Organization (S, E, B)

E = 2e lines per set

set
line

S=
2s sets

v tag 0 1 2 B-1

valid bit B = 2b bytes per cache line (the data)

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General Cache Organization (S, E, B)

E = 2e lines per set

set
line

S=
2s sets

d v tag 0 1 2 B-1

dirty bit
(if write-back) valid bit B = 2b bytes per cache line (the data)
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General Cache Organization (S, E, B)

E = 2e lines per set

set
line

Cache size:
S= C = S x E x B data bytes
2s sets Overhead:
Tag, valid bit, dirty bit.
Plus bits for implementing
replacement policy
(not shown).

d v tag 0 1 2 B-1

dirty bit
(if write-back) valid bit B = 2b bytes per cache line (the data)
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Cache Access
E = 2e lines per set

Address of word:
t bits s bits b bits

S = 2s sets
tag set Line
index offset

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Cache Access • Locate set

E = 2e lines per set

Address of word:
t bits s bits b bits

S = 2s sets
tag set Line
index offset

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Cache Access • Locate set

• Check if any line in set
has matching tag
E = 2e lines per set • Yes + line valid: hit

Address of word:
t bits s bits b bits

S = 2s sets
tag set Line
index offset

v tag 0 1 2 B-1

valid bit B = 2b bytes per cache line (the data)

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Cache Access • Locate set

• Check if any line in set
has matching tag
E = 2e lines per set • Yes + line valid: hit
• Locate data starting
at offset

Address of word:
t bits s bits b bits

S = 2s sets
tag set Line
index offset

data begins at this offset

v tag 0 1 2 B-1

valid bit B = 2b bytes per cache line (the data)

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Example: Direct Mapped Cache

Direct mapped: One line per set
Assume: cache line size 8 bytes

Address of char:
v tag 0 1 2 3 4 5 6 7
t bits 0…01 100

v tag 0 1 2 3 4 5 6 7

S = 2s sets
v tag 0 1 2 3 4 5 6 7

v tag 0 1 2 3 4 5 6 7

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 Carnegie Mellon

Example: Direct Mapped Cache

Direct mapped: One line per set
Assume: cache line size 8 bytes

Address of char:
v tag 0 1 2 3 4 5 6 7
t bits 0…01 100

v tag 0 1 2 3 4 5 6 7
find set
S = 2s sets
v tag 0 1 2 3 4 5 6 7

v tag 0 1 2 3 4 5 6 7

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Example: Direct Mapped Cache

Direct mapped: One line per set
Assume: cache line size 8 bytes

Address of char:
t bits 0…01 100

v tag 0 1 2 3 4 5 6 7

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 Carnegie Mellon

Example: Direct Mapped Cache

Direct mapped: One line per set
Assume: cache line size 8 bytes

Address of char:
valid? + match: assume yes = hit
t bits 0…01 100

v tag 0 1 2 3 4 5 6 7

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Example: Direct Mapped Cache

Direct mapped: One line per set
Assume: cache line size 8 bytes

Address of char:
valid? + match: assume yes = hit
t bits 0…01 100

v tag 0 1 2 3 4 5 6 7

block offset

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 Carnegie Mellon

Example: Direct Mapped Cache

Direct mapped: One line per set
Assume: cache line size 8 bytes

Address of char:
valid? + match: assume yes = hit
t bits 0…01 100

v tag 0 1 2 3 4 5 6 7

block offset

Byte 4 is here

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 Carnegie Mellon

Example: Direct Mapped Cache

Direct mapped: One line per set
Assume: cache line size 8 bytes

Address of char:
valid? + match: assume yes = hit
t bits 0…01 100

v tag 0 1 2 3 4 5 6 7

block offset

Byte 4 is here

If tag doesn’t match: old line is evicted and replaced

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Direct-Mapped Cache Simulation

t=1 s=2 b=1 4-bit address space, i.e., Memory = 16 bytes
x xx x B=2 bytes/line, S=4 sets, E=1 line/set

Address trace (reads, one byte per read):

0 [00002],
1 [00012],
7 [01112],
8 [10002],
0 [00002]

v Tag Line
Set 0 0 ? ?
Set 1
Set 2
Set 3

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Direct-Mapped Cache Simulation

t=1 s=2 b=1 4-bit address space, i.e., Memory = 16 bytes
x xx x B=2 bytes/line, S=4 sets, E=1 line/set

Address trace (reads, one byte per read):

0 [00002], miss
1 [00012],
7 [01112],
8 [10002],
0 [00002]

v Tag Line
Set 0 0 ? ?
Set 1
Set 2
Set 3

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 Carnegie Mellon

Direct-Mapped Cache Simulation

t=1 s=2 b=1 4-bit address space, i.e., Memory = 16 bytes
x xx x B=2 bytes/line, S=4 sets, E=1 line/set

Address trace (reads, one byte per read):

0 [00002], miss
1 [00012],
7 [01112],
8 [10002],
0 [00002]

v Tag Line
Set 0 0
1 0? ?
M[0-1]
Set 1
Set 2
Set 3

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Direct-Mapped Cache Simulation

t=1 s=2 b=1 4-bit address space, i.e., Memory = 16 bytes
x xx x B=2 bytes/line, S=4 sets, E=1 line/set

Address trace (reads, one byte per read):

0 [00002], miss
1 [00012],
7 [01112],
8 [10002],
0 [00002]

v Tag Line
Set 0 0
1 0? ?
M[0-1] The two bytes at memory address 0 and 1
Set 1
Set 2
Set 3

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 Carnegie Mellon

Direct-Mapped Cache Simulation

t=1 s=2 b=1 4-bit address space, i.e., Memory = 16 bytes
x xx x B=2 bytes/line, S=4 sets, E=1 line/set

Address trace (reads, one byte per read):

0 [00002], miss
1 [00012], hit
7 [01112],
8 [10002],
0 [00002]

v Tag Line
Set 0 0
1 0? ?
M[0-1] The two bytes at memory address 0 and 1
Set 1
Set 2
Set 3

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 Carnegie Mellon

Direct-Mapped Cache Simulation

t=1 s=2 b=1 4-bit address space, i.e., Memory = 16 bytes
x xx x B=2 bytes/line, S=4 sets, E=1 line/set

Address trace (reads, one byte per read):

0 [00002], miss
1 [00012], hit
7 [01112], miss
8 [10002],
0 [00002]

v Tag Line
Set 0 0
1 0? ?
M[0-1] The two bytes at memory address 0 and 1
Set 1
Set 2
Set 3

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 Carnegie Mellon

Direct-Mapped Cache Simulation

t=1 s=2 b=1 4-bit address space, i.e., Memory = 16 bytes
x xx x B=2 bytes/line, S=4 sets, E=1 line/set

Address trace (reads, one byte per read):

0 [00002], miss
1 [00012], hit
7 [01112], miss
8 [10002],
0 [00002]

v Tag Line
Set 0 0
1 0? ?
M[0-1] The two bytes at memory address 0 and 1
Set 1
Set 2
Set 3 1 0 M[6-7]
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Direct-Mapped Cache Simulation

t=1 s=2 b=1 4-bit address space, i.e., Memory = 16 bytes
x xx x B=2 bytes/line, S=4 sets, E=1 line/set

Address trace (reads, one byte per read):

0 [00002], miss
1 [00012], hit
7 [01112], miss
8 [10002],
0 [00002]

v Tag Line
Set 0 0
1 0? ?
M[0-1] The two bytes at memory address 0 and 1
Set 1
Set 2
Set 3 1 0 M[6-7] The two bytes at memory address 6 and 7

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Direct-Mapped Cache Simulation

t=1 s=2 b=1 4-bit address space, i.e., Memory = 16 bytes
x xx x B=2 bytes/line, S=4 sets, E=1 line/set

Address trace (reads, one byte per read):

0 [00002], miss
1 [00012], hit
7 [01112], miss
8 [10002], miss
0 [00002]

v Tag Line
Set 0 0
1 0? ?
M[0-1] The two bytes at memory address 0 and 1
Set 1
Set 2
Set 3 1 0 M[6-7] The two bytes at memory address 6 and 7

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 Carnegie Mellon

Direct-Mapped Cache Simulation

t=1 s=2 b=1 4-bit address space, i.e., Memory = 16 bytes
x xx x B=2 bytes/line, S=4 sets, E=1 line/set

Address trace (reads, one byte per read):

0 [00002], miss
1 [00012], hit
7 [01112], miss
8 [10002], miss
0 [00002]

v Tag Line
Set 0 0
1 1?
0 ?
M[8-9]
M[0-1] The two bytes at memory address 8 and 9
Set 1
Set 2
Set 3 1 0 M[6-7] The two bytes at memory address 6 and 7

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Direct-Mapped Cache Simulation

t=1 s=2 b=1 4-bit address space, i.e., Memory = 16 bytes
x xx x B=2 bytes/line, S=4 sets, E=1 line/set

Address trace (reads, one byte per read):

0 [00002], miss
1 [00012], hit
7 [01112], miss
8 [10002], miss
0 [00002] miss

v Tag Line
Set 0 0
1 1?
0 ?
M[8-9]
M[0-1] The two bytes at memory address 8 and 9
Set 1
Set 2
Set 3 1 0 M[6-7] The two bytes at memory address 6 and 7

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 Carnegie Mellon

Direct-Mapped Cache Simulation

t=1 s=2 b=1 4-bit address space, i.e., Memory = 16 bytes
x xx x B=2 bytes/line, S=4 sets, E=1 line/set

Address trace (reads, one byte per read):

0 [00002], miss
1 [00012], hit
7 [01112], miss
8 [10002], miss
0 [00002] miss

v Tag Line
Set 0 0
1 0?
1 ?
M[0-1]
M[8-9] The two bytes at memory address 0 and 1
Set 1
Set 2
Set 3 1 0 M[6-7] The two bytes at memory address 6 and 7

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E-way Set Associative Cache (Here: E = 2)

E = 2: Two lines per set
Assume: cache line size 8 bytes Address of short int:
t bits 0…01 100

v tag 0 1 2 3 4 5 6 7 v tag 0 1 2 3 4 5 6 7

v tag 0 1 2 3 4 5 6 7 v tag 0 1 2 3 4 5 6 7

v tag 0 1 2 3 4 5 6 7 v tag 0 1 2 3 4 5 6 7

v tag 0 1 2 3 4 5 6 7 v tag 0 1 2 3 4 5 6 7

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E-way Set Associative Cache (Here: E = 2)

E = 2: Two lines per set
Assume: cache line size 8 bytes Address of short int:
t bits 0…01 100

v tag 0 1 2 3 4 5 6 7 v tag 0 1 2 3 4 5 6 7

v tag 0 1 2 3 4 5 6 7 v tag 0 1 2 3 4 5 6 7 find set

v tag 0 1 2 3 4 5 6 7 v tag 0 1 2 3 4 5 6 7

v tag 0 1 2 3 4 5 6 7 v tag 0 1 2 3 4 5 6 7

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E-way Set Associative Cache (Here: E = 2)

E = 2: Two lines per set
Assume: cache line size 8 bytes Address of short int:
t bits 0…01 100

v tag 0 1 2 3 4 5 6 7 v tag 0 1 2 3 4 5 6 7

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E-way Set Associative Cache (Here: E = 2)

E = 2: Two lines per set
Assume: cache line size 8 bytes Address of short int:
t bits 0…01 100
compare both

v tag 0 1 2 3 4 5 6 7 v tag 0 1 2 3 4 5 6 7

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 Carnegie Mellon

E-way Set Associative Cache (Here: E = 2)

E = 2: Two lines per set
Assume: cache line size 8 bytes Address of short int:
t bits 0…01 100
compare both

valid? + match: yes = hit

v tag 0 1 2 3 4 5 6 7 v tag 0 1 2 3 4 5 6 7

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 Carnegie Mellon

E-way Set Associative Cache (Here: E = 2)

E = 2: Two lines per set
Assume: cache line size 8 bytes Address of short int:
t bits 0…01 100
compare both

valid? + match: yes = hit

v tag 0 1 2 3 4 5 6 7 v tag 0 1 2 3 4 5 6 7

Offset within a line

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 Carnegie Mellon

E-way Set Associative Cache (Here: E = 2)

E = 2: Two lines per set
Assume: cache line size 8 bytes Address of short int:
t bits 0…01 100
compare both

valid? + match: yes = hit

v tag 0 1 2 3 4 5 6 7 v tag 0 1 2 3 4 5 6 7

Offset within a line

short int (2 Bytes) is here

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 Carnegie Mellon

E-way Set Associative Cache (Here: E = 2)

E = 2: Two lines per set
Assume: cache line size 8 bytes Address of short int:
t bits 0…01 100
compare both

valid? + match: yes = hit

v tag 0 1 2 3 4 5 6 7 v tag 0 1 2 3 4 5 6 7

Offset within a line

short int (2 Bytes) is here

No match:
• One line in set is selected for eviction and replacement
• Replacement policies: random, least recently used (LRU), …
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2-Way Set Associative Cache Simulation

t=2 s=1 b=1
xx x x 4-bit address space, i.e., Memory = 16 bytes
S=2 sets, E=2 cache lines/set

Address trace (reads, one byte per read):

0 [00002],
1 [00012],
7 [01112],
8 [10002],
0 [00002]
v Tag Line
Set 0 0 ? ? 0

Set 1 0 0

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 Carnegie Mellon

2-Way Set Associative Cache Simulation

t=2 s=1 b=1
xx x x 4-bit address space, i.e., Memory = 16 bytes
S=2 sets, E=2 cache lines/set

Address trace (reads, one byte per read):

0 [00002], miss
1 [00012],
7 [01112],
8 [10002],
0 [00002]
v Tag Line
Set 0 0 ? ? 0

Set 1 0 0

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 Carnegie Mellon

2-Way Set Associative Cache Simulation

t=2 s=1 b=1
xx x x 4-bit address space, i.e., Memory = 16 bytes
S=2 sets, E=2 cache lines/set

Address trace (reads, one byte per read):

0 [00002], miss
1 [00012],
7 [01112],
8 [10002],
0 [00002]
v Tag Line
0
Set 0 1 ?
00 ?
M[0-1] 0

Set 1 0 0

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 Carnegie Mellon

2-Way Set Associative Cache Simulation

t=2 s=1 b=1
xx x x 4-bit address space, i.e., Memory = 16 bytes
S=2 sets, E=2 cache lines/set

Address trace (reads, one byte per read):

0 [00002], miss
1 [00012], hit
7 [01112],
8 [10002],
0 [00002]
v Tag Line
0
Set 0 1 ?
00 ?
M[0-1] 0

Set 1 0 0

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 Carnegie Mellon

2-Way Set Associative Cache Simulation

t=2 s=1 b=1
xx x x 4-bit address space, i.e., Memory = 16 bytes
S=2 sets, E=2 cache lines/set

Address trace (reads, one byte per read):

0 [00002], miss
1 [00012], hit
7 [01112], miss
8 [10002],
0 [00002]
v Tag Line
0
Set 0 1 ?
00 ?
M[0-1] 0

Set 1 0 0

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 Carnegie Mellon

2-Way Set Associative Cache Simulation

t=2 s=1 b=1
xx x x 4-bit address space, i.e., Memory = 16 bytes
S=2 sets, E=2 cache lines/set

Address trace (reads, one byte per read):

0 [00002], miss
1 [00012], hit
7 [01112], miss
8 [10002],
0 [00002]
v Tag Line
0
Set 0 1 ?
00 ?
M[0-1] 0

Set 1 1
0 01 M[6-7] 0

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 Carnegie Mellon

2-Way Set Associative Cache Simulation

t=2 s=1 b=1
xx x x 4-bit address space, i.e., Memory = 16 bytes
S=2 sets, E=2 cache lines/set

Address trace (reads, one byte per read):

0 [00002], miss
1 [00012], hit
7 [01112], miss
8 [10002], miss
0 [00002]
v Tag Line
0
Set 0 1 ?
00 ?
M[0-1] 0

Set 1 1
0 01 M[6-7] 0

12
 Carnegie Mellon

2-Way Set Associative Cache Simulation

t=2 s=1 b=1
xx x x 4-bit address space, i.e., Memory = 16 bytes
S=2 sets, E=2 cache lines/set

Address trace (reads, one byte per read):

0 [00002], miss
1 [00012], hit
7 [01112], miss
8 [10002], miss
0 [00002]
v Tag Line
0
Set 0 1 ?
00 ?
M[0-1] 1
0 10 M[8-9]

Set 1 1
0 01 M[6-7] 0

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 Carnegie Mellon

2-Way Set Associative Cache Simulation

t=2 s=1 b=1
xx x x 4-bit address space, i.e., Memory = 16 bytes
S=2 sets, E=2 cache lines/set

Address trace (reads, one byte per read):

0 [00002], miss
1 [00012], hit
7 [01112], miss
8 [10002], miss
0 [00002] hit
v Tag Line
0
Set 0 1 ?
00 ?
M[0-1] 1
0 10 M[8-9]

Set 1 1
0 01 M[6-7] 0

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Today
• Processes and Signals: running multiple programs concurrently
• Processes
• Process Control
• Signals

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Processes
• Definition: A process is an instance of a program
running in a computer..
• One of the most profound ideas in computer science
• Not the same as “program” or “processor”

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 Carnegie Mellon

Processes
• Definition: A process is an instance of a program
running in a computer..
• One of the most profound ideas in computer science
• Not the same as “program” or “processor”

• Process provides each program with two key

abstractions:
• “Owns” the CPU
• Each program seems to have exclusive use of the
CPU
• Done by the OS kernel through “context switching”
• Private address space
• Each program seems to have exclusive use of main
memory.
• Provided by OS through “virtual memory”
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 Carnegie Mellon

Processes
• Definition: A process is an instance of a program
running in a computer..
• One of the most profound ideas in computer science
• Not the same as “program” or “processor”

• Process provides each program with two key

abstractions:
• “Owns” the CPU
• Each program seems to have exclusive use of the CPU
CPU Registers
• Done by the OS kernel through “context switching”
• Private address space
• Each program seems to have exclusive use of main
memory.
• Provided by OS through “virtual memory”
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Processes
• Definition: A process is an instance of a program
running in a computer..
• One of the most profound ideas in computer science Memory
• Not the same as “program” or “processor” Stack
• Process provides each program with two key Heap
Data
abstractions: Code
• “Owns” the CPU
• Each program seems to have exclusive use of the CPU
CPU Registers
• Done by the OS kernel through “context switching”
• Private address space
• Each program seems to have exclusive use of main
memory.
• Provided by OS through “virtual memory”
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Multiprocessing: The Illusion

Memory Memory Memory
Stack Stack Stack
Heap Heap Heap
Data Data
… Data
Code Code Code

CPU CPU CPU

Registers Registers Registers

• Computer runs many processes simultaneously

• Applications for one or more users
• Web browsers, email clients, editors, …
• Background tasks
• Monitoring network & I/O devices

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Multiprocessing Example

• Running program “top” on Unit/Linux

• System has 123 processes, 5 of which are active
• Identified by Process ID (PID)
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Multiprocessing Illustration
Memory
Process 1 Process 2 Process N
Stack Stack Stack
Heap Heap Heap
Data Data Data
Code Code Code

CPU
Registers

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 Carnegie Mellon

Multiprocessing Illustration
Memory
Process 1 Process 2 Process N
Stack Stack Stack
Heap Heap Heap
Data Data Data
Code Code Code

CPU
Registers

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 Carnegie Mellon

Multiprocessing Illustration
Memory
Process 1 Process 2 Process N
Stack Stack Stack
Heap Heap Heap
Data Data Data
Code Code Code

Saved
registers

CPU
Registers

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 Carnegie Mellon

Multiprocessing Illustration
Memory
Process 1 Process 2 Process N
Stack Stack Stack
Heap Heap Heap
Data Data Data
Code Code Code

Saved
registers

CPU
Registers

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 Carnegie Mellon

Multiprocessing Illustration
Memory
Process 1 Process 2 Process N
Stack Stack Stack
Heap Heap Heap
Data Data Data
Code Code Code

Saved Saved
registers registers

CPU
Registers

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 Carnegie Mellon

Multiprocessing Illustration
Memory
Process 1 Process 2 Process N
Stack Stack Stack
Heap Heap Heap
Data Data Data
Code Code Code

Saved Saved
registers registers

CPU
Registers

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 Carnegie Mellon

Multiprocessing Illustration
Memory
Process 1 Process 2 Process N
Stack Stack Stack
Heap Heap Heap
Data Data Data
Code Code Code

Saved Saved Saved

registers registers registers

CPU
Registers

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 Carnegie Mellon

Multiprocessing Illustration
Memory
Process 1 Process 2 Process N
Stack Stack Stack
Heap Heap Heap
Data Data Data
Code Code Code

Saved Saved Saved

registers registers registers

CPU
Registers

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 Carnegie Mellon

Multiprocessing Illustration
Memory
Process 1 Process 2 Process N
Stack Stack Stack
Heap Heap Heap
Data Data Data
Code Code Code

Saved Saved Saved

registers registers registers

CPU
Registers

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 Carnegie Mellon

Multiprocessing Illustration
Memory
Process 1 Process 2 Process N
Stack Stack Stack
Heap Heap Heap
Data Data Data
Code Code Code

Saved Saved Saved

registers registers registers

Context switch
CPU
managed by the OS.
Registers
Not controllable by
programmers.
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Multiprocessing: The Multi-Core Case

Memory
Stack Stack Stack
Heap Heap Heap
Data Data … Data
Code Code Code
Saved Saved Saved
registers registers registers

CPU CPU
• Multicore processors
• Multiple CPUs on single chip
Registers Registers • Share main memory (and some of
the caches)
• Each can execute a separate process
• Scheduling of processes onto
cores done by kernel

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Concurrent Processes
• Each process is a logical control flow.
• Two processes run concurrently (are concurrent) if their flows
overlap in time
• Otherwise, they are sequential

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Concurrent Processes
• Each process is a logical control flow.
• Two processes run concurrently (are concurrent) if their flows
overlap in time
• Otherwise, they are sequential
• Examples (running on single core):

Process A Process B Process C

Time

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Concurrent Processes
• Each process is a logical control flow.
• Two processes run concurrently (are concurrent) if their flows
overlap in time
• Otherwise, they are sequential
• Examples (running on single core):
• Concurrent: A & B, A & C

Process A Process B Process C

Time

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Concurrent Processes
• Each process is a logical control flow.
• Two processes run concurrently (are concurrent) if their flows
overlap in time
• Otherwise, they are sequential
• Examples (running on single core):
• Concurrent: A & B, A & C
• Sequential: B & C
Process A Process B Process C

Time

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User View of Concurrent Processes

• Control flows for concurrent processes are physically disjoint in
time

• However, we can think of concurrent processes as running in

parallel with each other

Process A Process B Process C

Time

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Context Switching
• Processes are managed by a shared chunk of memory-resident
OS code called the kernel
• Important: the kernel is not a separate process, but rather runs as part of
some existing process.

• Control flow passes from one process to another via a context

switch
Process A Process B

user code

kernel code context switch

Time user code

kernel code context switch

user code

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Today
• Processes and Signals: running multiple programs concurrently
• Processes
• Process Control
• Signals

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Obtaining Process IDs

•pid_t getpid(void)
• Returns PID of current process

•pid_t getppid(void)
• Returns PID of parent process

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Creating and Terminating Processes

From a programmer’s perspective, we can think of a process as
being in one of three states

• Running
• Process is either executing, or waiting to be executed and will
eventually be scheduled (i.e., chosen to execute) by the kernel

• Stopped
• Process execution is suspended and will not be scheduled until
further notice (through something call signals)

• Terminated
• Process is stopped permanently

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Terminating Processes
• Process becomes terminated for one of three reasons:
• Receiving a signal whose default action is to terminate
• Returning from the main routine
• Calling the exit function

•void exit(int status)

• Terminates with an exit status of status
• Convention: normal return status is 0, nonzero on error
• Another way to explicitly set the exit status is to return an integer value
from the main routine

•exit is called once but never returns.

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Creating Processes
• Parent process creates a new running child process by calling
fork

•int fork(void)
• Returns 0 to the child process, child’s PID to parent process
• Child is almost identical to parent:
• Child get an identical (but separate) copy of the parent’s (virtual)
address space (i.e., same stack copies, code, etc.)
• Child gets identical copies of the parent’s open file descriptors
• Child has a different PID than the parent

• fork is interesting (and often confusing) because

it is called once but returns twice

26
 Carnegie Mellon

fork Example
int main()
{
pid_t pid;
int x = 1;

pid = Fork();
if (pid == 0) { /* Child */
printf("child : x=%d\n", ++x);
exit(0);
}

/* Parent */
printf("parent: x=%d\n", --x);
exit(0);
} fork.c

linux> ./fork
parent: x=0
child : x=2

27
 Carnegie Mellon

fork Example
int main() • Call once, return twice
{
pid_t pid;
int x = 1;

pid = Fork();
if (pid == 0) { /* Child */
printf("child : x=%d\n", ++x);
exit(0);
}

/* Parent */
printf("parent: x=%d\n", --x);
exit(0);
} fork.c

linux> ./fork
parent: x=0
child : x=2

27
 Carnegie Mellon

fork Example
int main() • Call once, return twice
{
pid_t pid;
• Concurrent execution
int x = 1; • Can’t predict execution
order of parent and child
pid = Fork();
if (pid == 0) { /* Child */
printf("child : x=%d\n", ++x);
exit(0);
}

/* Parent */
printf("parent: x=%d\n", --x);
exit(0);
} fork.c

linux> ./fork
parent: x=0
child : x=2

27
 Carnegie Mellon

fork Example
int main() • Call once, return twice
{
pid_t pid;
• Concurrent execution
int x = 1; • Can’t predict execution
order of parent and child
pid = Fork();
if (pid == 0) { /* Child */ • Duplicate but separate
printf("child : x=%d\n", ++x); address space
exit(0); • x has a value of 1 when fork
}
returns in parent and child
/* Parent */ • Subsequent changes to x
printf("parent: x=%d\n", --x);
are independent
exit(0);
} fork.c

linux> ./fork
parent: x=0
child : x=2

27
 Carnegie Mellon

fork Example
int main() • Call once, return twice
{
pid_t pid;
• Concurrent execution
int x = 1; • Can’t predict execution
order of parent and child
pid = Fork();
if (pid == 0) { /* Child */ • Duplicate but separate
printf("child : x=%d\n", ++x); address space
exit(0); • x has a value of 1 when fork
}
returns in parent and child
/* Parent */ • Subsequent changes to x
printf("parent: x=%d\n", --x);
are independent
exit(0);
} fork.c • Shared open files
• stdout is the same in both
linux> ./fork parent and child
parent: x=0
child : x=2

27
 Carnegie Mellon

Process Address Space

Memory
Kernel space invisible to
user code
User stack
(created at runtime)
%rsp
(stack
pointer)

Memory-mapped region for

shared libraries

brk
Run-time heap
(created by malloc)

Read/write data segment

Loaded from the (.data, .bss)
executable file Read-only code segment Program
(.init, .text, .rodata) Counter
0x400000
Unused
0 28
 Carnegie Mellon

Process Address Space

Memory
Kernel space invisible to
user code
User stack
(created at runtime)
%rsp
(stack
pointer)

Memory-mapped region for

shared libraries

brk
Run-time heap
(created by malloc)

Read/write data segment

Loaded from the (.data, .bss)
executable file Read-only code segment Program
(.init, .text, .rodata) Counter
0x400000
Unused
0 28