Dept of Electronics
III-Sem, HDL-Lab
Introduction to Vivado FPGA Tool Suite
VIVADO 2014.14 PROJECT NAVIGATOR TOOL TUTORIAL
1. Double click on Vivado 2014.4 icon
Fle Fo Toos ndo Heb
VIVADO Protucty tAut:pied
Rocont PrOjots
Quidk Start
CAESAtreer2
Open PPoed pen Eade PoRt
Tasks
Coen Hadat Manags Aa 1d S
Informaton Center
Doaaton and Tuluna Rdcane N Gade
2. Double click on create new project option
3. Click Next.
location, click next
4. Give project name and select the project
Next
5. Select RTL project Click
New Project
Add Sources Createa new source fle on
containing HDL and netist files, to add to your project.
SOdHOL and netdist fles, or directories alsO add and geate sources later.
You can
disk and add it to your project.
HDL Source For Location
Name Library
Index
Add Fles.. Add Directories. Create Fie.
flec into project
Scan and add RTL indude
Copy sources into project
subdirectories
Add sources from
Simulator language:Veriog
Target language:Veriog
Einish Cancel
<Badk Next> l
Engineering
EOE Dept. BMS College of
Dept of Electronics III-Sem, MDL-Lab
6. Click on Create File, select the target language, simulator language and source type as Verilog.
New Project
Add Sources
Spedfy HDL and netist fles, or drectories containing HDL and netist iles, to add to your project. Create a new source fle on
disk and add it to your project, You can also add and reate sOurces la ter.
Index Name Library HDL SOurce For LOcation
Create Source File
Create a new source file and add it to your project.
Ele type: Verilog
File name: gates
Fie location: 6 ocal to Project>
sOK Cancel
Scan and add RTL incdude fles into proec
Copy sOurces into project
D Add sources from subdirectories
Target languoge: Verilog Simulator language: Veriog
sSBack Next > Einish Cancel,
7. Enter the name for the source file to be created. Click Next.
New Project
Default Part
Choose a default Xilinx part or board for your project. This can be hanged later .
Select:EParts Boards
Flter
Product category: A Pakage: pg236
Artix-7 Speed grade:-1
Family:
Artix-7 Temp grade:
SubFamiy:
Reset AI Flterssi
Searh:Q
Available LUT Blok Gb GTPE
I/O Pin FlipFlops DSPs
Part Count IOBs lements RAMS Transceivers Trans
106 10400 20800 25 45 2
xc7a 15tpg236-1 236
KxTa35tapg 236-10 pAT 106E2080041600RI 5 0 E 9 0 K 2 2
106 32600 65200 75 120
xc7a50tcpg 236-1 236
aSBadk Next > FinishCancel
4
ECE Dept. BMS College of Engineerng
Dept of Electronics II-Sem, DL-Lab
8. Select the board details as mentioned in the above slide to
Artix-7 Board. Click Next.
implement the application code on the
9. Define a module, module name is the name of the source file
created (step 7)
10. Give the nane for the /O port to use in the source file. Choose the
inout.
direction as input or output or
11. If the /O ports are vector select bus, specify the the size of the vector by specifying the LSB and
MSB value. For ex: for an input of 4-bits LSB=0 and MSB=3.
Define Module
Define a module and spedfy I/O Ports to add to your source file.
For each port specfied:
MSB and LSB values will be ignored unless its Bus column is hecked.
Ports with blank names will not be written.
Module Definition
Module name:gates
I/O Port Definitons
Port Name Direction Bus MSB LSE
a,b,s input
y output C
OK Cancel
12.In the Sources pane, double-click the gates.v entry to open the file in text mode on
ECE Dept. BMSCollege of Engineering
Dept of Electronics II1-Sem, JDL-Lab
Sona
13.Click on Run Simulation > Run Behavioral Simulation under the Project Manager tasks of the Flow
Navigator pane. You will see a simulator output similar to the one shown below
4euutrHt
14. Synthesize the Design Step. Synthesize the
Summary output. Click on Run Synthesis underdesign with the Vivado synthesi_ tool and analyze the Project
the Synthesis tasks of the Flow Navigator pane. The
synthesis process will be run on the counter.v file (and all its
process is completed a Synthesis Completed dialog will appear. hierarchical files if they exist). When the
(expand Synthesized Design if necessary), click on Schematic to In The Flow Navigator, under Synthesis
View. view the synthesized design in a schematic
EOE Dept. BMS College of Engineering
6
