Sri Lanka Institute of Information Technology
B.Sc. Engineering (Hons) Degree
End Semester Examination
Year 3 – Semester 2 (2022)
EC3032 – Power Electronics
Duration: 2 Hours + 10 minutes
October 2022
Instructions to Candidates:
• This paper has four questions.
• Answer all questions.
• All questions carry equal marks.
• Total marks for the paper is 100.
• Marks allocated for each question and sub parts are indicated.
• Marks will be awarded to clear, logical steps in writing your solution.
• You are allowed to bring one A4 sheet of paper containing handwritten notes on
both sides.
Page 1 of 6
Question 1 [25 marks]
Fig. Q1 shows a full wave bridge type-controlled rectifier constructed using four thyristors, T1 to
T4. The input voltage to the circuit is sinusoidal with 50 Hz frequency and having an RMS value
of 230 V. The load is having a resistance RL of 100 . Each thyristor is fired at an angle of α, from
the time they become forward biased, where 0O < α < 180O. Assuming that the thyristors are ideal,
(a) Explain the circuit operation to obtain a variable output voltage across the load.
(3 marks)
(b) If α = 30O, for two cycles of the supply voltage waveform, sketch the following waveforms
one below the other, and aligned, on the graph sheet provided.
(i) The supply voltage waveform, vs
(ii) The output voltage waveform, vo
(iii) Voltage across thyristor T3, vT3
(6 marks)
(c) Derive an expression for the average value of the output voltage and use your expression
to obtain the maximum and minimum values of the output.
(10 marks)
(d) In designing the above circuit, what would be the minimum values required for the
(i) Maximum reverse blocking voltage (VRRM)
(ii) Average on-state current (ITAV)
(iii) RMS current
(6 marks)
T1 T4
+ vo -
vs -
RL
T3 vT3 T2
Fig. Q1
Page 2 of 6
Question 2 [25 marks]
Design a buck converter to meet the specifications given in Table Q2.
Table Q2
Output power, PO 3W
Output voltage, VO 12 V
Input voltage, VIN 30 V
∆𝑉𝑂 5%
× 100
𝑉𝑂
Switching frequency, fs 50 kHz
Your design must include the following:
(a) A labelled circuit diagram.
(2 marks)
(b) Derivation of any equations used with assumptions.
(15 marks)
(c) Values of the circuit elements used.
(8 marks)
Page 3 of 6
Question 3 [25 marks]
Fig. Q3 shows the circuit schematic of a 180O conduction type, 3 – phase voltage source inverter,
supplying a three-phase resistive load.
S1 S3 S5
15 V Va Vb Vc
S4 S6 S2
10 10 10
Fig. Q3
(a) Identify which switches are conducting during each phase interval indicated in Table Q3,
if S1, S5, and S6, are conducting during 0O to 60O interval. Copy Table Q3 into your answer
book and complete it by filling in ‘1’ for conducting switches and ‘0’ for non-conducting
switches.
(5 marks)
Table Q3
Interval S1 S2 S3 S4 S5 S6
O O
0 to 60 1 0 0 0 1 1
O O
60 to 120
120O to 180O
180O to 240O
240O to 300O
300O to 360O
Page 4 of 6
(b) For each switching interval in Table Q3, with the switching pattern identified by you,
calculate the phase voltages, Va, Vb and Vc.
(9 marks)
(c) Using your values in (b), sketch the phase voltages Va, Vb, and Vc on the graph sheet
provided.
(6 marks)
(d) Suggest a method to obtain three-phase sinusoidal voltages from your phase voltages in
(c).
(5 marks)
Page 5 of 6
Question 4 [25 marks]
Fig. Q4 shows a half wave AC voltage control circuit, which uses a thyristor (T) and a diode (D).
The supply voltage is vs = Vmsint, with an RMS value of 230 V at 50 Hz frequency, and a load
resistance, RL = 220 . The thyristor T is fired at an angle of (0O < α < 180O) from the time it
enters its forward bias region.
(a) Sketch the output voltage vo waveform for an = 45O.
(2 marks)
(b) Deriving any equations used, calculate the power delivered to the load, PL, if = 45O.
(12 marks)
(c) If the required power output to the load is 200 W, show how you would obtain that output.
(4 marks)
(d) If the required power output to the load is 100 W, it may not be possible to obtain that
power output from this circuit. Explain why.
(4 marks)
(e) How would you modify the circuit in Fig. Q4 to obtain the power output in (d)?
(3 marks)
D
vs RL vo
Fig. Q4
*END OF PAPER*
Page 6 of 6
