Springer Tracts in Electrical and Electronics Engineering

Sangeeta Singh
Shashi Kant Sharma
Durgesh Nandan Editors

Beyond
Si-Based
CMOS Devices
Materials to Architecture
Springer Tracts in Electrical and Electronics
Engineering

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Sangeeta Singh · Shashi Kant Sharma ·
Durgesh Nandan
Editors

Beyond Si-Based CMOS

Devices
Materials to Architecture
Editors
Sangeeta Singh Shashi Kant Sharma
Department of Electronic Department of Electronic
and Communication Engineering and Communication Engineering
National Institute of Technology Indian Institute of Information Technology
Patna, Bihar, India Ranchi, Jharkhand, India

Durgesh Nandan
School of Computer Science and Artificial
Intelligence
SR University
Warangal, Telangana, India

ISSN 2731-4200 ISSN 2731-4219 (electronic)

Springer Tracts in Electrical and Electronics Engineering
ISBN 978-981-97-4622-4 ISBN 978-981-97-4623-1 (eBook)
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Preface

The semiconductor industry has seen significant transformation in recent years,

driven by continuous innovation and the integration of cutting-edge materials with
established technologies. Primarily, this has increased funding for R&D due to the
necessity of breaking the conventional boundaries of silicon-based technology limi-
tations, as predicted by Moore. This field is looking more and more to novel materials
and heterogeneous integration approaches as powerful tools for potential improve-
ments in performance and functionality. The book takes the reader on a tour of these
innovative ideas that were significantly reshaping semiconductor technology and its
effects on numerous industries.
Advanced materials that offer new capabilities in electronics, like graphene,
carbon nanotubes, and 2D material, are leading the way from high-speed processing
to energy efficiency. These materials not only offer improved device performance, but
also pose significant challenges for their fabrication and integration at the nanoscale.
Integrating these newer materials with conventional CMOS technology offers a
variety of specific opportunities and challenges as the field keeps developing.
This book aims to present an overview of the most recent research findings
in the fields of advanced semiconductor device technologies, material science,
and nanotechnology. Researchers from numerous companies and universities have
contributed chapters to this book. It is devoted to the analysis, modelling, and simu-
lation of the application of these cutting-edge technologies. We aim to cover each
aspect of novel materials and semiconductor technologies, ranging from new device
architectures to integration strategies.
Through an extensive platform, researchers and academicians will be able to
discuss innovative approaches to address the different technical challenges that arise
in real-world applications of these advanced materials. This book discusses how
semiconductor technology can be used in a variety of industries, including computing,
energy, and telecommunications. Additionally, we want to give researchers a single
resource for using these cutting-edge materials in a variety of fields, with an emphasis
on potential problems and creative solutions. Additionally, examples associated with
theoretical models and practical applications will be covered in this book. These
would serve as excellent examples that strengthen the theory and help researchers,

v
vi Preface

academicians, scientists, and industrialists in their work. It is anticipated that by this

book it will close the gap between theoretical analysis and real-world application,
laying the foundation for the upcoming era of semiconductor devices and electronics.
Chapter 1 examines the advancement of integrated circuit scaling made possible
by CMOS technology, along with the shift towards heterogeneous integration and
beyond-CMOS devices. The first part discusses the potential revolutionary appli-
cations of semiconductors that are linked to new signal processing devices and
microarchitectures, as well as their challenges.
Chapter 2 discusses the performance of Si-CMOS devices based on nanowires,
particularly their integration and fabrication. The performance of the device could be
greatly enhanced by these features. The discussion goes into extensive detail about
the physical and chemical characteristics of silicon nanowires, highlighting their
importance in the creation of cutting-edge semiconductor devices.
Chapter 3 explores about carbon nanotube transistors. It demonstrates how they
can lower manufacturing costs for devices and allow for a greater reduction in device
size. This chapter provides a thorough overview of the benefits and uses of carbon
nanotubes in modern integrated systems.
Chapter 4 covers the practical applications of graphene in field-effect transistors.
It goes over the development, properties, and challenges of creating graphene-based
devices for various electronic uses. The main focus is on its ability to bring about
revolutionary changes in industries like home appliances and medicine.
Chapter 5 gives thorough explanation of the synthesis, characteristics, and uses
of black phosphorous and transition metal dichalcogenides that are thin-film 2D
materials. This chapter will look into how these materials, by making devices smaller
and using less power, can help advance sustainable technology.
Chapter 6 gives the integration of 2D materials for electronic, photonic, and energy
applications in Si-CMOS devices. The book provides a thorough analysis of the
steps involved in choosing materials, creating devices, and resolving issues related
to incorporating 2D materials into electronic and photonic technologies.
Chapter 7 examines and explores the Tunnelling Field-Effect Transistors (TFETs).
This chapter focuses on the ability of TFETs to overcome the drawbacks of traditional
MOS devices and simultaneously achieve improved performance with lower power
consumption is the main focus.
Chapter 8 covers the incorporation of ferroelectric negative capacitance into field-
effect transistors, which shows promise for improved power efficiency and manu-
facturing processes that work with current methods. The purpose of this work is to
explore the possibility of using negative capacitance to greatly increase transistor
efficiency.
Chapter 9 examines the development and application of nanoelectromechanical
systems (NEMS) switches, with a focus on their effectiveness, scalability, and poten-
tial to have a major impact on nanoelectronics through improved performance and
energy efficiency.
Chapter 10 gives the potential of hybrid phase-transition and phase-transition
Field-Effect Transistors (FETs) in device and circuit design, as well as how they
could help in the creation of future electronic systems.
Preface vii

Chapter 11 deals with Feedback Field-Effect Transistors (FBFETs) that are

introduced as a novel device with memory-like properties and potentially useful
applications in neuromorphic devices because of their remarkable performance
metrics.
Chapter 12 examines the advancement of steep-slope devices, namely the ReFET
(resistive gate field-effect transistor). It focuses on their potential for low-power
applications and discusses the possibilities and problems that come with their
integration.
Chapter 13 introduces the idea of a new type of Spin Field-Effect Transistor
(SFET). Its design principles are covered, and the importance of using spin to achieve
fast switching and better performance is highlighted.
This book provides a thorough and perceptive examination of the difficulties
involved in developing new semiconductor devices. It is meant to give academicians,
scientists, engineers, and researchers a broad perspective on the future of technology.
This initiative promotes innovation and advances the development of future electronic
systems by using a multidisciplinary approach. It represents a major advancement
in closing the knowledge gap between theoretical ideas and real-world applications
in semiconductor technology.

Patna, India Sangeeta Singh

Ranchi, India Shashi Kant Sharma
Warangal, India Durgesh Nandan
Contents

Part I Beyond Si-Based CMOS Devices: Needs, Opportunities

and Challenges
1 Beyond Si-Based CMOS Devices: Needs, Opportunities,
and Challenges . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
Amrita Rai, Dhananjay Gupta, Himanshu Mishra,
Durgesh Nandan, and Shamimul Qamar
2 Nanowire-Based Si-CMOS Devices . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
Raghvendra Kumar Mishra, Vinayak Mishra,
and Satya Narain Mishra
3 Carbon Nanotube FETS: An Alternative for Beyond Si Devices . . . . 89
Shailendra K. Tripath
4 Graphene-Based Devices for Beyond CMOS Applications . . . . . . . . . 101
Basanta Bhowmik
5 Other Potential 2-D Materials for CMOS Applications . . . . . . . . . . . . 121
Poonam Subudhi and Deepak Punetha
6 Heterogeneous Integration of 2D Materials with Silicon
Complementary Metal Oxide Semiconductor (Si-CMOS)
Devices . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 149
Raghvendra Kumar Mishra, Susmi Anna Thomas,
Deepa Sethi singh, Jayesh Cherusseri, Iva Chianella,
Hamed Yazdani Nezhad, and Saurav Goel

Part II Beyond CMOS Charge Based Steep Switching Devices:

Recent Trends and Opportunities
7 TFET: From Material to Device Perspective . . . . . . . . . . . . . . . . . . . . . 183
Pradeep Kumar Kumawat, Shilpi Birla, and Neha Singh

ix
x Contents

8 Negative Capacitance Field-Effect Transistor (NCFET):

Strong Beyond CMOS Device . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 205
Sukanta Kumar Swain, Abhishek Raj, and Shashi Kant Sharma
9 Nanoelectromechanical Switches: As a Steep Switching Device . . . . 233
Noel Prashant Ratchagar and Amitesh Kumar
10 The Device-Circuit Co-design Perspective on Phase-Transition
and Hybrid Phase-Transition (Hyper-) FETs, Phase-FETs,
and MOSFET . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 253
Abhishek Choubey, Shruti Bhargava Choubey, Durgesh Nandan,
and Kumar Gautam
11 Feedback Field-Effect Transistors/Zero Subthreshold Swing
and Zero Impact Ionization FET . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 273
Rapolu Anil Kumar, Kondavitee Girija Sravani,
Karumuri Srinivasa Rao, and Aime Lay-Ekuakille
12 Resistive-Gate Field-Effect Transistor: A Potential
Steep-Slope Device . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 291
Abhinandan Jain, Lalit Kumar Lata, Neeraj Jain,
and Praveen K. Jain
13 Spin Field-Effect Transistor: For Steep Switching Behavior . . . . . . . 307
Karumuri Srinivasa Rao, K. Rohith Sai,
Kondavitee Girija Sravani, and Aime Lay-Ekuakille
Editors and Contributors

About the Editors

Dr. Sangeeta Singh is an assistant professor at the Department of Electronics

and Communication Engineering, NIT Patna, India. She has been recognized as
an eminent scholar in the field of Electronics and Computer Engineering. She has
published many research papers in reputed national/international journals and confer-
ences. Along with this, she has actively participated in various technical course
workshops, seminars, etc., at the NITs. She has been recognized as an eminent scholar
in the field of Electronics and Computer Engineering. She has actively participated
in various technical course workshops and seminars at the NITs. She has edited three
books (titles and ISBN). She is a senior member of IEEE, IEEE EDS Society, IET,
etc. She has chaired sessions, served on TPCs, and served as a reviewer for over 10
reputable national and international conference proceedings. She holds three Indian
patents as an inventor or co-inventor.

Dr. Shashi Kant Sharma is working as an assistant professor in Department

of Electronics and Communication Engineering at Indian Institute of Information
Technology, Ranchi, India (An Institute of National Importance Under MHRD,
Government of India). He is in the Board of Governors of IIIT Ranchi and is also
serving as an associate dean: Faculty Affairs, Infrastructure and Campus Adminis-
tration. He holds a Ph.D. from Malaviya National Institute of Technology, Jaipur. He
has published more than 40 papers in many leading international journals, books and
international conferences. He has awarded 3 Ph.Ds. and also serves as a reviewer
in several peer-reviewed journals and conferences. His research interests include
modelling, simulation, and fabrication of emerging nanoscale devices and circuits.

Dr. Durgesh Nandan is working as an associate dean (Research) and associate

faculty in the School of CS and AI at SR University, Warangal, India. He received
the B.Tech. degree in ECE from the BCE, Bhopal, India, in 2006; the M.Tech. degree
with honours in Microelectronics and VLSI from TIT Bhopal, India, in 2013; and the

xi
xii Editors and Contributors

Ph.D. degree from the Jaypee University of Engineering and Technology, India, in
2018. He is a session chair, TPC, and reviewer for more than 100 reputed national
and international conference proceedings. He is the author or co-author of more
than 150 research papers, which were published in SCI, Scopus, and peer-reviewed
international journals and conference proceedings. His research interests extend to
several areas, like computer arithmetic, VLSI architecture for signal processing appli-
cations, speech processing, the hardware architecture of real-time big data and AI
applications, and the Internet of Things.

Contributors

Basanta Bhowmik Thin Film Devices Laboratory, Department of Electronics and

Communication Engineering, National Institute of Technology, Jamshedpur, India
Shilpi Birla Department of Electronics and Communication Engineering, Manipal
University Jaipur, Jaipur, Rajasthan, India
Jayesh Cherusseri Graphene and Advanced 2D Materials Research Group
(GAMRG), School of Engineering and Technology, Sunway University, No. 5 Jalan
University, Bandar Sunway, Petaling Jaya, Malaysia
Iva Chianella Enhanced Composites and Structures Centre, School of Aerospace,
Transport and Manufacturing, Cranfield University, Cranfield, UK
Abhishek Choubey Sreenidhi Institute of Science and Technology, Hyderabad,
Telangana, India
Shruti Bhargava Choubey Sreenidhi Institute of Science and Technology, Hyder-
abad, Telangana, India
Kumar Gautam AI Graduate School, Gwangju Institute of Science and Tech-
nology, Gwangju, Korea
Kondavitee Girija Sravani Department of ECE, VLSI-Microelectronics Research
Center, KL University, Vaddeswaram, Guntur, Andhra Pradesh, India
Saurav Goel School of Engineering, London South Bank University, London, UK
Dhananjay Gupta Embedded System Engineer, Intozi Tech Pvt Ltd, Gurugram,
India
Abhinandan Jain Department of Electronics and Communication Engineering,
Swami Keshvanand Institute of Technology, Management and Gramothan, Jaipur,
Rajasthan, India
Neeraj Jain Department of Electronics and Communication Engineering, Swami
Keshvanand Institute of Technology, Management and Gramothan, Jaipur,
Rajasthan, India
Editors and Contributors xiii

Praveen K. Jain Department of Electronics and Communication Engineering,

Swami Keshvanand Institute of Technology, Management and Gramothan, Jaipur,
Rajasthan, India
Amitesh Kumar Department of Electrical Engineering, National Institute of Tech-
nology, Patna, India
Rapolu Anil Kumar Department of ECE, VLSI-Microelectronics Research
Center, KL University, Vaddeswaram, Guntur, Andhra Pradesh, India
Pradeep Kumar Kumawat Department of Electronics and Communication Engi-
neering, Manipal University Jaipur, Jaipur, Rajasthan, India
Lalit Kumar Lata Department of Electronics and Communication Engineering,
Swami Keshvanand Institute of Technology, Management and Gramothan, Jaipur,
Rajasthan, India
Aime Lay-Ekuakille Department of Innovation Engineering, University of
Salento, Lecce, Italy
Himanshu Mishra Embedded System Engineer, Intozi Tech Pvt Ltd, Gurugram,
India
Raghvendra Kumar Mishra Enhanced Composites and Structures Center, School
of Aerospace, Transport and Manufacturing, Cranfield University, Bedfordshire,
Cranfield, UK
Satya Narain Mishra Department of Mathematics, Brahmanand PG College,
Kanpur, India
Vinayak Mishra International Institute of Information Technology, Hyderabad,
India
Durgesh Nandan School of Computer Science and Artificial Intelligence, SR
University, Warangal, India
Hamed Yazdani Nezhad School of Mechanical Engineering, Faculty of Engi-
neering and Physical Sciences, University of Leeds, Leeds, UK
Deepak Punetha Department of Electronics and Communication Engineering,
Motilal Nehru National Institute of Technology (MNNIT) Allahabad, Prayagraj,
Uttar Pradesh, India
Shamimul Qamar Computer Science and Engineering, College of Sciences and
Arts, King Khalid University, Abha, Kingdom of Saudi Arabia
Amrita Rai Department of Electronic and Communications, Lloyd Institute of
Engineering and Technology, Greater Noida, India
Abhishek Raj Department of Electronics and Communication Engineering, Indian
Institute of Information Technology, Ranchi, Jharkhand, India
xiv Editors and Contributors

Noel Prashant Ratchagar Department of Electronics and Communication Engi-

neering, Presidency University, Kolkata, India
K. Rohith Sai Department of Electronics and Communication Engineering, VLSI-
Microelectronics Research Center, Koneru Lakshmaiah Education Foundation
(Deemed to Be University), Vaddeswaram, Guntur, Andhra Pradesh, India
Shashi Kant Sharma Department of Electronics and Communication Engineering,
Indian Institute of Information Technology, Ranchi, Jharkhand, India
Neha Singh Department of Electronics and Communication Engineering, Manipal
University Jaipur, Jaipur, Rajasthan, India
Deepa Sethi singh Incharge of Zoology Department, Hindu College (M.J.P.
Rohailkhand Universty, Bareilly), Moradabad, Uttar Pradesh, India
Karumuri Srinivasa Rao Department of ECE, VLSI-Microelectronics Research
Center, KL University, Vaddeswaram, Guntur, Andhra Pradesh, India
Poonam Subudhi School of Advanced Sciences, Vellore Institute of Technology
(VIT) University, Chennai, Tamil Nadu, India
Sukanta Kumar Swain Department of Electronics and Communication Engi-
neering, Indian Institute of Information Technology, Ranchi, Jharkhand, India
Susmi Anna Thomas Department of Physics, Centre for Advanced Functional
Materials (CAFM), Bishop Moore College, Mavelikara, Kerala, India
Shailendra K. Tripath Department of Physics and Materials Science, Jaypee
University, Anoopshahr, Bulandshahr, Uttar Pradesh, India
 Part I
Beyond Si-Based CMOS Devices: Needs,
Opportunities and Challenges
Chapter 1
Beyond Si-Based CMOS Devices: Needs,
Opportunities, and Challenges

Amrita Rai, Dhananjay Gupta, Himanshu Mishra, Durgesh Nandan,

and Shamimul Qamar

Abstract Information processing is being driven by CMOS’s dimensional and

functional scaling1.technology into an ever-expanding range of fresh applications.
These applications have been made possible by scaling thanks to improvements in
complexity and performance. In order to increase the historical cadence of integrated
circuit scaling as dimensional scaling of CMOS inevitably approaches fundamental
constraints, a number of pioneering and advancement of signal processing devices
and microarchitectures for both present and innovative functions are ongoing. That
has flashed attention in processing and storage devices, as well as new heterogeneous
integration technologies and system architectural paradigms. As a result, this chapter
emphasizes an international roadmap of device and systems (IRDS) viewpoint with
advanced research of devices and provides a connection between existing classical
CMOS and the field of nano-electronics once CMOS scaling is achieved. The main
objective of proposed chapter is to explore, evaluate, and scale practical developing
facilities and new architectural approaches in terms of their long-term potential and
scientific maturity, as well as to identify logical and technical issues preventing the
semiconductor industry from accepting them as having an acceptable level of risk of
future development. Additionally, this chapter examines “Beyond CMOS devices”
for applications that go beyond Moore, such as hardware security.

Keywords CMOS scaling · Integrated circuit technology · Hardware security ·

Microarchitectures · Signal processing devices

A. Rai (B)
Department of Electronic and Communications, Lloyd Institute of Engineering and Technology,
Greater Noida, India
e-mail: [email protected]
D. Gupta · H. Mishra
Embedded System Engineer, Intozi Tech Pvt Ltd, Gurugram, India
D. Nandan
School of Computer Science & Artificial Intelligence, SR University, Warangal 506371, India
S. Qamar
Computer Science and Engineering, College of Sciences and Arts, King Khalid University,
Dhahran Al Janoub Campus, 64261 Abha, Kingdom of Saudi Arabia

© The Author(s), under exclusive license to Springer Nature Singapore Pte Ltd. 2024 3
S. Singh et al. (eds.), Beyond Si-Based CMOS Devices, Springer Tracts in Electrical and
Electronics Engineering, https://doi.org/10.1007/978-981-97-4623-1_1
4 A. Rai et al.

Beyond Si-Based CMOS Technology for Future Devices

Introduction

In 1965, Gordon Moore one of the co-founders of Intel Corporation predicted that
the number of transistor count in the Integrated Circuits would be doubled in every
two years (Moore’s Law). He also noted that shrinking or scaling down the transistor
would probably make it to operate at higher speed for same power and unit area. This
perhaps was formalized by Robert Dennard as the operating device voltage would
reduce and the switching frequencies would increase tremendously due to scaling
down of transistors (Dennard’s Law). These predictions severed its fulfilment over
decades and helped in understanding device behaviour. But this prediction lasted
for 40 years because the scaling down provided drastic increase in leakage, gate-
tunnelling, fall below the threshold of greater than the 60 mv/decade and lithography
limitations in convention Si-based CMOS devices (Das et al. 2021; Badaroglu 2021;
Prakash et al. 2023; Amsini et al. 2023).
In 2004, Dennard Scaling began to fail making it difficult for semiconductor
industries to face challenges because of scaling effects. This gave a way to look into
“more than Moore”, formally to go beyond current Si-based CMOS technologies
(Nguyen et al. 2016). These limitations of existing Si-based CMOS technology at
the device and system level demand a successor. There is not yet any reasonable
successor of current Si-based CMOS, but there are research going on to obtain
one in these paths (Haensch et al. 2006). The first path is to extend the current Si-
based CMOS beyond density and functionality that include high performance, low
power memories, high density, and low power supply. The second path is extending
the Si-based CMOS with an alternative material that have better performance and
reliability (Kazior 2014). The third path is to extend beyond in information processing
and computing paradigms involving several combinations of interconnects and logic
devices. The fourth path is extending it beyond in applications and functionalities
such as RF ICs, Memories, and Biosensors. Finally, the last objective is to narrow
the differences between traditional and unorthodox designs (Islam 2016) (Fig. 1.1).
Device Technologies:
The current Si-based CMOS technology is able to meet the demand of high perfor-
mance and low power but as we enter into nanotechnologies (< 100 nm), the use of
Si-based devices has lost its efficiency to provide the technical requirements. Because
of technology complexity and fabrication limitations of these Si-based devices has led
to go beyond in technologies like memory, information processing or logic devices
(Galitsis et al. 2015). It is becoming more difficult to scale Silicon CMOS further
without sacrificing performance, which is driving research into other channel tech-
nologies materials. Recent research examines the continuing difficulties in deploying
III-V/Ge CMOS fabrication technology for 7 nm and beyond, as well as the most
recent advancements in channel materials, process, and integration (Prakash et al.
2023; Hutchby et al. 2003).
1 Beyond Si-Based CMOS Devices: Needs, Opportunities, and Challenges 5

Fig. 1.1 Technology scaling paths beyond Si-based CMOS

One of the challenges for the new memories is they should be compatible with
current CMOS fabrication technology and should be beyond the current SRAM
and FLASH limitations. There is a limitation of MPU interaction with memory and
scaling down does not solve these problems with Si-based devices. One solution is to
increase the memory (SRAM) density of the MPU. Similarly, the development of high
speed electrically accessible non-volatile memory is todays need to revolutionize a
particular computer architecture. This sets a need to go beyond current CMOS devices
(Carballo et al. 2014; Chan et al. 2014; Mishra et al. 2023; Khan et al. 2023).
Sustainability of CMOS logic technology has become really challenging due
to scaling. One of the simplistic approaches is to replace the Si-based MOSFETs
with a different material that has higher potential speed and mobility of the quasi-
ballistic carrier. These non-silicon materials must have a low B2B tunnelling effect,
no Fermi pin levels in the channel/gate dielectric contact, and the ability to fabricate
high-K gates, dielectric, compatibility with heterogeneous materials and also should
reduce the leakage and power dissipation. However, seeing the saturation in the
current CMOS technology the industries are shifting towards devices which has
functional diversification and are beyond “Moore’s Law” (Rai 2023; Sharma et al.
2023; Badaroglu and Xu 2016).
6 A. Rai et al.

Progression of CMOS and Beyond CMOS

Recent advancement in technology for fast logical switching gives an emerging

thought about thinking of beyond silicon transistors, innovative logic switches are
being developed. If a proposed device can provide one or more of the said features,
such a replacement is deemed to be possibly practical (Das et al. 2021; Auth et al.
2017).
. A rise in device density (and associated cost reduction) over that made possible
by eventually scaled CMOS.
. An improvement in switching speed Beyond CMOS, such as by reducing switched
capacitance or improving the normalized driving current.
. A decrease in switching energy above CMOS, coupled with a decrease in the
energy used by the entire circuit.
. The ability to do innovative information processing tasks that are not as effectively
possible with traditional CMOS (Badaroglu 2021; Wang et al. 2018).
The furthermost tough task facing Beyond CMOS is delivering resources with
structured properties, which will allow the functioning of cutting-edge develop-
ment of devices in high density at the nanoscale. For the high-density development,
devices required the better control of material properties where material synthesis
must be combined with all available new and well-known methods and modelling.
The coming section “Emerging Materials Integration” deals with the above mention
objective.
The performance of most integrated circuits and technological scaling have histor-
ically been closely correlated, which has driven the semiconductor industry. The
demand for more advanced and quick microprocessors in the PC market was a
major factor in the advancement of the scalability of transistors and memory. Novel
materials and manufacturing techniques, such as “strained silicon”, “high-k gate
dielectrics”, and “metal gate electrodes”, were required for these devices, all of
which are already widely employed in IC production and will remain so. An entirely
new environment has formed in the last ten years. With advance and complicated
technology requirements, new system integrators have emerged in a variety of indus-
tries, including mobile, data centres, and the Internet of Everything. These system
integrators’ influence will extend beyond microprocessors to new fields including
medicine, energy, and the environment (Das et al. 2021; Hao et al. 2022; Marinella
et al. 2021) (Fig. 1.2).
To support this new More Moore scaling paradigm, novel materials for transistors,
memory, interconnects, and lithography procedures will be needed. Potential Beyond
CMOS solutions include completely new logic and memory devices that are not—
CMOS as well as new, non-Von Neumann circuit topologies as existing information
processing and storage technology hits its breaking point (Marinella et al. 2020). For
these solutions to benefit from the established processing infrastructure and to be able
to incorporate Si devices like memory onto the same chip, they should preferably
be integrated onto the platform based on silicon. The popularity of these Beyond
1 Beyond Si-Based CMOS Devices: Needs, Opportunities, and Challenges 7

Fig. 1.2 Integration of

existing technologies with
emerging material

CMOS structure is founded on completely novel material science and physics. Even
though they will probably be integrated on a Si-based Monolithic substrate. These
new materials face significant challenges before they can offer practical solutions for
upcoming integrated circuit technology (Agarwal and Yablonovitch 2015). Acceler-
ating material evaluation, improvement, and capabilities will be necessary to achieve
by the new materials. The researcher needs to be guided with new structure of mate-
rial and process for less cost effective, more reliable, advance sustainable technology
that will power future breakthroughs in engineering technology. The new integrated
material is classified based on the first materials Scaling for More Moore technology
for the purpose of different area of assembly and Packaging. Next Novel Material
for beyond CMOS for manufacturing ALU device, memory and storage of digital
data in large number required resistive-switching electronics based 2-D materials.
Lastly required highly disruptive materials for highly impacting emerging area as
such as in energy sector, healthcare units, agriculture, medical and environment, etc.
(Seabaugh and Qin 2010).

Emerging Material Integration for CMOS Beyond Si

Current Scenario in Technology

Historically, the performance of IC industry has significantly associated with the

technology scaling. The present market demand for increasingly advanced and quick
microprocessors primarily drove transistor and memory development and scaling.
Such devices demand the employment of novel materials and processing units, like
“strained silicon” components, “high-k gate dielectrics” materials, and “metal gate
electrodes” combination, which are now and will continue to be widely utilized in
IC production. A whole new ecosystem has been created in the last decade. From
smartphones to data centres to the Internet of everything, advance system integrators
8 A. Rai et al.

have emerged with novel and challenging technical needs. Such type of system
integration will have an impact on new applications in the fields of medicine, energy,
and the environment, as well as microprocessors (Bernstein et al. 2011; Moore 1998;
Dennard et al. 1974; Banerjee et al. 2009).

Drives and Targeted Skill Technology

To manage emerging material technologies, the ethyl methylimidazolium tetraflu-

oroborate (EMI) section is an ionic liquid that has been studied extensively for
material Properties. EMI segment emphasizes on multi-scale modelling and simula-
tion. Conventional multi-scale physics modelling was previously described by many
research where quantum mechanics to describe phenomena at the dynamic, multi-
component domain level is required to link between circuit characteristic with elec-
tronics properties. A potential role for machine learning and informatics has been
suggested in the EMI section by the many researcher as a substitute for mesoscopic-
level simulation, where inputs of molecular-level events generate output depicting
continuum-level phenomena. The various methods of these “Beyond CMOS tech-
nologies” are based on wholly novel materials and quantum physics, even though
these fabrication technologies will almost probably be integrated into a silicon-
based platform. Last but not least, suggested system integrators require materials that
provide functional scaling, a potentially cross-disciplinary advancement in mono-
lithically integrated complicated functionality. There are considerable challenges
that need to be overcome before these novel materials can offer practical solutions
for integrated circuit technology in future. Accelerating the assessment of mate-
rials, advancements, and capacities to offer these capabilities will require improved
metrology. The main goal is to promptly offer suggestions on solutions for improving
substantial and process performance, cost, consistency, and sustainability, which will
open the door to ground-breaking developments in future manufacturing technolo-
gies (Galatsis et al. 2015; Cowburn and Welland 2000; Saripalli et al. 2009; Wolf
et al. 2010; Alam et al. 2010).

Opportunity

International technology roadmap of device and system represents an intentional

shifting of the scale, requirements and establishment of developing prospects in the
community. Such type of research of the Emerging Materials Integration (EMI)
subjects is main purpose of all level scientists and working groups. The exten-
sive requirements and solutions tables incorporate data from prior existing research
chapters as well as suggestions from the most recent international scientist working
groups, and they will be updated in subsequent versions. This section is structured as
1 Beyond Si-Based CMOS Devices: Needs, Opportunities, and Challenges 9

follows and focuses on developing novel, ground-breaking, and theoretically disrup-

tive prospects for progressing material properties, artificial processes, and metrology
(Banerjee et al. 2009).
. Transistors (both BJT and FET), memory (volatile and non-volatile), intercon-
nects, lithography, heterogeneous integration, assembly, and packaging are among
the scaled technological materials needed for More Moore.
. Emerging memory and storage technologies, new computing paradigms, and new
computing architectures are all examples of novel materials for Beyond CMOS.
. Heterogeneous components where external system connectivity is needed and
high-impact applications in the fields like energy management systems, envi-
ronment monitoring, agriculture sector, health, and medicine are examples of
theoretically disrupting material prospects for efficient scaling and convergent
applications.

Technology Requirement and Possible Explanations

In preparation for the next emergent period of monolithic integrated systems with
increased total functional density, the international research group is searching for
a framework to manage the convergence of output signal received from sensors,
scaled signal processing, and memory, i.e. “More Moore (MM)” and “Beyond CMOS
(BC)”. The convergence of functional diversification with downsizing in a monolith-
ically integrated manner is a manifestation of the pattern of increasing complexity
in the “road-mapping process”. The international research group of scientists is a
representation of this growing complexity of technology with an increasing number
of proposed roadmap factors and desires associated with additional functionalities.
Emergent designs may benefit from the unique scheme and function of the device,
which necessitates the improvement of materials and mechanisms, even as EMI
continues to serve the evolutionary and semiconductor-centric needs of the tradi-
tional semiconductor community (Zhang et al. 2008; Awschalom et al. 2002; Borah
et al. 1996).
The special and desired properties of candidate EMI methods and materials may
necessitate atomic-level control over composition, interface, flaws, and structural
elements. Certain materials cannot always be produced with the necessary degree of
control using current synthetic or manufacturing processes (Das et al. 2021; Khan
et al. 2023).

Difficulty Challenges—Short Term

. Devices to extend CMOS scaling, utilizing new channel materials and device
structures.
10 A. Rai et al.

. Electrical devices based on novel mechanisms with performance and/or power

efficiency Beyond CMOS FET.
. Novel high-performance memory suitable for embedded applications and denser
than SRAM/DRAM.
. Novel memory devices (including selectors) more scalable than FLASH memory
for storage applications.
. Devices suitable for monolithic and heterogeneous integration.
. Materials and methods:
– These results impact “nanowire FETs” (Si, SiGe, Ge, and III-V) on the
performance and the power scaling.
– This increases the resistivity and dependability of copper interconnects.
– For ongoing DRAM/SRAM scaling and embedded NVM.
– This allows lithography to be extended up to substrate 10-nm dimensions with
predictable qualities.
– Utilizing in heterogeneous-based multichip, multifunction package integra-
tion.

Difficulty Challenges—Long Term

. Devices based on novel state variables and switching mechanisms to achieve

functionalities and performance beyond the capability of CMOS FET.
. Devices with native behaviours for the implementation of novel computing
paradigms, including neural network, analogue computing, in-memory
computing, photonic computing, etc.
. Devices with novel functionalities and applications, e.g. security, energy conser-
vation/ harvesting, etc.
. Devices to enable efficient implementation of unconventional computing.
And non-classical computing solutions novel device benchmark and device-
architecture co-optimization.
. Materials and methods:
– This allows for “3D monolithic” and “vertical integration of high mobility”,
steep sub-threshold transistors.
– Beyond CMOS logic that replaces or extends CMOS logic, both charge-based
and non-charge-based.
– That replaces copper interconnects at the nanoscale with increased durability
and electromagnetic performance.
– To replace DRAM/NVM with developing memory and select devices.
– This enables complicated functionality to be monolithically 3D integrated,
including temperature and yield difficulties.
1 Beyond Si-Based CMOS Devices: Needs, Opportunities, and Challenges 11

Types of Device Architecture for Logic Devices Beyond Si

About

The complementary “metal oxide semiconductor” field effect transistor (CMOSFET)

is the main component of all processing and memory circuits, which performance
is based on their scaling ability and becoming smaller than the existing one. As a
result, the capabilities of processing information per unit area on a chip affecting
also on per dollar processing rate and it is increased exponentially. This has led
not only to faster and/or cheaper existing goods on a chip, but also to an increase
in the integration of items that use semiconductor chips to increase functionality
from household things like toasters machine to life requirement mobile phones to
research-based super-computers (Nandan et al. 2017).
Dennard et al. published the FET scaling principles that made this revolution
possible in the early 1970s. The most important discovery was that if the working
voltage and all of the FET’s critical dimensions were decreased by the same amount,
the power density would remain constant while the speed of the FET increased
and the area and power decreased. However, the challenge of retaining performance
limits our ability to raise voltages in more recent chip generations. Furthermore, the
power problem would affect FETs made of any material, including novel choices like
carbon nanotubes or organic molecules, not only silicon (the semiconductor used in
CMOS FETs) (Hiroki et al. 2008).
The “International Technology Roadmap” first researched the power density chal-
lenge for future scaling for “Semiconductors Emerging Research” Device Technical
Working Group in the early 2000s. It’s exciting to remember that this search for
a different digital switching technique is not novel: the first bipolar semiconductor
device was created in the late 1940s when tubes and mechanical switches were expe-
riencing similar performance limitations, and the recently developed FET devices
replaced existing bipolar device in the common of semiconductor applications
(Kumar et al. 2019).
In the present era, different world research centre of studies working with different
approaches for defining CMOS logic, switch.
. The University of California at Los Angeles’ (UCLA’s) Western Institute of Nano-
electronics (WIN; “Prof. K Wang”, Director) researches spintronic and associated
phenomena, comprising materials, device architectures, and be integrated, for
logic uses and applications.
. The State University of New York (SUNY), Albany’s Institute for Nano-
electronics Discovery and Exploration (INDEX) focuses on novel phenomena
for logic devices. Competence centres are centred on excitonic rotation of
quantum dots, “magnetic, and graphene devices”, with a focus on “fabrication
and characterization”.
. University of Texas at Austin’s South-West Academy for Nano-electronics
(SWAN) (Director: Prof. Sanjay Banerjee) focuses on graphene while integrating
12 A. Rai et al.

projects in theory, materials fabrication, device structures, and metrology. It also

conducts research on magnetic materials, pseudo-spintronic materials, magnetic
and multiferroic materials, and plasmonic materials.
. The Midwest Institute for Nano-electronics Discovery (MIND), located at the
University of Notre Dame in Notre Dame (Director: Prof. Alan Seabaugh),
specializes on thermal phonon control, “non-equilibrium phenomena”, tunnelling,
nano-magnetism, and “non-equilibrium phenomena” for energy-efficient devices
and structures.

Existing Switching Technology and Physical Mechanisms

for Digital Switch

Recently, researches on various devices for digital switching and the evaluation of
devices are mentioned in Table 1.1. Digital or logical switching started from the
15 mm gate length MOSFET to the recently developed CMOS and nanotechnology
advanced model (Das et al. 2021; Badaroglu 2021; Jagadeeswara Rao et al. 2019).
Spin wave logic devices (Spin wave) are devices with surface inputs and output
leads on a SiO2 /NiFe bilayer, like the one Khitun et al. developed. Magnetic fields
perpendicular to the magnetization of the NiFe layer are produced by currents in the
input wires. In the NiFe, the incoming magnetic field causes spinning waves that
obstruct reasoning. A current loop is responsible for detection. The device in Fig. 1.3
does not include any amplification mechanisms, although strategies for adding gain
to the device are being researched (Howes et al. 1994).
In the direction of a thin-film Ferro magnet’s magnetization, nano-magnets encode
a binary logic state. A magnetic quantum dot architecture (MQCA) uses strings
of structured nano-magnets to carry out logic operations as well as information
transmission. Majority gates were proven; now being developed are timed logic
gates, as seen in Fig. 1.4. Reconfigurable array magnetic automata (RAMA) is a
new idea being investigated for switching nano-magnets in cellular architecture. In
RAMA, magneto capacitance and multi-ferroics are employed to sense the magnetic
polarization and reset the nano-magnet pillars, respectively (Itoh 2013).
Low power supply voltages and sub-60-mV/decade sub-threshold swing are made
possible by TFETs by the application of electric field gating of interband tunnel
currents. The energy band diagram and schematic for a graphene nanoribbon TFET in
the on- and off-states are shown in Fig. 1.5. The gate depletes the channel and prevents
interband tunnelling in the off-state. Positive gate bias and interband tunnelling in
the source are enabled in the on-state. In Fig. 1.5, simulated n- and p-channel TFET
current-per-unit-gate-width characteristics are displayed, together with access resis-
tance and parasitic capacitance. The heterobarrier (HetTFET), depicted in Fig. 1.6,
is used in a second implementation of the interband TFET investigated in this study.
A third transistor, known as a RIEFET (resonant-injection-enhanced) transistor and
described in, serves as a representation of the field control of resonant tunnelling. The
graphene-based Datta-Das spin FET (graphene Spin FET) is also listed in Table 1.1.
1 Beyond Si-Based CMOS Devices: Needs, Opportunities, and Challenges 13

Table 1.1 Device in benchmarking project

Devices Short Device State variable Reference
benchmarked
15 nm CMOS CMOS HP CMOS LG = Q Augustine
CMOS LP 15 nm
Excitonic FET ExFET Excitonic FET Q J. Appenzell,
Purdue,
unpublished
Magnetic tunnel MTJ logic Co/Mg/NiFe GMR Magnetic C. Ross, MIT
junction MTJ switch or polarization unpublished
logic switch Co/Cu/NiFe or
TMR
All spin logic All spin logic Semiconductor spin Electron spin B. Behin Aein
channel with
nano-magnet
Graphene PN Graphene PN Field control Electron wave J. u. Lee, Suny
junction junction graphene p–n phase Albany,
junction unpublished
Electronic ratchet Electronic Backgated Q M. Stan,
ratchet graphene structure unpublished
nanoribbon
Graphene thermal Thermal Graphene thermal T Y. P. Chen Purdur
logic transistor 10 nm × unpublished
10 nm
Binary decision BDD Arch Generic Q S. Datta and V.
diagram Narayanan,
architecture Penn
Nano-magnetic NML Perm alloy Magnetic A. Dingler
logic nano-magnet chains polarization
40 × 60 × 60
Graphene tunnel Tunnel FET Graphene q Q. Zhang
FET nanoribbon TFET
Spin torque Spin torque MgO tunnel Magnetic A. Krivorotov,
amplifier amplifier junction polarization UCLA
unpublished

The Bilayer Pseudo-spin FET (BiSFET), which we have already covered, is a novel
transistor design that makes use of tunnelling. In a BiSFET, a tunnel oxide separates
two independently contacted monolayers of graphene that are sandwiched between
two metal oxide gates. A collective many-body current between the two graphene
layers is conceivable when an exciton condensate arises between the layers under
specific gate circumstances (Das et al. 2021; Zhang et al. 2008). Banerjee et al.
implemented and examined the SPICE version of the BISFET circuit operating that
is the subject of this chapter (Badaroglu 2021; Jagadeeswara Rao et al. 2019).
It is evident from the evaluation of the suggested replacement switches that in
order to effectively increase-processing capacity, complementing technologies and
14 A. Rai et al.

Fig. 1.3 Emerging materials integration for CMOS beyond Si

fundamental ideas must also be taken into account. This last section lists a few of
these problems.
The ability to visualize the design of next-generation computing devices is getting
closer to being developed by the semiconductor industry. We provide some ideas in
the light of the study’s conclusions (Howes et al. 1994).
1. The total number of components, the number of random logic gates, the size of
the memory array, and other characteristics can be used to determine the present
make-up of high-performance microprocessors.
2. One may reasonably estimate the delay, power, and area of any circuit included
in a specific novel switch using the derivations from this work. The worst-case
power density projections, maximum fan out, and minimum noise immunity
combine to generate new criteria that can be used to forecast the design function
point for logical resources mapped to a new switch.

Requirement of Alternative Devices Beyond CMOS

Interconnects may experience serious issues as a result of continuous scaling of VLSI

circuits. We demonstrate that the effective resistivity of Cu will significantly increase
when the resistance of interconnect wires is taken into account along with scaling-
induced increases in electron surface scattering, fractional cross-sectional area occu-
pied by the high resistivity barrier, and realistic interconnect operation tempera-
ture. As a result, these interconnects’ power and delay are projected to increase
dramatically in future (Das et al. 2021; Itoh 2013).
Alternative solutions must be sought after in view of the different restrictions
associated with metal interconnects. We concentrate on two of these solutions: 3D
1 Beyond Si-Based CMOS Devices: Needs, Opportunities, and Challenges 15

(a)

(b)

Fig. 1.4 a SEM photo and magnetic force micrograph (MFM) of NAND2 with input output
arrangements. b Simulation graph output inductive voltage

Fig. 1.5 Graphene material: a the two atoms (A and B) in each unit cell of the hexagonal honeycomb
lattice; b the tight-binding band structure of the graphene bands with K
16 A. Rai et al.

Fig. 1.6 This illustration shows a novel electronic gadget developed at Purdue that substitutes
germanium for silicon as the semiconductor. Because it might allow the industry to produce smaller
transistors and more compact integrated circuits, germanium is one of the materials being evaluated
to replace silicon in future chips

ICs with many active Si layers and optical interconnects. Now research may reach
the sub-20 nm regime on Si through heterogeneous integration of novel structures
and materials, but this will require new fabrication technology solutions that are
generally compatible with existing Si production that is already in place.
Silicon has replaced germanium as the preferred semiconductor for industrial
CMOS technology. Future developments will be jeopardized as the industry soon
reaches the limit of how small silicon transistors can be produced. One material
being investigated to replace silicon is germanium, which could allow the industry
to produce transistors and integrated circuits that are smaller and more compact.
With regard to electrons and electron “holes”, germanium is also claimed to have
“higher mobility” in comparison with silicon, a property that makes for extremely
quick circuits (Prakash et al. 2023; Saha 2001).
It is challenging to build an N-type contact with low electrical resistance for
good current flow due to the material’s characteristics. Germanium is doped, or
impregnated, with impurities, which changes its characteristics. The resistivity is
lowest in the regions with the most contaminants. The most strongly doped area
of the germanium, which offers good contact, was exposed when the researchers
demonstrated how to scrape away the top layer of the material (Fig. 1.7).
Options for devices and materials to enhance device performance when conven-
tional scaling is limited by power. The three categories of these options are enhanced
short-channel behaviour, enhanced current drive, and enhanced switching. More
recently, a novel type of device (MESO), created by Intel and put forth in a 2018
publication, has surfaced. According to Intel, it has the potential to offer significant
advantages over CMOS.
The efficiency might increase by 10–30 times because it would only require
100 mV to run. Intel also asserted that it could increase logic density by 5 times.
1 Beyond Si-Based CMOS Devices: Needs, Opportunities, and Challenges 17

Fig. 1.7 Graph on performance and characteristic curves of IDS versus VGS as a function of
metal’s work-functions TFET

Along with having spintronic features and being non-volatile, the MESO device also
allows for the implementation of new types of circuits that are appropriate for AI.
“MESO is like a transistor-input voltage controls the current at the output (so it is
electrical voltage in and current out like MOSFETs, but it switches at [approximately]
10× lower voltage than a MOSFET”, claims Intel. “Wires only need to swing at a
10× lower voltage as a result, saving power”.
Many of the digital and high-performance microprocessor and memory can be
achieved with the scaling factor of transistors. Each 30% decrease in CMOS IC
technology node scaling has resulted in the following benefits: (1) A 43% increase
in maximum clock frequency; (2) a doubling of device density; (3) a 30% decrease
in parasitic capacitance; and (4) a 65% and 50% decrease in energy and active power
per transition, respectively.
The above data reflect the CMOS performance improvement with the power
density and circuit density trend and also represent a linear circuit performance
because of technology scaling.
More recently, a novel type of device (MESO) has appeared; it was created by Intel
and suggested in a study published in 2018. According to Intel, it has the potential
to offer significant advantages over CMOS. The efficiency might increase by 10–30
times because it would only require 100 mV to run.
Intel also asserted that it could increase logic density by 5 times. Along with
having spintronic features and being non-volatile, the MESO device also allows for
the implementation of new types of circuits that are appropriate for AI.
In order to scale nanoscale MOSFETs, it will be critical to consider higher mobility
materials like Ge and III-V materials along with cutting-edge device designs that
might outperform even extremely highly strained Si. Leakage issues must be resolved
for both “Ge and III-V devices”. To benefit from the anticipated advantages of “Ge
and III-V-based devices”, novel heterostructures will be required.
18 A. Rai et al.

Opportunity of Beyond Si-Based CMOS in Industries

The previous sections explored the universe of emerging research devices, presented
a parameterization scheme for their interconnection, and scaled CMOS with their
architectural structure and devices properties concepts. The developing parameter-
ization of the new developed device is shown in Fig. 1.8, which precise this infor-
mation at some upcoming point in time, but does not contain any information about
the evolutionary steps needed to reach that point. The different logic, memory, and
architecture tables contain some restricted structure of information and show how
time changed from left to right. The global evolutionary sequences that are expected
to develop and dominate our future technology have not, however, been addressed
(Prakash et al. 2023; Kumar et al. 2023).
The search for studying other channel materials is brought on by the growing
challenges of advanced scaling of silicon CMOS without negotiating performance.
This paper examines the continuing difficulties in deploying “III-V/Ge CMOS tech-
nology” for 7 nm and beyond, as well as the most recent advancements in channel
materials, process, and integration.
To utilize the current circuit platform to its best potential, the novel high mobility
material must be compatible with Si substrate. As a result, the insertion technology
node’s design rule and current Si CMOS process flow must be co-integrated with
“Ge and III-V materials”. Researchers have made great attempts to find a “high
dielectric constant (K)”, metal gate stack, and source/drain configuration for all
channel materials that will not degrade or compromise power/performance, as well
as a workable integration schemes.
In the In0.7Ga0.3As quantum-well field effect transistor (QWFET) on silicon
substrate, recent research has shown the integration of a cutting-edge composite
high-K gate stack (4 nm TaSiOx-2 nm InP), with thin EOT, “low gate leakage”,
“effective carrier confinement”, and “high effective carrier velocity (Veff)” in the
QW channel (Nguyen et al. 2016; Bir et al. 2020).
New non-classical device architectures have also been proven to address electro-
static field scaling concerns rather efficiently, which is encouraging given the develop-
ment of high-K materials to address MOSFET scaling issues. By using fully depleted

Fig. 1.8 Parametrization of emerging technologies and CMOS

1 Beyond Si-Based CMOS Devices: Needs, Opportunities, and Challenges 19

SOI and dual-gate architectures, for instance, short-channel effects, which are preva-
lent in the most advanced technology nodes at the 45 nm node and beyond, are signif-
icantly decreased. The ultrathin body totally depleted SOI (with a body thickness
10 nm) and Fin FET are two examples of these MOSFET architectures. Figures 1.9
and 1.10 display a schematic illustration of these two structures. Metrics intended for
the “long term” should support the development of new physical mechanism-based
technologies that are likely to follow completely new scaling laws. We anticipate
that technology will advance (Haensch et al. 2006, Bir et al. 2020).
Provide possible benefits orders of magnitude beyond technical performance
parameters (size, density, rate or information throughput rate, power dissipation, etc.)
compared to a 22 nm ITRS node for CMOS, among other metrics focused on long-
term approaches to information processing. (3) Scalable over multiple generations
with exponential improvement in technology performance metrics for incremental
cost increases, meeting metrics 2, 3, 4, 5, and 6 in the aforementioned near-term list.
(4) Provide a good balance between technical potential and risk, and (5) Compat-
ibility with CMOS infrastructure at the system level. Many novel ways for repre-
senting and processing, storing, and transferring information represented as bits are
being explored by new approaches to information processing technology.
These techniques include “entangled” quantum states represented by a q bit state
(or quantum bit), as well as the employment of innovative, ultra-scaled structures
(such as molecules, nanotubes, and nanowires) to mimic current means to represent

Fig. 1.9 Schematic

illustration of ultrathin
depleted SOI

Fig. 1.10 Schematic

illustration of Fin FET
20 A. Rai et al.

bits by charge, voltage, or current. It is outside the scope of this post to discuss such
a broad range of subjects. The fundamental constraints (size, energy, speed, etc.)
of the elementary switch, however, are a significant challenge in relation to novel
strategies for charge-based information processing.
Within the next 10–15 years, the advancement of silicon-based CMOS technology
will reach critical technical constraints. To increase silicon’s speed over these bounds,
new fabricable materials and device topologies must be introduced.

Researchers Which Driving Beyond CMOS Technology

The development of faster and smaller devices, which will enable more mechanisms
to be implemented in the same space, will make Beyond CMOS technology the
technology of the future for information. By describing the history of these devices
through Moore’s Law, MOSFET, current CMOS technology, and the ongoing devel-
opment of the Beyond CMOS, this article seeks to give the reader a brief introduction
to this revolutionary technology (Das et al. 2021; Bir et al. 2020). One of the organi-
zations that has studied this technology more is the NRI (Prakash et al. 2023; Khan
and Beg 2013), which has found that Spintronics is one of the underlying principles
of these technologies (Amsini et al. 2023, Shah et al. 2022). The Beyond CMOS
represents the information era since they have storage capacities that are incompre-
hensible to modern technology. Moore’s law has so far proven to be accurate in its
calculations, and because of the limitation imposed by the current CMOS technology,
a number of groups, including the NRI, have concentrated their efforts on developing
a technology that can keep up with the rate of thought and creation of the modern
human being.

Challenges of Beyond Si-Based CMOS Devices

1 Beyond Si-Based CMOS Devices: Needs, Opportunities, and Challenges 21

Challenging issue Concerns and prospective summary of relative

Issue
Replace SRAM and FLASH with high-speed, The need for new memory technologies to
dense, embeddable, volatile/non-volatile replace SRAM and FLASH memories is being
memory technologies in the right applications driven by the scaling limitations of these
two-dimensional (2D) memory technologies
Determine which technical methods are most
likely to provide “electrically accessible”,
“high-density”, “high-speed”, low power, and
(ideally) embeddable “volatile and non-volatile
materials”
Through and after high temperature and
corrosive chemical processing, the desirable
qualities of the material or device must be
preserved. Early in the process of developing
new technologies, reliability concerns should
be recognized and resolved
Extend CMOS scaling Create novel materials to replace silicon-based
semiconductor (or 11-V, Ge) as the source/drain
and alternate channel in MOSFETs. This will
minimize leakage currents, boost saturation
velocity, and further reduce power dissipation
and Vas
Provide methods for regulating the distributions
of statistics and crucial dimensions’ variability
(such as channel width and gate length)
concentrations of S/D doping, etc.
Allow for the diverse integration of different
materials
Through and after high temperature and
corrosive chemical processing, the desirable
qualities of the material or device must be
preserved. The early stages of the process
should involve identifying and resolving
reliability issues
Expand the capabilities and applications of Find and apply novel device technologies and
eventually scaled-down CMOS as a platform low-level architecture to create functional cores
technology (“More than Moore, MIM”) with optimized particular purposes (such as
accelerator functions) that are heterogeneously
integrable with CMOS
By including features that don’t always scale in
accordance with “Moore’s Law,” you can add
value
Compact systems with heterogeneous
integration of digital and analog functions will
be the main force behind a wide range of
application areas, including “communication
and automotive”, “environmental control and
healthcare”, and “security and entertainment”
(continued)
22 A. Rai et al.

(continued)
Challenging issue Concerns and prospective summary of relative
Issue
Close the gap between cutting-edge Determine appropriate chances in
technology and non-traditional approaches to non-traditional computing paradigms and
computing and architectures architectures that can make use of the special
qualities of cutting-edge gadgets
Find new devices that are more capable of
implementing computer fictions and
architectures than CMOS and Boolean logic in
terms of efficiency

Conclusion

The “Beyond CMOS” chapter thoroughly reviews novel technologies in

Sects. Beyond Si-Based CMOS Technology for Future Devices Introduction and
Progression of CMOS and Beyond CMOS, briefs on upcoming changes in memory
and logic circuits and devices in Sects. Emerging Material Integration for CMOS
Beyond Si, Types of Device Architecture for Logic Devices Beyond Si and exam-
ines alternative “architectures and computing paradigms” in Sect. Requirement of
Alternative Devices Beyond CMOS in order to look at potential solutions outside
the typical scaling of “CMOS-based technologies”. Although achieving high perfor-
mance with less power consumption has been the main goal. Novel features and
applications have grown more crucial for “Beyond CMOS devices”. The emphasis
is changing away from “high-precision complex computing” solutions and towards
novel computing standards with huge parallelism and quantum mechanisms due to the
recent appearance of advanced application, which required to energy-efficient with
data-intensive. The utilization of beyond silicon-based CMOSFET circuit’s architec-
tures and device offers research chances to investigate distinctive circuit properties
and fabrication layouts.
It is still possible to conduct research to develop beyond silicon-based CMOS
devices with significantly improved performance and scalability as well as lower
energy consumption per functional operation, even though a device that is as good as
a CMOS FET has not yet been found. Different novel strategies have been proposed
to give an order of magnitude scaling of signal processing beyond what is achievable
with finally scaled CMOS. The following collection of guiding principles is designed
to provide a useful foundation for organizing research on information processing
technologies that go “Beyond CMOS”.
1 Beyond Si-Based CMOS Devices: Needs, Opportunities, and Challenges 23

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Chapter 2
Nanowire-Based Si-CMOS Devices

Raghvendra Kumar Mishra, Vinayak Mishra, and Satya Narain Mishra

Abstract Nanowire-based Si-CMOS devices are rapidly emerging as promising

foundational components for the next generation of semiconductor devices. This
chapter delves into the intricate processes and technologies involved in creating
silicon nanowires and seamlessly integrating them into CMOS devices. The discus-
sions encompass various aspects, including growth techniques, patterning methods,
doping processes, and integration considerations. Silicon nanowires exhibit remark-
able advantages over bulk silicon, notably encompassing a substantially heightened
surface area, augmented electrical conductivity, and improved mechanical proper-
ties. These inherent benefits render nanowires highly versatile making them suitable
for a diverse array of applications ranging from logic circuits and memory devices
to sensors and catalytic processes. The chapter accentuates the vast potential of
nanowire-based Si-CMOS devices and their profound impact on the future of semi-
conductor technology. As researchers continue to pioneer advancements in nanowire
fabrication and integration, we anticipate that these innovative devices will usher in
transformative changes across various industries. This transformation is expected to
be characterized by enhanced device performance, reduced power consumption, and
the unveiling of novel applications in the realm of electronics. Ultimately, nanowire-
based Si-CMOS devices are set to pave the way for an exciting new era of cutting-
edge technology yielding wide-ranging implications for the field of electronics and
beyond.

Keyword Nanowires · CMOS devices · Fabrication · Integration · Applications

R. K. Mishra (B)
Enhanced Composites and Structures Center, School of Aerospace, Transport and Manufacturing,
Cranfield University, Bedfordshire MK43 0AL, UK
e-mail: [email protected]
V. Mishra
International Institute of Information Technology, Hyderabad, India
S. N. Mishra
Department of Mathematics, Brahmanand PG College, Kanpur 208004, India

© The Author(s), under exclusive license to Springer Nature Singapore Pte Ltd. 2024 27
S. Singh et al. (eds.), Beyond Si-Based CMOS Devices, Springer Tracts in Electrical and
Electronics Engineering, https://doi.org/10.1007/978-981-97-4623-1_2
28 R. K. Mishra et al.

Highlights

. Nanowires offer significant advantages over bulk silicon.

. Nanowire-based Si-CMOS devices have the potential to revolutionize various
industries.
. Researchers are pushing the boundaries of nanowire fabrication and integration.
. Nanowire-based Si-CMOS devices pave the way for a new era of cutting-edge
technology.

Introduction

Nanowire-based silicon complementary metal–oxide–semiconductor (Si-CMOS)

devices are employed to tackle the challenges associated with traditional silicon tran-
sistors. They make use of materials such as GeSn to enhance performance and mini-
mize leakage. This concerted effort to surmount existing limitations marks the onset
of a revolutionary phase in electronics innovation ushering in heightened capabilities
characterized by improved energy efficiency and performance. This exemplifies the
dedication to pushing the frontiers of electronic technology to achieve transforma-
tive advancements and foster innovative applications (Liu et al. 2023). The advent
of one-dimensional (1D) and two-dimensional (2D) materials presents an alternative
to silicon capitalizing on their high mobilities and effective gate control to enhance
device performance. This transition carries promise across multiple sectors trans-
forming the characteristics of transistors and fueling advancements in both mate-
rials science and electronics. It stands to redefine the technological terrain under-
scoring the commitment to advancing electronic capabilities through innovative
materials and design with far-reaching consequences (Knobloch et al. 2022; Prasad
et al. 2021). Incorporating n-MOS and p-MOS components represents a significant
step forward in enhancing the quality of hole spin-qubits for quantum computing.
This development amplifies the precision of quantum state manipulation offering
transformative computational potential. The amalgamation of these transistors plays
a pivotal role in enabling efficient quantum information processing signifying a
substantial advancement in quantum technology. It highlights the commitment to
innovative solutions in quantum computing through the synergistic collaboration
of diverse transistor types (Jin et al. 2023). The incorporation of n-MOS and p-
MOS silicon hole double quantum dots represents a crucial advancement in the
field of hole spin-qubits offering the potential for groundbreaking developments in
quantum computing. This collaborative strategy significantly improves the control
of quantum states opening the door to revolutionary applications of quantum tech-
nology. It marks a substantial step forward in leveraging quantum properties for inno-
vative computing solutions (Huo and Konstantatos 2018). The integration of III-V
compound semiconductors with silicon through vertical nanowires offers the poten-
tial for innovative device advancements addressing challenges such as the narrow
2 Nanowire-Based Si-CMOS Devices 29

band gaps observed in InAs MOSFETs. Current research endeavors seek to amalga-
mate the advantages of III-V materials with novel techniques leading to a revolution
in device performance that surpasses the constraints of conventional semiconduc-
tors. This undertaking represents the transformative power of merging materials to
achieve advanced electronic capabilities (Kilpi et al. 2017). To overcome the chal-
lenge of band-to-band tunneling in indium arsenide (InAs) metal–oxide–semicon-
ductor field-effect transistors (MOSFETs), researchers propose a solution involving
the incorporation of a wider band gap material, indium gallium arsenide (InGaAs) on
the drain side of nanowire MOSFETs. This heterostructure design effectively miti-
gates off-currents while maintaining on-performance levels comparable to standard
InAs MOSFETs. This innovative approach has the potential to enhance electronic
device performance by effectively addressing power consumption and band-to-band
tunneling challenges offering the prospect of improved efficiency and functionality
in semiconductor devices (Kilpi et al. 2017). The inclusion of a wider band gap mate-
rial, indium gallium arsenide (InGaAs) in nanowire MOSFETs effectively mitigates
band-to-band tunneling challenges found in indium arsenide (InAs) MOSFETs. This
advancement holds particular significance for IoT devices and high-performance
applications as it enhances power efficiency and functionality by tackling tunneling
issues and minimizing off-current levels. This represents a significant advancement
in the optimization of semiconductor device performance and the broadening of elec-
tronic technology applications (Yin et al. 2021). Nanowires are crucial in the develop-
ment of nanometer-scale transistors, which are essential for upholding Moore’s law
and enhancing device design and performance. This capability fuels the evolution
of technology facilitating miniaturization, efficiency improvements and innovative
applications all in alignment with the continuous advancement of electronics for a
transformative future. It emphasizes their fundamental role in advancing electronic
capabilities (Burg and Ausubel 2021). Nanowires exhibit exceptional electrical prop-
erties due to their diminutive dimensions and substantial surface-to-volume ratio,
thereby elevating device performance particularly in high-performance computing
and related domains. The integration of CD-CiM alongside FeFET-based macros
exemplifies inventive approaches aimed at enhancing electronic devices through
imaginative designs, novel materials, and computational techniques all in accordance
with the overarching objective of advancing electronic capabilities. This underscores
the relentless pursuit of pushing technological boundaries (Bankman et al. 2019).
Ferroelectric field-effect transistors (FeFETs) utilize ferroelectric materials in their
gate dielectrics to enable nonvolatile memory operations. FeFETs find wide-ranging
applications in both memory and logic circuits including the CD-CiM concepts leads
toward improved efficiency and increased density in innovative electronic designs.
This aligns perfectly with the overarching goal of advancing electronic capabil-
ities exemplifying a relentless drive to push the boundaries of technology (Kim
et al. 2021). Nonvolatile memory (NVM) offers advantages like increased density
and reduced power consumption. The voltage-mode charge-domain compute-in-
memory (CD-CiM) method focuses on energy-efficient applications utilizing capac-
itors. The integration of nanowires into device architectures aligns with the objective
30 R. K. Mishra et al.

Fig. 2.1 Illustrations

showcase the structures of
two variants: a vertical
nanowire GAAFET,
b vertical nanosheet
GAAFET (S: Source, D:
Drain)

of advancing electronic capabilities to enhance efficiency and performance high-

lighting the relentless pursuit of technological advancement (Kwong et al. 2012).
The progression of CMOS technology is in harmony with the growing demands
for data-centric applications, emphasizing low voltage, cost-effectiveness, and high
performance. The transition toward 3D architectures such as FinFETs and nanowire
FETs coupled with advanced materials and methodologies enhances control over
transistors diminishes leakage and amplifies mobility. This transformation under-
scores CMOS’s ability to align with the requirements of today’s cutting-edge elec-
tronics driven by a commitment to performance and innovation (Zhang et al. 2018;
Lauer et al. 2015). Figure 2.1 illustrates the characteristic structures of vertical
nanosheet and nanowire gate-all-around field-effect transistors (GAAFETs). These
visual representations provide insights into the configurations and arrangements of
these transistor designs highlighting their unique features and potential for improved
performance and integration density. The figures help to convey the advancements in
semiconductor technology and the innovative approaches being explored to address
the challenges of scaling down devices while maintaining high performance and
power efficiency.
In vertical nanowires, the gate pitch is decoupled from the nanowire length (Lg)
and spacer dimensions. The transistor density is governed by the spacing between
the wires. These figures underscore the innovation in semiconductor design focusing
on overcoming challenges related to device scaling and integration.
In conclusion, the evolution of semiconductor technology is witnessing significant
shifts driven by the need for enhanced performance, reduced power consumption,
and improved integration. The transition from conventional CMOS solutions to inno-
vative approaches like nanowires, III-V compound semiconductors, and GAAFETs
marks a pivotal phase in the field of electronics. These advancements fueled by inter-
disciplinary collaboration are reshaping device architectures, materials, and integra-
tion methods. From addressing challenges in traditional transistors to paving the
way for quantum computing and beyond, these innovations hold the potential to
usher in a new era of electronic capabilities. As research progresses, the path toward
efficient, high-performance and energy-saving electronic devices becomes clearer
demonstrating the relentless pursuit of pushing the boundaries of technological
possibilities.
2 Nanowire-Based Si-CMOS Devices 31

Transition in Semiconductor Technology

Semiconductor technology has undergone a remarkable transition over the decades

evolving from its humble beginnings to become the cornerstone of modern elec-
tronics. This transition has been characterized by continuous innovation, the pursuit
of smaller and more efficient components, and a relentless drive to push the bound-
aries of what is possible. In this exploration, we delve into the significant transitions
that have shaped semiconductor technology and paved the way for the advanced
electronic frontiers we see today (Etzkowitz et al. 2000). The silicon era which began
in the mid-twentieth century marked the inception of the semiconductor revolution.
Silicon’s abundance and favorable electrical properties made it the ideal material for
electronic components. The creation of the transistor in 1947 by John Bardeen, Walter
Brattain, and William Shockley at Bell Labs set the stage for a transformative shift
in electronics. Transistors with their ability to amplify and switch electronic signals
replaced bulky vacuum tubes enabling the miniaturization of electronic devices
(Smeeton and Humphreys 2017). One of the defining moments in semiconductor
history was the formulation of Moore’s law by Gordon Moore in 1965. Moore’s law
observed that the number of transistors on a microchip would double approximately
every two years while the cost per transistor would decrease. This empirical
observation became a guiding principle for the semiconductor industry driving
continuous miniaturization and performance improvements (Burg and Ausubel
2021). The era of microprocessors and integrated circuits emerged as semiconductor
manufacturers raced to adhere to Moore’s law. The transition from planar transistors
to fin field-effect transistors (FinFETs) and then to nanowire FETs allowed for better
control of electronic signals at nanometer scales. This transition ushered in the era
of high-performance computing enabling powerful computers, smartphones, and a
myriad of IoT devices (Clark 2014). While silicon remained dominant, researchers
began to explore new materials to further enhance semiconductor performance.
Gallium arsenide (GaAs), gallium nitride (GaN), and indium phosphide (InP)
offered advantages in specific applications such as high-frequency communication
devices and optoelectronics. Moreover, the integration of 2D materials like graphene
and transition metal dichalcogenides (TMDs) opened up new possibilities for
ultra-thin and flexible electronics (Burg and Ausubel 2021). The transition into the
realm of quantum computing represents a paradigm shift in semiconductor tech-
nology. Quantum bits or qubits that leverage the principles of quantum mechanics
promise computational capabilities that are in orders of magnitude beyond classical
computers. Companies and research institutions worldwide are investing heavily in
the development of quantum processors with superconducting qubits and trapped
ions as leading contenders (Laucht et al. 2021). Incorporating advanced materials like
ferroelectrics in transistors and capacitors has expanded the capabilities of electronic
devices. Ferroelectric field-effect transistors (FeFETs) enable nonvolatile memory
functions enhancing efficiency and density. Innovations such as compute-in-memory
(CiM) concepts utilizing capacitors for energy-efficient applications showcase
creative designs and materials for improved device architectures (Khan et al. 2020).
32 R. K. Mishra et al.

The transition in semiconductor technology is an ongoing journey marked by

constant innovation and adaptation. From the silicon era to the advent of quantum
computing and beyond, the semiconductor industry continues to redefine the possi-
bilities of electronics. As we look ahead, the collaboration between materials science,
physics, and engineering promises to unlock new frontiers in semiconductor tech-
nology shaping the future of electronics and computing in unprecedented ways. This
transition signifies a commitment to pushing the boundaries of what is achievable
propelling us toward a more technologically advanced and interconnected world.

Emerging Gate-All-Around Field-Effect Transistors

In the evolution of semiconductor technology, there is a notable transition from

FinFETs to gate-all-around field-effect transistors (GAA FETs) driven by the chal-
lenges of scaling. This transition encompasses both horizontal (hGAAFETs) and
vertical (vGAAFETs) designs strategically addressing the demands for enhanced
performance and efficiency especially in the context of the 3 nm semiconductor node.
This shift is a direct response to the scaling difficulties encountered, underscoring the
critical role of GAA FETs in advancing semiconductor technology at advanced nodes
(Bae et al. 2018). Extensive research efforts are dedicated to the refinement of both
horizontal (hGAAFETs) and vertical (vGAAFETs) gate-all-around field-effect tran-
sistors, focusing on aspects such as nanowire engineering, material advancements
and architectural optimizations. Among these, vGAAFETs emerge as particularly
noteworthy due to their advantages in vertical integration, effectively addressing
challenges associated with high mobility materials. This emphasis on vGAAFETs
signifies their pivotal role in shaping the trajectory of advanced semiconductor tech-
nology highlighting the continuous endeavor to enhance device performance and inte-
gration through innovative designs and materials (Zhang et al. 2018; Capogreco et al.
2018; Mertens et al. 2016). The dynamic path observed in semiconductor technology
underscores a steadfast dedication to inventive designs and integration methodolo-
gies ultimately reshaping the limits of semiconductor capabilities. The anticipated
results hold the potential for enhanced performance and applications that align with
the evolving needs of the industry, thereby propelling technological progress and
fostering innovation. This signifies an unwavering commitment to advanced elec-
tronic capabilities through imaginative approaches (Yadu Nath et al. 2018). The
investigation of vertical gate-all-around field-effect transistors (vGAAFETs) encom-
passes two distinct fabrication methodologies: bottom-up and top-down techniques.
These approaches play a pivotal role in the advancement of semiconductor tech-
nology and the integration of devices by offering viable strategies for constructing
vGAAFETs. This reflects the ongoing progress in augmenting electronic capabili-
ties through a diverse range of fabrication methods (Thomas et al. 2017). Bottom-up
methodologies generate vertical channels for vGAAFETs through self-assembly or
controlled growth, whereas top-down approaches craft channels using lithography
and etching processes. These varied techniques result in the creation of vGAAFETs
2 Nanowire-Based Si-CMOS Devices 33

Fig. 2.2 TEM

cross-sectional illustration of
a Si channel vertical
GAAFET (vGAAFET)
exhibiting the channel-last
fabrication method involving
growth from the bottom to
the top subsequent to the
establishment of bottom
borosilicate glass (BSG),
gate layer, and top BSG
layers (Oh et al. 2000)

with distinct materials and structures contributing significantly to the progress of

semiconductor technology. This illustrates the multifaceted strategies employed to
elevate electronic capabilities through a diverse array of fabrication methods (Mishra
2019). Figure 2.2 showcases the fabrication of a Si channel vertical gate-all-around
field-effect transistor (vGAAFET) through the channel-last bottom-up technique.
The process initiates by depositing bottom borosilicate glass (BSG), gate layer, and
top BSG layers followed by etching channel holes that terminate at the base Si layer.
Subsequent selective epitaxial growth from the base Si engenders a Si nanowire
that occupies the hole. Through annealing, source/drain regions are formed driving
dopants from BSG layers into the epitaxial Si while aligning with the gate (Oh
et al. 2000). This technique efficiently controls gate length through film deposition
and seamlessly aligns with the replacement metal gate methodology. Nevertheless,
when the channel hole diameter decreases and aspect ratios rise especially in verti-
cally stacked multi-device-layer setups, significant challenges arise in preserving
the quality of single crystal channels. This complexity becomes particularly signifi-
cant in the context of achieving high-performance logic circuits signifying a crucial
juncture in the vGAAFET fabrication process.
The vertical orientation of vGAAFETs introduces a unique fabrication challenges
demanding precise vertical control during manufacturing. This departure from the
conventional FinFET design highlights the innovative nature of vGAAFETs and
their role in advancing semiconductor technology. This underscores the importance
of creative solutions to tackle the vertical integration aspects of vGAAFETs (More
et al. 2018; Xiao et al. 2017; Sun et al. 2016). The duration of the etching process
following gate metal deposition plays a significant role in determining gate length
variation in vGAAFETs which in turn is crucial for device performance. This step
underscores the complexity of vGAAFET fabrication and underscores the necessity
for precise control over the fabrication processes. This emphasizes the significance of
optimizing etching processes to ensure consistent device performance in vGAAFETs
(Ramesh 2017). Challenges in vGAAFET fabrication become more pronounced as
nanowire pitch decreases and aspect ratios increase impacting the uniformity of gate
34 R. K. Mishra et al.

lengths. Methods such as anisotropic metal deposition and HDP oxide film deposi-
tion are employed to control gate length but ensuring precision becomes increasingly
intricate. This highlights the imperative need for innovative approaches to maintain
consistent dimensions in vGAAFETs (Larrieu et al. 2015). Innovative strategies such
as using electron beam resist for gate length definition are being explored to tackle
fabrication challenges associated with vGAAFETs. However, discrepancies in resist
thickness can lead to variability. The “vertical sandwich GAAFET” (VSAFET) inte-
gration process introduces a novel approach to manufacturing vGAAFETs with self-
aligned high-k metal gates. This minimizes gate-channel misalignment and asym-
metric source/drain regions enhancing uniformity and performance. These efforts
exemplify the dedication to precise integration methods to enhance the quality of
vGAAFET (Yin et al. 2020a). Innovative integration approaches are being employed
to tackle fabrication challenges associated with vGAAFETs leading to improved
performance and reliability. The introduction of VSAFET is a testament to the dedi-
cation to enhance semiconductor technology through inventive integration methods
with the goal of enhancing the efficiency and effectiveness of vGAAFETs in advanced
electronics. This reflects a proactive stance in overcoming obstacles and propelling
technological advancement (Yin et al. 2020b). Selective epitaxy growth (SEG) of
SiGe stressors within recessed source/drain (S/D) regions represents a significant
advancement to boost carrier mobility in miniaturized transistors. As technology
progresses, the focus is on increasing the germanium (Ge) content in SiGe S/D
regions with the goal of exceeding 50% in 10 nm FinFETs. This strategic approach
is centered on enhancing carrier mobility to optimize the efficiency and functionality
of semiconductor devices (Ghani et al. 2003; Jan et al. 2008). Figure 2.3 offers a
visual representation of Ge contents in S/D areas across various technology nodes.
This evolution underscores the strategic integration of SiGe stressors, tailored mate-
rial composition, and design to optimize carrier mobility and enhance transistor
performance exemplifying a pivotal direction in advancing semiconductor tech-
nology and design applications (Wang et al. 2020). The evolution of semiconductor
technology transitioning from FinFETs to vertical gate-all-around field-effect tran-
sistors (vGAAFETs) underscores the continuous pursuit of enhanced performance
and efficiency. In response to the challenges posed by shrinking transistor dimen-
sions, research efforts have yielded innovations such as VSAFET integration and the
integration of SiGe stressors. This relentless pursuit of innovation marked by interdis-
ciplinary collaboration and material optimization characterizes the field’s evolution
and its profound transformative impact.

Nanowire Advancements in Si-CMOS Devices

Nanowire advancements revolutionize Si-CMOS devices offering precise electronic

control and scalability solutions. Bottom-up and top-down fabrication methods tailor
nanowire properties enhancing efficiency and functionality. Exploring nanoscales
reveals quantum effects, driving innovation in quantum technology and pushing
2 Nanowire-Based Si-CMOS Devices 35

Fig. 2.3 Emerging trends: the growing impact of nanowire-based Si-CMOS devices (Scopus)

electronic capabilities’ boundaries for transformative applications and scientific

progress (Mishra et al. 2017). Nanoelectronic devices drive advancements in quantum
computing and communication in line with broader electronic goals. Investigating
quantum effects on the nanoscale transforms technology influencing information
processing and communication landscapes. This endeavor aligns with the overar-
ching objective of advancing electronic capabilities through quantum phenomena,
fostering innovation and transformative developments (Iyer and Lawrie 2022; Jha
et al. 2020). Technological advancement is closely linked to the emergence of
compute-in-memory (CiM) techniques particularly charge-domain CD-CiM with
nonvolatile memory (NVM). This novel method of employing ferroelectric field-
effect transistors (FeFETs) within a 2-transistor-1-capacitor (2T1C) arrangement
tackles issues related to power consumption and memory density. As a result, it
leads to energy conservation and improved memory accuracy. FeFET-based CD-CiM
showcases the prospect of efficient and high-performance electronics in line with the
objectives of technological progress (Koch et al. 2022). The flexibility of nanowires
on bendable substrates is crucial for wearable devices and displays. The use of
vapor–liquid–solid (VLS) mechanisms offers a cost-effective approach to nanowire
manufacturing supported by a new model that clarifies the growth process. This
controlled growth is in harmony with the progress of flexible electronics revolution-
izing electronic capabilities and their integration on curved surfaces. This represents
a dynamic shift in the evolution of electronics (Shakthivel et al. 2015). Enhancing
the production of precise 3D structures on flexible substrates, scientists refined an
electrohydrodynamic-based jet printing methods. This technique constructs 3D gold
micropillars forming arrays of micropillar electrodes (MEAs) with remarkable aspect
ratios. Through the amalgamation of additive manufacturing (AM) and hydrothermal
growth, they realized the growth of zinc oxide nanowires on MEAs without the
need for seed material leading to the development of flexible photodetectors with
36 R. K. Mishra et al.

robust UV-sensing capabilities. This innovative integration approach propels elec-

tronic technologies forward holding the potential for transformative applications
and pushing the field toward new frontiers (Ma et al. 2023). These progressions
mark the dawn of a fresh era in flexible electronics and contribute to our compre-
hensive comprehension of nanowire growth mechanisms. They broaden the scope
of fabrication options and potential applications across multiple domains encom-
passing sensors and biotechnology. Nanowires’ versatility in interfacing with an array
of materials facilitates the creation of customized electronic devices. Additionally,
templates like porous anodic aluminum oxide and polycarbonate membranes facili-
tate the development of intricate nanowire structures. This forward movement aligns
harmoniously with the persistent pursuit of elevating electronic capabilities through
nanotechnology and inventive materials, challenging the frontiers of technology
(Wang et al. 2021). The pursuit of integrated devices underscores the significance of
designing multi-component nanowires, as this design profoundly influences prop-
erties such as conductivity and stability. Meticulous attention to interfacial design
holds particular importance for emerging sensor and actuator technologies. Recent
progress encompasses a wide array of semiconductor nanowire synthesis methods
including laser-assisted catalytic growth spanning materials such as III-V compounds
and SiGe alloys. These advancements align seamlessly with the overarching objec-
tive of advancing electronic capabilities and materials driving innovation in the field
(Duan and Lieber 2000). Nanowires’ exceptional sensitivity opens up a wide array of
sensing applications spanning from health care to environmental monitoring. Their
potential to reshape diagnostic methods aligns harmoniously with the aspiration to
advance electronic capabilities and enhance the quality of life. This vision is closely
aligned with the overarching goal of fostering transformative applications that drive
progress in science and contribute to the betterment of human well-being (Abdul
Rashid et al. 2013). Organic field-effect transistors (OFETs) utilizing organic semi-
conductors (OSCs) exhibit robust chemical sensing capabilities enabling the detec-
tion of various analytes including biomolecules. The integration of these OFETs
into health care and diagnostic applications aligns seamlessly with the objective of
advancing electronic capabilities to address practical challenges. This highlights their
potential to bring about transformative improvements in diagnostics and enhance our
understanding of complex systems, thereby contributing to real-world advancements
(Li et al. 2019). Nanowire-based Si-CMOS devices play a crucial role in the devel-
opment of neuromorphic computing aiming to replicate brain functions for advance-
ments in artificial intelligence (AI). The utilization of scandium nitride (ScN) facili-
tates efficient optoelectronic synaptic operations in line with the overarching objec-
tive of pushing electronic capabilities for pioneering fields such as neuromorphic
computing. This evolution aligns with the broader goal of enhancing computational
efficiency and fostering innovation in the realm of AI and computing (Rao et al.
2023). Scandium nitride (ScN) optoelectronic synapses featuring both excitatory
and inhibitory functions significantly improve memory storage capabilities. ScN’s
stability, compatibility with CMOS technology, and photoconductivity make it ideal
for rapid photonic processing in neuromorphic computing with nanowires enhancing
2 Nanowire-Based Si-CMOS Devices 37

its capabilities. This endeavor resonates with the ongoing pursuit of advancing elec-
tronic capabilities for innovative applications, reflecting relentless progress in trans-
formative technological advancements (Chen et al. 2023). To drive innovation in
this field, it is imperative to foster interdisciplinary collaboration among experts in
materials science, nanotechnology, electronics, and physics. The growing volume
of research activity and publications dedicated to nanowire technology underscores
its increasing importance. Nanowires have the potential to enhance semiconductor
capabilities significantly leading to transformations in various industries and laying
the foundation for future advancements in nanowire-based devices. Figure 2.3 illus-
trates the escalating research engagement and publications concerning nanowire-
based Si-CMOS devices. With a trajectory from a solitary publication in 1998 to
a recent substantial surge, this technology is commanding attention and reshaping
the semiconductor landscape. Researchers are exploring its potential to enhance Si-
CMOS devices and catalyze innovation across industries. The upward publication
trend underscores the mounting importance of this field and its potential to drive
transformative advancements in semiconductor technology. This data exemplifies
the promising outlook and emerging trends in nanowire technology pointing toward
a future characterized by significant breakthroughs.
Nanowire-based silicon complementary metal–oxide–semiconductor (Si-CMOS)
devices hold the promise of transforming industries overcoming scaling limitations
and enhancing the efficiency of electronic systems. Silicon nanowires in partic-
ular play a pivotal role in Si-CMOS technology owing to their one-dimensional
nanoscale structure and the quantum confinement effects they exhibit. These effects
manifest when semiconductor dimensions approach the de Broglie wavelength of
charge carriers leading to the quantization of energy levels. The distinctive proper-
ties of nanowires arise from these effects impacting a wide range of Si-CMOS appli-
cations and propelling the advancement of semiconductor technology (Ray et al.
2017). Nanowire CMOS devices exhibit superior electrostatic control thanks to their
larger surface-to-volume ratio which enables more efficient gate control compared to
planar devices. This improved gate control allows for better penetration of the elec-
tric field into the nanowire, thereby regulating the channel current and mitigating
short-channel effects. Nanowires offer a solution to the scaling challenges faced by
conventional CMOS devices addressing limitations that arises with shrinking device
dimensions (Nela et al. 2021). Figure 2.4 illustrates the device’s architecture, oper-
ation, and key metrics. Nanowires are structured in the gate region with a 3D gate
electrode controlling parallel channels through nanowire sidewalls. Nanowire width
on the source side is adjusted for positive threshold voltage (V TH ) and enhancement-
mode operation crucial for power devices. The slanted FP termination on the drain
side distributes high electric fields and achieves high voltage-blocking capability
(VBR).
Nanowires’ extended effective channel length effectively mitigates short-channel
effects and facilitates further scaling in CMOS technology. Nanowire-based CMOS
operates at lower voltages resulting in reduced power consumption due to its
improved gate control. However, challenges persist in achieving uniform nanowire
properties during fabrication to ensure optimal device performance despite the
38 R. K. Mishra et al.

Fig. 2.4 a 3D schematic of the proposed multi-channel device featuring multiple parallel channels
to yield extremely low RON controlled three dimensionally by a tri-gate electrode. The tri-gate is
terminated in the nanowire region rather than in the planar region to better distribute the electric
field and result in high VBR b focused ion beam cross-section and schematic of the multi-channel
nanowires covered by the tri-gate structure along the line AB in a. The tri-gate enables a simultaneous
3D control over all the multiple channels in the nanowire. Scale bar, 100 nm, c top-view SEM image
of the nanostructured gate area (before gate oxide and electrode deposition) which includes starting
from the source side, an e-mode region achieved using 15-nm-wide nanowires and a slanted region
terminated on 100-nm-wide d-mode nanowires for optimal electric field management d, e high-
angle annular dark-field (HAADF) scanning transmission electron microscopy (STEM) image d of
a multi-channel AlGaN/GaN heterostructure with five parallel channels and its simulated energy
band diagram, e N is the electron concentration (in cm−3 ), and Ec is the conduction band energy,
f dependence of N s , µ, and Rsh on the number of channels (N ch ) at room temperature (RT ) which
were grown on sapphire substrates with undoped Al0.3Ga0.7N barrier layers (Nela et al. 2021)

promising potential of nanowire-based Si-CMOS technology (Nazir et al. 2020). Effi-

cient charge transport and reliable device operation in nanowire-based CMOS tech-
nology hinge on precise engineering to overcome challenges like contact resistance
and diameter variations. These issues can impact device performance and unifor-
mity emphasizing the importance of addressing them during nanowire integration
2 Nanowire-Based Si-CMOS Devices 39

into CMOS components (Radamson et al. 2020). Understanding the fabrication tech-
niques, whether bottom-up, involving precise assembly from atomic components, or
top-down, which gradually reduces larger materials to the nanoscale is crucial for
harnessing the potential of nanowires in Si-CMOS devices. These methods under-
score the importance of interdisciplinary collaboration and innovation in advancing
modern electronics and semiconductor technology (Chen et al. 2020). As we delve
into their full potential, the transformative impact of nanowire-based Si-CMOS on
electronics and beyond is an exciting journey to anticipate. Through continuous
refinement and innovative exploration, nanowire-based Si-CMOS devices will play
a pivotal role in driving progress and innovation within the semiconductor realm. This
chapter delves into the transformative landscape of these devices highlighting their
significant contribution to semiconductor technology advancement. Nanowire-based
Si-CMOS devices offer a promising solution to the scaling limits of planar CMOS
elevating device performance. This chapter underscores their potential to reshape
the future of semiconductor technology addressing limitations and revolutionizing
industries. As researchers refine techniques and explore applications, nanowire-
based Si-CMOS will propel electronics advancement solidifying their significance
in innovation.

Nanowire Fabrication Approaches

Nanowire-based Si-CMOS devices offer groundbreaking potential in semiconductor

technology addressing scaling limits of planar CMOS. This chapter explores princi-
ples, fabrication, and applications comprehensively highlighting their transformative
impact (Zhang et al. 2021a). Nanowire fabrication involves two main approaches:
bottom-up and top-down techniques. Bottom-up methods focus on controlled growth
for vertical channels while top-down techniques define channels through lithography
and etching. These approaches contribute to advancing nanotechnology and semi-
conductor device integration (Hobbs et al. 2012). These approaches play a pivotal role
in advancing semiconductor technology and device integration as shown in Fig. 2.5.

Bottom-Up and Top-Down Techniques

The bottom-up approach entails the fabrication of nanowire devices by assembling

atomic or molecular constituents. This technique provides meticulous control over
nanowire assembly. Materials are manipulated at the atomic or molecular scale to
create nanowires using processes such as chemical vapor deposition (CVD), molec-
ular beam epitaxy (MBE), or self-assembly methods (Ortega et al. 2017). The bottom-
up approach offers distinct advantages in achieving consistent nanowire dimensions
and properties which are crucial for optimal device performance. However, it can
be challenging to scale up and precisely regulate nanowire growth leading to issues
40 R. K. Mishra et al.

Fig. 2.5 Comparison of

semiconductor nanowire
fabrication approaches:
bottom-up and top-down
paradigms. Bottom-up
methods involve controlled
growth or self-assembly of
nanowires while top-down
techniques use lithography
and etching to shape
nanowire structures (Hobbs
et al. 2012)

of reproducibility and uniformity. In contrast, the top-down approach initiates with

larger materials and gradually reduces them to nanoscale dimensions. Techniques
like electron beam lithography and reactive ion etching are employed to pattern and
mold larger materials into nanowires. This method provides greater control over
nanowire dimensions and placement but can be more intricate and time-consuming.
Top-down fabrication is well-suited for creating specific designs and structures and is
often combined with existing semiconductor processing techniques (Yu et al. 2013).
Maintaining consistent and uniform nanowire dimensions throughout the fabrication
process can indeed be a challenge in both approaches. Each method has its distinct
advantages and limitations. The bottom-up approach is particularly effective in gener-
ating uniform nanowires with controlled properties making it suitable for applications
where precision is of utmost importance. However, scaling up and ensuring consistent
growth can be challenging in this approach (Dahiya et al. 2019). Indeed, a compre-
hensive understanding of both the top-down and bottom-up fabrication approaches
is essential for developing nanowire-based Si-CMOS devices. Each approach has its
advantages and challenges and choosing the most appropriate method depends on the
specific requirements and goals of the device being manufactured. Researchers and
engineers in the field of nanowire-based Si-CMOS technology need to consider these
factors to optimize device performance and uniformity while ensuring efficient manu-
facturing processes (Ortega et al. 2017; Yu et al. 2013; Dahiya et al. 2019). Indeed, the
choice between bottom-up and top-down approaches should align with the specific
requirements of the application considering factors like device performance, scala-
bility, and design complexity. Advances in both methods contribute significantly to
the progress of nanowire technology and their integration can provide solutions to
various challenges. A visual representation in Fig. 2.6 serves as a helpful reference,
emphasizing the benefits and challenges of each approach. A comprehensive under-
standing of these methods is crucial for informed decision-making in nanowire-based
Si-CMOS device production, ultimately advancing semiconductor technology.
2 Nanowire-Based Si-CMOS Devices 41

Fig. 2.6 Fabrication approaches for nanowire a bottom-up, b top-down

The bottom-up approach entails the growth of nanowires in the vapor phase
using metal catalysts, although achieving precise control over their diameter and
morphology can be challenging. Conversely, the top-down approach employs tech-
niques like electron beam lithography and reactive ion etching to precisely pattern
nanowires but it tends to be more complex and intricate in execution. Understanding
these fabrication methods is crucial for developing nanowire-based Si-CMOS devices
(Demontis et al. 2021). Incorporating nanowires into CMOS processes necessitates
modifications often involving the implementation of gate-all-around (GAA) struc-
tures. GAA structures are employed to fully utilize the distinctive properties and
characteristics of nanowires, thereby contributing to the advancement of semicon-
ductor technology. Within a GAA structure, the gate surrounds the nanowire leading
to improved electrostatic control and enhanced device performance (Mukesh and
Zhang 2022). Nanowire-based Si-CMOS devices are making significant contribu-
tions across various domains ushering in a revolution in multiple industries: (a)
Nanowire-based Si-CMOS devices exhibit faster switching speeds and reduced
power consumption enhancing the overall performance of logic circuits, (b) These
devices are well-suited for nonvolatile memory applications like flash offering
increased memory density and scalability, and (c) Nanowire CMOS devices are
highly sensitive making them ideal for use in sensors including gas and biosensors.
They excel in detecting and measuring various parameters with precision (Kwong
et al. 2012). The versatility of nanowire-based Si-CMOS devices in various applica-
tions arises from their exceptional responsiveness to external stimuli. These devices
hold the promise of revolutionizing the future of semiconductor technology driven
by their unique properties that enable miniaturization, improved performance, and
a wide range of applications (Zhu 2017). Continuous research and development
42 R. K. Mishra et al.

in nanowire fabrication and integration are expected to accelerate the adoption of

nanowire-based Si-CMOS devices in electronic devices. These devices are likely to
play a pivotal role in shaping the future of semiconductor technology as they continue
to advance and evolve.

Silicon Nanowire Fabrication and Technology

One-dimensional nanostructures like nanotubes (NTs) or nanowires (NWs) display

exceptional attributes owing to their elevated aspect ratios and substantial surface
areas (Yaragalla et al. 2018). Silicon nanowires (SiNWs) are recognized for their
compatibility with current technology and have utility in solar cells, sensors, cata-
lysts, and batteries due to their outstanding characteristics and integration possibili-
ties. However, the industrial-scale production of single SiNW-based devices encoun-
ters difficulties due to intricate methods and variable properties. “Nanonets,” formed
by randomly oriented NWs, offer a solution for applications by enhancing repro-
ducibility and leveraging the distinctive properties arising from both individual NWs
and the network structure. This transition mitigates constraints and augments the
potential of nanowire-based technologies (Srivastava et al. 2020). Silicon comple-
mentary metal–oxide–semiconductor (Si-CMOS) devices form the basis for inte-
grated circuits (ICs) and various memory technologies, including phase-change RAM
(PCRAM), magnetic RAM (MRAM) and resistive RAM (ReRAM). These emerging
memory technologies are characterized by unique features and are garnering atten-
tion for their potential to revolutionize the semiconductor industry. This discus-
sion encompasses the rationales, attributes, applications, and underlying mechanisms
contributing to their importance in semiconductor technology (Zhang et al. 2020).
Figure 2.7 provides a visual representation of how silicon complementary metal–
oxide–semiconductor (Si-CMOS) devices form the basis for advanced memory tech-
nologies. Memory technologies can be broadly categorized into two main types:
volatile memory which includes SRAM, DDR/SDRAM, VRAM, and nonvolatile
memory, encompassing FeRAM, PCM, RRAM, MRAM, FRAM, and CBRAM. Si-
CMOS technology plays a pivotal role in driving innovation within the semiconductor
industry by facilitating advancements in both volatile and nonvolatile memory tech-
nologies. In particular, Si-CMOS technology is crucial in various stages of memory
device production including NAND Flash, NOR Flash, EPROM, HDD, and SSD.
It is instrumental in developing control circuitry, address decoding, and data inter-
faces for emerging memory devices such as PCRAM, MRAM, and ReRAM. These
emerging memory technologies have the potential to replace NOR Flash and SRAM
in various applications as they become integrated into existing CMOS processing
leading to reduced manufacturing costs. However, well-established memory tech-
nologies like DRAM, NOR Flash, and SRAM continue to dominate the market
due to their cost-effectiveness and maturity (Spinelli et al. 2017). Silicon nanowire
technology represents a noteworthy progression in the fields of nanoelectronics and
nanophotonics. These nanostructures have diameters on the nanometer scale and
2 Nanowire-Based Si-CMOS Devices 43

lengths that span from micrometers to millimeters. Their exceptional characteris-

tics such as a substantial surface area relative to volume and the occurrence of
quantum confinement effects render them exceptionally appealing for a wide array of
applications. Silicon nanowires can be fabricated using both top-down and bottom-
up techniques. In the top-down approach, silicon wafers are etched and patterned
using conventional lithography methods underscoring their versatility in the manu-
facturing process (Arjmand et al. 2022). The top-down approach offers meticulous
control over the dimensions and placement of nanowires. In contrast, the bottom-up
method involves the production of silicon nanowires through vapor-phase growth
utilizing either the vapor–liquid–solid (VLS) or vapor–solid (VS) mechanisms. VLS
employs a metal catalyst to facilitate growth, whereas VS entails the direct conden-
sation of silicon vapor. Silicon nanowire technology brings with it several advan-
tages including the ability to fine-tune electrical and optical properties, high carrier
mobility, and the potential for integration with silicon complementary metal–oxide–
semiconductor (Si-CMOS) devices (Puglisi et al. 2019). These properties present
intriguing possibilities for the development of advanced nanoscale devices including
high-performance transistors, sensors, photodetectors, and optoelectronic compo-
nents. Scientists and engineers are continually improving silicon nanowire tech-
nology to harness its full potential. Ongoing progress in fabrication techniques and
materials holds the potential for innovative applications in fields such as biomedical
sensing, energy harvesting, and quantum computing. As silicon nanowire technology
continues to advance, it stands ready to play a crucial role in shaping the next wave
of nanoelectronic and nanophotonic devices across a wide range of disciplines (Ding
et al. 2018). Silicon nanowire fabrication plays a pivotal role in advancing Si-CMOS
devices and the vapor–liquid–solid (VLS) method is a noteworthy approach. With
the aid of a metal catalyst, VLS initiates nanowire growth from vapor-phase silicon.
This method’s precision in controlling nanowire diameter and morphology makes it
a preferred choice for high-quality silicon nanowire production. Continued advance-
ments in fabrication techniques hold promise for the widespread application of silicon
nanowires in various nanoelectronic devices and other innovative applications (Abdul
Rashid et al. 2013).
Epitaxial growth is a highly controlled technique used to produce silicon
nanowires. It involves growing these nanowires on a silicon substrate while care-
fully regulating factors such as temperature and gas flow. This method ensures
precise nanowire orientation and crystal structure making it particularly suitable
for applications that require specific orientations. Epitaxial growth is well-suited
for integrating nanowires with standard silicon wafers commonly used in traditional
CMOS processes. This compatibility enhances the versatility and potential of silicon
nanowires in the field of nanoelectronics (Mandl et al. 2010). Chemical vapor depo-
sition (CVD) is a versatile method for fabricating silicon nanowires. In this process,
silicon precursors and a carrier gas are introduced into a reaction chamber. When
heated, these precursors decompose leading to the formation of nanowires on a
substrate. CVD is advantageous because it can be scaled up for large-scale produc-
tion. Variations of CVD such as low-pressure CVD (LPCVD) and plasma-enhanced
CVD (PECVD) provide precise control over nanowire growth. This level of control
44 R. K. Mishra et al.

Fig. 2.7 Emerging memory technologies on the rise

makes CVD well-suited for industrial applications in the field of nanoelectronics. It

enhances the versatility and potential of silicon nanowires across various applica-
tions (Mishra et al. 2018). Sol–gel synthesis is a method that involves growing silicon
nanowires from a silicon precursor solution. This technique provides a simple and
cost-effective approach particularly suitable for specific applications. Laser-assisted
growth, on the other hand, employs a laser to induce localized nanowire growth from
a silicon source. This enables precise positioning of nanowires on substrates. These
innovative techniques significantly expand the toolkit for silicon nanowire fabrica-
tion making it adaptable to a wide range of application requirements in the fields
of nanoelectronics and nanophotonics (Bokov et al. 2021). Hydrothermal synthesis
is a technique that involves growing silicon nanowires within a hydrothermal solu-
tion. This method is particularly well-suited for flexible substrates and the creation
of three-dimensional structures. After the nanowires have grown, precise patterning
becomes crucial to fabricate devices with specific dimensions and features. These
techniques significantly expand the potential applications of silicon nanowires in
various contexts including flexible electronics and the integration of nanowires into
three-dimensional devices (Arjmand et al. 2022). Lithography-based methods such as
2 Nanowire-Based Si-CMOS Devices 45

electron beam lithography (EBL) and nanoimprint lithography (NIL) are employed
to precisely pattern silicon nanowires on substrates. These techniques involve the
removal or deposition of materials using masks, ensuring precise control over
nanowire dimensions and positioning. However, it is important to note that while they
offer high precision, lithography-based approaches can be time-consuming and may
not be the most suitable choice for large-scale manufacturing processes (Sharma et al.
2022). Focused ion beam (FIB) uses a precisely focused ion beam for material etching
allowing for nanoscale pattern creation on nanowires. This is primarily utilized for
research and prototyping purposes. Plasma etching on the other hand employs a
plasma to achieve highly anisotropic etching resulting in high-aspect-ratio nanowire
structures. Self-assembly techniques utilize the nanowires themselves to pattern the
substrate offering innovative approaches to nanowire integration and device fabri-
cation. These methods complement traditional lithography-based techniques and
enhance the versatility of silicon nanowire applications (Manoccio et al. 2020). Self-
assembly techniques take advantage of the natural alignment of nanowires, simpli-
fying pattern formation. Each method has its own advantages and limitations, and the
choice depends on the specific requirements of the application and the properties of
the nanowires. These approaches increase the flexibility of silicon nanowire appli-
cations meeting various needs in nanoelectronics and nanophotonics (Chen et al.
2022). In summary, silicon nanowire technology plays a leading role in the realms of
nanoelectronics and nanophotonics offering a versatile array of fabrication methods
including vapor–liquid–solid (VLS), epitaxial growth, chemical vapor deposition
(CVD), and self-assembly. Advancements in nanotechnology necessitate the down-
sizing of structures to dimensions below 100 nm achieved through techniques like
electron beam lithography (EBL), focused ion beam fabrication (FIB), nanoimprint
lithography (NIL), and scanning probe lithography (SPL). Each of these methods
offers unique characteristics related to factors such as resolution, speed, environ-
mental conditions, and cost tailored to specific nanofabrication applications. These
techniques provide precise control over nanowire properties rendering them attrac-
tive for a wide range of applications spanning high-performance transistors, sensors,
and optoelectronic components. The selection of the fabrication method hinges on
the specific requirements of the application permitting customized solutions in the
dynamic realm of silicon nanowire technology.

Electron Beam Lithography (EBL) for SiNW Fabrication

Electron beam lithography (EBL) represents a cutting-edge nanofabrication tech-

nique employed to achieve meticulous patterning on substrates through the utiliza-
tion of a focused electron beam. Si nanowire EBL is of paramount importance in
the production of electronic circuits employing lithographic procedures to expose
resist materials with finely focused electron beams. This technology is distinguished
by its exceptional precision and holds a central role in the realm of advanced semi-
conductor manufacturing processes (Fan et al. 2022). Electron beam lithography
46 R. K. Mishra et al.

encompasses two main systems: scanning lithography and projection lithography. In

projection electron beam lithography, a broad non-focused electron beam exposes
the entire image in a single exposure. This process involves a predefined pattern on a
photocathode which is situated on an optical mask. When ultraviolet rays illuminate
the photocathode, electrons are emitted from the irradiated areas enabling precise
patterning for a multitude of nanofabrication purposes (Thornton 1980). In projection
electron beam lithography, emitted electrons are uniformly directed onto the resist
surface through electrostatic and magnetic fields generating the entire pattern on
the substrate simultaneously as depicted in Fig. 2.8a. In contrast, scanning electron
beam lithography utilizes a focused electron beam precisely guided by a computer
program, allowing for intricate pattern creation with high precision. However, the
sequential scanning process in scanning lithography can result in longer exposure
times for complex patterns as shown in Fig. 2.8b. Both electron beam lithography
systems offer distinct advantages and are suitable for specific applications. Scanning
lithography provides precision but may require longer exposure times for complex
patterns. Projection lithography enables rapid exposure of entire patterns at once.
Si nanowire electron beam lithography advances technology driving innovation in
electronic circuits for improved performance and new applications in electronics.
In this example, the fabrication of Si nanowires using electron beam lithog-
raphy (EBL) is depicted illustrating the intricate process of creating silicon nanowire
patterns on a silicon substrate for innovative electronic devices. This journey encom-
passes the generation of high-energy electron beams, substrate preparation, and the
precise patterning of nanowires. It reveals the techniques involved in resist develop-
ment and etching which are essential for the formation of silicon nanowires merging

Fig. 2.8 Comparison of projection and scanning electron beam lithography a electron beam
lithography projection system, b electron beam lithography scanning system
2 Nanowire-Based Si-CMOS Devices 47

innovation with craftsmanship in the field of nanotechnology for advanced electronic

circuits. The final stage of silicon nanowire fabrication involves characterization and
exploration of applications in nanoelectronics, nanophotonics, sensors, and energy
storage. The fundamental steps in employing EBL for silicon nanowire production
consist of coating the substrate with a specific resist material that is sensitive to elec-
tron irradiation. Subsequently, the substrate is placed within an EBL system equipped
with a high-precision electron beam column for precise nanoscale patterning. Here,
a focused electron beam initiates chemical changes in the resist material. After the
electron beam exposure, a development process ensues to conclude the fabrication
process tailoring nanowire properties to suit diverse applications (Kim et al. 2011).
The development step entails submerging the substrate in a solvent which selectively
dissolves the unpolymerized resist regions. This action creates a patterned resist
mask that corresponds to the areas exposed to the electron beam. The mask serves
as protection during the subsequent etching process wherein the substrate mate-
rial is selectively removed in the regions that are left unprotected. This controlled
etching procedure yields silicon nanowires with precise dimensions and features,
thereby concluding the fabrication process for a variety of applications (Zaouk et al.
2005). Figure 2.9 depicts the stepwise procedure for producing silicon nanowires
using electron beam lithography (EBL), a precision-driven technique. The process
initiates with substrate coating and meticulous electron beam scanning, inducing
a chemical transformation in the resist material and resulting in the creation of a
patterned resist mask. Sequential stages of development and etching ultimately yield
silicon nanowires characterized by distinct dimensions and features. EBL plays a
pivotal role in propelling nanotechnology forward facilitating the development of
innovative electronic devices that exhibit enhanced performance and applications
spanning various domains.
Electron beam lithography (EBL) stands out as the preferred method for silicon
nanowire fabrication due to its exceptional precision. It offers precise control over
nanowire dimensions and patterns enabling the creation of sub-nanometer features.
This capability leads to the production of high-quality nanowires with exact geome-
tries, advancing nanotechnology applications in various fields. EBL’s versatility
allows for the fabrication of diverse nanowire configurations and shapes, which
is crucial for tailoring properties to specific applications. It proves invaluable in
research and prototyping, providing precise control over nanowire parameters. This
precision aids in understanding design effects and optimizing performance in various
applications. However, EBL does have limitations. Notably, it operates at a rela-
tively slow speed, which can make it time-consuming when dealing with extensive
nanowire patterns. The associated equipment and resources required for EBL are
costly, which restricts its use in large-scale commercial applications. Additionally,
its limited throughput makes it unsuitable for mass production purposes (Huang
et al. 2017). Alternative techniques like nanoimprint lithography or self-assembly
are better suited for high-volume manufacturing compared to electron beam lithog-
raphy (EBL). In summary, EBL is indispensable for silicon nanowire fabrication
due to its unmatched precision. Although it may not be suitable for large-scale
production, EBL plays a vital role in research, prototyping, and applications that
48 R. K. Mishra et al.

Fig. 2.9 Silicon nanowire fabrication: a hierarchical process of creating silicon nanowires by
electron beam lithography (EBL)

require exceptional precision. As nanofabrication continues to evolve, EBL will

remain pivotal in advancing nanowire-based Si-CMOS devices and semiconductor
technology (Fruncillo et al. 2021).

Sidewall Transfer Lithography for SiNW Fabrication

Sidewall transfer lithography (STL) and electron beam lithography (EBL) repre-
sent distinct methodologies for the fabrication of silicon nanowires. STL is a cost-
effective option designed for the high-volume production of relatively straightfor-
ward nanowire structures. In contrast, EBL stands out for its exceptional capacity
to intricately design and customize nanowire patterns with unmatched precision.
This makes EBL particularly well-suited for research purposes and applications
requiring low-volume production where precision remains a paramount considera-
tion (Chen 2015). The selection between STL and EBL is contingent upon the precise
objectives and prerequisites of silicon nanowire fabrication. Figure 2.10 furnishes a
comparative analysis of these methodologies considering their lithographic proce-
dures, pattern transfer techniques, and benefits and domains of application. STL is
well-suited for the efficient mass production of straightforward nanowires at a reason-
able cost. Conversely, EBL demonstrates exceptional precision making it optimal
for the creation of intricate, tailored patterns, especially in research and scenarios
demanding low-volume production.
2 Nanowire-Based Si-CMOS Devices 49

Fig. 2.10 Two paths to silicon nanowire fabrication: a comparative hierarchy of sidewall transfer
lithography (STL) and electron beam lithography (EBL)

Sidewall transfer lithography (STL) represents an effective approach for the fabri-
cation of silicon nanowires providing a combination of high throughput and metic-
ulous management of nanowire properties. STL relies on a resist pattern to transfer
nanowire configurations from a sacrificial layer onto a substrate rendering it a well-
suited choice for the scalable manufacturing of Si-CMOS devices integrated with
nanowires (Liu and Syms 2014). The process of sidewall transfer lithography (STL)
for silicon nanowire fabrication comprises several essential steps: (a) The substrate
is coated with a sacrificial layer that can be readily etched, (b) A resist material
is used to pattern the coated substrate defining the locations and configurations of
nanowires, (c) Selective etching of the sacrificial layer is performed revealing the
nanowire pattern, and (d) The resist material is removed leaving behind the nanowire
pattern which can be integrated into CMOS devices. STL offers an efficient and scal-
able approach for producing silicon nanowires while maintaining precise control over
their features (Tintelott et al. 2021).

Sacrificial Layer Materials

The choice of sacrificial layer material is contingent on the specific application and
the desired attributes of the nanowires. Common materials employed for this purpose
encompass silicon dioxide (SiO2 ) and silicon nitride (Si3 N4 ) (Cheng et al. 2006).
50 R. K. Mishra et al.

Resist Materials

The selection of resist material in sidewall transfer lithography (STL) is pivotal

for achieving pattern resolution and accuracy. Commonly used resist materials for
silicon nanowire fabrication encompass poly (methyl methacrylate) (PMMA) and
hexamethyldisilazane (HMDS) (Raghvendra 2018).

Sacrificial Layer Etching

The sacrificial layer removal in sidewall transfer lithography (STL) can be achieved
using various methods, such as reactive ion etching (RIE) or inductively coupled
plasma (ICP) etching. The selection of the technique depends on the specific material
and process requirements (Raghvendra 2018).
Sidewall transfer lithography (STL) stands out as a promising option for various
industrial applications due to its notable strengths, including high throughput
and precise control over nanowire characteristics. As research in nanofabrication
continues to advance, the importance of STL in silicon nanowire fabrication is
expected to increase. By combining STL with other nanofabrication techniques
and ongoing improvements in resist materials and etching processes, the potential
of silicon nanowire fabrication can be further extended offering opportunities for
the development of high-performance nanowire-based Si-CMOS devices (Engstrom
et al. 2011).

Si Nanonet Fabrication from SiNWs

The transition from microelectronics to macroelectronics is observable in applica-

tions such as flexible displays, solar cells, sensors, and intelligent surfaces. The
“More than Moore” paradigm highlights the necessity for intricate systems that
integrate multiple technologies including nanotechnology. This involves the devel-
opment of interfaces that facilitate the connection of devices at the macro, micro, and
nanoscale levels in response to the changing requirements and specifications in the
field of electronics (Dayananda et al. 2018). Facilitating the integration of various
functionalities and materials across different size scales presents a challenge that
revolves around identifying materials capable of low-temperature processing offering
high performance, transparency, and flexibility. Crystalline inorganic nanoparticles,
nanowires (NWs), and carbon nanotubes (CNTs) possess these desired character-
istics. Their submicrometer diameters and the ability to customize their material
properties through chemical synthesis render them well-suited for a broad spec-
trum of applications, thanks to their innate flexibility and adaptability (Khan et al.
2022). Although materials such as nanotubes and nanowires exhibit promising
characteristics, the assembly of these materials into functional devices remains a
formidable challenge. It is essential to achieve cost-effective and precise assembly at
2 Nanowire-Based Si-CMOS Devices 51

the nanometer scale while minimizing performance variations and ensuring scal-
ability for large-scale applications. Variations in doping levels, dimensions, and
defects in individual nanowires can significantly impact device reproducibility. One
potential solution lies in the use of nanotube and nanowire-based network materials
often referred to as nanonets. These nanonets have the potential to enhance large-area
electronics regardless of whether they exhibit metallic or semi-conductive behavior
(Khan et al. 2019). Indeed, semiconducting nanonets have received comparatively
less attention and development than their metallic counterparts. This discrepancy is
due to various factors including the length, diameter, chirality, and electrical charac-
teristics (whether they are semiconducting or metallic) of the nanotubes as well as the
interactions at tube-to-tube junctions. These factors collectively influence the elec-
tronic properties of semiconducting nanonets. Moreover, semiconducting nanonets
can be sensitive to environmental conditions that can lead to instability and limit
reproducibility. It is imperative to thoroughly explore and address these challenges
to advance the field of semiconducting nanonet technologies (Rouhi et al. 2011).
Nanonets, particularly when their thickness is significantly smaller than the individual
components, exhibit 2D percolation properties. While carbon and metallic nanonets
have been extensively investigated for their use in transparent and conductive thin
films especially in photovoltaic applications, there is a relatively limited body of
research on 2D nanonets using materials such as silicon (Si) and zinc oxide (ZnO).
Promising techniques for the precise and large-scale fabrication of 2D nanonets
include solution-based self-assembly and filtration methods. These methods offer
control over the thickness of the nanonets and enhance their versatility for various
applications (Prasad et al. 2021). Silicon nanowires are commonly used as the founda-
tional or precursor materials for producing silicon nanonets. The procedure typically
commences with the fabrication of silicon nanowires. There are several techniques
available for synthesizing silicon nanowires including vapor–liquid–solid (VLS)
growth, chemical vapor deposition (CVD), and other bottom-up methodologies.
These methods offer precise control over critical parameters such as nanowire diam-
eter, length, and orientation (Ding et al. 2019). Silicon nanowires possess specific
characteristics including a high aspect ratio, adjustable electrical conductivity, and
compatibility with silicon-based semiconductor technology rendering them well-
suited for the formation of silicon nanonets. These silicon nanowires are typically
slender resembling one-dimensional structures. To construct silicon nanonets, these
individual silicon nanowires are organized or assembled into a network-like config-
uration. Various techniques can be employed to accomplish this assembly process
(Raman et al. 2023). One method involves suspending the silicon nanowires in a
solution permitting them to undergo self-assembly on a substrate forming a nanonet.
The arrangement and density of the nanowires in the resulting nanonet can be influ-
enced by factors such as the choice of solvent, its concentration, and the properties
of the substrate. Another versatile technique is filtration in which the nanowires
are gradually deposited onto a filter surface. Over time, they accumulate to form
a nanonet on the filter, which can subsequently be transferred to other substrates.
By adjusting parameters like the solution volume and concentration, precise control
over the thickness and characteristics of the nanonet can be achieved. Following the
52 R. K. Mishra et al.

formation of silicon nanonets, thorough characterization may be necessary to ensure

they possess the desired properties. This characterization process can encompass
measurements of electrical conductivity, transparency, or other relevant parameters
to validate their functionality and suitability for specific applications (Legallais et al.
2019). Moreover, to enhance the uniformity and reproducibility of the nanonet struc-
ture, optimization steps may be implemented. Silicon nanonets constructed from
interconnected silicon nanowires hold promise in various fields of applications. They
can serve roles in transparent conductive films, flexible electronics, sensors, photode-
tectors, and more. The properties of these nanonets can be customized to meet the
specific demands of these diverse applications. In summary, silicon nanowires can
serve as the initial building blocks for fabricating silicon nanonets achieved through
processes such as self-assembly or filtration. These nanonets, comprising intercon-
nected nanowires, possess unique electrical, optical, and mechanical characteristics
rendering them valuable for a wide range of advanced technologies and applications
(Arjmand et al. 2022).

Synthesis of SiNWs

The production of silicon nanowires (SiNWs) is a highly precise procedure that relies
on the vapor–liquid–solid (VLS) mechanism originally conceptualized by Wagner
and Ellis. Gold was selected as the catalyst due to its capacity to create a low-
temperature eutectic phase with silicon which promotes the growth of SiNWs. This
growth process involved the utilization of silane (SiH4 ) as the silicon precursor gas
and phosphine (PH3 ) as the dopant allowing for the achievement of n-type properties
within the silicon nanowires (Mao et al. 2005). To maintain the utmost precision
during the growth process, hydrogen chloride (HCl) was introduced. Its role was
critical in preventing the diffusion of gold and lateral growth, guaranteeing the desired
development of SiNWs. These growth procedures were executed on <111> silicon
substrates, maintained at an exact temperature of 650 °C. The growth process was
initiated after a dewetting step involving a 2 nm-thick gold film which was carried
out at 800 °C. This meticulous control over the growth conditions ensured that the
diameters of the silicon nanowires were finely tuned to align with the size of the
catalyst used in the process (Oehler et al. 2009). This synthesis method signifies
a noteworthy milestone in nanotechnology providing meticulous control over the
dimensions and properties of SiNWs. These silicon nanowires exhibit tremendous
potential across a spectrum of applications spanning from cutting-edge transistors to
nanoscale sensors. Their successful synthesis unlocks a multitude of opportunities in
the realm of nanoelectronics and extends into broader horizons (Wang et al. 2014).
2 Nanowire-Based Si-CMOS Devices 53

2D Si Nanonet Assembly

The fabrication of 2D Si nanonets was accomplished through the utilization of the

vacuum filtration technique. In the initial stages, SiNWs were dispersed within deion-
ized water via ultrasonication, a process that lasted for 5 min. The concentration of
the solution was then adjusted to achieve an absorbance of 0.06 at 400 nm ensuring
a consistent content of nanowires. Subsequently, the diluted SiNW solution was
subjected to filtration through a 0.1 μm porous nitrocellulose membrane. During this
filtration process, the nanowires were captured and formed an interconnected 2D Si
nanonet structure offering versatility for applications across various fields (Arjmand
et al. 2022). The thickness and density of the resulting nanonets were adjusted by
filtering varying volumes of the SiNW solution ranging from 0 to 320 mL (Oehler
et al. 2009). Following this, the nanonets were transferred onto a Si substrate coated
with Si3 N4 (200 nm) by dissolving the nitrocellulose membrane using acetone. This
carefully controlled process resulted in the formation of 2D Si nanonets comprising
degenerated n-type silicon nanowires promising distinct properties and high repro-
ducibility for a wide range of applications in diverse fields. In summary, this synthesis
and assembly approach enables the precise fabrication of 2D Si nanonets consisting
of degenerated n-type silicon nanowires offering significant potential for applica-
tions across various domains due to their unique characteristics and reproducibility
(Wagner and Ellis 1964; Shao et al. 2010; Potié et al. 2011). Figure 2.11 provides
schematic representations (a and b) and colorized scanning electron microscopy
(SEM) top-view images (c and d) of the engineered electrical test structure featuring
the Si nanonet. The nanonet was meticulously transferred onto a silicon substrate with
a 200 nm insulating silicon nitride layer. Metallic contacts exhibiting a diameter of
200 μm and composed of Ni (120 nm), Al (180 nm), and Au (50 nm) were deposited
onto the substrate through electron beam evaporation. This deposition was carried
out using a shadow mask with a 50 μm pad pitch. Figure 2.11 offers a comprehen-
sive depiction of the processed electrical test structure, presenting both its design and
physical characteristics through schematics and SEM images. This structure plays a
pivotal role in testing and assessing the performance of the Si nanonet-based device.
The native oxide shell issue in silicon nanonets (SiNNs) has been effectively
tackled through inventive methods including patented sintering of junctions. This
development has rendered SiNNs highly resistant to oxidation. Consequently, elec-
tronic devices such as thin-film transistors (TFTs) can now be produced with
SiNNs. These devices offer notable advantages such as mechanical flexibility, optical
transparency, and the capability for solution-based room-temperature processing.
Furthermore, silicon-based nanonets exhibit superior stability in comparison with
organic semiconductors when exposed to oxygen, humidity, and UV radiations.
This enhanced stability enhances their applicability across various domains and use
cases (Arjmand et al. 2022). “Nanonets”, scientifically referred to as nanostruc-
tured networks, harness the distinctive properties of their building blocks such as
nanowires (NWs) or nanotubes combined with their structural characteristics. These
networks offer several advantages including an increased surface area that enhances
probe immobilization and reduces steric hindrance. Their optical complexity helps
54 R. K. Mishra et al.

Fig. 2.11 Schematics a and b illustrate the design and layout of the electrical test structure based
on the Si nanonet. This layout includes the placement of metallic contacts and the nanonet on the
insulating silicon nitride layer. Colorized SEM top-view images c and d provide a visual represen-
tation of the actual fabricated electrical test structure. These images show the physical arrangement
of the Si nanonet and the metallic contacts, offering a closer look at the device’s structure and layout
(Serre et al. 2015a)

to mitigate the reduction in efficiency of fluorophores. Nanonets can be fabricated

using various techniques including direct growth or self-assembly from solutions.
In this particular study, the vacuum filtration method was employed allowing for
cost-effective production of uniform nanonets with precise control over NW density.
This control spans from sub-monolayer coverage to thicknesses exceeding 1 μm
making it a versatile choice for a wide range of applications (Serre et al. 2015b).
The synthesis of silicon nanowires (SiNWs) involves the vapor–liquid–solid (VLS)
mechanism utilizing gold as a catalyst. Silane (SiH4 ) serves as the silicon precursor,
and phosphine (PH3 ) acts as the dopant to impart n-type characteristics. Hydrogen
chloride (HCl) is introduced to inhibit lateral growth. The resulting SiNWs have
lengths of approximately 10 μm and diameters ranging from 70 to 100 nm. These
SiNWs are subsequently assembled into 2D Si nanonets through vacuum filtration,
a process that allows precise control over the nanonet’s thickness and density. The
resulting nanonets exhibit coherency, well-interconnected structures, and random
orientation. SEM image analysis confirms their homogeneity and reproducibility.
These Si nanonets display nonlinear symmetric current–voltage (I-V) character-
istics, characteristic of Schottky behavior. The electrical conduction mechanisms
involve Schottky junctions and NW-NW junctions which have been explored in this
study. Importantly, these Si nanonets are above the percolation threshold enabling
electrical conduction (Serre et al. 2015a). Figure 2.12 provides a comprehensive
2 Nanowire-Based Si-CMOS Devices 55

visual representation of the Si nanonet including its morphology, structural details,

coverage area, and density in relation to the filtered volume of the SiNW solution.
Figure 2.12a presents a scanning electron microscope (SEM) image of the Si nanonet
offering a detailed view of the network structure formed by silicon anowires (SiNWs)
on the substrate. This image visually conveys the arrangement and morphology of
SiNWs within the nanonet. Figure 2.12b illustrates a schematic representation of
the two-dimensional (2D) nanonet composed of SiNWs. It labels various parameters
such as L for nanostructure length, D for nanostructure diameter, S for the projected
surface area of a nanostructure, and J for surface overlap when two SiNWs intersect
within the network. This schematic aids in understanding the structural intricacies
of the nanonet. Figure 2.12c demonstrates how the coverage area of SiNWs changes
concerning the filtered volume of the SiNW solution. The coverage area is deter-
mined through image analysis of SEM images often using software like ImageJ. The
error bars in this graph represent the variability in SiNW coverage observed from
one image to another at a specific location on the nanonet. Figure 2.12d provides
a graphical representation of the SiNW density as a function of the filtered volume
of the SiNW solution. The density calculation relies on the coverage area data, and
extrapolation is applied when the coverage area reaches saturation typically at around
100%. This graph provides insights into how the SiNW density varies with changes in
the filtered volume helping to understand the relationship between these parameters
(Serre et al. 2015a). These figures collectively provide a comprehensive and multi-
faceted understanding of the fabrication and morphological properties of Si nanonets.
The SEM image visually represents the nanonet’s intricate structure allowing for
direct observation of its morphology. Meanwhile, the schematic diagram and graphs
offer quantitative information shedding light on critical aspects such as coverage
area, density, and the relationship between these parameters. Together, these visual
representations contribute to a thorough characterization of the Si nanonet aiding in
both qualitative and quantitative analysis of its properties and potential applications.
Si nanonet fabrication is a cutting-edge process that leverages the self-assembly of
block copolymers to create precise silicon nanowires (SiNWs). This method involves
the formation of ordered nanowire patterns through controlled heating, followed by
etching resulting in Si nanonets with increased surface area and complex optical
properties. Various techniques including direct growth and self-assembly can be
employed for fabrication with vacuum filtration being a cost-effective and versatile
option. Si nanonets hold a great potential for a wide range of applications especially
in large-scale manufacturing and are driving advancements in the semiconductor
industry through ongoing research and development aimed at improving precision
and versatility. The fabrication process of Si nanonets consists of three key steps:
coating the substrate with block copolymer inducing self-assembly into nanowire
patterns through heating and finally etching to create silicon nanowires. This method
offers precise control over nanowire dimensions and patterns making it versatile
for various applications. It represents a promising approach for silicon nanowire
fabrication with the potential to impact the semiconductor industry and other fields.
Nanonets composed of randomly oriented nanowires offer advantages in terms of
handling and integration. Their electrical properties are influenced by percolation
56 R. K. Mishra et al.

Fig. 2.12 a SEM image of a Si nanonet obtained from 45 mL of SiNW solution, b schematic of a
2D nanonet illustrating dimensions and surface features, and c SiNW coverage area versus filtered
volume, determined from SEM images using ImageJ software. Error bars represent image-to-image
variability, d Si NW density vs. filtered volume calculated from coverage area with extrapolation
when saturation occurred (Serre et al. 2015a)

theory with SiNWs and NW/NW junctions forming conducting paths. Low thermal
annealing can stabilize long-channel Si nanonet resistors expanding their applica-
tions to field-effect transistors. Precise control of integration and silicidation is crucial
for reliable device manufacturing promising significant advancements in the semi-
conductor industry as shown in Fig. 2.13 (Legallais et al. 2018). Si nanonet fabri-
cation provides advantages in terms of high throughput and cost-effectiveness for
producing silicon nanowires on a large scale. However, it may not offer the same
level of precision as some other fabrication techniques, and the careful selection of
block copolymers is essential for successful results. Ongoing research efforts are
focused on improving Si nanonet fabrication making it a promising material for
various applications especially in situations where scalability and cost-effectiveness
are critical. Si nanonets are essentially 2D networks composed of silicon nanowires,
and they are formed through the self-assembly of block copolymers on a substrate
that is heated above the copolymers’ melting point.
2 Nanowire-Based Si-CMOS Devices 57

Fig. 2.13 Si nanonet hierarchical fabrication process for silicon nanowire fabrication

Advantages of Si Nanonets

Si nanonets in conjunction with Si nanowires are positioned to be catalysts for

advancements in electronics, optoelectronics, and various other domains. Their
substantial surface area bolsters their utility in catalytic and sensing applications
by facilitating enhanced interactions between reactants and analytes. As research
continues to evolve, Si nanonets offer the potential for innovative, high-performance
devices that can effectively tackle contemporary challenges and make significant
contributions to technological progress (Ye and Qi 2011). Si nanonets indeed exhibit
enhanced electrical conductivity making them valuable for electronics and sensor
applications where efficient charge transport is crucial. Furthermore, their robust
2D structure enhances mechanical durability reducing the risk of mechanical failure
which is essential for various practical applications. The versatility in fabrication
techniques allows for tailoring Si nanonets to specific requirements further expanding
their potential applications in diverse fields (Liao et al. 2023). The extensive surface
area of Si nanonets makes them highly attractive for various applications including
fuel cells and hydrogen generation where active sites are crucial for catalytic reac-
tions. Additionally, their capabilities in chemical and biological sensing have the
potential to revolutionize sensor technology offering improved sensitivity and perfor-
mance. Si nanonets’ enhanced electrical properties make them valuable for transis-
tors and energy-efficient electronic devices which can contribute to advancements in
58 R. K. Mishra et al.

electronic component development. Their versatility and potential in these diverse

fields highlight their importance in driving innovation and addressing contemporary
challenges (Ivars-Barceló et al. 2018). Table 2.1 offers a comprehensive summary
of Si nanonets highlighting their advantages, applications, assembly techniques, and
key features. It underscores their potential in catalysis, sensing, and electronics due
to their unique properties such as a high surface area and mechanical robustness.
The various assembly methods provide flexibility for tailoring Si nanonets to suit
diverse applications. The remarks section acknowledges their significance in catal-
ysis and sensing, electronic potential, and durability while also recognizing ongoing
challenges and hinting at future prospects in energy storage, photonics, and biotech-
nology. This table effectively showcases the versatility of Si nanonets and their role
in advancing technology across various fields.

Table 2.1 Comprehensive advantages and applications of Si nanonets and their potential in the
future of technology and research
Advantages of Applications Assembly Remarks Reference
Si nanonets techniques
High surface Catalysis Layer-by-layer Si nanonets enhance Gao et al.
area assembly catalytic efficiency (2019)
Fuel cells, Precise control over Si nanonets offer Xu et al.
hydrogen thickness and high (2021)
generation orientation surface-to-volume
ratio
Environmental Complex and Abundant active Robert and
remediation customizable sites improve device Nallathambi
devices performance (2020)
Enhanced Sensing Template-assisted Si nanonets improve Jeong et al.
electrical growth charge transport (2020)
conductivity Chemical and Scalability and Si nanonets enable Yang et al.
biological potential for mass efficient sensors (2017)
sensing production
High sensitivity Template removal Si nanonets enhance Lin et al.
and specificity may be challenging electronic device (2011)
efficiency
Improved Electronics Chemical vapor Si nanonets exhibit Liang et al.
mechanical deposition (CVD) unique mechanical (2014)
properties on templates properties
Energy-saving Compatible with Si nanonets have Serre et al.
electronic existing potential for durable (2015b)
devices semiconductor applications
processes
Transistors and Growth of Si Si nanonets offer Kayaharman
electronic nanowires directly increased durability et al. (2017)
components on templates and reliability
2 Nanowire-Based Si-CMOS Devices 59

Assembly Techniques for Si Nanonets with Si NWs

The integration of Si nanonets with Si nanowires (Si NWs) is a crucial step in

harnessing the potential of these nanostructures and creating advanced devices with
enhanced capabilities. Si nanonets known for their high surface area and unique
2D structure offer significant advantages in fields such as catalysis, sensing, and
electronics. When combined with Si nanowires which provide superior electrical
conductivity and mechanical strength, the resulting hybrid structures hold immense
potential for technological advancements. Various assembly techniques including
direct bonding, interfacial bonding, and van der Waals bonding have been employed
to seamlessly integrate Si nanonets with Si NWs enabling innovative applications
across different domains (Kato et al. 2019). The choice of assembly technique for
Si nanonets with Si nanowires (Si NWs) is a critical factor that impacts the mechan-
ical strength, electronic performance, and overall efficiency of the resulting devices.
Careful selection of the most suitable assembly method and optimization of process
parameters are essential steps for maximizing the potential of Si nanonet-Si NW
hybrid structures. This meticulous approach empowers researchers and engineers to
explore and develop innovative applications in various domains including sensing,
energy harvesting, optoelectronics, and more. The versatility of these hybrid struc-
tures holds promise for addressing a wide range of technological challenges and
advancing the field of nanotechnology (Heo et al. 2008).

Direct Bonding

Direct bonding is a technique that physically connects Si nanonets and Si nanowires

(Si NWs) through high-temperature bonding typically at 800–1000 °C. This method
creates strong bonds by allowing atoms on their surfaces to diffuse. While direct
bonding offers a straightforward and clean interface without the need for additional
agents achieving high bond strength can be challenging especially for structures with
differing dimensions or surface properties. Precise temperature and pressure control
is crucial to ensure successful bonding without material damage or introduction of
strain or defects. This technique holds potential for various applications, provided
optimization is carefully executed (Schmidt et al. 2009).

Interfacial Bonding

Interfacial bonding involves the use of a bonding agent such as silane, between
Si nanonets and Si nanowires (Si NWs), followed by heating to facilitate strong
bonding at the interface. This intermediary layer enhances adhesion between the
nanonets and nanowires. Interfacial bonding offers advantages over direct bonding
especially for structures with different dimensions or surface properties providing a
reliable and adaptable method for creating robust connections between Si nanonets
and Si NWs enhancing their potential in various applications (Rao et al. 2018).
60 R. K. Mishra et al.

Interfacial bonding facilitated by a bonding agent enhances bond strength for a more
reliable connection between Si nanonets and Si NWs. It ensures a well-controlled
and uniform interface reducing the risk of interface defects that could impact device
performance. This method offers improved structural integrity and performance in
devices that combine these nanostructures (Arjmand et al. 2022). Interfacial bonding
which is more complex than direct bonding requires precise control of bonding
agent deposition and heating parameters for consistent results. Controlling bonding
agent thickness and uniformity is critical to prevent delamination or excessive strain
ensuring structural integrity. With careful optimization, this method holds promise for
creating high-performance nanocomposite materials and devices tailored for diverse
applications (Ferraris 2009).

Van Der Waals Bonding

Van der Waals bonding relies on weak attractive forces between Si nanonets and
Si NWs requiring no high temperatures or bonding agents. This simple and cost-
effective process offers practical integration of nanostructures making it easily acces-
sible for diverse applications (Rance et al. 2010). Van der Waals bonding allows
complex hybrid structures with different crystal orientations but offers relatively
weak bond strength. Additional reinforcement may be needed for high-stress appli-
cations, yet it remains attractive for simpler applications where cost-effectiveness
and simplicity are key (Liu and Speranza 2019).

Si Nanonet Morphology and Properties

Si nanonets, 2D networks of SiNWs offer versatile applications through self-

assembly using block copolymers. Precise control of nanowire diameter is achieved
by selecting suitable copolymers and optimizing conditions. This innovative fabri-
cation process capitalizes on unique morphology and properties for diverse techno-
logical advancements (Serre et al. 2015b). Controlling nanowire diameter, length,
and density in Si nanonets is pivotal for tuning electrical and mechanical properties.
Deposition parameters like time and temperature affect nanowire length, surface
area, and conductivity. Precise regulation of nanowire density through deposition
rate and temperature influences device efficiency. Nanowire diameters ranging from
20 to 100 nm provide versatility for tailored applications (Kato et al. 2019). Control-
ling Si nanowire length from 100 to 1000 nm offers adaptable aspect ratios for
diverse applications. Precise nanowire density control within the range of 104 –
108 nanowires/cm2 fine-tunes the active surface area of Si nanonets optimizing their
performance for specific needs. This versatility in length and density customization
enhances nanonet properties for various applications (Mayer et al. 2015). The ability
to control nanowire density in Si nanonets is critical for applications like catalysis
and sensing where surface area directly impacts performance. Si nanonets with their
exceptional properties and up to 1000 times larger surface area compared to bulk
2 Nanowire-Based Si-CMOS Devices 61

silicon excel in catalytic and sensing applications. This increased surface area offers
abundant active sites improving catalytic efficiency and sensitivity in sensing devices
(Bergin et al. 2012). Furthermore, Si nanonets exhibit significantly improved elec-
trical conductivity up to 100 times greater than that of bulk silicon making them
highly suitable for advanced electronic devices such as transistors and sensors. This
enhanced electrical property arises from their unique 2D network structure which
facilitates efficient charge transport. Additionally, the network-like configuration
imparts enhanced mechanical strength to Si nanonets rendering them well-suited
for demanding mechanical applications requiring durable and dependable materials.
Figure 2.14 presents various scales of a nanonet’s morphology: Fig. 2.14a depicts a
nanonet with a density of 10.8 × 107 nanowires per square centimeter (NWs/cm2 )
created using 46 mL of filtered volume and transferred onto a Si/Si3 N4 substrate
with a closer view provided by scanning electron microscopy (SEM). Figure 2.14b
offers a high-resolution transmission electron microscopy (HRTEM) image illus-
trating the interface between two nanowires, NW 1 and NW 2 in the absence of a
sintering process. Here, green represents crystalline silicon (Si), and red represents
amorphous silicon dioxide (SiO2 ) indicating the presence of SiO2 at the interface.
Finally, (c) presents another HRTEM image of the interface between two different
nanowires, NW 3 and NW 4, post sintering. This process has led to the formation of
an 11 nm-wide neck between the two nanowires, NW 3 and NW 4, with a diameter
of approximately 100 nm. NW 1 and NW 4 appear to be cut along their axes while
NW 2 and NW 3 are observed in cross-section (Nguyen et al. 2019).
Figure 2.15 illustrates the optical and mechanical characteristics of Si nanonets
with three distinct sections labeled as (a), (b), and (c) to highlight different aspects
of the material. In Fig. 2.15a, it showcases the material’s flexibility demonstrating
its ability to bend and deform without fracturing. This property is crucial for poten-
tial applications requiring flexible electronic devices. Transitioning to Fig. 2.15b,
the figure emphasizes the uniformity and consistency of the nanonets across three
different nanonet (NN) densities. This visual representation underscores the even
distribution of nanowires throughout the material highlighting its uniform struc-
ture. In Fig. 2.15c, the figure explores the optical transparency of Si nanonets
through optical transmittance measurements. As expected, transmittance decreases as
nanonet density increases. This decline in transmittance is linked to reduced porosity
as nanonet density rises. Specifically, with a nanonet density of 10.8 × 107 nanowires
per square centimeter (NWs/cm2 ), a transmittance of 70% is achieved in the visible
wavelength range, specifically at 550 nm (Nguyen et al. 2019).
The electrical properties of Si nanonets with a consistent density of 27 × 106 NWs/
cm2 are highly reproducible with I-V curves showing symmetric nonlinear behavior
and fluctuations within ± 18%. This reproducibility indicates consistent electrical
behavior among nanonets with similar characteristics. The observed rectifying
response in I-V curves is attributed to back-to-back Schottky contacts primarily
at metal-nanowire junctions. Conduction mechanisms involve Schottky interface
junctions, surface conduction along nanowire sidewalls mediated by gold (Au),
and conduction through the nanowires themselves. NW-NW junctions play a role
in conduction, but the nanonets’ intrinsic conductance is not limited by nanowire
62 R. K. Mishra et al.

Fig. 2.14 Illustrates the nanonet morphology at different scales ranging from macro to nano.
a Depicts a nanonet with a density of 10.8 × 107 nanowires per square centimeter (NWs/cm2 ),
fabricated using 46 mL of filtered volume on a nitrocellulose membrane and subsequently trans-
ferred onto a Si/Si3 N4 substrate. A closer view of the nanonet’s morphology is captured using scan-
ning electron microscopy (SEM). b Presents a high-resolution transmission electron microscopy
(HRTEM) image of the interface between NW 1 and NW 2 without the sintering process. To enhance
clarity, crystalline Si is represented in green while amorphous SiO2 is depicted in red highlighting
the presence of SiO2 at the interface. c Displays another HRTEM image of the interface between
NW 3 and NW 4 after applying the sintering process. In this case, an 11 nm-wide neck has formed
between the two nanowires, NW 3 and NW 4, with a diameter of approximately 100 nm. NW1
and NW4 appear to be sectioned along their axes while NW2 and NW3 are seen in cross-section
(Nguyen et al. 2019)

conduction. Conductance varies with SiNW density showing distinct regimes: OFF-
state at very low densities, percolation behavior in the intermediate range (13 × 106
to 35 × 106 NW/cm2 ), and near-linear behavior at high densities (> 35 × 106 NW/
cm2 ). This transition from OFF-state to bulk-like behavior in Si nanonets is a novel
observation consistent with percolation theory (Serre et al. 2015a). The electrical
properties of Si nanonets are influenced by storage atmosphere and time. In nitrogen,
nanonets remain stable but in air, conductance exponentially decreases with a 2.2-
day decay attributed to oxidation. HF vapor exposure restores properties. SiNWs
with a diameter around 100 nm exhibit slower oxidation due to nanonet structure
with conductance decay related to oxide thickness at NW-NW junctions and elec-
tron tunneling. Protecting Si nanonets from oxidation is crucial. Working under
2 Nanowire-Based Si-CMOS Devices 63

Fig. 2.15 Optical and mechanical characteristics of Si nanonets, picture of nanonet: a on plastic
substrate (PET); b on glass (three different densities); c the transmittance of SiNN with the three
densities, the transmittance of the substrate (bare glass) (Mayer et al. 2015; Nguyen et al. 2019)

inert atmospheres or using encapsulation layers is recommended. Passivation treat-

ments are explored for stable properties with sensing functionality. Annealing metal
contacts under nitrogen at 400 °C enhances electron transport across Schottky barriers
improving current response and creating reproducible metal–semiconductor inter-
faces without achieving ohmic contact due to oxide junctions and surface states (Serre
et al. 2015a). In summary, Si nanonets possess unique properties including customiz-
able nanowire dimensions, high surface area, enhanced electrical conductivity and
mechanical strength which make them highly versatile materials with applications in
catalysis, sensing, electronics and beyond. Ongoing research continues to explore and
expand their potential in various technological domains opening up numerous possi-
bilities for customizing nanoscale materials and pushing the boundaries of science
and technology.

Doping of Silicon Nanowires

Doping silicon nanowires is a crucial and versatile process that allows for the precise
tuning of their electronic properties. This technique involves introducing specific
impurities known as dopants into the silicon crystal structure during the nanowire
fabrication process. Doping provides control over nanowire conductivity and carrier
concentration making it essential for tailoring nanowires to suit a wide range of
applications in the field of nanoelectronics and beyond (Wallentin and Borgström
2011). Doping silicon nanowires plays a critical role in the creation of functional
electronic devices such as transistors by optimizing the types and concentrations of
charge carriers. This process is essential for advancing nanoelectronics and fostering
innovation in the field. Doping can be categorized into two main types: p-type and
n-type depending on whether dopant atoms with fewer or more valence electrons
than silicon are introduced. For example, boron is a commonly used p-type dopant
64 R. K. Mishra et al.

for silicon nanowires enabling the customization of electronic properties to meet

specific device requirements (Akbari-Saatlu et al. 2020). Doping silicon nanowires
with boron introduces positively charged holes into the material which can signifi-
cantly impact its electrical properties. This p-type doping is valuable for various elec-
tronic applications where positive charge carriers are required. Conversely, n-type
doping with elements like phosphorus introduces negatively charged electrons into
silicon nanowires. This is essential for devices that rely on negative charge carriers.
The concentration of dopants in silicon nanowires plays a crucial role in defining their
electronic behavior and can be tailored to suit specific device requirements (Pi 2012).
Precise control of the doping process in silicon nanowires is essential for achieving
tailored carrier concentrations. This level of control directly influences the electrical
properties of the nanowires including conductivity and carrier mobility. By carefully
adjusting the dopant concentration, researchers and engineers can fine-tune the elec-
tronic characteristics of silicon nanowires to meet the specific needs of various appli-
cations in nanoelectronics and beyond (Ohmagari et al. 2018). Various techniques
including in-situ doping provides precise control over the doping process in silicon
nanowires. In-situ doping involves introducing dopant atoms into the nanowires
during the growth process typically using methods like chemical vapor deposition
(CVD). This level of control allows researchers and engineers to customize the elec-
tronic properties of silicon nanowires enhancing their versatility for a wide range
of nanoelectronic devices and applications (Wallentin and Borgström 2011). In-situ
doping, ion implantation and diffusion doping each have their advantages and are
suitable for different scenarios. In-situ doping offers precise control and uniformity
in dopant distribution during the growth process making it ideal for large-scale arrays
and applications where uniformity is critical. Ion implantation provides control over
dopant concentration, but it can introduce lattice damage. Annealing is often required
to repair the lattice structure which can be a drawback in some cases. Diffusion doping
is a simpler and compatible method with conventional semiconductor processes. It
does not disrupt the lattice structure which is an advantage. This makes it suitable for
silicon nanowires and semiconductor manufacturing. The choice of doping technique
depends on the specific requirements of the nanowire application and the trade-offs
between control, uniformity and potential lattice damage. Researchers select the most
suitable method based on these factors to achieve the desired electronic properties
in silicon nanowires (Barri et al. 2021). Doping plays a pivotal role in optimizing
the performance of field-effect transistors (FETs) which are fundamental compo-
nents of electronic devices. By carefully controlling the doping levels in silicon
nanowires used in FETs, researchers and engineers can fine-tune key parameters like
charge carrier type (n-type or p-type), carrier mobility, and switching behavior. This
level of control allows for the customization of FETs to meet the specific require-
ments of various electronic applications from digital logic circuits to analog ampli-
fiers and beyond. It highlights the importance of doping as a fundamental tech-
nique in nanoelectronics and semiconductor device engineering (Zafar et al. 2018).
Doping is a versatile tool in tailoring the performance of nanowire-based sensors
and photodetectors. In gas sensing and biosensing applications, precise control of
dopant concentration can enhance the sensitivity and selectivity of the sensors. By
2 Nanowire-Based Si-CMOS Devices 65

carefully choosing the type and level of dopants, nanowire sensors can be designed
to respond selectively to specific analytes improving their accuracy and reliability. In
photodetectors, doping can influence the absorption properties of nanowires enabling
them to efficiently convert light into electrical signals. This is particularly important
for high-performance photodetectors used in imaging and communication systems.
By optimizing the dopant concentration, engineers can enhance the responsiveness
and efficiency of photodetectors leading to improved image quality and faster data
transmission rates (Sha et al. 2022). In conclusion, doping of silicon nanowires is
a powerful technique that allows for precise control of their electronic properties
making them versatile building blocks for various electronic devices. By tailoring
the doping type and concentration, researchers and engineers can unlock the full
potential of nanowire-based Si-CMOS devices paving the way for enhanced perfor-
mance, reduced power consumption, and the exploration of new applications in the
semiconductor industry. Doping is a pivotal tool in the advancement of nanoelec-
tronics and holds great promise in revolutionizing the landscape of electronic devices
and technology. Its versatility and significance in nanowire-based applications make
it an indispensable aspect of modern semiconductor research and development.

Si Nanowires in CMOS Devices

Silicon nanowires (NWs) hold great promise in advancing logic complementary

metal–oxide–semiconductor (CMOS) devices and exploring the potential of quantum
computing. Their unique properties at the nanoscale including enhanced carrier
transport and tunneling effects make them valuable candidates for future electronic
applications. Quantum simulations are essential tools for gaining a deep under-
standing of the electronic behavior of silicon nanowires particularly in the context
of carrier transport and tunneling phenomena. These simulations provide insights
into how nanowires operate at quantum scales helping researchers to optimize their
performance for specific applications. Electrical characterization plays a crucial
role in assessing the performance of nanowire transistors. It allows researchers to
measure key parameters such as current–voltage characteristics, threshold voltage,
and switching behavior. This information is vital for optimizing the design and oper-
ation of nanowire transistors ultimately contributing to the development of more
efficient and powerful electronic devices. As quantum computing and nanoelec-
tronics continue to evolve, silicon nanowires are likely to play a significant role
in pushing the boundaries of what is possible in terms of computing power and
device miniaturization. Ongoing research and development in this field will pave
the way for innovative technologies with applications in various domains (Ternon
et al. 2015). Silicon nanowires (NWs) do indeed offer promising opportunities in
the development of CMOS memories especially in the realm of resistive random-
access memory (RRAM) due to their unique properties. However, integrating NWs
into CMOS technologies whether in the front-end-of-line (FEOL) or back-end-of-
line (BEOL) processes presents a set of challenges that require innovative solutions.
66 R. K. Mishra et al.

Some of the integration challenges that researchers and engineers are addressing
include: (a) Ensuring that silicon nanowires can be seamlessly integrated with the
existing materials used in CMOS processes without causing compatibility issues, (b)
Developing reliable and scalable fabrication techniques for creating silicon nanowires
in a controlled and cost-effective manner, (c) Achieving uniformity in nanowire
dimensions, doping levels and properties across large-scale integration to ensure
consistent device performance, (d) Ensuring the long-term reliability of devices
incorporating silicon nanowires as well as understanding the impact of aging and
environmental factors, (e) Addressing the scaling challenges associated with inte-
grating nanowires into CMOS technologies as smaller feature sizes become more
prevalent, (f) Determining the best ways to incorporate silicon nanowires into CMOS
memory architectures and optimizing their performance within these structures. As
these integration hurdles are overcome through ongoing research and development,
silicon nanowires have the potential to revolutionize logic CMOS devices. They can
enhance device performance, enable novel memory technologies like RRAM, and
contribute to the development of disruptive device technologies that push the bound-
aries of what is possible in the field of semiconductor technology (Zahoor et al.
2023). Silicon nanowires (NWs) hold great promise for revolutionizing logic comple-
mentary metal–oxide–semiconductor (CMOS) devices. Their exceptional properties
open up various potential applications in different aspects of logic CMOS devices:
(a) Silicon nanowires can be used as the channel material in field-effect transis-
tors (FETs). Their high surface area and improved electrical conductivity enable
the fabrication of highly efficient and compact transistors. Moreover, the precise
doping capabilities of NWs allow for customizing the electrical characteristics of
these transistors making them suitable for a wide range of applications, (b) Silicon
nanowires can play a role in enhancing the performance of CMOS memory devices.
They can be integrated into novel memory architectures such as resistive random-
access memory (RRAM) to improve data storage and retrieval efficiency, and (c)
Silicon nanowires are highly sensitive to changes in their environment. This sensi-
tivity makes them valuable for use in sensors integrated into CMOS devices. They
can be employed in various sensor types including gas sensors, biosensors, and envi-
ronmental sensors to detect and respond to specific stimuli with high precision, (d)
The improved electrical conductivity of silicon nanowires makes them suitable for
use as interconnects in CMOS devices. They can facilitate faster and more efficient
data transfer between components reducing signal propagation delays and improving
overall device performance, (e) Silicon nanowires exhibit excellent light-absorption
properties making them ideal candidates for photodetectors integrated into CMOS
devices. These photodetectors can find applications in imaging, communication,
and optical sensing, (f) The unique electronic behavior of silicon nanowires at the
nanoscale makes them valuable for exploring quantum phenomena. Researchers are
investigating their potential use in quantum devices for future quantum computing
applications, (g) Silicon nanowires can contribute to the development of energy-
efficient CMOS devices. Their high surface area allows for efficient transport which
can lead to reduced power consumption in electronic circuits, (h) Silicon nanowires
2 Nanowire-Based Si-CMOS Devices 67

can be integrated into logic gates enabling the creation of more compact and energy-
efficient logic circuits. These gates can be tailored to specific applications enhancing
the overall functionality of CMOS devices, (i) Silicon nanowires can be incorporated
into nanoelectromechanical systems (NEMS) devices for various purposes including
sensing, actuation, and signal processing. In summary, silicon nanowires offer a
wide range of potential applications in logic CMOS devices driven by their unique
properties and versatile characteristics. Ongoing research and development efforts
continue to explore and unlock the full potential of these nanowires paving the way
for innovative and high-performance electronic devices in the future.

Quantum Simulation and Electrical Characterization of NWs

Quantum simulations of nanowires (NWs) are essential for comprehending the elec-
tronic behavior in the context of shrinking complementary metal–oxide–semicon-
ductor (CMOS) device dimensions where quantum effects become prominent. NWs
with their quasi-one-dimensional (quasi-1D) characteristics provide a unique plat-
form for exploring and leveraging these quantum phenomena. This computational
approach is crucial for advancing our understanding of NWs in nanoelectronics (Yang
et al. 2010). Nanowires characterized by their small diameters and varying lengths
showcase distinctive quantum behaviors such as quantum confinement, tunneling,
and discrete energy levels. These quantum effects absent in bulk materials profoundly
influence the electronic and transport characteristics of nanowires. Understanding
and harnessing these phenomena are vital for advancing nanowire-based nanoelec-
tronics (Mohammad 2014). Quantum confinement in nanowires arises when the
wire’s diameter approaches the de Broglie wavelength of electrons causing energy
levels to become quantized along the wire’s length. As nanowire diameter decreases,
energy levels become discrete altering the electronic band structure and giving rise to
sub-band structures. Understanding this phenomenon is crucial for tailoring nanowire
properties in nanoelectronics and quantum devices (Mohammad 2014). Quantum
tunneling in nanowires enables electrons to traverse energy barriers leading to
phenomena like resonant tunneling and tunnel field-effect transistors (TFETs). This
understanding is pivotal for optimizing nanowire-based devices. Quantum simula-
tions involving the Schrödinger equation provide a computational approach to study
particle behavior in these quantum effects aiding in device design and performance
enhancement (Esseni et al. 2017). Quantum simulations offer insights into nanowire
electronic properties and behavior aiding in predicting their response to varying
conditions. These simulations model charge carrier movement in nanowires under
electric fields crucial for optimizing transistor performance. They also elucidate elec-
tron tunneling behavior and predict tunneling current in diverse scenarios (Konar et al.
2015). Quantum simulations aid in designing efficient tunneling devices by uncov-
ering the impact of quantum confinement on nanowire energy levels and electronic
properties. This understanding has practical applications in nanoelectronics espe-
cially in optimizing CMOS transistor design for enhanced performance and energy
68 R. K. Mishra et al.

efficiency. Insights from quantum simulations enable precise control of quantum

effects in nanowires (Taha et al. 2022). Quantum properties of nanowires hold poten-
tial for quantum transistors, qubits in quantum computing, and sensitive sensors in
future computing applications. Quantum simulations help researchers to comprehend
these effects crucial for advancing nanoelectronics and creating innovative quantum
devices. Understanding intricate quantum phenomena at the nanoscale is essential
for technological progress (Laucht et al. 2021).

Nanowire-Based Si-CMOS Memories

Data storage devices are categorized into volatile and nonvolatile memories. Volatile
memories like SRAM and DRAM require continuous power to retain data while
nonvolatile memories like Flash can store data without power. DRAM uses one
transistor and one capacitor making it cost-effective but slower. SRAM is fast but
expensive due to its six-transistor structure. Flash memory, the youngest of the three,
stores data without power but is slower than SRAM and DRAM. Each has advantages
and trade-offs in terms of cost, speed, and power consumption (Bez et al. 2003). The
nonvolatile memory market encompasses various sectors including consumer elec-
tronics, automotive, computing, and communication. Figure 2.16 demonstrates the
substantial increase in NVSM memory use notably in digital cellular phone produc-
tion since 1990. The demand for flexible and transparent electronics especially for
affordable wearables has spurred research in flexible technology while silicon-based
semiconductor memories have been crucial in consumer electronics. There is a shift
toward soft nonvolatile memory for cost-effective, large-area, and energy-efficient
flexible applications. Despite market fluctuations, long-term growth is expected
driven by innovation, transparency, flexibility, and 3-D technologies. Nanowires are
advantageous for CMOS memories due to their unique properties including a high
surface area and customizable electrical traits. One promising application is resistive
random-access memory (RRAM) which has the potential to transform data storage
by offering enhanced performance and efficiency. The impact of these memory tech-
nologies could lead to significant advancements in data storage solutions (Meena
et al. 2014). RRAM employs resistive switching in tiny conductive filaments for data
storage. Nanowires are ideal for RRAM due to their small size enabling compact
memory cells and reduced power usage. This technology offers the potential for
greater memory density and efficiency compared to traditional memory solutions
(Meena et al. 2014). This aligns with the increasing need for energy-efficient elec-
tronics. Nanowires offer faster switching speeds due to their nanoscale size resulting
in quicker data operations. Their unique electrical properties like enhanced carrier
mobility and surface effects enhance device performance and reliability (Meena
et al. 2014). RRAM is a nonvolatile memory technology meaning that it retains data
even when power is turned off. Nanowire-based RRAM extends this non-volatility
advantage while also provides the benefits mentioned above. Nanowire-based RRAM
devices can be fabricated in a compact layout making them well-suited for modern
2 Nanowire-Based Si-CMOS Devices 69

Fig. 2.16 Various NVSM applications in the electronics industry by market size (Meena et al.
2014)

miniaturized electronic devices. The integration of nanowires into RRAM devices

involves careful engineering of the nanowire properties including size, composition,
and interface characteristics. This precise control ensures reliable and consistent
device performance (Pan et al. 2010).
Nanowire-based RRAM technology holds promise for traditional and emerging
memory applications like neuromorphic and in-memory computing. The demand
for high-performance, energy-efficient, and compact memory solutions is driving
its significance. Continuous research and innovation are crucial to fully unleash
the potential of nanowire-based memories in various electronic devices, shaping
the future of memory technology (Christensen et al. 2022). Researchers are inves-
tigating ways to enhance digital storage capacity and minimize device size. This
exploration focuses on utilizing electron properties, specifically spin, for more effi-
cient data storage solutions. The objective is to develop innovative approaches
that leverage electron spin to advance data storage technology (Khan et al. 2019).
Researchers have explored alternative materials for enhanced data storage. Their
study examines a novel nanowire design to improve digital data storage. The
research centers on electron behavior and magnetic properties for creating more
efficient, compact data storage devices. Unlike traditional ferromagnetic materials,
this approach aims to minimize data disruption caused by external magnetic fields
(Geng et al. 2021). To overcome the limitations of traditional ferromagnetic mate-
rials in data storage, researchers focused on antiferromagnetic materials which are
immune to external magnetic influences and offer higher data density potential.
They developed a quantum many-body theory considering electron interactions and
identified chromium-doped nanowires with a germanium core and silicon shell as
candidates for antiferromagnetic behavior while maintaining semiconducting prop-
erties. This innovative approach relies on super exchange where germanium elec-
trons serve as intermediaries, enabling interaction between isolated chromium atoms
and facilitating antiferromagnetic behavior (Bai et al. 2020). The research not only
achieves antiferromagnetic behavior in semiconductor nanowires but also enhances
70 R. K. Mishra et al.

our understanding of electron communication between atoms. This breakthrough

holds significant potential for smaller, more efficient electronics with antiferromag-
netic features offering advantages like electrical control of magnetic domains, immu-
nity to magnetic disturbances, and rapid spin dynamics. Furthermore, spin-dependent
quantum transport calculations suggest a high ON/OFF current ratio in nanowire
junctions indicating practical applications in data storage and manipulation are on
the horizon (Choi et al. 2017).

NWs for Evolutionary Devices

Nanowires (NWs) can significantly boost the performance of CMOS devices

by serving as superior channel materials. Their integration in CMOS transistors
enhances charge carrier mobility reducing leakage current and leading to faster
switching speeds and improved energy efficiency. This utilization of NWs optimizes
the operation of CMOS transistors leveraging their exceptional electrical properties
for enhanced device performance (Liu et al. 2023). Nanowires (NWs) offer effec-
tive solutions to address leakage currents in shrinking transistors. Their reduced
cross-sectional area mitigates leakage improving energy efficiency and reducing
power dissipation. NWs’ enhanced surface-to-volume ratio enables precise gate
control, efficiently modulating transistor conductance for better performance and
reduced power consumption (Kwong et al. 2012). Integrating NWs into CMOS
devices reduces operating voltages enhancing energy efficiency and device longevity.
Tailoring NWs’ electrical properties enables customized transistors for diverse
applications. NWs also introduce novel functions such as high-sensitivity sensing,
enhancing CMOS devices with integrated sensing capabilities (Zhang et al. 2021b).
NWs can be integrated into CMOS processes to create hybrid devices combining
the strengths of both technologies. This approach offers a solution to challenges
in traditional CMOS scaling and fosters innovation. However, challenges include
precise NW control, compatibility with existing processes and maintaining consistent
device performance (Cavalcanti et al. 2008). Researchers have created submicron-
scale green micro-LEDs (μLEDs) using a unique bottom-up approach with nanowire
arrays addressing issues like sidewall etching damage. These nanowires with diame-
ters of 100–200 nm and close spacing serve as the foundation for the μLEDs featuring
a core–shell multiple-quantum-well (MQW) structure with InGaN wells and AlGaN
barriers (Liu et al. 2020). The AlGaN layers within the nanowires feature a gradient in
Al content generating free electrons due to differences in internal polarization fields
between GaN and AlN. This innovative approach resolves issues like sidewall etching
damage and wavelength instability. The gradient in Al content stabilizes the elec-
troluminescence peak wavelength ensuring consistent color output across varying
current injections (Wu et al. 2022). The researchers have developed a technique
for growing high-quality GaN epilayers on silicon substrates. This enables seamless
integration of submicron-scale green μLEDs with CMOS electronics paving the way
for compact and high-performance photonic circuits. This breakthrough has potential
2 Nanowire-Based Si-CMOS Devices 71

applications in integrated RGB displays and other optoelectronic fields requiring effi-
cient light sources with nanowire-based fabrication and wavelength stability driving
advancements in next-generation μLED technologies (He et al. 2023). Figure 2.17a
shows a schematic of the InGaN/AlGaN multiple-quantum-well nanowire array illus-
trating the structure used in the study. Figure 2.17b demonstrates the remarkable
stability of the electroluminescence peak wavelength even with a significant change in
current injection highlighting the wavelength stability achieved in the μLED device.
Figure 2.17c displays the current–voltage characteristics of a device emphasizing its
good rectification ratio and strong green emission which is visible to the naked eye.
These results illustrate the promising attributes of the nanowire-based μLEDs and
their potential for practical applications in optoelectronics (Wu et al. 2022).

Fig. 2.17 a Schematic of the InGaN/AGaN multiple-quantum-well nanowire array. b The peak
wavelength of the device’s electroluminescence stays constant over one order of magnitude of
change in current injection. c The current–voltage characteristics of a device that shows good
rectification ratio and strong green emission visible to the eyes (Wu et al. 2022)
72 R. K. Mishra et al.

Researchers have developed an innovative artificial neuron device that offers the
potential to dramatically reduce the computational power and hardware needed for
training neural networks. This device can perform neural network calculations with a
remarkable energy and space efficiency up to 1000 times better than existing CMOS-
based hardware.
Neural networks play a vital role in tasks like image recognition and autonomous
vehicles, and this advancement addresses a critical bottleneck by significantly cutting
the energy and area requirements for neural network computations (Ivanov et al.
2022). This innovative artificial neuron device achieves energy and space efficiency
by utilizing a widely-used activation function, the rectified linear unit (ReLU). It
accomplishes this through a gradual change in resistance driven by a Mott transition
in a nanoscale layer of vanadium dioxide. The heating required for this transition is
provided by a nanowire heater composed of titanium and gold. This breakthrough
technology offers a highly efficient approach to neural network computations (Park
et al. 2022). The researchers have successfully integrated arrays of artificial neuron
and synaptic devices to construct a hardware-based neural network. This network
showcased its convolution capabilities through edge detection in image processing,
a crucial element for deep neural networks. While this system is currently a proof
of concept, the researchers envision scaling it up and stacking more layers to create
complex systems for applications like self-driving car recognition. This advancement
holds the potential to revolutionize the energy efficiency and capabilities of neural
network training and applications (Saleh and Koldehofe 2022). Figure 2.18 displays
a custom printed circuit board featuring an array of activation (neuron) devices and
a synaptic device array. This setup represents the integration of artificial neurons
and synapses for creating hardware-based neural networks. It is a key component of
the researchers’ proof-of-concept system for energy-efficient neural network appli-
cations potentially impacting areas like image recognition and self-driving cars (Oh
et al. 2021).

NWs for Disruptive Devices

Nanowires are extremely thin elongated structures with diameters on the nanometer
scale. “Disruptive devices”, it typically refers to innovative technologies or electronic
devices that have the potential to disrupt or significantly change existing industries,
markets, or technologies. Therefore, “NWs for disruptive devices” suggests the use
of nanowires in the development of novel and groundbreaking electronic devices
that have the potential to revolutionize industries or create entirely new markets.
Nanowires have unique properties that make them suitable for a wide range of appli-
cations, and researchers are exploring their use in areas such as nanoelectronics,
sensors, energy storage, and more. These disruptive devices could offer improved
performance, energy efficiency, or entirely new functionalities compared to tradi-
tional technologies leading to significant advancements in various fields. Nanowires
have the potential to revolutionize CMOS technology by enabling disruptive devices.
2 Nanowire-Based Si-CMOS Devices 73

Fig. 2.18 Custom printed circuit board built with an array of activation (or neuron) devices and a
synaptic device array (Oh et al. 2021)

One such innovation is the integration of nanowires into tunnel field-effect transis-
tors (TFETs) which leverage quantum tunneling for highly energy-efficient charge
transport. TFETs offer ultralow power consumption and subthreshold swing funda-
mentally reshaping the landscape of electronics for enhanced energy efficiency
(Radamson et al. 2020). Nanowires’ nanoscale properties make them ideal for imple-
menting quantum tunneling in TFETs enabling low-energy carrier transport and
reduced power consumption. NW-based TFETs have the potential to significantly
lower the power usage particularly in IoT devices and wearables addressing crit-
ical energy conservation needs. This technology holds promise for enhancing the
74 R. K. Mishra et al.

efficiency of electronic devices in power-sensitive applications (Ionescu and Riel

2011). NW-based TFETs offer the potential for significantly lower subthreshold
swings enhancing the efficiency of transistor switching. Traditional transistors face
limitations in energy efficiency due to the Boltzmann factor which TFETs, through
quantum tunneling, can overcome for improved energy efficiency. This technology
may address challenges in CMOS scaling including reducing power dissipation and
leakage currents enabling more energy-efficient circuits (Upadhyay et al. 2022).
NW-based TFETs hold promise in traditional and emerging computing fields but face
challenges like precise NW control and compatibility with existing processes. Collab-
orative interdisciplinary efforts are needed to overcome these challenges and unleash
the disruptive potential of NW-based devices. In summary, NW-based TFETs offer
a disruptive path to push the boundaries of CMOS technology. Leveraging quantum
tunneling for charge carrier transport, NW-based TFETs have the potential to deliver
unprecedented energy efficiency, subthreshold swing, and scalability. These devices
hold promise for transforming various applications and technologies ushering in a
new era of energy-efficient and high-performance electronics (Upadhyay et al. 2022).

Integration of SiNWs in FEOL

Front-end-of-line (FEOL) is a pivotal stage in semiconductor manufacturing laying

the groundwork for integrated circuits (ICs) on silicon wafers. During FEOL, essen-
tial components like transistors and resistors are fabricated through processes like
doping, thin film deposition, and etching. This stage is fundamental to create the
active elements of electronic devices forming the initial building blocks for ICs
(Lienig and Scheible 2020). FEOL refers to the initial stages of semiconductor fabri-
cation typically involving the creation of transistors and other active components
on a silicon wafer. During FEOL processing, the basic building blocks of the semi-
conductor device are formed. This includes the fabrication of transistors, capaci-
tors, and resistors. Transistors such as metal–oxide–semiconductor field-effect tran-
sistors (MOSFETs) are a fundamental part of FEOL processing. FEOL processes
involve doping silicon wafers to create regions with specific electrical properties
depositing thin films of materials and etching patterns into the silicon to define tran-
sistor structures. At the end of FEOL processing, the semiconductor wafer contains
the active components necessary for electronic functions. Successful integration
demands precise alignment and interconnection with existing CMOS components.
This involves innovative techniques and interdisciplinary collaboration to achieve
seamless integration. FEOL is a complex series of steps crucial for creating the foun-
dational components of modern technology setting the stage for subsequent circuit
formation in BEOL. It relies on silicon wafers which are meticulously cleaned to
maintain pristine surfaces for precise component fabrication. FEOL is followed by
BEOL where these components are interconnected to create functional electronic
circuits advancing technology development (Kim 2022). FEOL involves key steps
2 Nanowire-Based Si-CMOS Devices 75

like SiO2 layer growth for gate insulation, photolithography to define patterns, chem-
ical treatment for etching and deposition, doping to alter electrical properties, and
deposition of materials like metal and dielectric layers. These processes are essential
in shaping the silicon wafer into the intricate components needed for transistors and
other electronic elements. They lay the foundation for the fabrication of advanced
integrated circuits and electronic devices (Batude et al. 2011). Annealing activates
dopants and repairs previous damage while planarization smoothens the wafer for
subsequent circuitry layers. FEOL is the crucial phase where semiconductor devices
and integrated circuits are prepared on the silicon wafer. These processes ensure the
foundation for advanced electronics is in place for further development (Li et al.
2017). FEOL followed by BEOL adds metal layers and interconnects to create
functional integrated circuits including microprocessors and memory chips. This
process is vital for developing powerful electronic devices in modern technology.
FEOL is a foundational stage enabling innovation in electronics that shape our world
(Mallavarapu et al. 2020). Integrating SiNWs with CMOS at the FEOL stage is crucial
for utilizing their biosensing potential in lab-on-chip (LOC) devices. SiNWs offer
high sensitivity and label-free detection due to their nanoscale dimensions. Seamless
integration with CMOS circuitry is essential for fully harnessing SiNWs’ capabil-
ities in LOC biosensors (Gao et al. 2014). FEOL integration of SiNWs requires
compatibility with existing CMOS processes. Gate-all-around (GAA) structures are
employed to enhance SiNW sensor performance. Sidewall transfer lithography (STL)
is a key FEOL technique enabling efficient SiNW fabrication for high-density sensor
arrays on a single chip (Datta et al. 2019). STL provides precise control of SiNW
dimensions for tailored DNA hybridization detection. FEOL process flow is CMOS-
compatible enabling large-scale production of SiNW sensors. Designing a pixel
matrix based SiNW LOC sensor is a key focus in FEOL integration for biomarker
detection (Rigante et al. 2015). Design focuses on specific and multi-target detection
with high selectivity and sensitivity. SiNW pixel matrix monitors electrolyte changes
using a fluid gate simplifying access to test sites. Integration eliminates complex
microfluidics using photolithography and reactive ion etching (Ruano et al. 2003).
FEOL integration brings SiNWs closer to being fully integrated with CMOS circuitry
resulting in real-time readout of the sensor’s output signal and providing a compact,
portable, and high-speed sensor. This seamless integration opens up exciting possi-
bilities for advanced LOC biosensors that leverage the benefits of CMOS circuits and
SiNW technology. The successful integration of SiNWs in the FEOL scheme has
the potential to revolutionize disease monitoring and detection leading to improved
life expectancy and healthcare outcomes (Jayakumar et al. 2014). LOC biosensors
which stands for “lab-on-a-chip” biosensors are compact analytical devices designed
to perform various biochemical and biological assays or tests on a small integrated
platform. These sensors are used for detecting and analyzing specific biological
molecules such as proteins, DNA, RNA, or chemical substances often in very low
concentrations. LOC biosensors offer several advantages, including high sensitivity,
rapid analysis, reduced sample volumes, and the ability to perform multiple assays in
parallel. The integration of SiNWs with CMOS circuits enhances the development of
cost-effective and highly sensitive sensors for point-of-care diagnostics. SiNWs have
76 R. K. Mishra et al.

shown promise in detecting various molecules without the need for labels. Addi-
tionally, incorporating high-K dielectrics like HfO2 improves sensor performance
by enhancing current response near the limit of detection. Overcoming challenges
in selective etching is crucial for the successful integration of HfO2 with SiNWs
in the FEOL stage which has been achieved in recent research. This advancement
holds potential for revolutionizing diagnostic technologies (Jayakumar et al. 2019).
In conclusion, FEOL integration of SiNWs with CMOS technology holds immense
promise for advancing lab-on-chip biosensors. The combination of STL fabrication,
GAA structures, and high-K dielectrics offers a powerful platform for developing
highly sensitive and selective biosensors. The ongoing research and development
in this field will pave the way for more than Moore applications of SiNW-based
devices and integrated circuits revolutionizing the landscape of electronic devices
and technologies and transforming healthcare and disease diagnostics. With contin-
uous improvements in FEOL integration techniques, SiNWs are poised to become a
game-changer in biosensing and usher in a new era of personalized and point-of-care
diagnostics.

Integration of SiNWs After BEOL

The integration of SiNWs post-BEOL in advanced CMOS technology is a signif-

icant challenge necessitating precise alignment with existing CMOS elements.
This integration aims to harness SiNWs’ unique properties for enhanced function-
ality. Innovative approaches like 3D integration, nanoscale patterning, and selective
etching are under investigation to facilitate the seamless incorporation of SiNWs
into advanced CMOS nodes advancing the potential of semiconductor technology
(Huang et al. 2013). Integrating silicon nanowires (SiNWs) into semiconductor
devices post-BEOL is challenging but essential. The BEOL process involves creating
interconnects and metal layers on the chip’s surface. Incorporating SiNWs post-
BEOL requires meticulous planning for alignment and interconnection with existing
CMOS elements. 3D integration utilizing vertical interconnects is explored for effi-
cient SiNW integration in advanced semiconductor technology (Hellström et al.
2014). SiNWs are integrated within stacked layers enhancing device performance
and density. Precision in alignment and interconnection between layers is crit-
ical. Advanced nanolithography ensures accurate positioning and interconnection
of SiNWs with CMOS structures reducing the risk of issues. This strategy improves
semiconductor technology (Hellström et al. 2014). Selective etching is essential for
SiNW integration without damaging CMOS. Efficient contacts and reliable elec-
trical connections are crucial for optimal device performance. Innovative contact
engineering approaches are explored to achieve this (Datta et al. 2019). Investiga-
tion into techniques for transferring SiNWs post-BEOL involves precise alignment
and wafer bonding. SiNWs are integrated onto a separate wafer and bonded to the
CMOS wafer enabling late-stage integration. This approach addresses challenges in
SiNW integration with existing CMOS processes (Fruncillo et al. 2021). Researchers
2 Nanowire-Based Si-CMOS Devices 77

are seeking materials to bridge SiNWs and CMOS in integration. These materials
must be compatible and enable seamless alignment. This effort aims to enhance
SiNW-CMOS integration for advanced semiconductor technology (Hellström et al.
2014). Challenges persist in ensuring compatibility, performance, and yield rates in
SiNW integration. Collaboration across disciplines is vital for effective strategies in
advanced CMOS technology. It aims to overcome these challenges for successful
integration (Livi et al. 2014). The integration of SiNWs post-BEOL can advance
CMOS devices improving performance and energy efficiency. This contributes to the
ongoing evolution of semiconductor technology. Collaboration and innovation are the
keys to achieve this integration success (Khan et al. 2018). In conclusion, the integra-
tion of silicon nanowires (SiNWs) into complementary metal–oxide–semiconductor
(CMOS) technology particularly in the front-end-of-line (FEOL) stage represents
a significant step in harnessing the unique properties of SiNWs for biosensors and
other advanced applications. This integration involves careful planning, innovative
techniques like 3D integration and selective etching, and interdisciplinary collabora-
tion to overcome challenges. Successfully integrating SiNWs into CMOS can lead to
high-performance, energy-efficient devices revolutionizing fields like disease moni-
toring and diagnostics and contributing to the continued evolution of semiconductor
technology.

Conclusion: Potentials and Challenges

Silicon nanowires (NWs) hold immense promise across scientific and technological
domains. Their remarkable attributes encompassing superior surface area, augmented
electrical conductivity, and meticulous doping regulation establish them as versatile
components applicable to diverse fields. Throughout this discourse, we have delved
into the potentials and hurdles entwined with silicon NWs delineating their multi-
faceted impact on research and innovation. The morphology and characteristics of
silicon nanowires combined with their flexibility in the manufacturing process open
doors to exciting prospects in device development. Their substantial surface area
and enhanced electrical conductivity make them invaluable in catalytic, sensing,
and electronic applications offering the potential for improved effectiveness and
efficiency. Additionally, their heightened mechanical resilience renders them suit-
able for applications demanding durability and reliability. Doping silicon nanowires
plays a pivotal and versatile role in manipulating their electronic characteristics.
The precise introduction of specific impurities empowers researchers to customize
the nanowires’ conductivity and carrier concentration rendering them suitable for
an array of electronic devices including transistors, sensors, and photodetectors.
Quantum simulations and electrical characterizations of silicon nanowires are invalu-
able for gaining essential insights into their behavior at the nanoscale. These research
efforts are paramount for comprehending carrier transport, tunneling phenomena,
78 R. K. Mishra et al.

and confinement effects. They aid in fine-tuning transistor performance and inves-
tigating innovative quantum devices. Silicon nanowires are also poised to revolu-
tionize CMOS memory and evolutionary devices. Their expansive surface area and
customized electrical properties outperform traditional planar devices paving the way
for high-density, low-power, and high-performance memory solutions. Additionally,
silicon nanowires have the potential to introduce disruptive elements notably tunnel
field-effect transistors capable of redefining the boundaries of CMOS technology.
These groundbreaking devices bring the promise of ultralow power consumption
and subthreshold swing both for the progression of energy-efficient electronics. The
seamless incorporation of silicon nanowires after the back-end-of-line (BEOL) and
front-end-of-line (FEOL) processes stands as a critical hurdle to surmount. Precise
alignment, harmonious interconnection with existing CMOS components, and adher-
ence to process flows are pivotal challenges that diligent researchers are actively
addressing. In summation, silicon nanowires exhibit vast potential for advancing a
multitude of technological domains encompassing electronics, photonics and more.
Their intrinsic properties and adaptable nature render them versatile and alluring
contenders for an extensive array of applications. Nevertheless, the successful inte-
gration into practical CMOS technology necessitates the resolution of specific chal-
lenges, a pursuit that researchers are fervently engaged in. As this technology
continues to burgeon, silicon nanowires are poised to assume a pivotal role in shaping
the future of electronics, communication, and computing unlocking novel avenues
for innovation and scientific exploration.

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Chapter 3
Carbon Nanotube FETS: An Alternative
for Beyond Si Devices

Shailendra K. Tripath

Abstract The fundamental building blocks of IC technology must change due to

the physical limitations of device scaling. Emerging nanoelectronics can offer a solu-
tion to lower fabrication costs and enables further device size scaling in the midst
of current nanotechnology research and development. Modern integrated systems
mostly consist of copper/aluminum cables and silicon-based transistors. These tran-
sistors and wires might both be changed to carbon nanotube transistors and carbon
nanotube wires, respectively. In carbon nanotube field-effect transistors (CNFET),
the CNT is used as a transistor component. It appears that a carbon nanotube
has taken the role of the silicon-based channel material in a MOS transistor. The
carbon nanotube-FET shows the potential characteristics to be exploited in futuristic
low-power and high-performance circuit design.

Keywords Carbon nanotube (CNT) · CMOS · Carbon nanotube field-effect

transistor (CNFET) · Nanoelectronics · Emerging devices

Introduction

The scaling of silicon-based transistors to ever-smaller sizes has recently been the
driving force behind the shrinking of electronic devices. Alternative materials and
device topologies are, however, being investigated as the limits of silicon-based
devices are approached. One such substitute can be the CNFET which offers a
number of benefits over conventional silicon-based devices. The usage of CNFETs
in non-silicon devices will be covered in this chapter. CNFETs or carbon nanotube
field-effect transistors carbon nanotubes (CNTs) are used as the channel mate-
rial in CNFETs. CNTs are carbon-atom-based cylindrical tubes with lengths up
to several microns and diameters on the order of nanometers. They have great

S. K. Tripath (B)
Department of Physics and Materials Science, Jaypee University, Anoopshahr, Bulandshahr, Uttar
Pradesh, India
e-mail: [email protected]

© The Author(s), under exclusive license to Springer Nature Singapore Pte Ltd. 2024 89
S. Singh et al. (eds.), Beyond Si-Based CMOS Devices, Springer Tracts in Electrical and
Electronics Engineering, https://doi.org/10.1007/978-981-97-4623-1_3
90 S. K. Tripath

thermal conductivity and outstanding electrical characteristics such as strong electron

mobility.
The CNT acts as a conduit between the source and drain electrodes in a CNFET.
By applying a voltage to the gate electrode which is positioned around the CNT,
the electric field can modulate the conductance of the channel. Depending on the
CNT type utilized, CNFETs can operate in either p-type or n-type modes (Haron and
Hamdioui 2008; Kuhn 2011; Haensch et al. 2006). In 1998, the first demonstration of
the carbon nanotube-FET took place. CNFETs, which are based on semiconducting
single-walled carbon nanotubes (SWNT), perform similar to their silicon MOSFET
equivalent. Low leakage current and good switching features are the features of
CNT-based circuits. An oxide film is positioned between a conductive gate and the
SWNTs that serve as the MOS device’s channel in order to create a CNFET. On
both ends of the SWNTs, conductive metal connections are constructed to act as the
source and drain. Additionally, NFET compatible with current CMOS technology
is the CNFET (Wong and Akinwande 2011; Kuhn 2012). Further, CNFETs offer
superior electrical characteristics including high electron mobility and strong on/off
ratios. Additionally, they show minimal leakage currents which is another drawback
for silicon-based devices. The excellent thermal conductivity of CNTs can aid in
transferring heat away from the device and preventing overheating.

CMOS Scaling Challenges

The phrase “Moore’s law” refers to the gradual reduction of the horizontal and
vertical feature sizes of CMOS transistors made of silicon. The primary driving
force behind the development of today’s advanced electronic device technology has
been this enormous endeavor. At the end of this decade, according to the International
Technology and Roadmap for Semiconductors (ITRS), it will eventually cross the
border at a size of about 22 nm. It denotes that CMOS transistors are getting closer
to the limits of atomistic and quantum mechanical physics (Ieong et al. 2004). The
design of CMOS devices and circuits takes a number of difficulties into account.
Due to these difficulties, designers were compelled to create novel technologies
like CNFET, nanowire field-effect transistors (NWFET), and other technologies that
goes beyond CMOS. The difficulties are detailed below. With the continued growth
of MOS transistors, these problems are becoming more and more prevalent (Nowak
2002; Ellinger et al. 2011).
(a) Physical challenges
(b) Material challenges
(c) Power-thermal challenges
(d) Technology challenges
(e) Economic Challenges.
Numerous impacts arise in the MOSFET nanoscale regime that essentially limits
the performance among the broad categories of CMOS scaling problems outlined
3 Carbon Nanotube FETS: An Alternative for Beyond Si Devices 91

above (Kuhn 2012; Asra et al. 2011; Lababidi et al.; Low and Zhang 2012). These
effects include interconnect delays, short channel effects, high field effects, and thin
gate oxide tunneling issues.
Further, the market is looking for replacement components and materials that
works with the current CMOS technology (Ghani 2009). Additionally, the biggest
obstacle to sustained system integration is energy efficiency. Research into alter-
native “beyond-CMOS” technologies has been compelled by problems with tran-
sistor scaling in combination with demands for low-power dissipation. It has been
suggested that the traditional MOSFET will be replaced in the future by field-effect
transistors (FETs) with carbon nanotubes (CNTs) deposited in the channel region.
The CNFET, also known as a carbon nanotube field-effect transistor, has the poten-
tial to replace CMOS in future (Usmani and Hasan 2009; Ale et al. 2010; Imran
and Azam 2012). The CNT differs from MOSFET in a number of ways including
better mobility in CNT, greater drive current, and simpler high-k dielectric material
integration (Karmani et al. 2011).

Carbon Nanotube (CNT)

Sumio Iijima, a Japanese scientist, made the discovery of the carbon nanotube (CNT)
in 1991. CNTs are grapheme (a type of carbon) nanostructures with exceptional elec-
trical, thermal, and mechanical capabilities. Depending on how the carbon atoms are
arranged within the twist of the CNTs (Chirality), they can either be metallic or
semiconducting. Additionally, if small energy is required to push an electron to an
unoccupied excited level, a CNT is considered to be metallic. On the other hand, the
CNT is referred to as semiconducting if there is a limited energy difference between
the vacant state and occupied state (Shabrawy et al. 2010; Patil et al. 2009a; Bandaru
2007). In comparison with MOSFETs, the CNT has a number of unique characteris-
tics including better carrier mobility in semiconductor tubes, larger driving currents,
and simpler integration of high-k dielectric materials. As shown in Fig. 3.1, the
carbon nanotubes typically are of two types: (a) single-walled CNTs (SWCNTs) and
(b) multi-walled CNTs (MWCNTs). The SWCNTs are cylindrically rolled grapheme
layer tubes. The length ranges from 0.2 to 5 µm, while the diameter is between 1 and
2 nm. MWCNTs are revealed as coaxial tubes with SWCNT layers. Their interlayer
spacing is approximately 0.36 nm and their diameter ranges from 2 to 25 nm. While
SWCNTs are more expensive and perform better than MWCNTs, MWCNTs are
simpler to make in large quantities (Javey et al. 2003; Reilly 2007).
On the basis of chiral vector (C) and chiral angel, there are three different types
of carbon nanotubes. If m = n and θ = 0, a carbon nanotube is referred to as zigzag.
If m = 0 and θ = 30 as seen in Fig. 3.2, CNT is said to be chiral type and known
as armchair if chiral vector m n and chiral angel lies between 0 and 30. The crucial
variables that depends on the diameter DCNT, number of tubes (N), and pitch (S) of
a carbon nanotube are also shown in Eqs. (3.1)–(3.4).
92 S. K. Tripath

Fig. 3.1 Single and multi-walled carbon nanotubes

√
a n2 + m2 + nm
DCNT = (3.1)
π
aVπ
Vth = √ (3.2)
qDCNT 3

W = (N − 1) ∗ S + DCNT (3.3)

 0.84 eV
g= (3.4)
DCNT

In this case, a = 2.49 A (the lattice constant), m and n denote the indices of
Graphene lattice’s chiral vector. Further, q is the charge of electron, and V denotes
carbon-bond energy (3.033 eV).

Fig. 3.2 Different types of CNTs

3 Carbon Nanotube FETS: An Alternative for Beyond Si Devices 93

Carbon Nanotube Field-Effect Transistor (CNFET)

To overcome the difficulties of the current CMOS technology, CNFET is a very

promising device (Deng and Wong 2007a, 2006). CNTs are superior channel mate-
rials for high-speed and low-power electronics because of their near ballistic trans-
port capabilities and band structure (Wong and Akinwande 2011). The arrangement
of carbon atoms in the twist (Chirality) of the CNTs determines whether they are
metallic or semiconducting. The design of a carbon nanotube field-effect transistor
is depicted in Fig. 3.3. The CNFET features a larger drive current, more carrier
mobility, increased transconductance, and improved channel management. When we
are designing CNFET-based devices, numerous factors like CNT diameter (DCNT),
threshold voltage (V th ), and others need to be taken into account.
For beyond-silicon devices, carbon nanotube field-effect transistors (CNFETs) are
a viable replacement for conventional silicon-based field-effect transistors (FETs).
One-dimensional nanostructures comprised of carbon atoms called carbon nanotubes
(CNTs) have extraordinary electrical and mechanical capabilities. Instead of silicon,
CNFETs employ a single CNT or a group of CNTs as the transistor’s channel.
Compared to conventional Si FETs, CNFETs provide a number of benefits. They
have improved thermal and mechanical stability with considerably high operating
frequencies. Additionally, CNTs have a very high carrier mobility that translates
into extremely efficient electron transport. CNFETs must first overcome a number of
obstacles before becoming a widely used technology. The capacity to produce CNTs
with the necessary characteristics is a significant problem. As various CNTs might
have varied electrical characteristics, finding consistency in performance across
multiple CNTs is another difficulty.
Despite these obstacles, CNTFET research has been advanced significantly in
recent years and they show enormous potential for electronic devices for materials
other than silicon in the future.

Fig. 3.3 Top view of

CNFET with three CNTs
94 S. K. Tripath

The literature has discussed the ongoing development of CNFET model and
performance estimate. The benefits and practicality of CNFET over regular MOSFET
are clear, but the outcomes of circuits using CNFET are sufficient to outperform
traditional MOSFETs (Possani et al. 2012). The literature has published the research
papers based on the CNT/CNFET (Imran and Azam 2012; Raychowdhury et al.
2004; Deng and Wong 2007b; Hayat et al. 2013a; Fregonese et al. 2008; Khan and
Zaidi 2000). Quantum confinement in both axial and circumferential directions is
one of the non-idealities that Deng et al. predicted. The intrinsic CNFET with (19,
0) CNT is expected to provide a 13-time C-V/I improvement over the bulk n-type
MOSFET at the 32-nm node (Deng and Wong 2007b).
Elastic scattering in the channel area, the Schottky barrier resistance, the resistive
source–drain, and the parasitic gate capacitance was all incorporated in the HSPICE
compatible model utilized by Deng et al. The findings were far more intriguing
than CMOS. The energy consumption was 7 times lower, the energy delay product
was 15–20 times lower, and the CNFET circuits with 1–10 CNTs per device were
approximately 2–10 times quicker (Deng and Wong 2007a).
Using a SPICE model, Hayat et al. investigated the RF characteristics of a CNFET-
based circuit. A CNFET-based circuit has a transconductance (gm ) that is 2.7 times
greater than CMOS. Additionally, the inverter circuit is projected to operate 10 times
more quickly than traditional MOS circuits (Hayat et al. 2013a). In order to predict
the CNFET threshold voltage distribution and propagation delay from simulation
of the ring oscillator circuit, a physics-based model of CNFET for MOSFET-like
functioning is provided. Other analog and digital building components’ performance
may be estimated with the aid of this approach (Fregonese et al. 2008).
Circuit-compatible models for single-walled semiconducting CNFETs were
proposed by Raychowdhury et al. for the first time. The I-V and C-V relations for a
simple CNFET circuit were given while considering model non-idealities. This model
was subsequently developed to predict how CNFET-based circuits will perform in
the literature (Raychowdhury et al. 2004). Imran et al. presented a second-generation
current conveyor (CCII) utilizing a CNFET and discovered that a number of metrics
including band width and input output impedances (RX, RY, & RZ) were superior
to those of the circuits based on CMOS. In contrast to 13.1 GHz of CMOS, the
current band width of a circuit based on CNFETs was 26.7 GHz. Investigations on
the impact of diameter variation have also been conducted (Imran and Azam 2012;
Imran et al. 2012). Usmani et al. studied that carbon nanotube-based amplifier offers
superior amplification over CMOS and described a carbon nanotube-based amplifier.
Additionally, a hybrid design that combines PMOS and nCNFET was suggested that
demonstrated a superior frequency response (Khan and Zaidi 2000).
3 Carbon Nanotube FETS: An Alternative for Beyond Si Devices 95

Survey on Circuits Using CNFETs

Experimental confirmation of the characteristics of CNTs has proven superiority over

silicon. The height of the Schottky barriers at the metal/nanotube interface regulates
the ON-current of CNFETs. Current variations at low frequencies are mostly caused
by 1/f noise. It also refers to the quantity of carriers being conveyed (Lin et al.
2007). Additionally, Bandaru provided a research (Bandaru 2007) on the electrical
characteristics of carbon nanotubes that considers the phenomena like thermoelec-
tricity, superconductivity, electroluminescence, and photoconductivity. Additionally,
the work gives details on the use of CNTs in high-frequency nanoelectronics, field
emission, and biological sensing (Dresselhaus et al. 2000). A CNT’s diameter is
inversely correlated with its band gap. As a result, CNTS with a tiny diameter can
be employed in applications related to electrical switching and transistors (Low and
Zhang 2012; Dresselhaus et al. 2004; Franklin et al. 2012; Fedawy et al. 2012; Singh
et al. 2016). The researchers also examined how the flaws in the CNT manufacturing
process affected the circuit performance (Patil et al. 2009b; Javey et al. 2004; Guo
et al. 2005). These include the changes brought on by doping in the source and drain
regions of CNFETs.
Therefore, the ability to integrate CNTs with transistors is made possible by the
electrical characteristics of CNTs. Among other new nanoelectronics technologies,
Kim (Yong Bin Kim 2011) has discussed the breadth of CNFET technology. The
operation principle and device structure of the CNFET technology is comparable to
that of the current CMOS technology, and the manufacturing method is compatible
with both. In addition, the CNFET technology can make the use of the current
infrastructure. It has been explained, how to examine the electrical structure and
carrier transport characteristics of CNT (Avouris et al. 2003). The paper covered the
creation of CNFETs as well as their performance characteristics and a comparison to
CMOS. According to the findings, CNFET will perform better than current silicon
devices.

Simulation and Modeling Work on CNFET

The literature (Dwyer et al. 2004; Deng and Wong 2007b) presents the simulation
work on CNFETs. The models show improved performance outcomes compared
to CMOS circuits. In 2007, Deng put out a comprehensive device model that was
compatible with a single-walled CNFET’s intrinsic channel area. The model takes
into account non-idealities such as the screening impact of parallel CNTs and the
quantum confinement effect on axial and circumferential directions. The findings
demonstrate an intrinsic CNFET’s 13-time CV/I improvement over bulk n-type
MOSFETs using 32-nm nodes (Kazmierski et al. 2009; Luo et al. 2013).
Sebastien (Fregonese et al. 2008) has also investigated a small physics-based
model for MOSFET-like CNFETs. With the help of a research of CNT diameter
96 S. K. Tripath

dispersion, the model also establishes the threshold voltage distribution. The non-
linear cubic spline approximation of the non-equilibrium mobile charge density
serves as the model’s foundation. The suggested model’s I-V properties are contrasted
with those of the current Stanford HSPICE model. The model displays improved
accuracy while using the same amount of CPU time. In this work, the perfor-
mance of both ballistic and non-ballistic effects was investigated. The exploration of
CNFET-based analog and digital circuits was greatly facilitated by the HSPICE-based
modeling (Kazmierski et al. 2009).

Overview of CNFET Experimental Work

In 1998, the initial research on the creation of carbon nanotube-FETs has been
published on specific SWCNTS and MWCNTs. Starting at normal temperature, the
conduction seemed to diffuse but not ballistic. More than five orders of magnitude
might be added to the conductance of single-wall CNFETs. It has a larger carrier
density than graphite. Furthermore, structural deformation can attain FET-like char-
acteristics even if large diameter, multi-walled CNTs does not have a gate effect on it.
Additionally, Sander J. provided details on how to create a CNFET using SWCNTs
(Tans et al. 1998). The device runs at ambient temperature. Semi-classical band-
bending models can be used to explain transistor properties. In order to lower the
Schottky barrier, Javey et al. (2003) introduced the modification to the nanotube–
metal junction in 2003. Javey first experimented with the manufacturing of CNFETs
with ohmic contacts and high-K dielectrics by using CNTs on the connection.

Circuit Applications of CNFET

Compared to CMOS, CNFET device has lower parasitic capacitances. The 45-nm
technology node is assumed to be consistent with the CNFET and MOSFET design
standards. An approach for improving the CNFET parameters is given in 2009 (Kim
et al. 2009). In terms of fan-out factor, latency and power consumption, this technique
produced the best results. The optimal pitch and quantity of CNTs were used in the
suggested approach that resulted in a 56% decrease in dynamic power and a 22%
reduction in latency. Kureshi and Hasan (2009) has also contrasted the features of
6 T SRAM cells based on CMOS and CNFET. According to the findings, CNFET
memory cells would have a 21% increase in reading static noise margin. Furthermore,
compared to CMOS design, leakage (standby) of carbon nanotube-FET cell is 84%
lower. Compared to MOS, SRAM employing carbon nanotube-FET is 1.84× quicker.
Additionally, Moaiyeri et al. (2011) has suggested a CNFET-based full-adder
to work on low VDD and high switching speed. Due to the use of just two CNT
pass-transistors, the circuit has a short critical path. The work also made use of the
ability of CNT diameter change to modify the CNFET device’s threshold voltage.
3 Carbon Nanotube FETS: An Alternative for Beyond Si Devices 97

The findings demonstrate that a CNFET-based device outperforms a CMOS design in

terms of speed, power consumption, and PDP. Inverting amplifier design employing
CMOS, CNFET, and hybrid technologies was demonstrated (Usmani and Hasan
2010). It was concluded that the (pCNFET-nMOS) mixed design has a superior ampli-
fier characteristics. Additionally, pMOS-nCNFET demonstrated superior transient
responsiveness than CMOS. Additionally, CCII is produced via CNFET (Imran et al.
2012). The outcome shown that CNFET-based CCII provides greater high-frequency
responsiveness while using less power than CMOS.
Rahman (Rahman et al. 2011) described an elliptical filter design based on Op-
Amp. Additionally, the results demonstrated that the circuit using carbon nanotube-
FET has greater phase-margin and low power requirement. A trade-off would always
exist between the quantity of CNTs and power use. More power would be consumed if
there were more CNTs present. Further, an inverter, ring oscillator, and LC oscillator-
based circuits using CMOS and CNFET technology were compared by Hayat (Hayat
et al. 2013b). The inverter using CNFET has speed 10× that of a CMOS inverter,
while the oscillation frequency of a ring oscillator is three times more than that
of a CMOS oscillator. Another significant piece of research was published related
to capacitance and oxide layer height including silicon nanowire-FETs, CNFETs,
and MOSFETs with single and double gates (Sinha and Chaudhury 2013). The
findings demonstrate that silicon nanowire-FET and CNFET both exhibit the feature
of decreasing gate capacitance with decreasing oxide thickness in the deep nanometer
regime. In single-gate or double-gate MOSFETs, it is not feasible.

Conclusion

The electronics industry has witnessed a tremendous downsizing of transistor sizes

during the past three decades. This was made possible by the invention of novel
materials, including high-k dielectrics and different nitrides and silicides. It was the
downscaling roadmap for MOS devices. The carbon nanotube exhibits superior func-
tionality in terms of increased carrier velocity, reduced silicon scattering, increased
mobility in semiconductor tubes, increased drive current, and simple high-K dielec-
tric inclusion. As a result, the market is seeking for alternatives to current CMOS
technology in terms of materials and equipment. Energy efficiency is another major
obstacle to the further integration of systems. The search for new “beyond-CMOS”
technologies has become necessary because of the problems with transistor scaling
and demands for reduced power dissipation. The standard MOSFET is replaced with
the CNFET as an alternative device. The so-called CNFET has the capability to
replace CMOS in the future. With their superior electrical characteristics and scal-
ability, CNFETs are a possible replacement for conventional silicon-based devices.
Among the other things, its prospective uses include flexible electronics and high-
performance computers. CNFETs may become more crucial to the development of
beyond-silicon devices as this field of study advances.
98 S. K. Tripath

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Chapter 4
Graphene-Based Devices for Beyond
CMOS Applications

Basanta Bhowmik

Abstract Graphene, a single-layer thick atomic planner sheet with densely packed
honeycomb crystal lattice having excellent electronic, optoelectronic and mechanical
properties is grabbing worldwide market in the area of electronics, home appliances
and medical field. The present book chapter emphasizes on graphene-based field
effect transistor devices towards different applications. It comprehensively reviewed
the synthesis of graphene, properties of graphene and fabrication of graphene nanos-
tructure (nanowire, nanoribbons)-based devices. Mostly, single and bilayer graphene-
based field effect transistor structures have been discussed with special emphasis
on logic and radio frequency applications. Further, use of graphene transistor for
switching and electronics applications have been taken into consideration to prove
the potentiality of the material. Challenges for synthesis of graphene with difficul-
ties to fabricate field effect devices towards different application and their probable
potential solution to mitigate the issues for future opportunities have been illustrated.

Keywords Graphene · Nanowires · Logic applications · Nanoribbons · Synthesis

techniques

Introduction

Graphene behaves as an emerging and promising material since its discovery and
possess unique properties such as high charge carrier mobility at room temperature of
about 200,000 cm2 /v-sec, velocity 1/300 of the speed of light, large specific surface
area (2630 m2 g−1 ), carrier density ~ 1012 cm−2 with resistivity of 10–6 Ω (Banerjee
et al. 2010; Yuan and Shi 2013; Obeng and Srinivasan 2011; Nag et al. 2018; Singh
and Singh 2016; Wu et al. 2018; Peres 2009; Novoselov et al. 2007; Balandin 2011;
Ovid’ko 2013). Graphene possesses low resistivity at room temperature having 2D
honeycomb structures consisting of single-layer sp2 carbon atom (Yuan and Shi 2013;

B. Bhowmik (B)
Thin Film Devices Laboratory, Department of Electronics and Communication Engineering,
National Institute of Technology, Jamshedpur 831014, India
e-mail: [email protected]

© The Author(s), under exclusive license to Springer Nature Singapore Pte Ltd. 2024 101
S. Singh et al. (eds.), Beyond Si-Based CMOS Devices, Springer Tracts in Electrical and
Electronics Engineering, https://doi.org/10.1007/978-981-97-4623-1_4
102 B. Bhowmik

Obeng and Srinivasan 2011). High mobility properties of graphene attracted world-
wide attention for the high frequency applications employing MOSFET devices.
In addition, the unique band structure, fast transport properties with greater stability
makes it suitable material for high frequency CMOS and beyond CMOS device appli-
cations (Lee et al. 2008; Jia et al. 2011; Khan et al. 2016; Choi et al. 2010; Park et al.
2011; Kim et al. 2016a, 2015; Lee et al. 2012b; Liu et al. 2015; Basu et al. 2014; Liao
et al. 2010; Abergel et al. 2010; Zhan et al. 2014; Schwierz 2010a, 2010b; Schwierz
et al. 2010; Chen et al. 2008; Lemme et al. 2014). Also, it has applications in solar
cells, liquid crystal devices, fabrication of transistors, analog and digital devices
such as voltage and power amplifiers, noise amplifiers, etc. Pure graphene is made
up of 2D sheets that are bonded by carbon atoms to form hexagonal crystal lattice.
In the last decade, graphene has been widely used to develop gas sensor due to its
superior properties like high surface to volume ratio, distinctive nanopores structure,
excellent carrier mobility, unique electrical, thermal and optical properties with good
mechanical strength (Peres 2009; Novoselov et al. 2007; Balandin 2011; Ovid’ko
2013; Lee et al. 2008; Jia et al. 2011; Khan et al. 2016; Choi et al. 2010; Park et al.
2011; Kim et al. 2016a; Lee et al. 2012b; Liu et al. 2015; Basu et al. 2014; Liao et al.
2010). Single-layer graphene sheet is sufficient enough for adsorbing gas molecules
as it provides large sensing area per unit volume. Graphene offers low electrical
noise because of its crystal lattice along with 2D structure. Such properties make it
very reactive towards gases as few amount of extra electrons may cause change in
conductance of graphene. Therefore, small change in resistance of graphene sheet
due to adsorption of gas molecule is easily noticeable (Liao et al. 2010; Kim et al.
2015; Abergel et al. 2010; Zhan et al. 2014; Schwierz 2010a, 2010b, 2014; Schwierz
et al. 2010; Chen et al. 2008; Lemme et al. 2014; Koswatta et al. 2011; Lin et al. 2010;
Lee et al. 2012a; Wang et al. 2010; Petrone et al. 2013; Radsar et al. 2021; McCann
2006; Rhee 2020; Lemme 2009; Hong et al. 2011; Pradhan et al. 2016; Szkopek
and Martel 2021; Shi et al. 2018; Nakamura et al. 2022; Randviir et al. 2014; Singh
and Nalwa 2015). In recent times, graphene is used in industries for CMOS design.
Performance of integrated circuits can be improved by minimization of the CMOS
size. Size minimization not only reduces power consumption but also increases the
processing speed. IBM engineers designed 10,000 times faster chip using graphene.
For achieving high-performance CMOS chip, silicon carbide (SiC) wafer is better
choice to deposit graphene layer. Conventional CMOS possess some drawbacks
such as gate leakage, source to drain leakage, channel mobility degradation due to
increased dynamic power dissipation, device-to-device variations and leakage due
to tunnelling at high doping level. System design using CMOS non-planer (3D)
technology tremendously reduces the power consumption and offers faster speed
and area overhead (Randviir et al. 2014; Singh and Nalwa 2015; Mahmoudi et al.
2018; Cohen-Karni et al. 2010; Kim et al. 2018; Van Bavel 2019; Kim et al. 2016b;
Gil-Tomàs et al. 2019). Apart from gas sensors, graphene was broadly used in light
emitting diodes, nano-generators, solar cells and photodetectors (Kim et al. 2015;
Abergel et al. 2010; Zhan et al. 2014; Schwierz 2010a, 2010b, 2014; Schwierz et al.
2010; Chen et al. 2008; Lemme et al. 2014; Koswatta et al. 2011; Lin et al. 2010; Lee
et al. 2012a; Wang et al. 2010; Petrone et al. 2013; Radsar et al. 2021; McCann 2006;
4 Graphene-Based Devices for Beyond CMOS Applications 103

Rhee 2020; Lemme 2009; Hong et al. 2011; Pradhan et al. 2016; Szkopek and Martel
2021; Shi et al. 2018; Nakamura et al. 2022; Randviir et al. 2014; Singh and Nalwa
2015; Mahmoudi et al. 2018; Cohen-Karni et al. 2010). Among these applications,
solar cells and photo detectors require multilayer graphene layer to enhance light
absorbing efficiency where pristine pure monolayer graphene is sufficient enough
to react with target molecules. In solar or photo-detector applications, thin mono-
layer of graphene does not absorb sufficient light for converting light into electrical
energy. Graphene with zero band gap possibly provides lower lifetime for an excita-
tion which may affect the photo-responsivity (Wu et al. 2018). Further, higher dark
current is induced in case of graphene-based photodetectors. Such drawbacks can
be reduced by hybridization of high mobility graphene with quantum dots of large
quantum efficiency. Hybridization with nanostructure offers superior properties like
spectral tenability, higher carrier mobility, higher light absorption capability and
faster charge transfer between graphene and quantum dots heterojunction interface
which possibly promotes the generation of photocarrier (Wu et al. 2018). In addition,
graphene has been widely used in supercapacitors, cells and batteries as anode due
to its large strength-to-weight ratio, large surface area and less charging time. It is
also used in catalysis, nanoelectronics and biomedical engineering applications due
to its unique properties (Peres 2009).

Graphene

Properties of Graphene

Graphene has attained worldwide attention as a research topic as it possess remark-

able properties. It shows higher carrier mobility (200,000 cm2 /(V.s)), better mechan-
ical strength, light transparency, higher conductivity, excellent thermal properties,
high current density and greater chemical stability (Peres 2009). It may exist either
as monolayer that is formed on top of a substrate of other material or as free-standing
sheets which may be isolated from environment. Bilayer graphene has the ability to
exhibit tunable band gap structure, while multilayer graphene offers gate tunable
overlap between the conduction band and the valence band (Novoselov et al. 2007).
At room temperature, it possesses better thermal conductivity with much higher value
compared to other forms like graphite, diamond and carbon nanotubes (Novoselov
et al. 2007; Balandin 2011). As per Fourier’s law, thermal conductivity K is related
to heat flux (q) and temperature gradient (ΔT ) following the relation q = −KΔT .
. The temperature gradient (ΔT ) in amorphous carbon and diamond/graphene was
found to be ~ 0.01 W mK−1 and 2000 W mK−1 respectively at room tempera-
ture (Balandin 2011). In graphene two-dimensional crystals, thermal conductivity is
divergent in nature and such divergent properties could be restored either by reducing
the size of the crystal or by incorporating the disorder in the crystal (Balandin 2011).
Even though high-quality few-layer graphene fabrication is difficult as compared
104 B. Bhowmik

to bulk graphite counterpart, its better thermal properties make them highly prefer-
able material than the bulk one. The mechanical properties of a crystalline lattice
structure of pure graphene depend on structural defects like dislocations and grain
boundaries for macroscopic samples along with fracture toughness (Ovid’ko 2013).
For a defect less single-layer graphene, the interaction between the atoms causes
elastic properties and is considered to be the strongest material. One of the reasons
for extraordinary mechanical properties of graphene are stable sp2 bonds forming
the hexagonal crystal lattice (shown in Fig. 4.1) and oppose n-plane deformations
(Balandin 2011). Elastic properties of the monolayer graphene and their intrinsic
strength have been studied by Lee et al. (2008). In their studies, arrays of circular
wells were patterned on Si substrate with SiO2 grown on it. Graphite monolayer flakes
were deposited mechanically on the substrate over circular pore to create uniform
free-standing membranes. Mechanical properties of free-standing membrane were
investigated through AFM analysis. AFM study reveals nonlinear elastic properties
with brittle fracture in graphene. Upon application of tensile load on graphene, it
produces nonlinear elastic response which is correlated as σ = Eε + Dε2 where
D = third-order elastic modulus, σ = Piola–Kirchhoff stress (applied stress), ε =
Lagrangian strain (elastic strain) and E = Young’s modulus (Ovid’ko 2013; Lee et al.
2008). The exceptional electronic properties of graphene are due to the fact that the
electrons present in graphene possess long mean free paths but it does not disturb
the interactions between electrons and disorders. Electrons that propagate through
honeycomb lattice structure of graphene lose their effective mass thereby producing
a quasi-particle described by the Dirac equation (Ovid’ko 2013; Lee et al. 2008).
Charge carriers in graphene obey liner dispersion relation which is similar to mass-
less relativistic particles that can be described by Dirac Hamiltonian H = −ihvF σ ∇F
where vF (Fermi velocity) = 10 m/s and σ = Pauli matrices (Novoselov et al. 2007).
According to Peres et al. in case of bulk graphene, the Dirac spectrum mainly controls
the behaviour of the transport properties (Peres 2009) (Fig. 4.2).

Fabrication of Graphene

Graphene nanoforms can be synthesized by different chemical and physical

processes. Among them, the most popular is exfoliation of graphite through quantum
mechanical lithography, CVD, chemical and sonochemical methods (Jia et al. 2011).
Graphene can be easily obtained from high-grade graphite sheets by bond breaking
mechanism since graphite is the combination of multilayer graphene sheets bonded
through week van der Waals force. Exfoliation is a repeated peeling process from
the surface that uses mechanical or chemical energy to break the weak bonds to
provide individual graphene sheets. Though, the mechanical exfoliation processes
can produce few-layer and single-layer graphene sheets but it is challenging to
produce graphene in large quantities for practical use. In micromechanical cleavage,
peeling off the multilayer graphite of ~ 100 µm on SiO2 substrate resulted in single-
layer graphite having thickness ~ 10 µm (Khan et al. 2016). As rightly pointed
4 Graphene-Based Devices for Beyond CMOS Applications 105

Fig. 4.1 Schematic showing graphene zigzag and armchair edges with XPS and Raman spec-
troscopy (reuse with permission from reference (Kim et al. 2018), Copyright © 2018 American
Chemical Society)

Fig. 4.2 a FESEM of graphene flakes with circular holes (partially covered area I, fully covered
area II and fractured from indentation area III, b atomic force microscopy of one membrane in
noncontact mode (diameter = 1.5 mm), c graphene membrane on circular holes are forces for nano-
indentation, d fractured membrane observed through atomic force microscopy, e nano-indentation
set up of graphene over hole synthesized through CVD process, f FESEM image of suspended
graphene over holes, and g curve showing the force as a function displacement in nano-indentation
test; inset shows the AFM image of suspended graphene film before and after fracture (reuse with
permission from reference (Al-Quraishi et al. 2020), copyright © 2020, Taylor & Francis Group)
106 B. Bhowmik

by Jia et al., hydrazine plays an important role in removing oxygen from graphene
nanoribbons which improves the electrical conductivity in it (Jia et al. 2011). To the
similar note, Choi et al. reported the use of hydrophobicity of graphite oxide and
exfoliating it in liquid phase by ultrasonication in aqueous solution to reduce the
film in H6 N2 O at 100 °C for 24 h (Choi et al. 2010). However, it was found that
there was partial reduction and still had some amount of oxygen. Thermally induced
chemical vapour deposition (CVD) proved to be most potential process to reliably
synthesize high-quality large number of single-layer graphene layers as explained by
Khan et al. (2016). Even though the CVD method generates uniform graphene films,
the transfer and patterning of graphene frequently results in the appearance of wrin-
kles and physisorbed polymer residues. As a result, the roughness and morphology
of graphene electrodes have an impact on how effectively organic thin film transis-
tors can perform. In this process, a metal substrate was used that acted as a catalyst.
The carbon precursor used in this method was methane and ethylene where the
molecules form either gas phase at low pressure or liquid phase at high temperature.
Such forms were made for interacting with the substrate surface. Carbon atoms free
from functionalities can be easily attached to the surfaces with the help of suitable
precursor. Diffusion of carbon atoms on the substrate surface leads to the formation
of graphene layers. It was also used for preparing graphene nanoribbons in large
quantities at less time. Graphite filaments of 10 mm length and 10–200 nm thickness
were produced by decomposing CO/H2 /Fe(CO)5 at 400–700 °C as reported by Jia
et al. (2011). TEM image showed formation of uniform graphene sheets where edges
of graphene looks like loop structure when annealing was carried out at 2800 °C.
One can slice graphene sheets to get graphene nanoribbons using scanning tunnelling
microscopy lithography technique. Plasma enhanced chemical vapour deposition is
another method for production of graphene. For example, Choi et al. reported forma-
tion of thick graphite like carbon on Si wafer by dc discharge PECVD method (Choi
et al. 2010). The substrate Mo, W, Ni, etc., are popular substrates with gas mixture
of 0–25% H2 and CH4 . The gas pressure was maintained at 10–150 Torr for the
formation of graphite-like carbon. Solution-based techniques are adopted in order
to avoid the use of substrate (Khan et al. 2016). This method offers considerable
flexibility in terms of compatibility with chemical functionalization and is advan-
tageous for high-yield production. Single-layer graphene sheets with high grade
quality can be obtained from colloidal dispersion of graphite or graphite intercalation
compounds. Colloidal suspension of graphene sheets having horizontal dimensions
of few hundred nm can be obtained by mixing graphite powder in an organic solvent
like N-methylpyrrolidine. It was observed that such graphene sheets offered elec-
trical conductivity of 6500 Sm−1 when optical transparency of 42% was applied.
Self-assembly with layer-by-layer approach for functionalized graphene nanosheets
was used by Park et al. to fabricate graphene thin films (Park et al. 2011). Modified
hummers method synthesized graphene oxide from graphite powder. The dispersion
of carboxylic acid-functionalized graphene nanosheets was combined with hydrazine
and heated to 80 °C for 1 h. Plasma-treated quartz substrate was used to convert the
surface polarity with negatively charge. Slide stainer with programmable facility was
employed to form charged graphene nanosheets in layer-by-layer assembly process.
4 Graphene-Based Devices for Beyond CMOS Applications 107

Such graphene thin films offer sheet resistance (Rsh ) ~ 1.4 k/sq under 80% light
transmittance and proved to have better electrical properties.

Macroscopic Graphene Field Effect Transistors

The first structure of graphene-based transistor that has been reported theoretically
and experimentally was the Schottky barrier type (Kim et al. 2016a). The other
popular topologies such as asymmetric gate, double gate, single gate, dual mate-
rial gate have been explored till date. Graphene has wide applications in electronics
particularly in field effect transistors (FETs) as it is one atomic layer thick and
thus shows superior performance for high speed and high frequency applications
like digital logic applications. Favourable properties of graphene-based TFTs which
attracted worldwide researchers are high carrier mobility, high mechanical flexi-
bility, highly stability at higher temperature, presence of both electron and hole
conduction, high ON–OFF current ratio, high optical transparency and low contact
resistance (Banerjee et al. 2010; Yuan and Shi 2013; Obeng and Srinivasan 2011;
Nag et al. 2018; Singh and Singh 2016). Graphene field effect transistors can be
back gated, top-gated and back-top dual-gated (Nag et al. 2018; Singh and Singh
2016; Wu et al. 2018; Peres 2009; Novoselov et al. 2007). Organic thin film transis-
tors have attained much research due to their potential to produce low-cost, flexible
and light weight electronic devices (Kim et al. 2016a). Recently graphene-based
vertical field effect transistors have gained much interest for high driving current, high
speed of operation, high flexibility, scalability and 3D integration (Wu et al. 2018;
Peres 2009; Novoselov et al. 2007; Balandin 2011; Ovid’ko 2013). It overcomes
the limitations like high temperature activation, high energy ion implementation
and ultraviolet lithography processes for fabricating short channels in transistors.
Structurally, it is different from conventional planner TFTs. Kim et al. reported a
macroscopic model for terminal current simulation of the graphene heterojunction
FET that can be used for applications with low driving voltage, large transconduc-
tance gain and high current density (Kim et al. 2016a). Their work demonstrated
quasi-diode model where gate induced electric field injects the charge from fully
depleted source towards drain through graphene layer. Bottom-gated graphene TFT
(shown in Fig. 4.3a) fabricated on plastic substrates employing graphene oxide as
the gate dielectric demonstrates high optical transmittance with good mechanical
flexibility (Lee et al. 2012b). Here, CVD process was used to fabricate monolayer
graphene sheet which was transferred onto a SiO2 /Si wafer. Reactive ion etching
under oxygen ambient and photolithography were used to create the gate patterns for
the films. The photoresist patterned gate dielectric area was covered with a graphene
oxide gate dielectric layer using the LB method which was subsequently removed
under extremely high vacuum (Lee et al. 2012b). On graphene oxide, the mono-
layer graphene was formed and patterned to serve as the channel. Without using
conventional metal electrodes, the graphene film was monolithically patterned to
provide the source, drain and channels. Similarly, Liu et al. also studied vertical
108 B. Bhowmik

Fig. 4.3 a Bottom-gated graphene/GO transistor [reuse with permission from reference (Lee
et al. 2012b)] and b cross-sectional Si back-gated device structure where graphene as channel
and Au used to form source electrodes and drain electrodes (reuse with permission from reference
(Liu et al. 2015), Copyright © 2015 American Chemical Society)

TFTs based on heterostructure of monolayer graphene with organic semiconducting

thin film (shown in Fig. 4.3b) (Liu et al. 2015). Author employed the field tuning
work function change of graphene for promoting vertical carrier transport across the
intrinsic short channel length for high current density and I ON /I OFF ratio. Vertical
transport of charge carriers across the channel leads to the direction of current flow
in parallel to the electrical field (Liu et al. 2015). The self-passivated channel sand-
wiched between source electrode and drain electrode was used to provide air stability
for both p-channel and n-channel devices (Liu et al. 2015). Length of the channel
in organic thin film transistor is determined by the film thickness. In general, such
organic semiconductor devices offer low carrier mobility operating at frequency near
to 0.4 MHz (Liu et al. 2015). One electrode is transparent to the gate electric field
which aids in the efficient control of carrier transport and prevents the electrostatic
screening effect that would otherwise occur. Basu et al. demonstrated organic thin
film transistors based on monolayer graphene and pentacene (Basu et al. 2014). Their
device showed I ON -I OFF ratio of ~ 105 with mobility ~ 0.1 cm2 V−1 s−1 . This may
be attributed to the effect of source-drain electrode, low barrier energy of graphene
interface and lower contact resistance (Basu et al. 2014). Lower contact resistance in
association with the smaller contact thickness contributes in faster electron transfer
from graphene to channel region through the metal electrodes.

Graphene Nanowire Transistors

Nanowire field effect transistors also known as surround gate field effect transis-
tors comprises of a thin nanowire embedded in the channel of the transistor (Liao
et al. 2010; Kim et al. 2015). This helps in improved carrier mobility than traditional
Si technology for excellent thermal conductivity with high carrier velocity for fast
switching (Kim et al. 2015). According to numerous studies, a common drawback of
top-gated graphene transistors is its higher access resistance that results from imper-
fect alignment of gate electrodes, drain junction and source junction (Nag et al.
4 Graphene-Based Devices for Beyond CMOS Applications 109

2018; Singh and Singh 2016; Wu et al. 2018; Balandin 2011). This can be espe-
cially harmful for short channel devices. The development of self-aligned nanowire
graphene transistors for high-speed application may overcome the limitations of stan-
dard device production methods that frequently result in imperfections in the mono-
layer of carbon lattices. To the similar note, CO2 Si–Al2 O3 core–shell nanowire-based
graphene transistor having self-aligned top-gate reduces the imperfection in lattice
structure (Liao et al. 2010). Self-aligned approach in device fabrication enhances the
device performance by preventing from such lattice degradation. A device with core–
shell nanowire as gate on top of graphene was studied by Liao et al. (2010). Nanowire
diameter was used as the channel length in their study and can be controlled up to
10 nm regime without deviation in graphene high carrier mobility (Liao et al. 2010).
The smaller diameter leads the charge carrier’s inversion changing from surface to
bulk because of quantum confinement. Recently, hybrid nanostructures of graphene-
metal have attracted researchers because of their low electrical resistance, high trans-
mittance and excellent mechanical flexibility and stretchability. Kim et al. fabricated
graphene-based field effect transistors where channel was formed by graphene layer
between source and drain without any physical discontinuity (Kim et al. 2015). The
channel length was varied between 10 and 110 µm and channel width was 5 µm.
The device showed ambipolar behaviour of graphene with ≈ 20–30 V as the positive
charge neutrality points. The charge carrier mobility of graphene for having channel
length 70 µm was found to be 2925 ± 78 cm2 V−1 s−1 (Kim et al. 2015) (Fig. 4.4).

Bilayer Graphene and Substrate Effects

The carbon atoms in bilayer graphene can be stacked in a variety of patterns including
rhombohedral (ABC stacking), Bernal (AB stacking), and hexagonal (AA stacking)
(Choi et al. 2010). It comprises stacking two monolayers with quasiparticles being
large chiral fermions. It features a quadratic low energy band structure that generates
scattering properties that are distinct from those of the monolayer (Abergel et al.
2010). Massive Dirac fermions properties were evident in bilayer graphene where
mass of charge carriers is finite (Peres 2009; Novoselov et al. 2007; Balandin 2011;
Ovid’ko 2013; Lee et al. 2008; Jia et al. 2011; Khan et al. 2016; Choi et al. 2010).
Neutral bilayer graphene has low energy band structure without any gap that shows
a wide range of second-order phenomena (Choi et al. 2010; Abergel et al. 2010). It
has certain properties that are similar to monolayer graphene like very high electron
mobility and high mechanical stability. Bilayer graphene possesses parabolic bands
having all the properties of gapless semiconductors (Choi et al. 2010; Liao et al.
2010). It also possesses a property that has tunable band gap by variation of potential
difference between the two layers and can be easily controlled by a top gate or
by external doping. Asymmetry between the two layers of bilayer graphene can be
achieved by biasing of gate voltage which changes the carrier concentrations at the
channel. This technique leads to the formation of semiconducting gap in bilayer
graphene as well as restoration of normal anomalous quantum hall effect (Choi
110 B. Bhowmik

Fig. 4.4 a Schematic of graphene and SiNW devices on integrated circuits, b Single layer graphene
FET image in optical study, c SiNW-Gra-FET d Raman spectrum of the graphene (reuse with
permission from reference (Cohen-Karni et al. 2010), Copyright © 2010 American Chemical
Society)

et al. 2010; Kim et al. 2015). Such unique feature of tunability along with excellent
electron mobility and easy fabrication techniques has led to many applications of
bilayer graphene.
Substrates can be of two types, viz (i) nonconductive bendable substrates like
polymers, papers, and textiles to help the active materials that must have the ability
to deform under stress/strain, and (ii) conductive substrates that are highly conductive
like carbon nanotubes and graphene films. Properties of electromechanical devices
can be influenced by the quality of graphene and the substrate over which it is
deposited. There are certain metals like Pd, Ni, and Co that can easily be attached
to graphene, whereas some other materials such as Au, Pt, Cu, Ag and Al do not
combine easily on graphene (Zhan et al. 2014). Zhan et al. reported on Cu and Ni as
preferred substrate material possibly due to the good matching of Cu and Ni lattice
constants with the graphene lattice (Zhan et al. 2014). However, atomic structures of
Cu and Ni may alter the structure of the graphene, cohesive energy and strength (Zhan
et al. 2014). Graphene and metal substrates junction can be beneficial for tuning the
interfacial properties. Zhan and co-workers also reported that effective gating from
substrates is inferior to effective doping from the underlying substrate. In addition, the
interaction between single-layer graphene with substrate leads to charge exchange
at the interface that creates dipole. Movement of such dipole and their direction
depends on the contact potential developed across the graphene-substrates junction
4 Graphene-Based Devices for Beyond CMOS Applications 111

(Lee et al. 2012b; Liu et al. 2015; Basu et al. 2014; Liao et al. 2010; Kim et al. 2015;
Abergel et al. 2010; Zhan et al. 2014).

Graphene MOSFET for RF and CMOS Logic Applications

Graphene MOSFET for CMOS Logic

Complementary metal oxide semiconductors (CMOS) used in modern digital logics

is based on silicon technology. Scaling of MOSFET device is the governing factor for
the growth of digital logic design. With the size scaling, complexity and compact-
ness in the design increase by many folds. In accordance with Moors laws, inte-
grated circuit complexity doubles every 18 months and similar tendencies were
also observed in case of performance of ICs. However, in recent days scaling of
MOSFET is approaching its limit and does not obey the Moore’s law (Schwierz
2010a). Such limitation necessitates looking for alternative approach such as new
material MOSFET devices for future application.
Figure 4.5a shows the FET transistor having source-drain electrode, current
conducting channel region, a barrier region separating the channel and gate elec-
trodes. Conductivity of conventional FET channel was controlled by gate voltage.
Therefore, for application in high-speed circuits, FET should have short gates and
fast channel carriers to respond quickly for any variation in V GS (Schwierz 2010a).
However, FET with short gate suffers from short channel phenomena including
threshold voltage roll off, impaired saturation of drain currents and drain-induced
barrier lowering (Schwierz 2010b). As per scaling theory statements, the FET with
thin barriers and thin gate-controlled channel regions are resistant to the effects of
short channels (Schwierz et al. 2010). Also, the silicon MOSFETs can switch between
the on-state and the off-state that enables CMOS technology to have low static power
dissipation (Schwierz 2010b). As a result, the new material used to replace the silicon
MOSFETs used in CMOS logic must have good switching characteristics as well as
I on /I off ratio. It is investigated in the transfer characteristics of the work in Schwierz
(2010a) that, switching behaviour can be assessed by subthreshold swing (SS) and
terminal transconductance, gmt of the MOSFET device (Schwierz 2010a). There is
a single-layer graphene having two-dimensional structures with lattice constants of
regular hexagons. The bond length between the carbon atom is L b 1.42 Å and the
lattice constant, a, is 2.46 Å (Schwierz 2010a). Other is large-area graphene which
is a semimetal. It is unsuitable to be used as channels of transistor due to zero band
gap. However, the band gap of graphene can be modified. It offers many proper-
ties to be used in future MOSFETs (Schwierz 2010a). The nm-gate graphene and
the narrowest channel which is only one atomic layer thick are both resistant to
short channel effects. It can be scaled further than silicon MOSFET limitation. The
scale length is not applicable for gapless graphene MOSFETs (Schwierz 2010b). At
room temperature, high carrier mobility is offered by graphene. Exfoliated graphene
112 B. Bhowmik

Fig. 4.5 Graphene nanoribbon FET based a NOT Gate and b NAND Gate (reuse with permission
from reference (Gil-Tomàs et al. 2019), Copyright © 2019 by the authors. Licensee MDPI, Basel,
Switzerland)

depicts mobilities of 10,000–15,000 cm2 V−1 s−1 . The highest range of mobilities
was found to be 40,000–70,000 cm2 V−1 s−1 (Chen et al. 2008). It was investigated
that at high fields, the electron velocity does not reduce drastically in graphene and
the nanotube as compared to the iii–v semiconductors (Schwierz 2010a). Conse-
quently, graphene and nanotubes appear to be superior to traditional semiconductors
in terms of high-field transfer.

Graphene MOSFET for RF Applications

Graphene possesses high charge carrier mobility which is advantageous for obtaining
fast switching as well as ‘on’ current (I ON ). It induces a large off current because
of zero band gap (Lemme et al. 2014). FET used in RF applications is generally
on-state biased (Koswatta et al. 2011). Weak RF signal to be amplified must be
fed into the transistor input. Amplification of the input signal can be augmented
through the increase in current gain as well as power gain which decreases with the
increase in frequency (Lemme et al. 2014). The performance of the RF transistor
is decided by the cut-off frequency ( f T ) for that current gain magnitude reduced to
unity and the maximum oscillation frequency ( f max ) at the point where power gain
equals unity (Lemme et al. 2014). Power gain and f max are prominent parameters
in RF applications than current gain and f T . The fastest graphene MOSFET having
240 nm gate was reported to have higher cut-off frequency of f T = 100 GHz than the
same gate length of silicon MOSFETs (Lin et al. 2010). RF MOSFET suffers from
unsatisfying saturation behaviour which effect transistor cut-off frequency, intrinsic
gains, etc. (Schwierz 2010a; Lin et al. 2010), while silicon MOSFETs can operate
with weak current saturation (Schwierz 2010a).
4 Graphene-Based Devices for Beyond CMOS Applications 113

Graphene MOSFET for Nonmainstream Applications

In recent days, research is going on towards utilization of graphene in place of

conventional semiconductor where it performs poorly (Schwierz 2014). In partic-
ular, materials used in flexible and printable electronics were organic semiconduc-
tors. They are printable and bendable but offer lower carrier mobility (0.01–1.0 cm2 /
Vs). Therefore, fast and low operating voltage device cannot be possible from organic
semiconductors (Schwierz 2014). The mono-crystalline conventional semiconduc-
tors, i.e. group III-V compounds and silicon are found to be rigid and also not suitable
for the above application (Schwierz 2014). However, graphene transistors are found
to be widely used as an alternative material for printable and flexible electronics.
Figure 4.6a–d shows one of such graphene FET structure, FESEM image of struc-
ture, resistance variation as a function of gate voltage and drain current as a function
of gate voltage (Kim et al. 2016b). Large area graphene was found to be bendable
and easily depositable over flexible substrates (Lee et al. 2012a). Also, graphene
inks were proved to be better for printed electronics. Mobility of charge carriers for
graphene layer over flexible substrates and printed graphene structures were found
to be 1000–4930 cm2 /Vs and 100–365 cm2 /Vs, respectively (Lee et al. 2012a; Wang
et al. 2010). Some of the challenging results of graphene transistors deposited over
flexible substrates were evident in the work of ref Petrone et al. (2013). Graphene
MOSFET having 500 nm gate deposited on polyethylene naphthalate substrate shows
a cut-off frequency of f T of 10.7 GHz and a maximum frequency of oscillation f max
of 3.7 GHz (Petrone et al. 2013). Graphene-based GHz circuits deposited on plastic
substrate were found to be faster than the organic transistors. Moreover, fabrication of
printed graphene was possible without lithography. It opened the path for graphene
to have low-cost printed circuits. The gapless big area graphene channels used in
both the flexible and printed graphene MOSFETs does not turn off (Schwierz 2014).

Graphene Nanoribbons-Based Transistors

Graphene nanoribbons are considered as one of the suitable nanostructures to be

used as transistor channels. Some of the similar properties of graphene with the
carbon nanotubes are stronger mechanical strength, better electrical properties,
higher carrier mobility and high thermal conductivity (Rhee 2020). It is more control-
lable than carbon nanotubes. However, graphene was processed differently than
carbon nanotubes but similar with silicon processing processes (Rhee 2020). It offers
very high current conducting capability, e.g. 1000 times larger than copper (Radsar
et al. 2021). However, zero band gap properties limit its use in integrated circuits.
However, opening the band gap in graphene could be possible through the one direc-
tional quantum confinement technique (McCann 2006). It was observed that energy
gap opening in graphene obeys exponential nature leading to the increase in effective
mass with decrease in mobility. Band gap of graphene nanoribbons varies inversely
114 B. Bhowmik

Fig. 4.6 a Showing schematic of TGFET structure, b FESEM of TGFETs where graphene was
deposited between the two metal strips (Al, Pt) electrodes, c resistance of the TGFETs as a function
of gate voltage; inset showing formation of P-N-P junction corresponding Fermi level change at the
graphene junction under different gate voltage and d drain current versus gate voltage (reuse with
permission from reference (Kim et al. 2016b). This work is licensed under a Creative Commons
Attribution 4.0 International License.)

with its width (Radsar et al. 2021). At room temperature, 5-nm-width graphene
nanoribbons offer an energy band gap of 0.5 eV. The graphene nanoribbons are clas-
sified into two types: (i) armchair and (ii) zigzag edge terminated ribbons as shown in
Fig. 4.1a. Both of these types may be either semiconducting or semimetallic (Lemme
2009). In armchair ribbons, the shift from 2D graphene to 1D graphene results in the
development of a band gap via the quantum confinement process (Radsar et al. 2021;
McCann 2006; Rhee 2020; Lemme 2009). The band gap value also depends on the
atomic number ‘N’ across the ribbon. Nanoribbons with N = 11 is semi-metallic,
i.e. N is equal to 3 m−1 , while m is an integer whereas nanoribbons with atomic
numbers 12 and 13 mostly possess semiconducting nature (Lemme 2009).
4 Graphene-Based Devices for Beyond CMOS Applications 115

Alternative Graphene Switches

Graphene or graphene oxide (GO) and reduced graphene oxide (RGO)) are frequently
employed for switching memory fabrication due to its larger surface area and
better electrical and mechanical properties (Hong et al. 2011; Pradhan et al. 2016).
Graphene and related materials have been used for resistive switching memory.
Resistive switching memory offers higher speed at lower operating voltages. In
addition, switching devices possess excellent ON–OFF current ratio of the order
of 103 with brilliant flexibility without shortage of memory performance (Hong
et al. 2011; Pradhan et al. 2016). Graphene oxide is used as insulating layer in the
metal–insulator-metal capacitor structure of resistive memory. In this structure, to
increase the adherence of graphene oxide to the bottom electrode, indium tin oxide
(ITO) was placed on glass or a SiO2 substrate and subjected to UV radiations (Hong
et al. 2011). For maintaining lower operating voltage on electronic switch, one has
to keep adequate ON/OFF current ratio of the devices. The monolayer graphene
with low elastic modulus and low adhesion energy was found to be perfect material
for electromechanical switches. Various two-terminal and three-terminal switches
have been designed employing graphene for MEMS/NEMS applications. 2T switch
has the advantage of simple structure, but it has some disadvantages such as oper-
ating voltage V DD is greater than pull in voltage V pi . The adhesion force (F adh )
which is proportional to contact area (Ac ) is difficult to control. 3T switches are
more complex structures that overcomes the limitation of 2T switch. 3T switch can
be actuated for both V G > 0 and V G < 0 in conventional FET structure (Szkopek
and Martel 2021). RGO is commonly utilized in applications involving non-volatile
switching memory due to its endurance, good retention, scalability and large surface
area properties. With an ON/OFF ratio of two orders of magnitude and an operating
threshold switching voltage of less than 1 V, the manufactured RGO metal memory
device displayed dazzling switching capabilities (Pradhan et al. 2016). Currently,
GO is used as a promising material for resistive random access memory applications
due to its good resistive switching performance, high flexibility and easy processing.
In this, 0 and 1 states are used to categorize high resistance states. High switching
uniformity assures reading and writing operation (Schwierz 2010b). Huge numbers
of oxygen-functional groups such as carbonyl, epoxide and hydroxyl groups are
present in graphene oxide and can move around in a strong electric field. There is a
limit to how much more oxygen-functional groups can exist because too much oxida-
tion would lead the stacked GO to decompose into quantum dots. Consequently, it
could be hard to attain complementary resistive switching by adjusting the amount of
oxygen defects that are accessible for the production of conducting filaments in GO
films (Shi et al. 2018). Graphene heater-based on-chip optical switches with great
speed and efficiency are another option. In the fabrication of optical switches, a near-
infrared camera was used to examine the graphene microheater’s direct interaction
with the resonator. The transmission spectra showed that this device had high heating
efficiency of 7.66 K m3 /mW and high wavelength tuning efficiency of 0.24 nm/mW.
At 100 kHz, they evaluated the real-time high-speed operation with response and
116 B. Bhowmik

recovery time of 1.2 µs and 3.6 µs, respectively. The graphene-based optical switch
was able to modulate signals at high speeds. It is expected that high-performance
silicon photonic and optoelectronic applications would utilize these graphene-based
optical switches on devices with high efficiency and speed (Nakamura et al. 2022).

Graphene Electronics

Due to unique electrical and optoelectronic properties of graphene, it devoted much

more attention in electronics application like solar cell, long lasting batteries, circuit
boards and liquid crystal displays. As we know that conductivity of graphene is
very high as graphene is a zero band gap material which is ideal for high-speed
electronics. In the case of data storage or maintaining the capacity of data storage
devices, the device made up of graphene oxide was ten times larger than that of 16 GB
USB flash drives. Graphene exhibited a high internal surface area of 2630 m2 g−1 .
Most supercapacitor uses graphene material to store charge as supercapacitors are
energy storage technologies that enable higher currents than conventional capacitors
(Randviir et al. 2014). In LCD, smart windows and organic light emitting diode
(OLED) display devices, two flexible polymers and graphene electrodes are joined
by a layer of liquid crystal. Mobile and tablet devices with flexible touch panels are
among the applications for such technology. Currently, OLED technology uses ITO
as electrode which are brittle and requires less supply. Further, research has been
done on using flexible graphene OLED as counter electrodes (Randviir et al. 2014)
(Fig. 4.7).
Graphene material can be used in solar cell or photovoltaic cells. For long-term
stability of photovoltaic cells (against light illumination, temperature and air), the

Fig. 4.7 CMOS technology scaling road map [following the reference (Bavel 2019)]
4 Graphene-Based Devices for Beyond CMOS Applications 117

conducting electrode like graphene has been the preferable choice by the researchers.
Graphene can be utilized as conductive electrode for solar cell as it possess highly
transparent properties. Power conversion efficiency of 10–15% is evident from
hybrid heterojunction solar cells consisting of graphene and inorganic semiconduc-
tors whereas perovskite solar cells fabricated with graphene alone offer efficiency
of 15.6% (Singh and Nalwa 2015). At the beginning of solar cell fabrication, ITO
and fluorine-doped tin oxide (FTO) were mostly used as electrodes but ITO and
FTO has a drawback of being sensitive to high and low pH with high cost because
of insufficient availability. It is also brittle in nature so that it can easily crack on
flexible substrates. In replacement, graphene is used as electrode in flexible organic
solar cells (Mahmoudi et al. 2018).

Conclusion

Being the gapless semiconductor, single-layer atom graphene sheets having linear
energy spectrum possess many unusual electronic properties such as inconsistent
quantum hall effect and non-appearance of Anderson localization. As the demand of
the electronic devices is becoming stringent in day to day life, more and more efforts
are required to be imposed to synthesize graphene with different nanostructures.
Fundamental research of graphene or composite form of graphene with other mate-
rials towards new applications requires understanding of integrated spectroscopy
characterizations techniques such as scanning tunnelling microscopy, transmission
electron microscopy and Raman spectroscopy. It was found that, at near Fermi level,
zigzag edges have high electron density states which distinguish them from the
armchair edges. As far as graphene nanostructure is concerned, graphene nanorib-
bons can be produced in large scale and can be proved to be a significant nanomate-
rial for the designing of logic gates and radio frequency devices. On the other hand,
graphene nanowires and quantum dots show the potentiality towards fabrication of
electronic switches due to their one-dimensional carrier flow through the confinement
path.

Acknowledgements This work is supported in part by Ministry of Micro, Small & Medium
Enterprises (MSME), Government of India, IDEA Heckathan 2022, Project ref No. IDEAJH003262.

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Chapter 5
Other Potential 2-D Materials for CMOS
Applications

Poonam Subudhi and Deepak Punetha

Abstract New advancements in thin film two-dimensional (2D) materials have

resulted in an assortment of intriguing innovative techniques enabling CMOS
nanodevices and energy production. The number of devices that focus on non-
graphene monolayers has significantly increased due to the novel characteristics and
applications arising from two-dimensional confinement. An attempt has been made
here to comprehensively describe the present state of the technology and future
possibilities for 2D materials other than graphene, which includes an emerging
class of transition metal dichalcogenide materials, synthetic boron nitride, and an
allotrope of phosphorus known as black phosphorous. Such materials are currently
being considered for both high and low-end application areas. The assessment of
multiple synthesis approaches with the ability to produce ways of regulated large-
scale synthesis is described together with an overview of the structural and physical
characteristics of 2D materials. By leveraging the novel qualities resulting from these
materials, state-of-the-art applications are also summarized. Such devices would
drastically lower device dimensions as well as power consumption, which is required
for the development of future sustainable technology.

Keywords Thin film two-dimensional (2D) materials · CMOS nanodevices ·

Transition metal dichalcogenides · Synthesis approaches · Sustainable technology

P. Subudhi
School of Advanced Sciences, Vellore Institute of Technology (VIT) University, Chennai 600127,
Tamil Nadu, India
D. Punetha (B)
Department of Electronics and Communication Engineering, Motilal Nehru National Institute of
Technology (MNNIT) Allahabad, Prayagraj, Uttar Pradesh 211004, India
e-mail: [email protected]

© The Author(s), under exclusive license to Springer Nature Singapore Pte Ltd. 2024 121
S. Singh et al. (eds.), Beyond Si-Based CMOS Devices, Springer Tracts in Electrical and
Electronics Engineering, https://doi.org/10.1007/978-981-97-4623-1_5
122 P. Subudhi and D. Punetha

Introduction

Silicon readily dominates the assiduity of semiconductors or microelectronics by

developing new technologies based on silicon setting a first step toward mass
manufacturing. Several materials have been sought to replace silicon throughout
the years, including compounds with enhanced “charge carrier mobility” akin to
“germanium” and colored “group III–IV elements”. However, none have been able
to achieve widespread commercial success and have only made improvements in
specific specialized markets. Achromatism appears to have been accomplished by
further silicon scaling, however these lower scales limit carrier mobility and provide
significant challenges because of growing unpredictability and trust ability issues.
It is thus expected that 2D materials would advance significantly in the upcoming
years. The scientific world has been paying close attention to 2D material research
in recent years. Free charges in a two-dimensional (2D) atomically thin material
can move in the other two spatial dimensions but remain fixed in one. Due to this
characteristic, 2D materials differ from 3D or bulk materials and can perform new or
improved functions. A 2D electron gas that is free to move in two dimensions was first
produced in the late 1970s in the group of III–V semiconductors. An epitaxial depo-
sition methodology called molecular beam epitaxy produces electron gas with high
mobility of more than 10 × 106 cm2 /Vs (Umansky et al. 1997). This property charac-
terizes its application in transistors to produce CMOS or high-frequency integrated
circuits that may be further used to create antennas, sensors, aerospace applications,
and other devices. Although 2D electron gas has enormous potential for electronics
in the future, widespread utilization will present challenges. It is brought on by the
intricate fabrication process, high power usage, constrained scalability, temperature
sensitivity, and expensive manufacture. To get around these restrictions, 2D mate-
rial research was rekindled. In 2004, the crystalline carbon element graphite under-
went exfoliation, yielding graphene, a thin sheet-like structure (Kumar et al. 2023a).
Superior to materials with higher thermal conductivity, two-dimensional graphene
demonstrated exceptional qualities in terms of strength, lightness, flexibility, high
optical transmittance, and electron-carrying speed. Due to this material’s exceptional
electrical properties, transistors and ultra-wide bandwidth optical modulators may
be made more quickly and easily than those that are currently on the market. As a
result, graphene is a miraculous substance with effective optical and electrical qual-
ities (Subudhi and Punetha 2023a). Although graphene is known for its formidable
properties, there are several restrictions on its use in electrical applications (Radisavl-
jevic et al. 2011; Kumar et al. 2017, 2023b). These drawbacks include the absence of
an energy bandgap, innate flaws, and a notable decrease in carrier mobility brought
on by surface adatoms or defects-induced scattering. “Transition metal dichalco-
genides (TMDs)” are a class of materials that have encouraged scientific interest in
recent years. The TMDs are layered materials with hexagonal structure and molecular
formula MX2 . The “transition metal atoms” (M: Nb, Mo, Ta, W, etc.) are sandwiched
between two layers of “chalcogen atoms” (X: Se, Te, S), forming a TMD material
with isomorphic characteristics and P63/MMC space symmetry group (Kumar et al.
5 Other Potential 2-D Materials for CMOS Applications 123

2023a). In addition to TMD compounds, materials such as “black phosphorus (BP)”

and “hexagonal boron nitride (h-BN)” are also exhibiting similar semiconductor
properties. Hexagonal boron nitride represents the isomorph of graphene with the
difference that it has boron and nitrogen atoms instead of carbon, whereas black
phosphorus is a material producing mono layers of phosphorene. Such materials are
easily exfoliated into two-dimensional monolayer flakes from a bulk configuration
due to the presence of strong and weak in-out plane bonding. Over 150 exotic layers
from bulk materials of MoS2 , MoSe2 , BN, WS2 , WSe2 , germanene, and their hybrids,
can be exfoliated into atomic thick layers. The emerging 2D materials are creating
a new era of research since these are more dependent on dimension rather than size.
Furthermore, the exfoliated or atomic layer of 2D material can be categorized into
metallic, semi-conducting, or insulating based on the “chemical composition” and
configuration of its structure. The group of 2D TMD materials and black phosphorus
possess semi-conducting characteristics, while “hexagonal boron nitride” is a “wide-
band gap insulator”. These characteristics make such 2D materials more suitable for
applications in transistors, sensors, photodetectors, battery electrodes, topological
insulators, valleytronics, and other devices (Radisavljevic et al. 2011; Kumar et al.
2017, 2023b; Zhang et al. 2014; Subudhi et al. 2023; Dixit et al. 2018; Punetha and
Pandey 2019a). The advantage of such 2D materials over conventional silicon is
mainly its inherent flexibility that can be used to produce flexible devices.

Emerging 2D Materials with Embryonic Prospect

New two-dimensional (2D) materials with remarkable mechanical, chemical, and

physical characteristics, such h-BN, BP, and “transition metal dichalcogenides”, are
drawing interest from all over the world. The following section explores the various
properties of emerging 2D materials.

Transition Metal Dichalcogenides

The two-dimensional “transition metal dichalcogenide materials (TMDs)” are

compounds typically composing three layers: the upper and lower layers are made
up of “chalcogen atoms”, and the “middle layer” is made up of “transition metals”.
These individual layers form a layered crystal structure by being bound to each
other by “weak van der Waals force” (see Fig. 5.1). The typical thickness of the
structure is 6–7 Å with a hexagonally packed plane. Since transition metals build
up such materials, based on the group V (Ta, Nb, and V) metals, metallic TMDs
are produced, while based on group VI (W and Mo), semiconducting or metallic
crystal structures are formed. Thus, the different chemical compositions affect the
crystal structures leading to different optical and electrical properties. Furthermore,
the properties can be affected by the number of layers and their sequence (Chhowalla
124 P. Subudhi and D. Punetha

et al. 2013; Punetha and Pandey 2019b). Semi-conducting TMDs are one of the most
well-known types of TMDs; nonetheless, as their thickness decreases, they undergo
peculiar changes in their electrical band structure. When transition metal dichalco-
genides are thinned to an atomic monolayer, their bandgap shifts from indirect to
direct. Normally, these materials are found in bulk and have an indirect bandgap
(Mak et al. 2010). In bulk form, the “conduction band minimum” is at halfway along
the [-K symmetry lines, while the “valence band maximum” is at the [-point. The
states at the K-point are constant because the transition metal atoms have localized
d-orbitals. But in the case of chalcogen atoms, the states at the point are extremely
sensitive to the layer numbers since the p-orbitals of chalcogen atoms cause strong
interlayer coupling. The well-known transition metal dichalcogenide materials are
MoSe2 , WS2 , WSe2 , and MoS2 . The “band gap energies” of such TMDs are typi-
cally in the range of 1–2 eV (Kang et al. 2020). Other TMDs, such as PtSe2 and
HfS2 , also have distinctive electronic properties. In mono and bilayer form, PtSe2 ,
for instance, exhibits a “wide band gap range” of 0.3–1.2 eV, suggesting its potential
use as a broadband photodetector. Strong photoluminescence, “strong light-matter
interaction”, high “exciton binding energy”, and “valley polarization” are only a few
of the extraordinary qualities that monolayer TMDs have displayed (Mak et al. 2013;
Britnell et al. 1979).
Because of its high mobility, inherent band gap, and quantum confinement,
“monolayer molybdenum disulfide (MoS2 )” is proving to be a potential contender
for future nano and optoelectronics (Radisavljevic et al. 2011; Punetha et al. 2018).
“2D MoS2 -based FETs” will be extremely advantageous for electronics with lower
power requirements in “post-Si-based technologies”. Apart from its use in transis-
tors, MoS2 has demonstrated its effectiveness in Li-ion batteries, photocatalysts,
sensors, photodetectors, solar cells, and several other applications (Shukla et al.
2023a). For scalable applications, MoS2 and other TMD isomorphs have been thor-
oughly studied in this area (Bhandavat et al. 2012). MoS2 is an sp3 -bonded solid
structure composed of two Mo-S atoms covalently bonded in a “layered structure”

Fig. 5.1 Crystal structure of a layered MoS2 and b top and side view of the structure (He and Que
2016)
5 Other Potential 2-D Materials for CMOS Applications 125

with interlayer “van der Waals” interactions linking the single layers together. It
has a non-centrosymmetric structure with “long-range periodic order” (Splendiani
et al. 2010). MoS2 is primarily composed of hexagonal honeycomb arrangements
of atoms, much like graphene, with the Mo layer sandwiched between two S layers
that occupy separate sublattices. Within this configuration, every Mo atom possesses
a triangular prismatic coordination. The MoS2 unit cell was discovered to have a
vertical gap between S layers (“c”) of 3.11 Å and a lattice parameter (“a”) of 3.12 Å,
resembling a honeycomb (Ting et al. 2012). Nonetheless, depending on the number of
layers, MoS2 ’s band gap fluctuates from 0.8 to 1.8 eV, according to computer calcu-
lations and experimental methods. Because of the previously reported third-orbital
interactions, a variety of TMD materials share characteristics with MoS2 (Mattheiss
1973). However, in the visible to near-infrared light spectrum, carrier production
causes dimension-dependent band gap changes, which raises the possibility of using
these materials in ecologically benign solar energy conversion systems (Abrams and
Wilcoxon 2005).

Boron Nitride

The two-dimensional monolayered boron nitrides (BN), sometimes referred to as

boron nitrene or boronitrene, white graphene, are isostructural to “graphene”. It is
an insulating material with a high band gap of between ∼5.0 and 7.0 eV and a
hexagonal shape. They have a high breaking voltage as a result, usually ∼ 1 × 106
Vm−1 . However, the precise value varies slightly depending on the amount of convo-
lution layer in BN. Hexagonal boron nitride nanoribbons (h-BNNRs), which exhibit
edge-dependent quantum confinement, exhibit anisotropic electrical and “magnetic
characteristics” based on their edge forms (armchair or zigzag), just like graphene.
Consequently, the band gap and electrical transport properties of h-BNNRs show
oscillations akin to those of graphene nanoribbons (GNRs) depending on the width,
edge structure, and chemical functionalization (Zhang and Guo 2008; Mukherjee and
Bhowmick 2011; Xu et al. 2010). Experimental evidence indicates that the “optical
band gap of h-BNNSs” in this situation is 6.0 eV. Thus, through the visible area,
“low-dimension h-BNNSs” exhibit excellent transparency. Additionally, the “Stark
Effect”, which alters the “band gap of h-BNNSs” by altering the “number of layers”,
the width, or the application of an external field, is well-known (Watanabe et al. 2004;
Kim et al. 2012). Similar to graphene, the “band gap of 2-D h-BNNS” nanostructures
may be altered by applying longitudinal strain, introducing defects, and molecule
functionalization. The “reversal effect” refers to the fact that although the “band gap
of h-BNNSs” decreases with functionalization, the “band gap of graphene” rises with
“chemical functionalization” (Wang 2010; Anota et al. 2012; Li et al. 2008). Apart
from their association with the electrical, optical, magnetic, and dielectric properties
of h-BNNSs, the physical features of 2-D h-BNNSs are significantly influenced by
their crystallinity, stacking order, and defects (Anota et al. 2012; Li et al. 2009).
Thus far, 2-D h-BNNSs have proven to be an efficient addition to a wide range of
126 P. Subudhi and D. Punetha

applications, such as energy storage, composites, deep ultraviolet lasing, substrates

for graphene electronics, catalysts, and piezoelectric devices (Qi et al. 2012; Wang
et al. 2011; Zhi et al. 2009).
The term “white graphite” is commonly used to describe boron nitride because
of the similarities in the crystallographic properties of the two materials. Hexag-
onal forms of BN, like graphite, feature a “planar honeycomb layered lattice” with
“interlayer van der Walls interactions” and strong interatomic (B–N) covalent bonds.
Because of its “interatomic bond distance” of 2.51 Å and “interlayer distance” of
3.35 Å, BN and graphite are almost isostructural. H-BN isomorphs are the softest
of the BN isomorphs and have a variety of characteristics, much like graphite. One
atomic layer of h-BN, sometimes referred to as boron nitride nanosheet (h-BNNS),
boron nitrene, or boronitrene, white graphene, has certain intriguing characteristics.
The only thing that separates “graphite and h-BN” is the interlayer stacking sequence,
which is superposed. As seen in Fig. 5.2a, every “B and N atom” in the instance of
h-BN is positioned exactly adjacent to each other in the area between the two layers.
Nonetheless, the graphite layers are divided from one another by a half-hexagon. A
single graphene layer and h-BNNS are identical except for the half of nitrogen atoms
that separate them. As the width reduces from the submicron to the nanometer scale,
boron nitride nanosheets also display a ribbon structure, as shown in Fig. 5.2b–d. As
h-BNNRs have armchair and zigzag edge configurations that impact their charac-
teristics, just like graphene. Due to the structural similarities between graphene and
BNNS, carbon can easily take the place of boron and nitrogen to create a new mate-
rial known as carbo-boron nitride (CBN). The connection of BN and graphene is the
main structural difference between them. Covalent and ionic bonding are combined
in the in-plane bonds between B and N atoms due to their differing electronegativity.
C–C atoms can only establish covalent interactions in graphene, though. The inter-
layer stacking sequence, which establishes whether the band structures are direct or
indirect, is entirely linked to the band structure and band gap of h-BN, per recent
research (García-Miranda Ferrari et al. 2021).
Black Phosphorous
Straight band structure for all atom-thick layers and enhanced carrier mobility, black
phosphorous (BP) has garnered a lot of interest as a 2D material for CMOS technology
(Castellanos-Gomez 2015). It has a single element of phosphorus atoms arranged
in layers. Because phosphorous atoms contain five outer shell electrons, BP’s puck-
ered orthorhombic structure of the D2h18 point group shows lesser symmetry than
that of other group IV counterparts, including graphene. Predictions indicate that
BP might potentially bridge the gap between graphene and TMDs because of its
broad thickness-dependent bandgap range of 0.3–2.0 eV. In contrast to graphene, BP
has notable optical and electrical anisotropy. The conductivity ratio along the two
directions can reach up to 1.5 from hole mobility of 1000 cm2 /Vs along the armchair
direction and 600 cm2 /Vs along the zigzag direction at 120 K (Xia et al. 2014). Given
its broken symmetry structure, BP is more adaptable for possible usage in CMOS
and optoelectronic devices than TMDs since it has a direct band structure throughout
the whole thickness range.
5 Other Potential 2-D Materials for CMOS Applications 127

Fig. 5.2 Illustration of boron nitride structural models: a interlayer stacking of BN and a “single
nanosheet of hexagonal BN nanosheets consisting of armchair and zigzag edges”; b represents
zigzag and armchair BN nanoribbons that resemble the nanostructures of graphene (García-Miranda
Ferrari et al. 2021)

Synthesis Process of 2-D Materials

Lately, several methods for producing 2-D materials have been proposed. Here, we
look at these procedures from the perspective of “CMOS integration”. Two different
approaches may be used to synthesize 2-D materials: top-down techniques and
bottom-up procedures. Using external energy sources like mechanical or ultrasonic
energy, the top-down strategy entails removing one or a few atomic layers from the
main material to create 2-D nanostructures. In contrast, the bottom-up approaches
create 2-D nanostructures by depositing atoms onto a substrate through chemical
and/or heat interactions. Mechanical exfoliation, chemical exfoliation, “chemical
synthesis processes”, and “thermal chemical vapor deposition” are the most popular
methods for creating “2-D nanostructures (CVD)”. For the synthesis of “2-D nanos-
tructures”, other techniques such as high-energy electron beam irradiation, carboth-
ermal reduction, laser ablation, and laser thinning have also been proposed. This
section provides a quick summary of the 2-D nanostructure synthesis methods,
emphasizing both their benefits and drawbacks. After that, a summary of the “top-
down and bottom-up synthesis” procedures used to create novel 2-D nanostructures
is given.

Top-Down Approach

Mechanical Exfoliation

Mechanical exfoliation uses force to remove many layers from the primary crystal.
One or more graphene layers were initially generated using this technique on a bulk
crystal of graphite (Shim et al. 1979). Because of its straightforward mechanism,
128 P. Subudhi and D. Punetha

adaptability, affordability, and ability to work with nearly any kind of 2D material,
mechanical exfoliation has become a very common procedure. Natural bulk crystals
can be used to create high-quality monolayers of 2D materials, however this is an
unscalable and time-consuming process (Yuan et al. 2015). “Scotch tape, ball milling,
roll milling, gel-assisted exfoliation, metal-assisted exfoliation”, and layer-resolved
splitting are examples of “mechanical exfoliation techniques” (Kang et al. 2020).
Since TMDs such as MoS2 in 2D form has the potential to replace silicon in upcoming
CMOS technology, several reports have demonstrated the successful synthesis of 2D
nanosheets using mechanical exfoliation. In the same vein, a minimal number of
reports have exhibited the process for boron nitride. The most popular mechanical
exfoliation technique that produces one to many layers of 2D crystalline flakes while
preserving the crystal’s structure and characteristics is the scotch tape method. The
performance of the first transistor made of a single-layer MoS2 flake was reported
using this technique (Radisavljevic et al. 2011). In this method, a small piece of scotch
tape is placed sticky side down onto the bulk 2D material and then gently lifted away.
To improve the adhesion between the substrate and thinner 2D material layers, the
tape is then gently pushed into position after being carefully put onto a substrate
(such as SiO2 ). The tape is carefully pulled off, exposing 2D material monolayers
on the substrate (Novoselov et al. 2005). In the case of MoS2 and all other TMD
materials, the interlayer bonds, like those in graphite, are nearly 100 times weaker
than “in-plane primary bonds”, making it easy to peel a single layer from the bulk
while keeping “in-plane bonds intact”. The optical properties of exfoliated layers
obtained using the scotch tape method can be analyzed using optical microscopy.
Further, combining “optical microscopy” or “transmission electron microscopy” with
“atomic force microscopy” reveals the exact number of exfoliated layers.
A gold-assisted exfoliation technique combines thermal release tape with the
gold layer that has been deposited (100–150 nm). Around 500 µm2 of the exfoliated
monolayer”, MoS2, may be found (Desai et al. 2016). When the procedure and
surface for the “gold exfoliation of TMDs” were investigated further, the STEM
imaging method revealed that the distance using which the “gold surface” and the
“connected top sulfur atom of MoS2 ” were separated was 3.5 Å. Given that this
distance is larger than the covalent bond between gold and sulfur (2.2 Å), a strong
van der Waals interaction rather than a chemical bond was used to establish contact
between the gold and sulfur atoms. High-quality exfoliation requires a pristine gold
layer because the binding energy between gold and MoS2 decreases quickly with
increasing distance between the two materials. This is consistent with the studies
where a longer period of air exposure to the gold surface resulted in a lower proportion
of monolayer MoS2 being transferred. By using DFT simulation, missing “gold
atoms” on the surface were also investigated (Velický et al. 2018). Researchers are
working to develop a wafer-scale exfoliation approach since the “Scotch tape” and
“metal-assisted exfoliation technologies” are not scalable. The layer-resolved 2D
material splitting approach is a novel methodology developed (Shim et al. 1979). A
WS2 monolayer with a 2-in. wafer size may be isolated using this method. Instead
of naturally generated “bulk crystal”, the exfoliation topic for this procedure was a
WS2 multilayer created using “chemical vapor deposition (CVD)” on a “sapphire
5 Other Potential 2-D Materials for CMOS Applications 129

substrate”. The CVD-grown sample has a top layer that is uneven and discontinuous.
However, the underlayers are a continuous, homogenous coating. By covering the
multilayer WS2 with a thick coating of Ni, the WS2 multilayer has been lifted off the
sapphire substrate. Later, a second, thick Ni layer was placed on the multilayer WS2 ’s
bottom, and each “WS2 monolayer” was separated from it. It is important to note
that the scotch tape approach produces higher-quality monolayer samples than the
LRS method since it employs naturally generated samples. It is important to mention
the thinning technique here, which involves removing layers to create a “thin film of
TMDs”. A few layers of TMD flakes are positioned on a substrate and are thinned
using heat energy or a laser. TMD flake from the top layer was sublimated using heat
energy. A thick exfoliated TMD is used to create a laser-produced monolayer TMD
by eliminating superfluous layers (Lu et al. 2013). This process allows for placement
and structural control of monolayer TMD, in contrast to conventional exfoliation
and thinning techniques. This technique may be used in unique structurally designed
devices.
Additionally, efforts have been made to produce hexagonal boron nitride
nanosheets (h-BNNSs) via mechanical exfoliation techniques (Pacilé et al. 2008).
Fabricating “monolayer h-BNNS” using “mechanical exfoliation” is a challenging
task due to the stronger interlayer bonds in h-BN compared to graphite. Some studies
propose producing abundant “mechanically exfoliated BNNS” and other “2D mate-
rials” via “low-energy ball milling” and combined ball milling with sonication.
Although the “ball milling technique” is useful for generating a significant amount
of 2D BNNS, the production of mono- to few-layered sheets through this method
is limited. Moreover, the “ball milling process” lacks consistency in controlling
the morphology of nanosheets and the occurrence of structural defects (Li et al.
2011; Kumar et al. 2023c). “Mechanical exfoliation” is a cost-effective method
for producing “2D materials” and is highly suitable for fundamental research. It
is commonly utilized for producing high-performance flexible devices. However, its
scalability and ability to cover large areas are limited, i.e., it is challenging to scale up
the production of 2D flakes through this method. Mechanical exfoliation can produce
single-layered TMD materials, but it is challenging to do so with single-layered
BNNS because h-BN has higher interlayer bonding energy than other materials that
have interlayer van der Waals bonds (García-Miranda Ferrari et al. 2021; Li et al.
2011; Mantri et al. 2023). Moreover, several other elements, including stoichiometry
and stacking orders, are essential to the efficient “fabrication of monolayer MX2
nanostructures” by “mechanical exfoliation”.

Chemical Exfoliation

Another top-down technique creates 2D nanosheets by exfoliating bulk stacked mate-

rials with sonication; they are then distributed in liquid solvents. This process is
known as chemical or liquid exfoliation. As an external energy source, low-power
sonication is employed to exfoliate the “bulk crystals” into “atomically thin sheets”.
Depending on the “bulk crystal material”, various kinds of organic solvents are
130 P. Subudhi and D. Punetha

utilized as a dispersion medium in this “liquid-state exfoliation process”. Further-

more, sonication of particles in a solvent followed by centrifugation may be used
in this method to disperse the powders. Liquid exfoliation techniques have been
used to create several 2-D materials (Coleman et al. 1979; Lee et al. 2011; Eda
et al. 2011). These procedures produce 5–20 layers of uniformly distributed 2-D
nanosheets in a liquid. Using the solvent exfoliation method, the synthesis of “hybrid
2-D nanosheets” made of “BN/graphene”, “WS2 /graphene”, and “MoS2 /graphene”
has been successfully shown. “Liquid-phase exfoliation” is a highly helpful tech-
nique for producing 2D materials in big quantities and at low cost for a variety of
applications. Furthermore, 2D materials may be deposited on a range of substrates
since the process can be done at low temperatures. Nanocomposites, conductive
“electrodes”, “inkjet-printed electronics”, and “thin-film transistors” can all benefit
from this method (Torrisi et al. 2012; Punetha and Pandey 2019c; Punetha et al.
2020; Xiao et al. 2010). The obvious drawbacks of liquid-phase exfoliation are small
particle size, high defect density, high probability of chemical group contamination,
and possible phase change of exfoliated TMDs. While a number of liquid-phase exfo-
liation methods have been documented, the two most popular methods are solvent-
based and ion intercalation methods (Shen et al. 2015; Zeng et al. 2011). The steps
in a “solvent-based exfoliation process” include insertion, stabilization, immersion,
and exfoliation. Figure 5.3 shows a schematic representation of the “solvent-based
exfoliation” procedure. The 2D material must be fully submerged in the solvents for
sonication to effectively exfoliate it. Also, they need to exfoliate the material with
great concentration and avoid stacking-exfoliated 2D material again. Surface tension,
“Hildebrand, and Hansen solubility” factors must be considered when choosing
the best solvent for a certain 2D material to meet the requirements. Based on the
solvent needs, the finest well-known solvents are “IPA/water, acetone/water, and
THF/water”. Depending on the 2D material, the ideal volumetric solvent-to-water-
to-water ratio will vary. For h-BN, WS2 , and MoSe2 , it is a 1:1 IPA/water ratio,
whereas, for MoS2 , it is a 7:3 ratio (Shen et al. 2015).
Though essential for electronic applications, direct chemical exfoliation cannot
remove only one layer of a 2-D nanostructure. To overcome this issue “ion inter-
calation” method is introduced. The “intercalation of impurities between layers of
bulk TMD crystal” to expand the interlayer gap is the basic idea underlying the ion
intercalation process. Then, given the “energy barrier to exfoliation”, the increase in
“interlayer space” decreases “van der Waals’s” force. “Alkali metal”, “organometal-
lic”, polymeric, and “atomic species” are some of the intercalants. Because of its
large reduction potential and excellent mobility, lithium-ion is a suitable mate-
rial. “N-Butyllithium (n-BuLi) solution” in hexane has been used extensively for
lithium intercalation. When an electron is sent to the TMD layers by the n-Bu-,
the Li+ ion intercalates for the charge balance. Lithium intercalation efficiency has
been increased using ultrasonication or microwaves. By hydrolyzing and sonicating,
the “lithium-ion intercalated TMD bulk crystal” is exfoliated. Figure 5.4 depicts
a lithium-intercalated exfoliation procedure (Lee et al. 2014). An advanced “Li-
ion intercalation” method using the “electrochemical approach” was introduced, as
shown in Fig. 5.4b. Lithium intercalation via an electrochemical technique provides
5 Other Potential 2-D Materials for CMOS Applications 131

Fig. 5.3 Schematic depicts the solvent-based exfoliation method (Kang et al. 2020)

a quicker and more controlled process (Zeng et al. 2011). A voltage is supplied
for the lithium intercalation process between “anodic lithium foil” and “cathodic
bulk TMD” in an electrolyte. The technique involves sandwiching Li+ ions between
the TMD layers. The “Li+ ion intercalated TMD bulk crystal” is stirred to produce
TMD nanosheets. This exfoliating procedure may cause the exfoliated material to
distort structurally. Lithium intercalation causes a charge transfer from “n-BuLi” to
the “TMD crystal”, which transforms the crystal’s original 2H structure into a 1T
structure (Shi et al. 2018). While the dosage of lithium is rising, this phase transition
is more advantageous. Nevertheless, an “annealing process or exposure to infrared
(IR) light” reverses this intercalation-induced phase transition (Eda et al. 2011; Fan
et al. 2015).

Fig. 5.4 Schematic illustrates the ion intercalation method: a depicting lithium intercalation and
exfoliation process and b showcasing electrochemical lithium intercalation for 2D materials (Kang
et al. 2020)
132 P. Subudhi and D. Punetha

The “Lithium (Li) intercalation” method for producing a single sheet of MoS2 was
developed by intercalating “Li+ ions” between the layers of MoS2 , which may then
be pushed to separate into monolayers to produce a stable MoS2 colloidal solution.
Bulk MoS2 crystals can be intercalated with Li by soaking them in a “butyllithium-
hexane solution” for a few days in a flask covered with inert gas (Eda et al. 2011).
Lix MoS2 is produced during this reaction, which may be completely recovered by
filtering and then washing with hexane to get rid of extra “lithium and organic waste”.
By executing a thermal annealing procedure, the intercalation-induced phase tran-
sition is completely undone, restoring the semiconductor characteristics of the orig-
inal MoS2 as seen by the presence of the band gap in “photoluminescence spectra”
(Eda et al. 2011). Similar to this, MoS2 monolayers have also been created using
different Fe/Co-based intercalation exfoliation techniques to serve as a substrate for
“magnetic materials” (Frindt et al. 1991). The gram-scale synthesis of 2D nano-
materials can benefit from the much desired, adaptable method of chemical exfo-
liation. However, it might be difficult to achieve a homogenous dispersion of 2D
materials since a successful dispersion depends on the particular “surface tension of
the solvent”. Like the previous example, a “Li+ ion-based intercalation” procedure
includes “physisorbed Li+ ions” at the surface, degrading the electrical and thermal
characteristics of the final products.

Bottom-Up Approach

Chemical Synthesis

Various carbonaceous and non-carbonaceous 2D nanosheet types can be success-

fully made using the low-cost, room-temperature chemical synthesis method. In the
bottom-up method of chemical synthesis, “atoms, and molecules” are deposited on a
substrate in a series of deposition steps to create a 2D layered structure (Shukla
et al. 2023b). While chemical synthesis techniques are currently being actively
researched to obtain additional improvements, liquid exfoliation is already highly
tuned and often used to manufacture 2D nanostructures. Fundamentally, they are
wet chemical techniques that produce 2D nanostructures on the substrates by chem-
ical processes. For 2D TMD materials, “chemical synthesis is a low-cost, scalable
synthesis method”. Achieving the ideal stoichiometry in the final product, however, is
somewhat challenging when a TMD is manufactured chemically. A few studies have
shown how 2D MoS2 , WS2 , BN, etc., can be synthesized utilizing chemical synthesis
techniques. Additionally, 2D materials such as NbSe2 , TaS2 , TaSe2 , and NaTaO3 , can
also be synthesized using this method (Sekar et al. 2005). Each type of material has
several synthesis methods, starting elements, and precursors. These methods often
have several advantages and disadvantages. One method exhibits how to produce
MoS2 and WS2 by breaking down a single source metal and sulfur precursor in oley-
lamine, which resulted in a high-quality 2D free-standing single nanosheet (Altavilla
et al. 2011). Another intriguing method exhibits how a precursor 1D W18 O49 nanorod
5 Other Potential 2-D Materials for CMOS Applications 133

undergoes rolling-out shape change to generate a 2D WS2 layer, as shown in Fig. 5.5.
In effect, a simultaneous decrease from oxide to sulfide occurred together with the
transition from nanorods to nanosheets. As a result, this study also demonstrated how
the continual heterogeneous transition from a 1D to a 2D nanostructure led to the
creation of significant strain in the final product. Moreover, this mechanism led to the
assembly of nanosheets into a multilayered structure due to van der Walls attraction
(Seo et al. 2007). The technique can create 2-D nanosheets of excellent quality with a
surface area of up to 100 nm in size. Moreover, the 2-D nanosheet’s open-edge shape
may be crucial in maintaining the high intercalation capacity, making this particular
restructured material a superior electrode.
Another study used the reaction of urea and boric acid to show how “2-D boron
nitride nanosheets (h-BNNS)” can be created chemically. Also, the “influence of the
molar ratios” of urea and boric acid was studied, with the conclusion that a higher
urea content in the reaction mixture resulted in fewer layers in the final product. As
a result, it was asserted that this technique is quite effective at managing the quantity
of BN layers generated (Nag et al. 2010). More thorough research is required into
the wet chemical synthesis manufacturing of alternative non-carbonaceous 2D TMD
materials. Chemical synthesis techniques themselves are very helpful since they

Fig. 5.5 Formation mechanism of 2D WS2 nanosheets involves a rolling-out shape-transformation

process of 1D W18 O49 nanorod precursors. TEM images b depicts W18 O49 nanorod precursors,
while c shows the formation of 2D WS2 (Seo et al. 2007)
134 P. Subudhi and D. Punetha

could be able to create 2D nanomaterials at the grams scale with fewer flaws and less
crystalline disorder than other techniques.

Chemical Vapor Deposition (CVD)

The microelectronics industry and a CMOS foundry rely heavily on CVD, which is
perhaps the most extensively researched method of depositing a film. It is a reason-
ably straightforward bottom-up growth technique with a flexible metal precursor
and a rather quick growth rate. “Chemical Vapor Deposition (CVD)” is a high-
temperature process for depositing materials onto substrates. For the synthesis of
“thin film coatings” of a variety of materials, including metals, “semiconductors, and
insulators”, CVD methods have been widely researched. Boron nitride nanosheets
and large-scale homogenous “2-D transition metal dichalcogenides” have both been
synthesized using the CVD method. By interacting sulfur vapor with thin metal
films at high temperatures in an inert environment, CVD is a fairly simple process
for making metal sulfides. “Large area 2-D MoS2 synthesis” within the MX2 group of
TMDs has been established using CVD techniques. Large area 2-D MoS2 synthesis
using CVD techniques has been accomplished for the MX2 group of TMDs. This
procedure converts a “molybdenum (Mo) thin film” into a 2D molybdenum sulfide
thin layer by exposing it to a flow of sulfur (S) vapor at high temperature and in
an inert environment. By first depositing a thin layer of Mo on the substrate and
then using the CVD technique, one study showed how to synthesize MoS2 on SiO2 /
Si. A CVD furnace containing a Mo-coated substrate and sulfur powder was used.
A steady flow of around 200 sccm of N2 was used to maintain the inertness of the
reaction environment. For 90 min, the temperature was raised to 750 C, allowing
Mo to combine with the evaporating sulfur to form the synthetic MoS2 coating on
SiO2 /Si. This is one of the earliest reports of a direct CVD approach to producing
“single and few-layered MoS2 on SiO2 /Si substrates”. The authors noted that there
is a predictable relationship between the substrate size and Mo thickness and the size
and thickness of the 2D MoS2 layer.

Physical Vapor Deposition

In a “CMOS foundry, physical vapor deposition (PVD)”, often referring to “thermal

evaporation or sputtering”, serves as a convenient substitute for CVD. A wide group
of 2D materials can be processed on a massive scale using the PVD synthesis tech-
nique (Punetha and Pandey 2019d, e). This method has been utilized for decades to
create thicker vdW films (Muratore et al. 2019; Kumari et al. 2023), and the deposi-
tion of a few layers has also recently been demonstrated (Huang et al. 2016; Suman
et al. 2021). There is no basic restriction on the size or form of the films that may
be made using this method. While growth on any substrate is intrinsically feasible,
PVD does not additionally need the transfer of the produced material onto the chosen
5 Other Potential 2-D Materials for CMOS Applications 135

Fig. 5.6 Schematic representation of magnetron sputtering of MoS2 on carbon nanopowders

(Rowley-Neale et al. 2018)

substrate. An example of a MoS2 source that serves as a target is shown in Fig. 5.6
(Rowley-Neale et al. 2018).
The main concept behind sputtering is that small fragments of the target material—
even single atoms—are sputter-blasted off a section of the target material by ions from
a gaseous plasma. These sputtered particles finally settle on the selected substrate
after exiting the chamber. A magnetic source is frequently integrated with the target to
limit the electrons to areas near the target’s surface. Any film may be sputtered using
this technique, known as magnetron sputtering, regardless of its melting temperature.
MoS2 and WS2 films have both been deposited by magnetron sputtering (Chen et al.
2021). The main issue with sputtered 2D films is that the material is polycrystalline
and frequently not stoichiometrically deposited. High polycrystallinity results in low
charge mobilities, approximately 0.0136 cm2 /Vs for bi-layer and 0.0564 cm2 /Vs for
five-layer MoS2 (Huang et al. 2016). During a high-temperature annealing stage, the
mobility may be increased to around 10 cm2 V −1 s −1 , which is still much less than
the mobilities attained for CVD or MBE-grown films (Muratore et al. 2019). The
advantages of sputtering for CMOS integration would thus be defeated by annealing
the material at high temperatures.

Molecular Beam Epitaxy

“Molecular-beam epitaxy (MBE)” has been employed since the 1960s for fabri-
cating CMOS devices. It enables large-scale epitaxial growth. Typically, an “ultra-
high vacuum (UHV)” is needed for the deposition, which generally falls below
“10−8 –10−12 Torr” (Tiefenbacher et al. 1994). The “molecular source for MBE”
epitaxial film growth came from “effusion cells”, which were heated or supplied
with a gas supply. No chemical reaction occurred during the creation of the “molec-
ular source”. Instead, the “chemical reaction” happened on the target substrate (as
136 P. Subudhi and D. Punetha

Fig. 5.7 a Schematic of MBE deposition system, b AFM image of MBE-grown MoS2 monolayer
(Kang et al. 2020)

shown in Fig. 5.7) (He et al. 2019). MBE can create a precise, “atomically thin
layer between epitaxy layers” by accurately manipulating the shutters of individual
effusion cells. The ability of the UHV environment to generate highly pure-grown
films is another benefit of employing MBE. Figure 5.7a depicts a typical MBE setup,
which includes Knudsen effusion cells that produce precursors by “heat evaporation”
in the form of a “molecular beam”. The substrate is kept in place by a holder and
is situated at the focal point of the “effusion cells”. “Reflection high-energy elec-
tron diffraction (RHEED)” is used to monitor the “film’s crystallinity” and growth
rate, and a residual gas analyzer (RGA) is used to detect the “partial pressure” of
the different “gas species” present in the chamber. “TMDs” and other elemental “2D
materials” have all been realized using MBE, which is a particularly effective method
for generating “high-quality crystalline 2D films”. MBE has also been used to create
lateral and vertical vdW heterostructures (Thomas et al. 2020).
One of the first scalable techniques for fabricating TMD monolayers is MBE.
Beginning in the 1980s, a monolayer of MoSe2 was created on a substrate of
CaF2 (111) (Koma et al. 1990). The addition of an additional molecular beam source
makes it possible to dope TMD. Therefore, MBE has the potential to fabricate
heterostructures with doped layers. MoS2 monolayer on h-BN has been accom-
plished (Fu et al. 2017). An AFM picture of a “seamless MoS2 monolayer grown
on an h-BN/sapphire wafer” is shown in Fig. 5.7b. This approach can produce TMD
monolayers on wafers, but it requires costly effusion equipment and takes around 10
hours to build MoS2 monolayers on 2-in. wafers (Fu et al. 2017).
As of right now, integrating MBE into a CMOS technological flow presents a
number of difficulties. Key issues for mass manufacturing are the high vacuum
requirements and high process sensitivity to minute changes. For this reason, tech-
nology is still primarily used to research the basic characteristics of different material
systems (Ugeda et al. 2014). But if these problems are solved and there are more
benefits than drawbacks to MBE integration in a CMOS foundry, this integration
5 Other Potential 2-D Materials for CMOS Applications 137

may happen in the near future. MBE’s utility in multi-wafer VCSEL synthesis has
already been demonstrated in a few cases, which might accelerate its transition to
mass-production CMOS foundries (Filipovic and Selberherr 2022).

Atomic Layer Deposition

Compared to conventional CVD, “atomic layer deposition (ALD)”, a method for

creating thin films provides more control over layer conformality and thickness.
Because ALD can deposit important oxides and nitrides like as HfO2 and TiN, it
has become an essential process in the production of advanced nodes of semicon-
ductors. This is primarily because the process is inherently self-limiting. Every stage
involves a surface catalytic reaction to ensure that a certain precursor is coated on the
surface. The required film is subsequently generated when this precursor predomi-
nantly interacts with the organisms that enter the chamber in step two. As a result,
very accurate thin films with excellent conformality and thickness control down to
the angstrom level can be produced using ALD (Hao et al. 2018). The ALD technique
may address the “BEOL CMOS integration of 2D materials” since it does not require
extremely high temperatures (Xu et al. 2022). The efficient creation of monolayer
and bulk MoS2 using ALD at 300 °C with precursors for Mo and S, respectively,
comprising MoCl5 and H2 S, has already been demonstrated (Sreedhara et al. 2018;
Tan et al. 2014). The main issue with ALD is that it has been demonstrated that the
substrate material and deposition circumstances have a “considerable influence” on
the nucleation and development of the films (Groven et al. 2018). For instance, it was
discovered that the substrate SiO2 was less reactive and formed bigger grains when
WS2 was deposited using “plasma-enhanced atomic layer deposition (PEALD)” on
Al2 O3 .
Each time, the film’s crystallinity was considerably lower than with the CVD
or MBE techniques, so with methods like sputtering, a post-ALD annealing step is
frequently needed to increase the crystallinity and the material characteristics. Never-
theless, as this stage frequently demands temperatures of up to 800 °C or 900 °C, it
is presently not practical to combine this procedure with the BEOL (Cai et al. 2020).
Another problem with integrating “2D materials with CMOS technology” is the
challenges of “patterning the films”, which will suffer greatly if subjected to plasma
etching. MoCl5 and H2 S precursors at 400 °C can be used to concurrently deposit and
etch MoS2 layers (Ahn et al. 2021). As seen in Fig. 5.8, the authors provide a selec-
tive deposition technique in which, even after 400 ALD cycles, the Mo-precursor
MoCl5 would adsorb into the surface areas covered by aluminum rather than into the
SiO2 surface. As is common for an ALD process, the SiO2 and aluminum surfaces
were fully coated when the MoCl5 pulse time was set to one second. Only when the
MoCl5 pulsing time was set to 5 s—a setting that was too long—did this happen. This
finding may spur investigations into a practical method for patterning these films in
a way that is compatible with CMOS foundries.
Although some 2D semiconductors have been successfully grown using the
ALD approach, CMOS integration is ultimately hampered by the requirement for a
138 P. Subudhi and D. Punetha

Fig. 5.8 Schematic representation of the atomic layer deposition process of MoS2 (Ahn et al. 2021)

high-temperature post-ALD anneal. If an alternative “BEOL-compliant” annealing

method that does not require high temperatures is found, ALD may become the major
enabling technology for introducing “2D materials” into the “CMOS foundry”. Given
that ALD involves complex chemistry, it is also necessary to determine which precur-
sors to use and the ideal chamber conditions for them to construct monolayers of
particular materials. This means that before new material can be used to create viable
films, a whole new chemistry must first be found and then optimized.

Roadmap for CMOS Integration of 2-D Materials

While evaluating the use of 2-D materials in future consumer and industrial applica-
tions, a number of issues should be taken into account. Because of their exceptional
mechanical strength and atomic thinness, they are perfect for high-performance flex-
ible electronics (Verma et al. 2020). They exhibit an indirect-to-direct bandgap tran-
sition in their electrical structure, which makes them attractive for optoelectronics
(Zhou et al. 2018). Their large surface-to-volume ratio offers great potential for
energy storage and sensing applications (Punetha et al. 2018; Wang et al. 2021).
Even if other roadmaps have comparable components, our primary focus will be
on the potential of 2-D materials as speed and functionality boosters in addition
to standard CMOS technology (Ferrari et al. 2015). Due to self-passivation, ultra-
thin nature, and high atomic thickness limit mobilities, “2-D materials” are excellent
candidates for this application. The basic technological processes for integrating 2-D
materials in the CMOS manufacturing flow are shown in Fig. 5.9. Selecting a few
items from this expanding library among the hundreds of 2D compounds that are
5 Other Potential 2-D Materials for CMOS Applications 139

Fig. 5.9 Roadmap for integration of 2D materials into CMOS applications (Resta et al. 2019)

presently being separated or synthesized becomes a crucial integration choice. Mate-

rials can be chosen based on application-specific needs, or by benchmarking against
existing silicon technology (Marin et al. 2017; Punetha et al. 2023). The availability
of high-quality large-area materials and the material’s resilience in the environment
are two more integration options.
Regardless of how they are chosen, a few materials, like MoS2 , WS2 , WSe2 , h-BN,
and black phosphorus, have already garnered a lot of interest. The main components
of device and circuit design and manufacturing are modeling and simulation. Under-
standing device functioning requires modeling, particularly the effects of contact
barriers, nonidealities, and potential flaws on transistor functionality (Jiménez 2012;
Yadav et al. 2018; Das and Mahapatra 2018). Understanding of basic materials and
devices is progressing significantly (Illarionov et al. 2016). Simulation tools are
crucial components of ubiquitous circuit design using and 2D materials is the goal,
in addition to the significant design recommendations they create. The challenging
procedures of synthesis and transfer aim to create materials with a high degree of
crystalline clarity, atomically controlled thickness, and substrate integration. The
production of exact heterostructures and large single crystals demonstrated successful
results (Ranjan et al. 2017). Two basic transfer methods become apparent when 300-
mm integration is the goal: “wafer-to-wafer transfer” on full “300-mm blankets
or die-to-wafer” placement of tiny crystals (Castellanos-Gomez et al. 2014). The
“integration core” stage involves both limiting unintended consequences resulting
from the “substrates, encapsulating materials”, or “device processing” in addition
to scaling up successful lab-scale techniques to “industry-compatible 300-mm plat-
forms”. Precision manipulation of the device’s electrical characteristics, such as
polarity and threshold voltage (V TH ), is related to integration. Although significant
progress has been achieved in the area of doping, a standard has not yet been estab-
lished. The accurate regulation of V TH of various devices is essential for proper
circuit operation (Xu et al. 2017; Ranjan et al. 2018; Lockhart de la Rosa et al.
140 P. Subudhi and D. Punetha

2018). However, although some materials only exhibit “n-type or p-type conduc-
tion”, others combine the two, providing intriguing new avenues for the development
of doping-free devices and improved circuit design.
Characterization techniques are crucial for the majority of processing steps to
ensure yield and dependability. Wafer-scale characterization approaches are still in
their infancy, even if the existing 2-D material characterization allows for inves-
tigating various features. AFM, photoluminescence, and Raman spectroscopy are
the main methods used to assess the quality of 2-D materials (Splendiani et al.
2010; Binnig et al. 1986). For the creation of dependable and stable transistors, tech-
niques to comprehend interface qualities must be extensively established (Gaur et al.
2017; Liu and Hersam 2018). In-line metrology will undoubtedly require additional
approaches to thoroughly explore the condensed dimensions and unique features
of 2-D materials. It’s significant to note that work is still being done to provide a
standardized toolbox for characterization that can assess everything from material
quality to “electrical characteristics”, including “interface aspects”. In conclusion,
several technological advancements are still required to fully realize the potential
of “2-D materials” as boosters in “VLSI systems”. These advancements range from
an improvement in the “quality of the grown material” to the creation of an effec-
tive “transfer technique” to the scaling up of “processes to 300-mm platforms”. Yet,
recent developments in the knowledge of the “characteristics of 2-D materials” and
the presentation of unique devices have kept the study area alive and attractive to
businesses and academic institutions.

Performance Projection at Scaled Device Dimensions

Due to its exceptional properties, graphene is the first and most essential member of
the “family of 2D materials” to demonstrate value for various applications, including
electronics, photonics, energy, and a wide range of other sectors (Subudhi and
Punetha 2023b; Punetha and Pandey 2020). Despite advantages, including zero
band gap and challenges in layer control and intrinsic defects, utilizing graphene
for future semiconductor devices is highly challenging. Hence, there has been a
significant market need for the creation of more 2D materials with inherent semi-
conductor characteristics. For instance, the electron-hole pair excitation caused by
the 2D MoS2 direct band gap may be utilized in LEDs, photodetectors, and other
photonic devices (Dixit et al. 2019). 2D MoS2 transistors offer potential for low-
power digital circuits, while materials like MoS2 , MoSe2 , WS2 , WSe2 , etc., may
serve as flash memory floating gates, meeting retention, endurance, and reducing
power operations for nonvolatile memories. Reduced gate stack thickness results in
lower voltage operations and offers up a wide range of possible solutions for applica-
tions requiring ultra-high densities and device downsizing. MoS2 has been developed
for uses other than transistors, such as a “photocatalyst”. Most crucially, doping and
applied mechanical strain are both efficient ways to modify a 2D monolayer MoS2 ’s
capacity for photocatalysis (Li et al. 2013). P-type doping has the ability to promote
5 Other Potential 2-D Materials for CMOS Applications 141

direct electron transfer, thereby separating water-splitting processes at the sites of Mo

and p-dopant. Research on MoSe2 , WS2 , WSe2 , and other transition metal dichalco-
genides for scalable “photooxidation and photocatalysis” that results in “H2 evolution
and energy storage” appears promising (Bhandavat et al. 2012). Li-ion battery anode
material 2D WS2 has an “electrochemical capacity of 118 mAh/g” after 50 cycles. As
WS2 is heavy, it cannot be utilized in place of more common lightweight materials
due to its weight. Relatively new material h-BNNS is recommended for usage as a
“substrate for graphene electronics” because of its exceptional mechanical, thermal,
and chemical inertness properties (Bhandavat et al. 2012).

Conclusion and Future Perspective

The TMDs, boron nitride, and black phosphorous are emerging 2D semiconductor
materials with distinct mechanical, electrical, and optical characteristics. Because
of this, the materials can make up for graphene in applications for next-generation
semiconductor devices. There were several growth techniques introduced in this area.
Even though the underlying concepts of manufacturing procedures may be similar to
those used in other “van der Waals materials”, 2D materials need a unique approach
due to the variety of compounds and growth processes. The bulk crystals are used
in mechanical exfoliation techniques to generate high-quality samples conveniently
and quickly. Surprisingly, employing CVD-grown multilayer 2D materials such as
TMDs on a SiO2 substrate, the LRS technique produces a monolayer of wafer size.
Pure few-layer TMDs are produced in large quantities via liquid-phase exfoliations.
Wafer-scale growth can occur using chemical vapor deposition techniques. Pure few-
layer TMDs may be bulk produced via liquid-phase exfoliations. Wafer-scale TMD
monolayers can be grown using chemical vapor deposition methods, along with the
ability to modify the growth site, limit the number of TMD layers, and adjust the
size of the TMD grain. By being aware of preparatory techniques, one may choose
an appropriate strategy that is suitable for their research applications and goals. Due
to the excellent electrical capabilities of the MX2 group of 2D nanostructures and
other emerging 2D materials, Moore’s Law’s theoretical size scaling limitations for
nanoelectronics devices may soon be reached if nanoelectronic devices are built
using these novel 2D materials. Further uses for these materials include memory
devices, photocatalysis, energy storage, and many others. The numerous production
and tuning techniques for 2D and hybrid nanostructures are shown through several
additional general approaches.
High-quality 2-D materials are currently exceedingly challenging to develop,
although international multidisciplinary initiatives have greatly aided technical
advancement. So, it is anticipated that using these findings might result in the develop-
ment of new functional materials, tools, and systems that would significantly improve
already existing ones. For these ground-breaking applications, we require numerous
142 P. Subudhi and D. Punetha

atomic thin film component technologies, including synthesis, crystal growth, manu-
facturing, measurement, and analysis capabilities. There are still several additional 2-
D materials that might be extremely significant that have not yet been found. Perhaps,
the numerous technical problems that graphene is unable to address can be resolved
by these recently found TMD materials. Utilizing abundant 2D materials can bring
remarkable characteristics at low cost, potentially revolutionizing various industries
by overcoming scarcity and resource localization drawbacks. Silicon technology,
following Moore’s law, has brought downsizing, enhanced integration, improved
performance, lower power dissipation, and reduced costs. However, the ITRS antici-
pates unprecedented challenges in the next decade, such as transistor scaling, device
integration, and power consumption issues. Despite multiple attempts to address
these issues, the future of silicon technology below 10 nm remains uncertain. In
particular, problems with heat dissipation and power consumption persist when the
transistor is reduced in size. Alternative state variables (Q-bits, spin, molecules, etc.)
are being investigated to substitute electrons in CMOS in order to lower power dissi-
pation. As of right now, no other element can compete with the electron. Although
atomically thin materials provide very efficient control of charge transport via surface
gates, the exceptionally high surface-to-volume ratio of 2D materials is an inherent
advantage for future power reduction in nanotechnology. Under these circumstances,
revolutionary 2D materials-based nanoelectronics may be able to realize the ultimate
scale scaling that Moore’s Law and other theories have promised.

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Chapter 6
Heterogeneous Integration of 2D
Materials with Silicon Complementary
Metal Oxide Semiconductor (Si-CMOS)
Devices

Raghvendra Kumar Mishra, Susmi Anna Thomas, Deepa Sethi singh,

Jayesh Cherusseri, Iva Chianella, Hamed Yazdani Nezhad, and Saurav Goel

Abstract This chapter conducts a thorough exploration of integrating “two-

dimensional (2D) materials” with “silicon (Si) complementary metal oxide semicon-
ductor (Si-CMOS)” devices, with a focus on applications in electronics, photonics,
and energy. Various integration strategies are discussed, encompassing the synthesis
and characterization of “2D materials”. The chapter scrutinizes critical criteria for
material selection compatible with Si-CMOS devices, emphasizing the need for
precision. It delves into the intricacies of device fabrication processes and assesses
real-world applications. The comprehensive overview, constructed through an exten-
sive literature review, deeply analyzes the current state-of-the-art. From this anal-
ysis, integration strategies, including transfer, direct growth, and hybrid techniques,
are identified. The chapter highlights the critical importance of precise material

R. K. Mishra (B) · I. Chianella

Enhanced Composites and Structures Centre, School of Aerospace, Transport and Manufacturing,
Cranfield University, Cranfield, UK
e-mail: [email protected]
S. A. Thomas
Department of Physics, Centre for Advanced Functional Materials (CAFM), Bishop Moore
College, Mavelikara, Kerala 690110, India
D. S. singh
Incharge of Zoology Department, Hindu College (M.J.P. Rohailkhand Universty, Bareilly),
Moradabad, Uttar Pradesh 244001, India
J. Cherusseri
Graphene and Advanced 2D Materials Research Group (GAMRG), School of Engineering and
Technology, Sunway University, No. 5 Jalan University, 47500 Bandar Sunway, Petaling Jaya,
Malaysia
H. Y. Nezhad
School of Mechanical Engineering, Faculty of Engineering and Physical Sciences, University of
Leeds, Leeds, UK
S. Goel
School of Engineering, London South Bank University, London SE10AA, UK

© The Author(s), under exclusive license to Springer Nature Singapore Pte Ltd. 2024 149
S. Singh et al. (eds.), Beyond Si-Based CMOS Devices, Springer Tracts in Electrical and
Electronics Engineering, https://doi.org/10.1007/978-981-97-4623-1_6
150 R. K. Mishra et al.

selection and thorough characterization to ensure compatibility with Si-CMOS

devices. It further examines the existing technology landscape, identifying chal-
lenges in research and development. Additionally, the chapter outlines potential
directions for advancements in this promising field, providing guidance for upcoming
developments.

Keywords 2D materials · Si-CMOS transition metal oxides ·

Silicon-complementary metal oxide semiconductor · Heterogenous integration

Highlights
• This chapter starts by introducing 2D materials and their properties. It then
explores Si-CMOS devices and their limitations.
• This chapter covers detailed analysis of benefits from integrating 2D materials
with Si-CMOS devices.
• Si-CMOS devices integrated with 2D material-based FETs, like MoS2 FETs,
show superior performance.
• Emphasis on future research: prioritize scalable integration, improved hardware
compatibility, enhanced reliability, and reduced integration costs.

Introduction

In the pursuit of miniaturization in silicon-based microelectronics, the focus is on

essential integrated circuits (ICs) to advance the “Internet of things (IoT) and data
science” (Clough et al. 2019). The critical challenge lies in achieving higher transistor
densities for sub-7 nm technology nodes. The primary objectives for “silicon-based
metal oxide semiconductor field-effect transistors (FETs)” involve enhancing speeds
and reducing power consumption (Ye et al. 2021; Keyes 2005). The integration of 2D
materials such as “graphene” and “transition metal dichalcogenides (TMDs)” with
“complementary metal oxide semiconductor (CMOS)” devices is actively explored
by researchers (Li et al. 2016). Continuing debates persist on the challenges and feasi-
bility beyond the 5-nm scale in silicon technology nodes (Yao et al. 2022). Figure 6.1
illustrates the evolution of Si-based transistor technology nodes over the past two
decades, emphasizing the escalating need for alternative materials and device archi-
tectures [Source: Web of Science]. Attention is directed toward 2D materials like
graphene, TMDs, and black phosphorus, prized for their distinctive properties (Huang
et al. 2020; Mishra 2019; Yadu Nath et al. 2018; Prasad et al. 2021). However, inte-
grating these materials into Si-CMOS devices poses challenges, including compat-
ibility issues and disparities in thermal and mechanical properties (Serdar 2019;
Kazior 2014). Addressing these challenges involves employing various techniques,
including transfer, direct growth, and hybrid integration (Chakraborty et al. 2022).
Heterogeneous integration of “2D materials” with “Si-CMOS” devices holds the
6 Heterogeneous Integration of 2D Materials with Silicon … 151

promise of enhanced performance, reduced power consumption, and improved func-

tionality, especially in transistors and photodetectors (Jiang et al. 2019). Synthesis
techniques, including “mechanical exfoliation (ME)”, “chemical vapor deposition
(CVD)”, and “liquid-phase exfoliation (LPE)”, are selected based on specific applica-
tion requirements (Alam et al. 2021). Crucial insights into structural, electronic, and
optical properties are obtained through characterization techniques such as “Raman
spectroscopy”, “SEM”, “TEM”, “AFM”, and “X-ray photoelectron spectroscopy”
(Mishra et al. 2022, 2023). The choice of suitable 2D materials for heterogeneous
integration depends on application requirements and compatibility with Si-CMOS
substrates (Prasad et al. 2021; Mishra et al. 2017a; Mishra and Abdulrahman 2022).
Numerous studies contribute valuable insights to the advancement of 2D material
integration with Si-CMOS devices. Wang et al. emphasize the need for scalable
integration techniques (Wang et al. 2022a). You et al. explore the implementation
of “graphene” in “Si-CMOS” integrated circuits (You et al. 2020). Huang et al.
present “graphene/Si-CMOS” hybrid hall integrated circuits (Huang et al. 2014).
Akinwande et al. delve into challenges and opportunities of integrating TMDs with
high-density interconnects (Akinwande et al. 2019). Understanding a highly flexible
hybrid “CMOS inverter” based on molybdenum disulfide and Si nanomembrane is
provided by Das et al. (2016). In monolithic 3D integration, Jiang et al. suggest
using “2D materials” for both “active and passive devices” (Jiang et al. 2019). A
new monolithic “3D integration” with a “2D material field-effect transistor (FET)”
on “Si FinFET” that is compatible with the rear end is presented by Guan et al.
(2023). Understanding the extremely repeatable “van der Waals integration” of “2D
electronics” at the wafer scale is made possible by Yang et al. (2023a). Das et al.
discuss the potential of “2D materials” in future “integrated circuits” (Das et al.
2021). The integration of “2D materials” with “Si-CMOS devices” has the potential
to revolutionize next-generation electronics (Jayalakshmy and Mishra 2019). This
chapter emphasizes the evolution, challenges, and promising future prospects of inte-
grating 2D materials with Si-CMOS devices. As the field advances, researchers strive
to overcome compatibility issues, optimize manufacturing techniques, and explore
novel materials, contributing to the continuing evolution of microelectronics.

Heterogeneous Integration: 2D Materials Enriching

Si-CMOS Devices

In the dynamic field of microelectronics, advancements have downsized semicon-

ductor devices, optimizing cost-effectiveness and efficiency. However, traditional
planar CMOS transistors encounter challenges at the nanoscale (Ieong et al. 2006).
Despite exploring non-classical CMOS alternatives, Si transistors remain vital in
consumer logic applications (Ieong et al. 2006). While scaling CMOS transistors
presents challenges, planar Si-CMOS technology still holds potential (Liao et al.
2005). Over four decades, lithography advances have adhered to Moore’s law,
152 R. K. Mishra et al.

Fig. 6.1 Previous two decades steady advancement in Si transistor technology nodes. Source Web
of Science

doubling component density annually (Cavin et al. 2012). Despite increasing lithog-
raphy tool costs, the cost per transistor has decreased, and Si-CMOS technology is
projected to endure for decades (Cavin et al. 2012). Challenges in scaling CMOS
transistors, including leakage currents and parasitic effects, impede further minia-
turization (Jacob et al. 2017). The integration of “2D materials” like “graphene”
and “transition metal dichalcogenides (TMDs)” into “Si-CMOS technology” offers
promise for addressing contemporary microelectronics challenges. Despite obstacles
in defects, contamination, and manufacturing standards, integrating 2D materials is
anticipated to enhance chip capabilities (Kim et al. 2019). Current initiatives are
directed toward the reduction of transistor channel length, with TMDs like MoS2
and WSe2 demonstrating advantageous features for the miniaturization of “field-
effect transistors (FETs)” and addressing concerns related to short-channel effects
(Mukherjee 2012). However, manufacturing bottlenecks persist, as exemplified by
a European pilot line working to overcome production challenges (Moriceau et al.
2010). While the potential of 2D materials is evident, challenges remain in meeting
industry specifications, controlling dielectric interfaces, and addressing doping issues
(Das et al. 2016). Resolving these bottlenecks is crucial for successful integration,
unlocking the potential for enhanced chip capabilities (Moriceau et al. 2010). A
comprehensive strategy is imperative to extend the limits of “Moore’s law”. This
involves innovations in device architecture and the introduction of new materials
like graphene and carbon nanotubes. Additionally, it encompasses the exploration
of three-dimensional integrated circuits (ICs), involving the stacking of multiple
layers of transistors and memory cells for enhanced efficiency and power efficiency
(Muralidhar et al. 2022). Advancements in materials, device architectures, and system
design are essential for active scaling (Muralidhar et al. 2022). Kazior highlights
substantial progress in heterogeneous integration, envisioning a landscape where
6 Heterogeneous Integration of 2D Materials with Silicon … 153

dissimilar materials enhance device performance beyond traditional CMOS archi-

tectures (Kazior 2014). In order to enhance the possibilities of silicon-based systems,
Wang et al. provide 2D materials as a supplementary technology for “heterogeneous
integration with silicon” (Ieong et al. 2006). Jeong et al.’s paper on “heterogeneous
and monolithic 3D integration” clarifies whether integrating dissimilar technologies
at the device level is feasible (Jeong et al. 2022). Holt et al. introduce a novel approach
to creating a radio frequency gas sensor platform by integrating 2D materials, partic-
ularly monolayer graphene, with Si-CMOS (Holt et al. 2017). Akinwande et al.
delve into the promises and challenges of integrating “2D materials” with “silicon
chips”, offering a “heterogeneous platform” with potential applications (Akinwande
et al. 2019). Das et al. address challenges associated with very large-scale inte-
gration (VLSI) and explore monolithic or heterogeneous integration strategies for
future integrated circuits (Das et al. 2021). The relevance of adhesive wafer bonding
in seamless material integration is emphasized in Quellmalz et al.’s wafer bonding
strategy for “large-area integration of 2D materials” and associated “heterostruc-
tures” (Quellmalz et al. 2021). With its “monolithic 3D integration” and back-end-
compatible “2D material field-effect transistors (FETs)” on Si FinFET, Guan et al.
add to the changing environment. This integration demonstrates the potential bene-
fits of 3D integration compared to conventional 2D technologies (Guan et al. 2023).
The integration of dissimilar materials holds promise for addressing the limitations
of traditional CMOS architectures and pushing the boundaries of semiconductor
technology.

Integration Strategies of 2D Materials with Si-CMOS

Devices

The semiconductor industry faces significant challenges related to power consump-

tion, heat dissipation, and device performance, particularly with the continuous
scaling of Si-CMOS devices. In order to overcome these obstacles, new materials
must be investigated, particularly two-dimensional materials with their distinctive
“mechanical”, optical, and “electronic characteristics”. (Huyghebaert et al. 2018).
This exploration seeks to overcome key obstacles in advanced Si-CMOS scaling,
such as short-channel effects and material limitations. In support of this endeavor,
Jiang et al. investigate the integration of “monolithic 3D” with “2D materials” and
assess the viability of “low-temperature transfer-free growth” in “monolithic 3D”
production (Jiang et al. 2019). The study compares the performance of these mate-
rials with bulk materials. Franklin addresses scaling challenges in advanced CMOS
devices, focusing on the potential of carbon nanotubes (CNTs) and graphene in
printing (Jacob et al. 2017; Franklin 2017). The studies discuss the adaptation of
these nanomaterials in the “back-end-of-line (BEOL)” on top of Si-CMOS and resis-
tive random-access memory (RRAM) memory. Graphene, known for exceptional
154 R. K. Mishra et al.

electrical conductivity and electron mobility, exhibits promise for diverse appli-
cations (Franklin 2017). The exploration extends to various materials, including
TMDs, “black phosphorus”, “hexagonal boron nitride (hBN)”, and “2D material
heterostructures” (Thomas et al. 2022; Tyagi et al. 2020). These materials, with
their unique properties, offer advantages such as improved performance, reduced
power consumption, and expanded functionalities (Tyagi et al. 2020). However,
challenges arise in integrating 2D materials with Si-CMOS devices, involving struc-
tural and dimensional mismatches, contact resistance, and material compatibility.
Despite these challenges, materials like graphene, TMDs, and black phosphorus
show significant potential, particularly in electronic and photonic applications due
to their distinctive properties (Nourbakhsh et al. 2018). Jeong et al. investigate the
bandgap tuning of black phosphorus, revealing a strong nonlinear dependence on the
externally applied bias field (Jeong et al. 2022). Abid et al. explore the bandgap prop-
erties of graphene oxide (GO) and its reduced form (rGO), providing insights into
the reduction process at different temperatures (Abid and Islam 2018). Successful
integration of “2D materials” with “Si-CMOS devices” hinges on effective synthesis
methods and thorough characterization. Various methods, including CVD, ME, and
LPE, are employed (Ould et al. 2018). Characterization techniques like AFM, SEM,
TEM, and Raman spectroscopy offer crucial insights for optimizing electronic prop-
erties and addressing integration challenges (Kumbhakar et al. 2021). In a related
context, Sarney et al. explore the landscape dynamics of HZO through “materials
characterization”, “device modeling”, and “electrical measurements” (Sarney et al.
2023). The focus is on HZO-based “ferroelectric field-effect transistors (FeFETs)”,
“three-terminal devices” with compelling properties for “embedded memory” and
“in-memory computing architectures”. HZO films, processed at CMOS-compatible
temperatures, exhibit ferroelectricity without necessitating field processing, with
notable characteristics such as an “average remnant polarization” between 10 and 20
μC/cm2 and a coercive field of approximately 0.6 MV/cm (Sarney et al. 2023). Strong
synaptic plasticity over a 3.5 order of magnitude conductive range is demonstrated
by the integration of HZO into “BEOL FeFET device” designs using WSe2, offering
insights into material manufacturing, “dimensional scaling”, and HZO-based FeFET
integration (Sarney et al. 2023). In an investigation led by Patel et al., the research
targets mitigating the substantial risk associated with radioactive leakage in Indian
nuclear power plants, integral to the nation’s power production (Patel et al. 2023).
The proposed solution integrates CMOS and the IoT for precise “radioactive leakage
detection”. CMOS, renowned for its precision in radiation measurement, collaborates
with IoT, forming a sophisticated alert system to preempt disasters through timely
and accurate information (Patel et al. 2023). Turning attention to silicon photonics,
Tang et al. offer a review of the incorporation of “2D materials” into silicon-based
platforms. This presents a promising avenue to overcome challenges inherent in
traditional silicon-based information technology (Tang et al. 2023). In addition to
reviewing three common “2D opto-electronic devices” for “silicon photonic appli-
cations”, the paper thoroughly investigates the optical characteristics of “2D mate-
rials” and considers the possibility of “3D monolithic heterogeneous integration”
6 Heterogeneous Integration of 2D Materials with Silicon … 155

of these devices (Tang et al. 2023). Wang et al. discuss the importance of “ferro-
electric materials” with electrically “switchable spontaneous polarization” for gen-
next “low-power nanoelectronics” in the field of ferroelectronics (Maszara 2018).
Acknowledging challenges linked to conventional thin-film ferroelectrics, the study
emphasizes emerging “2D ferroelectric materials” with “nanoscale dimensions” and
“moderate bandgaps” (Maszara 2018). Transitioning to photonics and nanostruc-
tures, Omeis et al. assess the performance of “resonant waveguide (RWG)” rejection
filters and “hybrid Fabry–Perot (FP) band-pass filters”. This evaluation encompasses
factors like “spectral response”, “tunability”, “angular” and “polarization tolerance”,
and “noise sensitivity” (Omeis et al. 2023). The thorough examination clarifies the
combined capacity of an “ambient light sensor (ALS) array” to recover spectrum
data, providing engineers and manufacturers with a systematic framework to guide
them through the selection of applications and sensing capabilities. Li and Yang
contribute to the field of mid-infrared (MIR) photodetection using two-dimensional
(2D) and mixed-dimensional (nD, n = 0, 1, 2, 3) heterostructures (Li and Yang 2023).
The study accentuates the widespread utilization of 2D materials in MIR photode-
tectors due to their “tunable bandgaps”, “high carrier mobility”, and “strong light
absorption”. The authors systematically outline synthesis strategies for van der Waals
(vdWs) heterostructures, presenting motivations, device designs, mechanisms, and
performances of MIR photodetectors. In a distinct exploration, Yang et al. delve into
anisotropic mass transport in crystalline GeSe with an orthorhombic structure, high-
lighting its utility in fabricating “planar memristive devices” exhibiting directional
memory and “transient switching” phenomena (Yang et al. 2023b). The “anisotropic
switching” behaviors, originating from the morphology of metallic filaments, facili-
tate the emulation of various synaptic events, offering opportunities for applications
in “multifunctional brain-inspired computing systems” (Yang et al. 2023b). Experi-
mental results are presented in Figs. 6.2 and 6.3 and highlight practical implications
of integrating 2D materials into Si-CMOS devices (Hoseinpour et al. 2023; Rahil
et al. 2022). In Zhang et al.’s investigation, a dual-gate black phosphorus (DGBP)
transistor was employed to study bandgap tuning under bias (Zhang et al. 2020).
Figure 6.2a illustrates the DGBP thin-film transistor used for “bandgap tuning”,
while Fig. 6.2b details bandgap tuning features with varying BP film thicknesses.
The transistor featured a “thin-film BP channel” between a “90 nm silicon oxide”
and a “24-nm aluminum oxide gate dielectric”. “Source and drain electrodes” were
“chromium/gold (3/30 nm)”, and the top gate was “titanium/platinum (1/10 nm)”,
with the “silicon substrate” as the “back gate”. Bandgap assessment involved exam-
ining “BP conductance” at the neutral charge point under a vertically aligned biasing
field. To minimize metal/BP contact impact, a four-probe system was employed,
as shown in Fig. 6.2b. Analysis of a “4-nm thick” BP sample indicated alignment
with theoretical calculations, demonstrating a nonlinear bandgap modulation with
increasing gating field. This revealed a highly strong “nonlinear dependence” on
the externally applied bias field, with a tunable range extending beyond a moderate
“displacement field”, reaching up to “1 V/nm” (Zhang et al. 2020).
Figure 6.3 displays UV–Visible spectroscopy analysis of GO dispersion and rGO
film during thermal reduction (Abid and Islam 2018). The analysis provides insights
156 R. K. Mishra et al.

Fig. 6.2 a Pictorial representation of “dual-gate BP thin-film transistor” employed for the bandgap
tuning b bandgap tuning features of BP film having layers 4, 5,6, 7, 16,17, 18, and 19 with a
tight-binding model developed with DFT (solid lines). BP films having variation in thickness hold
variant tuning character. Purple dots represent the calculated bandgap tuning of 4-nm thick BP
film holding approximately seven layers. Reproduced with permission from Zhang et al. (2020).
Copyright (2017) Springer Nature

Fig. 6.3 UV–Visible spectroscopy of a GO dispersion with respect to ultrasonication time b rGO
film in accordance with thermal reduction time. Reproduced with permission from Abid and Islam
(2018). Copyright (2018) Springer Nature

into structural transformations and bandgap modifications during the thermal reduc-
tion process. In Fig. 6.3a, UV–Visible spectroscopy of the prepared GO dispersion
after ultrasonication (1 h, 3 h, and 5 h) shows a maximum absorption peak at 237 nm,
indicating the π–π* transition by aromatic C–C bonds. Figure 6.3b demonstrates
UV–Visible spectroscopy of the rGO sample after reduction at 250 °C for varying
durations. The absorption peak shifts to 266 nm, quantitatively representing the
reduction process. This detailed analysis in Fig. 6.3 offers crucial insights into the
structural transformations and bandgap modifications during the thermal reduction
of GO to rGO (Abid and Islam 2018).
6 Heterogeneous Integration of 2D Materials with Silicon … 157

Table 6.1 enhances comprehension of the intricate connection between 2D

materials and Si-CMOS technology. It summarizes properties of hBN, MXene,
graphdiyne, and perovskite nanosheets, facilitating analysis. The table underscores
the need for exploration and advancement in this dynamic field, emphasizing the intri-
cate link between 2D materials and Si-CMOS technology. Integrating 2D materials
with Si-CMOS devices shows potential in addressing challenges in power consump-
tion, heat dissipation, and device performance. The distinctive properties of 2D mate-
rials position them as pivotal contributors to semiconductor technology evolution,
promising innovations in electronic and opto-electronic applications.

Synthesis Methods for Heterogeneous Integration of 2D

Materials in Si-CMOS Device

The integration of “2D materials” with “Si-CMOS” devices is a transformative

approach for advancing semiconductor technology. This integration requires careful
consideration of synthesis techniques to ensure compatibility with CMOS processes.
Various synthesis methods, each with distinct advantages and limitations, play a
pivotal role in this endeavor (Huyghebaert et al. 2018; Das et al. 2015). Epitaxial
growth, as demonstrated by Elias et al., provides an exemplary instance wherein
monolayer boron nitride (hBN) is grown epitaxially before graphene through Brazil
decomposition on a metal surface (Elias 2019). Figure 6.4 presents a detailed AFM-
based surface topographical analysis, offering valuable insights into the epitaxial
growth of BN on graphite and “highly oriented pyrolytic graphite (HOPG)”. The
AFM-based surface topographical analyses in Fig. 6.4a illustrate the complete
coverage of a HOPG substrate by the hBN layer. Subsequent phase-channel data
in Fig. 6.4b highlights regions of exposed HOPG uncovered by hBN. The charac-
teristic monolayer hBN step height is examined in Fig. 6.4c, providing a “small-
area” “contact-mode AFM” image of the mBN boundary adjacent to an exposed
HOPG region. A detailed view in Fig. 6.4d confirms exposed graphite detected by
hBN growth, with further validation through phase-channel images in Fig. 6.4e.
Surface coverage analysis, including single-layer hBN and 3D hBN aggregates,
utilizes phase-channel data, while Fig. 6.4f quantifies the monolayer hBN step
height at approximately 0.35 nm. These analyses offer crucial insights into BN
epitaxial growth on graphite and HOPG, contributing to an enhanced understanding
of structural characteristics (Elias et al. 2019).
In the investigation of 2D materials, the analysis methods focus on structural
features, enhancing synthesis and integration understanding (Elias 2019). The study
utilizes AFM-based analyses to explore epitaxial monolayer BN on graphite and
mBN growth on HOPG, delivering comprehensive coverage (Elias 2019). Crucial
information about monolayer BN at the mBN boundary near exposed HOPG is
provided (Elias et al. 2019). Various synthesis techniques such as CVD, PECVD,
Table 6.1 Comprehensive comparison of these 2D materials
158

Class of materials Materials Bandgap Additional notes Ref.

Carbon nanomaterials 2D graphene Zero bandgap, high thermal PL lifetime in femtosecond range, Jiang et al. (2020a),
conductivity, 2 × 105 cm2 V–1 s−1 low PL quantum yield of 2.3% Tiwari et al. (2018)
“carrier mobility”, 2.3% optical
absorption, tunable potentials,
ultrafast recovery, and large
modulation depth
2D graphene “2D graphene allotrope” features Graphene, a 2D graphene allotrope Mishra et al. (2023,
unique “carbon hybridization”, with unique carbon hybridization, 2017a)
monolayer with 0.44–1.47 eV offers potential for opto-electronic,
bandgap, 450–750 nm emission, and energy devices, solar cells, and LEDs
≈1.6 ns lifetime due to broadband emission and short
lifetime
2D graphene oxide GO has 2.2 eV bandgap; rGO ranges Graphene oxide (GO) is insulating, Abid and Islam (2018),
1–1.69 eV depending on reduction. more disordered than graphene, and Krishnamoorthy et al.
PL spectrum shows sharp UV attractive for graphene preparation (2012)
emission peak at 365 nm due to oxygen-containing functional
groups and diverse carbon sites
Transition metal 2D MoS2 2H-phase MoS2 peaks at 1.85 eV. Excitonic properties in monolayer Wang et al. (2018)
dichalcogenides Monolayer has direct 1.85 eV TMDs (MX2 formula) show distinct
bandgap, changing to 1.6 eV indirect PL features from multilayer
gap. MoS2 nanoscroll’s indirect gap counterparts due to strong
larger than 1.54 eV bilayer. PL light–matter interaction and large
spectra has 1.86 eV, 2.01 eV peaks at binding energies
862 nm, 618 nm with 488 nm
excitation
(continued)
R. K. Mishra et al.
Table 6.1 (continued)
Class of materials Materials Bandgap Additional notes Ref.
2D tungsten disulfide Single layer holds a direct bandgap – Musoke and Luckham
(WS2 ) of 2.1 eV with strong quantum yields (2004)
of about 6% but few-layer WS2 is an
indirect semiconductor that has
indirect bandgap of 1.35 eV
2D tin disulphide (SnS2 ) Room temperature PL spectra show – Arulanantham et al.
strong near-band edge emission at (2017)
558 nm (2.24 eV) due to free or
bound exciton recombination
2D molybdenum PL spectra have strong peaks Wang et al. (2015a)
diselenide (MoSe2 ) appeared at 566 and 561 nm with an
emission wavelength of 516 and
512 nm
2D tungsten diselenide WSe2 possess an indirect bandgap of Kashyap et al. (2021)
(WSe2 ) 1.27 eV to a direct bandgap of
1.55 eV after performing exfoliation
Phosphorus Black phosphorus Bandgap range: 0.3 eV (bulk) to 2 eV High carrier mobility, strong in-plane Deng et al. (2017), Liu
6 Heterogeneous Integration of 2D Materials with Silicon …

(monolayer), fast recovery time (ps), anisotropy, adjustable bandgap, and et al. (2017)
resonance of PL: 918, linewidth of wide operation range bridge
PL: 90, optical absorption 10% or graphene-TMD gap with anisotropic
50% PL/absorption
Born nitride hBN Large 6 eV bandgap, UV region PL hBN has insulating properties, high Elias et al. (2019), Cai
emission, 300–400 meV bandwidth, thermal conductivity, and potential et al. (2019)
fast picosecond recovery, PL for electrostatic gating, making it
resonance at 230, useful for useful in electronics and thermal
opto-electronic devices management
(continued)
159
Table 6.1 (continued)
160

Class of materials Materials Bandgap Additional notes Ref.

Indium chalcogenides Few-layer InSe by InSe, a III-VI layered material, has a Few layer in chalcogenides is a Li et al. (2018),
mechanical exfoliation or narrow direct bandgap varying from promising material for Brotons-Gisbert et al.
CVD 1.26 eV (bulk) to 2.11 eV opto-electronics. InSe exhibits high (2016)
(monolayer). Few-layer InSe photoresponsivity and acceptable
displays strong quantum response time, making it a potential
confinement, high mobility, large candidate for photodetection and
photoresponsivity (>1 A W−1 ), and photovoltaic applications.
acceptable response time (μs–ms) Mechanical exfoliation and CVD are
the main methods for synthesizing it
Indium sulfide (InS) Single crystalline βIn2 S3 holds a –
bandgap of 2– 2.4 eV, but
polycrystalline β-In2 S3 possess
values in the range of 2–3.7 eV
Indium telluride (InTe) In2Te3 hol ds a narrow direct –
bandgap in the range of 1.29 eV at
room temperature
MXenes MXene by selective “2D transition metal carbides”, MXenes are composed of “transition Jiang et al. (2020b)
etching of MAX phase “nitrides”, or “carbonitrides” have metal” (Sc, Ti, etc.), carbide/nitride
materials tunable properties, including low (X), and surface termination (OH, F,
“optical loss”, variable “bandgap”, etc.) with n = 1–3. The abundance of
and high “electrical conductivity”. “material composition” and “surface
Ti3C2Tx “quantum dots” exhibit a functions” gives MXenes remarkable
10% “quantum yield”, tens of ns and tunable properties
lifetime, and a low absorption rate of
≈1% at 460 nm
(continued)
R. K. Mishra et al.
Table 6.1 (continued)
Class of materials Materials Bandgap Additional notes Ref.
Perovskites Perovskite nanosheets by Perovskite nanosheets are a Perovskite nanosheets are a Jiang et al. (2020b)
solution-based synthesis significant class of 2D materials with promising material for
or CVD appropriate “bandgaps”, strong “PL opto-electronics and energy
response”, high power conversion conversion devices. Solution-based
efficiency, giant absorption, “long synthesis and CVD are the main
carrier lifetime”, and “large methods for their synthesis
mobilities”. They may meet the
growing demands for “on-chip
communication systems” and devices
2D double perovskites Bandgap in the range of 2.09 eV – Hoseinpour et al.
(2023)
2D For n = 1 to 4, the bandgap is General formula of Rahil et al. (2022)
Ruddlesden–Popper-type reducing from 2.51 to 1.92 eV RNH3 )2 (MA)n−1 Mn 3n+1
organic–inorganic For n = 1, the PL peak is at 518 nm where RNH3 is organic cation, MA is
perovskites n = 2, peak is at 573 nm a methylamine which stand as a small
((RNH3)2(MA)n − 1Mn n = 3, peak at 616 nm and for n = 4, organic cation, n corresponds to the
3n + 1) the peak is found to be in the range of metal halide octahedron MX6 layer
6 Heterogeneous Integration of 2D Materials with Silicon …

654 nm between insulating organic layer

composed of RNH3 and MA, M2+ is
divalent metal cation, and X− is
halide anion
(continued)
161
Table 6.1 (continued)
162

Class of materials Materials Bandgap Additional notes Ref.

2D monoelemental 2D silicene DFT calculations demonstrated that With respect to the absence of Oughaddou et al.
Xenes silicene is a zero-gap semimetal graphite structured Si in nature, (2015)
where the valance band maxima and silicene is synthesized through the
conduction band minima is touching bottom-up approach, basically
to each other in the k-point of first epitaxial growth over the substrate
Brillouin zone. Spin–orbit coupling
inclusion demonstrates that there
exists a bandgap of 1.55 meV in the
Dirac point of silicene
Germanene Spin–orbit gap present in germanene Germanene holds prominent Ould et al. (2018)
is less than 23.9 meV, which is about electronic features same as silicene
0.05 meV greater than silicene and and graphene. With respect to the
graphene reduced buckled structure and higher
spin–orbit coupling which
introducing germanene as an ideal
material to exhibit quantum spin-hall
effect
2D-layered metal 2D NiO p-type wide bandgap semiconductor 2D metal oxides have atomically thin Kumbhakar et al.
oxides (MO) holding bandgap in the range of dimension, and it holds higher (2021)
3.6–4 eV. Absorption spectra hold by amount of exposed surface sites
NiO have peak in the range of which produces a large efficiency of
1.5–3 eV which stand in the visible them to interact with other functional
range groups
2D CuO This is a most stable oxidized copper – Kumbhakar et al.
form, it exhibits a narrow bandgap of (2021)
1.2–1.8 eV, and it is a p-type
semiconductor
(continued)
R. K. Mishra et al.
Table 6.1 (continued)
Class of materials Materials Bandgap Additional notes Ref.
2D FeO It possesses an efficient Kumbhakar et al.
anti-ferromagnetism as like as its (2021)
bulk, the bandgap of 2D FeO lies in
the range of 2.12 eV, and its bulk is
about 2.05 eV
2D-layered metal 2D TiO2 Bulk counterparts of TiO2 are a wide Influence of oxygen present in its Kumbhakar et al.
oxides (MOx ) type M bandgap semiconductor having surface is altering the surface (2021)
= Ti, Sn, Mn, V and x bandgap in the range of 3 eV, and its energies and results to the
= 2, 3 2D sheets are holding a bandgap of improvement in materials properties
about 3.65 eV and found application in
photodetectors and CMOS
2D MnO2 MnO2 ’s bandgap energy is 2.23 eV, - Sakai et al. (2005)
relative to the photocurrent action
spectrum. MnO2 monolayer film
shows a 0.16% photon-to-electron
conversion efficiency under 400 nm
monochromatic light
6 Heterogeneous Integration of 2D Materials with Silicon …

(continued)
163
Table 6.1 (continued)
164

Class of materials Materials Bandgap Additional notes Ref.

2D metal oxides 2D V2 O5 Prominent absorption bands of V2 O5 2D MOs have improved mechanical Wang et al. (2022b)
(Mx Oy ) type (M = Mn, lie in the range of 350–450 nm which stability which introduces an efficient
Cu, V, Fe, Ga, Zn, Ti indicates that V2 O5 is an efficient fabrication of non-collapsible unit,
and x, y = 2, 3) material for photodetector and if we add other frameworks/
applications. Optical bandgap of composite structure, it cannot alter its
V2 O5 is in the range of 2.73 eV properties and retain their features for
a long span of time
2D Ga2 O2 Ga2 O2 monolayer is an indirect Shao et al. (2021)
semiconductor with bandgap in the
range 2.72 eV. It possesses an
efficient hole mobility of 4720 cm2
V−1 S−1 . This oxide structure has
higher absorption coefficient which
is greater than 105 cm−1 in
ultraviolet range
R. K. Mishra et al.
6 Heterogeneous Integration of 2D Materials with Silicon … 165

Fig. 6.4 AFM-based analyses explore epitaxial monolayer BN on graphite and mBN growth on
HOPG. The “AC-mode AFM topography of mBN” on HOPG reveals bright regions corresponding
to 3D hBN aggregates at “HOPG step edges” a. “Phase-channel data” highlights exposed HOPG
regions, untouched by hBN growth b. A “small-area contact-mode AFM” image captures the charac-
teristic monolayer BN step height at the mBN boundary near exposed HOPG c. A detailed view of a
zoomed-in region provides insights into specific features d. The phase-channel image corresponding
to the zoomed-in region enhances understanding of local properties e. A line-profile analysis along
the mBN-HOPG interface reveals the characteristic monolayer BN step height f. The reproduced
data are used with proper permission (Elias et al. 2019). Copyright (2019) Springer Nature

exfoliation, epitaxial growth, and electrochemical exfoliation are employed in seam-

less integration with Si-CMOS devices (Yi et al. 2021; Beaudette et al. 2020). Transfer
printing technology emerges as a promising method, offering precise control over
thickness and morphology for integrating composites with different properties (Yi
et al. 2021; Beaudette et al. 2020). Each technique caters to diverse applications
and material types, presenting a versatile toolkit for researchers (Moosa and Abed
2021). Advanced integration techniques like transfer printing, direct growth, and
indirect integration play a crucial role in optimizing integration (Ma et al. 2020).
Transfer printing offers precision and flexibility, while direct growth techniques
enable in-situ growth of “2D materials” on Si-CMOS devices for compatibility.
Successful integration of “graphene”, MoS2, and other “2D materials” has been
demonstrated, advancing electronic and opto-electronic devices (Mortazavi Zanjani
et al. 2017). Indirect integration techniques involve interlayers to address structural
and dimensional differences, minimizing lattice mismatch and offering compati-
bility with various 2D materials. However, these techniques add processing steps,
increasing complexity and cost (Kistanov et al. 2018). Hybrid integration, combining
direct growth and forwarding techniques, optimizes integration benefits, providing
166 R. K. Mishra et al.

high-quality materials and device-specific structures. However, it necessitates precise

control and optimization of the integration process (Wang et al. 2015b, 2017). The
careful selection of synthesis methods and integration techniques is imperative to
yield high-quality materials compatible with CMOS processes. Within the field
of microsystems, totally depleted “silicon-on-insulator (SOI)” CMOS technology
shows promise as a low-power, low-voltage option for integrated microsystems that
can also operate at microwave frequencies and at temperatures between 200 and
350 °C (Flandre et al. 2001). With channel lengths of around 1 μm, SOI CMOS shows
great promise for applications using heterogeneous micropower (Flandre et al. 2001).
The integration of advanced photoactive materials into wearable opto-electronic
systems marks a significant stride in scientific progress. Notably, recent develop-
ments in the synthesis of organic–inorganic halide perovskites and atomically thin
2D nanosheets have made it easier to create flexible, energy-efficient opto-electronic
devices designed for wearable applications (Lee et al. 2023). These materials demon-
strate efficient light–matter interaction and low-power multispectral sensing capabili-
ties (Lee et al. 2023). In the pursuit of achieving broad-spectrum detection and large-
scale integration in infrared photodetectors, a novel “defective macro-assembled
graphene nanofilm (D-nMAG)/silicon (Si) photodetector” has been introduced. This
groundbreaking device utilizes trap-assisted gain to optimize the “photoelectric
response”, demonstrating a commitment to environmental friendliness and compat-
ibility with CMOS technology. Importantly, it exhibits high responsivity across a
broad-spectrum region (Cao et al. 2022). Structural engineering emerges as a critical
factor in tailoring the properties of 2D BP for advanced photonic IC (Yuan et al.
2023). Systematic studies covering “deformation”, “atomic defects”, “superlattice”,
“alloying”, “thickness”, and “phase transition” have significantly contributed to a
profound understanding of the impact of “structural engineering” on the perfor-
mance of “2D BP-based devices” (Yuan et al. 2023). The “seamless integration” of
“2D materials” with “Si-CMOS devices”, spanning microsystems, opto-electronic
systems, and photodetectors holds promising potential for diverse applications. The
continuous progress in synthesis techniques and integration methods plays a crucial
role in optimizing the compatibility of high-quality materials with CMOS processes.
This comprehensive approach is indispensable for realizing efficient and versatile
electronic and opto-electronic devices, underscoring the continuous evolution in
scientific methodologies (Lee et al. 2023; Cao et al. 2022; Yuan et al. 2023).

Materials Selection and Compatibility for Heterogeneous

Integration

The “integration of 2D materials” with “Si-CMOS devices” holds promise for

advancing electronics (Huyghebaert et al. 2018). However, challenges exist, and
diverse properties of Si-CMOS and 2D materials pose obstacles, demanding careful
consideration in hetero-integration (Serdar 2019). Successful integration necessitates
6 Heterogeneous Integration of 2D Materials with Silicon … 167

meticulous material selection, taking into account factors such as thermal expansion,
electrical characteristics, chemical compatibility, and adhesion. hBN is chosen for
its thermal expansion coefficient resembling Si-CMOS, mitigating challenges like
delamination and cracking in the heterostructure (Serdar 2019). Graphene, with its
high carrier mobility, is ideal for applications requiring high-speed electronic devices,
ensuring optimal electronic performance. WS2 and MoS2 contribute to efficient
charge transfer, facilitating successful hetero-integration due to high conductivity and
work function alignment (Gupta et al. 2020; Alharbi and Shahrjerdi 2016). Chemical
compatibility is crucial for harmonious coexistence, with graphene exhibiting robust
adhesion characteristics, though challenges arise with TMDs and hBN. Techniques
are required to enhance adhesion and address challenges with TMDs and hBN in
Si-CMOS processes. BP presents challenges due to its sensitivity to environmental
conditions, requiring protective measures for stability in the Si-CMOS environment
(Wu et al. 2019). The intersection of machine learning (ML) and materials science
has significantly accelerated the discovery and understanding of novel materials
and their electronic properties (Dongale et al. 2022). Dongale et al. utilized ML
to establish design guidelines and predict the performance of “resistive switching
(RS)” memory devices, displaying its potential in industry-standard applications
(Dongale et al. 2022). Employing supervised and unsupervised ML techniques, the
researchers provided design guidelines for categorical and continuous feature sets,
revealing insights into how various device parameters influence “RS performance”.
The “ML predictions” were experimentally validated through the fabrication of
corresponding RS devices, affirming the accelerated discovery enabled by ML tech-
niques. In the pursuit of CMOS-integrable smart gas sensor devices, Mutinati et al.
addressed technological challenges associated with the integration of gas-sensitive
materials into CMOS devices (Mutinati et al. 2012). Focusing on ultrathin SnO2
layers, our study demonstrates a heightened response to H2, with linear “V-I char-
acteristics” throughout the “operating temperature range”. The promise of deposited
SnO2 layers for “post-CMOS processing of sensor films” is highlighted by their good
step coverage on passivated CMOS devices (Mutinati et al. 2012). The NanoElec-
tronics Roadmap for Europe, part of the NEREID project, offers a comprehensive
view of the future of European Nanoelectronics (Ahopelto et al. 2019). The objec-
tive of this cooperative endeavor is to formulate a medium- and long-range strategy
for the European nanoelectronics sector, tackling social obstacles and pinpointing
innovations with promise. The roadmap highlights meeting societal demands and
utilizing the advantages of the European eco-system and covers Advanced “Logic
and Connectivity”, “Functional Diversification”, “Beyond-CMOS”, “Heterogeneous
Integration”, and “System Design” (Ahopelto et al. 2019). In microelectronics and
nanoelectronics, Gao et al. proposed a novel approach to heterogeneously inte-
grating a monolithic oscillator chip using “FlexMEMS technology” (Gao et al.
2019). The “3D-stacked IC exhibits excellent performance, highlighting the potential
of FlexMEMS technology in system-on-chip hetero-integration applications (Gao
et al. 2019). A new substrate coupling simulation methodology, as presented by
Karipidis et al., provides insights into crosstalk effects in mobile communications
system-on-chip (SoC) designs (Karipidis et al. 2023). This methodology integrates
168 R. K. Mishra et al.

the “boundary element method (BEM)” with a computational “Python-based phys-

ical layout extraction” and “RC modeling” method, enabling rapid and accurate
extraction of a substrate RC mesh. The study emphasizes the necessity of consid-
ering PCB transmission lines and package parasitics for realistic simulation results
(Karipidis et al. 2023). Mizsei and Lappalainen address the More-than-Moore Grand
Challenge, focusing on 3D heterogeneous integration to surpass the limitations of
standard CMOS technology (Mizsei and Lappalainen 2018). The study introduces
the thermal-electronic logic circuit (TELC), utilizing a patented phonsistor (phonon
transistor) to represent bits using both electrical and thermal quantities within one
system. By summarizing different bit representation methods, the study lays the
foundation for advancing solid-state electronics and overcoming challenges posed
by the “red brick wall” (Mizsei and Lappalainen 2018). In the realm of microcalori-
metric sensors for measuring reaction heats, Vereshchagina et al. present a “low-
cost”, “low-power polysilicon-based microcalorimetric sensor” applicable in “cat-
alytic microreactors” and “sensor microsystems” (Vereshchagina et al. 2011). The
polysilicon thin films exhibit a “temperature coefficient of resistance (TCR)” suit-
able for “temperature monitoring” of highly “exothermic reactions”, demonstrating
immediate and reversible responses to propane in air (Vereshchagina et al. 2011).
“The integration of 2D materials” with “Si-CMOS devices” presents a transforma-
tive opportunity for advancing electronic devices, requiring meticulous considera-
tion of material properties. Graphene, TMDs, hBN, and BP are commonly explored
materials, each presenting unique properties and challenges that demand careful
consideration for seamless integration (Mishra 2018a, b; Mishra et al. 2017b, 2019).
“Wafer-level heterogeneous integration”, pivotal for “MOEMS”, “MEMS”, and
“NEMS”, accommodates diverse technologies, ensuring flexible MEMS business
models (Lapisa et al. 2011). It allows utilizing the same chip area without compro-
mising material selection. Demonstrations extend beyond conventional applications
to health care, IoT, and AI computing solutions, presenting adaptability at the panel
level (Knickerbocker et al. 2018). Exploring “epitaxial Ge” on Si with an “AlAs/
GaAs buffer architecture” for “low-power fin field-effect transistors” reveals crit-
ical aspects. Selection of epitaxial layers and their impact on fin height, along with
valence band offset, plays a crucial role in this Si-compatible heterogeneous inte-
gration (Hudait et al. 2014). Challenges arise in chiplet heterogeneous integration
concerning material demands for large-scale integration, intensified by ultra-short-
reach communication requirements (Li et al. 2020a). Mid-infrared silicon photonics
leverage low material costs and compatibility with integrated systems. The integra-
tion utilizes silicon and deposition-compatible dielectric materials, demonstrating
versatility for advanced nanophotonic platforms (Spott et al. 2017). Investigations
into epitaxial growth and layer-transfer techniques highlight the broad spectrum of
possibilities for heterogeneous integration in electronic and photonic devices (Kum
et al. 2019). The DARPA DAHI program focuses on transistor-scale heterogeneous
integration to advance semiconductor manufacturing technology (Green et al. 2015).
High-throughput multiple dies-to-wafer bonding, compatible with silicon photonics,
enhances III/V-on-Si hybrid laser integration (Luo et al. 2015). “On-chip quantum
photonic circuits” with “single quantum dot devices” advance quantum photonic
6 Heterogeneous Integration of 2D Materials with Silicon … 169

applications through heterogeneous integration (Davanco et al. 2017). The adapt-

ability and compatibility of heterogeneous integration technologies drive innovations
across diverse fields, from healthcare solutions to quantum photonic circuits.

Device Fabrication and Applications of Heterogeneous

Integration of 2D Materials with Si-CMOS

The convergence of “2D materials” with “Si-CMOS” technology presents trans-

formative potential across diverse industries (Jeong et al. 2018; Dragoman et al.
2021). This integration signifies a new era for high-performance devices appli-
cable in opto-electronics, energy storage, sensing, and spin electronics (Jeong et al.
2018; Dragoman et al. 2021). In opto-electronics, the amalgamation of “2D mate-
rials” with “Si-CMOS” is poised to revolutionize photodetectors and photovoltaic
devices (Cheng et al. 2021). These integrated solutions offer compact, low-power,
and high-speed options for optical communication, biomedical imaging, and sensor
systems (Cheng et al. 2021). The strategic selection of 2D materials and their inte-
gration with Si-CMOS technology holds promise for efficient energy storage solu-
tions, including high-performance batteries and supercapacitors (Gao 2017). This
integration addresses the growing demand for energy storage technologies with
enhanced performance (Gao 2017). Furthermore, the inherent high sensitivity and
selectivity of “2D materials” make them ideal candidates for various sensing appli-
cations (Wouters et al. 2006). These applications span gas, bio, and environmental
sensors, potentially resulting in “highly sensitive and selective sensors” capable of
detecting and quantifying diverse environmental factors (Wouters et al. 2006). The
flexibility and transparency of “2D materials”, such as “graphene and TMDs”, make
them well-suited for flexible displays and biomedical devices (Glavin et al. 2020).
This characteristic opens up new possibilities for designing and adaptable electronic
devices (Glavin et al. 2020). Additionally, the unique electronic and “magnetic
characteristics” of “2D materials” contribute to advancements in spin electronics
applications (Ahn 2020). This progress is particularly significant for data storage
and quantum computing, exhibiting the potential for future breakthroughs in these
fields (Ahn 2020). Integration challenges with Si-CMOS can be addressed using
strategies like transfer printing and direct growth (You et al. 2020). “2D materi-
als”, including “Graphene and TMDs”, possess outstanding properties such as high
“electrical and thermal conductivity”, electron mobility, and carrier density (You
et al. 2020). Graphene-based transistors, with electron mobility exceeding 300 GHz,
show promise for high-speed applications (Koppens et al. 2014). This is particularly
beneficial for practical high-frequency applications (Koppens et al. 2014). The inte-
gration of “2D materials” with “Si-CMOS” extends to improving photonic compo-
nents. For instance, graphene-based photodetectors and TMD-based LEDs have been
explored (Yu et al. 2018). Graphene-based photodetectors, valued for their reactivity
and detectability, are applicable in real-world imaging and sensing scenarios (Yu
170 R. K. Mishra et al.

et al. 2018). Meanwhile, TMD-based LEDs demonstrate high brightness and effi-
ciency, making them promising for practical display and lighting applications (Yu
et al. 2018). In the energy sector, the fusion of 2D materials and Si-CMOS holds
potential for practical batteries and supercapacitors (Li et al. 2017). The exceptional
surface area and catalytic activity of 2D materials position them favorably for use in
practical batteries and supercapacitors, highlighting their potential in energy-related
applications (Huang et al. 2012). High-energy–density graphene-based batteries and
supercapacitors exhibit rapid charge/discharge rates, promising applications in elec-
tronics and electric vehicles (Cherusseri et al. 2019). Transition metal dichalco-
genide (TMD)-based catalysts demonstrate high activity and selectivity, making them
appealing for fuel cells and solar cells (Mikolajick et al. 2021; Kataria et al. 2017).
This interdisciplinary approach converges materials science, electronics, and energy
research, highlighting the potential of integrating 2D materials with Si-CMOS for
practical applications. Kim et al. conducted detailed “electrical characterization” of
“200 mm CMOS-compatible GaN/Si HEMTs”, offering insights into key transistor
parameters at deep cryogenic temperatures (Kim et al. 2022). Addressing integration
complexities, Jiaoyan et al. explored controlled doping of TMDs for CMOS applica-
tions, utilizing Ar plasma treatment for controllable p- and n-type doping (He et al.
2023). Swayam et al. presented a systematic study on CMOS integration with the
Internet of things for detecting radioactive leaks in nuclear plants, addressing critical
challenges in the nuclear power sector (Patel et al. 2023). Park et al. introduced a
portable mini-Raman spectrometer, integrating a CMOS image sensor for analytical
advancements (Park et al. 2023). Ga Hye et al. proposed room temperature-grown
“nanocrystalline tellurium thin-films transistors” for “large-scale CMOS circuits”
(Kim et al. 2023). Wanying et al. demonstrated fabricating “CMOS inverter arrays”
using “large-area p-MoTe2 and n-MoS2” (Du et al. 2021). Fatima et al. compared
spectral sensor technologies, evaluating resonant waveguide and Fabry–Perot cavity
filters for ALS applications (Omeis et al. 2023). Rimcy et al. studied the effect of
different scintillator choices on “X-ray imaging” performance in “CMOS sensors”
(Alikunju et al. 2023). Udo et al. conducted finite element method (FEM) simula-
tions of Rayleigh waves on a stacked AlN/SiO2 /Si (100) device (Kaletta et al. 2014).
The integration of “2D materials” with “Si-CMOS” technology shows promise for
revolutionizing electronics and energy applications. In Si photonics, integrating 2D
materials enhances on-chip devices, influencing phenomena like the Rabi splitting
effect and the Purcell effect. Photoelectric modulation, altering the refractive index
with an electric field, enriches on-chip Si photonic devices (Sun et al. 2016; Li et al.
2020b; Chabi and Kadel 2020; Briggs et al. 2020; Melnichuk and Wood 2010).
Compatibility of 2D materials with Si-CMOS extends to sensing, enhancing detec-
tion capabilities. High surface area-to-volume ratios and carrier mobility enable rapid
detection of small analyte changes. Functionalization modifies electronic proper-
ties, improving selectivity for specific analytes. Atomically thin 2D materials with
strong light absorption facilitate highly sensitive optical sensors (Turunen et al. 2022;
Nikolic et al. 2020). Spin electronics, utilizing electrons’ intrinsic spin for infor-
mation encoding, is promising. Graphene and TMDs, with high electron mobility,
6 Heterogeneous Integration of 2D Materials with Silicon … 171

extended spin lifetimes, and significant surface area-to-volume ratios, offer advan-
tages for spin electronics (Liu et al. 2020; Wang and Khalili Amiri 2012; Brotons-
Gisbert et al. 2018). Integrating these materials with Si-CMOS holds promise for
high-performance spintronic devices in data storage and quantum computing (Liu
et al. 2020; Wang and Khalili Amiri 2012; Brotons-Gisbert et al. 2018). Merging 2D
materials with Si-CMOS transforms electronic devices across diverse fields. Excep-
tional characteristics, combined with Si-CMOS processability, unlock unprecedented
functionalities and possibilities.

Challenges and Future Directions

Integrating two-dimensional (2D) materials with silicon complementary metal oxide

semiconductor (Si-CMOS) devices represents a significant leap in next-generation
electronics, offering improved performance and expanded functionalities (Radamson
et al. 2020). However, scalability issues pose challenges that demand attention. The
development of scalable integration techniques is crucial for achieving widespread
commercial viability, driving ongoing research into tailored approaches for large-
scale device production (Radamson et al. 2020). Simultaneously, addressing hard-
ware compatibility becomes a central concern, encompassing both material compat-
ibility and the establishment of a suitable interface between 2D materials and Si-
CMOS devices (Das et al. 2021). Despite the formidable challenges, these issues
present opportunities for enhancing device performance, improving energy effi-
ciency, and introducing functionalities (Wang et al. 2022a). The unique mechanical,
optical, and electronic properties exhibited by 2D materials, such as graphene and
transition metal dichalcogenides (TMDs), hold the potential to augment the capa-
bilities of Si-CMOS devices (Knobloch et al. 2022). Integrating 2D materials with
Si-CMOS enhances performance, advancing power efficiency and enabling flex-
ible electronics, and gas sensors (Knobloch et al. 2022). Despite these prospects,
ensuring long-term device reliability is crucial, demanding materials and tech-
niques to minimize degradation over time (Akinwande et al. 2019). Future research
should prioritize stabilizing integrated devices, focusing on cost reduction through
process optimization and exploring alternative materials (Jiang et al. 2019; Akin-
wande et al. 2019). Heterogeneous integration of 2D materials with Si-CMOS holds
transformative potential, demanding dedicated research to overcome challenges
(Radamson et al. 2017). Experts propose new integration approaches to address
device performance, emphasizing the study of 2D FETs’ variation, stability, and reli-
ability (Das et al. 2021; Radamson et al. 2020). The exploration of two-dimensional
devices and their integration into silicon lines encompasses material synthesis, device
design, and circuitry integration, addressing on-chip challenges (Wang et al. 2022a).
Nanoscale CMOS logic based on 2D materials faces challenges, with an emphasis
on successfully integrating both n-type and p-type FETs into CMOS (Knobloch
et al. 2022). Notable contributions highlight challenges in 2D integration with Si-
CMOS, reshaping research goals to optimize transistor performance in Si-CMOS
172 R. K. Mishra et al.

technology (Akinwande et al. 2019). Proposals for ultimate monolithic-3D integra-

tion with 2D materials assess the first fully integrated M3D-IC with 2D materials,
discussing associated challenges (Jiang et al. 2019). Tackling challenges in advanced
CMOS processes from 2 to 3D outlines research directions for vertically integrating
many layers or devices in the chip (Radamson et al. 2017). A comprehensive review
spanning six decades of research on 2D materials explores challenges related to their
integration into hybrid 2D CMOS–2D memristor systems (Schwierz and Ziegler
2022). In conclusion, integrating 2D materials with Si-CMOS devices poses chal-
lenges that, when strategically navigated, present unprecedented opportunities for
advancing electronic technologies.

Conclusions

The integration of “2D materials” with “Si-CMOS devices” holds promise for
advancing next-generation electronics. This article offers a comprehensive overview,
beginning with an introduction to 2D materials and their properties. Subsequently, it
delves into Si-CMOS devices, elucidating their limitations and thoroughly examining
the benefits of integrating 2D materials with them. Various integration techniques,
such as transfer printing and direct growth, are discussed, highlighting challenges
like disparate thermal expansion coefficients and distinct material properties. Case
studies featuring graphene-based field-effect transistors (FETs) and MoS2-based
FETs integrated with Si-CMOS devices demonstrates superior performance and
enhanced functionality. The exploration of diverse integration techniques demon-
strates the versatility of 2D materials in overcoming challenges associated with
Si-CMOS devices. In conclusion, the article reflects on the future prospects of
integrating 2D materials with Si-CMOS devices, emphasizing their impact across
various applications, including electronics, sensing, and energy conversion. This
research contributes valuable insights to the field, paving the way for advancements
in electronic technologies.

Acknowledgements The research has received funding from the UK Engineering and Phys-
ical Sciences Research Council (EPSRC), Ref. EP/R016828/1 (Self-tuning Fiber-Reinforced
Polymer Adaptive Nanocomposite, STRAIN comp) and EP/R513027/1 (Study of Microstructure
of Dielectric Polymer Nanocomposites subjected to Electromagnetic Field for Development of
Self-toughening Lightweight Composites).

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 Part II
Beyond CMOS Charge Based Steep
Switching Devices: Recent Trends
and Opportunities
Chapter 7
TFET: From Material to Device
Perspective

Pradeep Kumar Kumawat, Shilpi Birla, and Neha Singh

Abstract Due to continuous scaling of the MOS, the performance has been degraded
due to PVT variations. The high level of leakage currents, threshold variations, and
short-channel effects are responsible toward the degradation of the MOS devices. At
this point of time, a device which exhibits low leakage and low subthreshold swing
is much needed, and tunnel field-effect transistors (TFETs) reported to be a suitable
alternative to MOSFETs. TFETs basically worked on the quantum tunneling effect,
and the band-to-band tunneling mechanism is used in which the charge carriers
whether electrons or holes pass through a thin energy barrier between the source
and the channel regions. It has basically three regions: source, drain, and channel.
Semiconductor material like silicon or III–V compounds is used for channel regions.
For gate oxide, the dielectric material is used, and choice of high k dielectric material
is very crucial. The high dielectric constant materials (high k) are preferred as they
help in reducing the tunnel barrier. In this chapter, we have discussed need of TFET
devices, their structure type of TFETs along with applications.

Keywords TFETs · MOSFET · Band-to-band tunneling · Short channel effect

Introduction

The thermionic emission principle used by MOSFETs results in high power

consumption because carriers must pass the potential barrier. In the device carrier
tunnels from source to channel in tunnel FETs (TFETs) due to gate field-
induced band-to-band tunneling (BTBT), its operation is different from conventional
MOSFET. The gate voltage required to raise the drain current by ten times is referred
to as subthreshold swing (SS). In the log I ds − V gs plot, the region where V gs is
lower than the threshold voltage is known as the subthreshold region. V dd scaling
is significantly impacted by the subthreshold swing given the necessary on-state

P. K. Kumawat · S. Birla (B) · N. Singh

Department of Electronics and Communication Engineering, Manipal University Jaipur, Dehmi
Kalan, Jaipur, Rajasthan, India
e-mail: [email protected]

© The Author(s), under exclusive license to Springer Nature Singapore Pte Ltd. 2024 183
S. Singh et al. (eds.), Beyond Si-Based CMOS Devices, Springer Tracts in Electrical and
Electronics Engineering, https://doi.org/10.1007/978-981-97-4623-1_7
184 P. K. Kumawat et al.

current I on and off-state current I off (Satheshkumar 2012). The subthreshold swing
in a MOSFET is computed by ln10 (kT /q) and exhibits a minimum of 60 mV/decade
at 300 K temperature (Zhang et al. 2006; Poorvasha et al. 2017). A high subthreshold
swing causes MOSFET limitations. TFET can overcome the limitations of MOSFET
because TFET has the advantage of operating on the band-to-band tunneling prin-
ciple. This mechanism uses much less power than a MOSFET, and by modifying
certain device parameters, the subthreshold swing of a TFET can be improved. These
device parameters include the dielectric material and its thickness, the gate material
and its work function, the body thickness and doping, etc. (Saurabh 2017).
In this chapter, we study the basics of TFET devices. Different device structures
of TFET and types will be described to understand the characteristics of TFETs and
further illustrate the use of TFETs in digital circuits and their applications. In the last
part of this chapter, rectifiers and charge pumps using TFETs are demonstrated.

Need for TFETs

MOS technology experienced a large transition in the device parameters and

compactness when downsizing. However, the rate of scaling has recently slowed
down. The threshold voltage must be scaled down to improve the current, but due
to a decrease in threshold voltage, leakage current will increase, and in the case of
MOSFET, the threshold voltage cannot be lowered as a result of the subthreshold
swing constraint.
Source–drain leakage current, power consumption, subthreshold swing, and short-
channel effects (SCEs) are very important parameters that should be required very
less in a device, and MOSFET devices exhibit high leakage current, high-power
consumption, high subthreshold swing, and short-channel effect. So, it is very crucial
to investigate novel device structures that can provide subthreshold swing values
as low as possible, low power consumption, and leakage current. It is extremely
difficult to decrease the supply voltage in MOSFET devices that use thermionic
injection. Several devices such as nanowire gate-all-around FETs, carbon nanotube
FETs, FinFETs, impact ionization FETs, and tunnel FETs have been demonstrated
by numerous researchers to consider the roadmap for the future.
The important feature of the TFET device is that it demonstrates improved perfor-
mance in terms of subthreshold swing (< 60 mV/dec at 300 K) and it can be improved.
This is only possible due to the device parameter variation and various source-to-
channel carrier injection techniques used in TFETs. Impact ionization FET displays
less subthreshold swing as well. However, because impact ionization FETs require
an extremely high voltage to operate, TFET is the only alternative to FinFET and
nanowire FETs which shows promise (Saurabh 2017).
7 TFET: From Material to Device Perspective 185

Fig. 7.1 TFET device structure a NTFET and b PTFET (Saurabh 2017)

TFET Device Structure

The TFET device consists of asymmetric structure because the source and the drain
on both sides have different doping types. This also restricts the exchange of source–
drain which is possible in MOSFETs. The source and the drain on both sides have
different doping types while the channel is either intrinsic or lightly doped. Due to
BTBT, the charge carriers tunnel from the source to the channel and this tunnelling
helps to achieve I on /I off ratio. The energy level in the valence band of the source
and the energy level in the conduction band of the channel are not aligned in the off
condition of the device that prevents carriers from tunneling and keeps the leakage
current very low. When the gate is biased and the device is in the on state, the
conduction band of the channel region is pushed downward, allowing it to align with
the valance band of the source. This alignment permits carrier injection and tunneling
from the source region to the channel region by reducing the breadth and height of
the tunneling barrier. As a result, TFET devices can operate effectively below the
subthermionic limitations with subthreshold swing values below 60 mV/dec. When
the bands are in alignment, this enables a quick turn-on. The charge carrier flowing in
the channel defines the type of the TFET. TFETs are two types: When the electrons
inject from source to channel, the TFET is called as N-type TFET, and when the holes
are injected into the channel through the source, the TFET is called as P-type TFET
(Saurabh 2017). The device structure of N-type and P-type TFETs is demonstrated
in Fig. 7.1.

CMOS Versus TFET

Tunnel FETs (TFETs) are currently the subject of much interest and have emerged
as an alternative of CMOS devices. For extremely low-power and energy-efficient
computing applications, the tunnel FET has been proposed as a replacement for tradi-
tional CMOS technologies. The TFET is one of the most appealing steep subthreshold
slope devices. As a result, TFETs have been researched a lot as a solution for low
power density and energy efficiency issues.
186 P. K. Kumawat et al.

Fundamentally, tunnel FETs can scale their threshold voltage (V th ) and V dd beyond
the capabilities of CMOS without affecting their static leakage and current because
of their extremely steep subthreshold slope. Numerous studies have looked at TFET
benchmarking at circuit level with a variety of objectives that are useful in device
design. Numerous studies have been done that compares TFET transistors to CMOS
(Núñez and Avedillo 2017).

Types of TFET

The simplistic design of a TFET when compared to MOSFET exhibits a steeper

subthreshold swing at room temperature. The difficulty with this realistic TFET
construction is to achieve better on-state current (I on ). Based on device structure,
TFET is divided into two categories: (i) planar TFET and (ii) three-dimensional
structures of TFETs (Mamidala et al. 2016).

Planar TFETs

A device with a planar current-carrying surface is referred to as a planar TFET. 2-D

structure of surface tunnel transistor, SOI structured TFET, junctionless TFET, dual-
gate TFET, heterojunction TFET, and PNPN structure TFET are some examples of
planar TFET demonstrated in this section.

Surface Tunnel Transistor

The first transistor to use a tunneling mechanism was the surface tunnel transistor.
The surface tunnel transistor is a planar type TFET, and the device structure is similar
to a p-i-n diode structure. In a surface tunnel transistor, the channel is intrinsic, and
the channel and gate are separated by an insulator. The type of doping for drain and
source is not similar (Baba 1992; Turkane and Kureshi 2016). For source, the type
of doping is different from drain or opposite in nature. The structure of the surface
tunnel transistor is depicted in Fig. 7.2.

SOI Structured TFET

A buried oxide (BOX) thin layer distinguishes an SOI TFET structure from the
surface tunnel transistor. The structure of an SOI TFET is depicted in Fig. 7.3. It is
made from a layer of ultrathin (about 10 nm) silicon (Si) formed on a Si substrate
above a layer of buried oxide (roughly 100 nm). Before the deposition of the gate,
source, and drain metal contacts, the gate oxide is mounted on the thin silicon layer.
7 TFET: From Material to Device Perspective 187

Fig. 7.2 Surface tunnel transistor (Baba 1992)

Fig. 7.3 SOI TFET

structure (Turkane and
Kureshi 2016)

The drain and source are then made using the proper doping in the Si layer. When
the whole thin Si layer is drained, the buried oxide layer in an SOI TFET prevents
all sources to drain leakage across the bulk region. The source/drain to substrate
capacitance is decreased as a result of the smaller source–body and drain–body
depletion regions that also improved gate control (Mamidala et al. 2016; Turkane
and Kureshi 2016).

Junctionless TFET

As implied by the name, there is no P–N junction and metallurgical junction exists in
JTFET. The benefits of both TFET and JLFET are present in JLTFET. In this, source
and drain both have the same type of doping. The channel is also heavily doped.
Frequently, silicon is used to create junctionless TFETs. The subthreshold swing
and current can be improved by using a high-k material. The p-gate and control gate
have different work functions. The control gate work function is often lower than the
p-gate work function to achieve higher current and subthreshold swing (Ghosh and
Akram 2013). Figure 7.4 depicts the JLTFET’s structure.

Dual-Gate TFET

Dual-gate TFET exhibits a primary and auxiliary gate where each gate has a
different work function (Dutta et al. 2018). To enhance the gate control over the
188 P. K. Kumawat et al.

Fig. 7.4 Junctionless TFET structure (Ghosh and Akram 2013)

Fig. 7.5 Dual-gate TFET

(Usha and Vimala 2019)

channel, multiple gate materials can be employed. Dual-gate TFET provides supe-
rior gate control than single-gate TFET or conventional TFET. Dual-gate TFETs
have improved electrostatic control, minimal DIBL effects, high on-state current,
low off-state current, and a high I on to I off ratio (Usha and Vimala 2019). Figure 7.5
depicts a dual-gate TFET structure.

Heterojunction TFET

Heterojunction TFET consists of different materials at the source–channel interface.

Usually, III–V compound materials are used in heterojunction TFETs. Heterojunc-
tion TFET shown in Fig. 7.6 consists of AlGaAs as the source material and InGaAs
as the drain material. The same material can be used for the channel region also.
Heteromaterial junction can give better results for III–V compound semiconductors.
In the source, small direct gap material is used to enhance I on, and, in the channel
and drain region, a large bandgap material is used to diminish the off current. The
best results in terms of leakage current and subthreshold swing are displayed by
heterojunction TFETs (Turkane and Kureshi 2016; Salehi et al. 2013). Figure 7.6
depicts the heterojunction TFET structure.
7 TFET: From Material to Device Perspective 189

Fig. 7.6 Heterojunction TFET (Turkane and Kureshi 2016)

PNPN Structure TFET

Another well-known TFET that uses a source pocket is the PNPN TFET that boosts
the tunneling rate. In PNPN structure TFET, the tunneling is done at the interface
of the source and source pocket that results in a reduced tunneling width and an
improved tunneling rate. PNPN TFET structure is depicted in Fig. 7.7. As compared
to conventional TFETs, this PNPN TFET exhibits higher I on current and a low
subthreshold current (Marjani and Hosseini 2014).

Three-Dimensional TFETs

The FinFET and the gate-all-around nanowire TFET are two of the most significant
three-dimensional structures (Mamidala et al. 2016).

Fig. 7.7 PNPN structure TFET (Marjani and Hosseini 2014)

190 P. K. Kumawat et al.

Fig. 7.8 Tri-gate (22-nm

node) transistor (Naif 2021)

FinFET

FinFETs are one of the types of multi-gate field-effect transistors that have supe-
rior gate control to planar MOSFET. A fin-like piece of the thin silicon film is
used in FinFETs. FinFET is a non-planar three-dimensional device. The gate in
a FinFET regulates both sides of the fin channel. To improve electrostatic control
over subthreshold leakage and saturation current, the FinFET structure was created.
FinFET can replace bulk MOSFETs due to their improved SS, improved stability,
higher I on /I off ratio, improved short-channel performance, and lower intrinsic gate
capacitance. Among other FinFET variants, tri-gate and double-gate structure show
good short-channel properties (Maurya and Bhowmick 2022). It was Intel that
commercially released the first silicon chips based on FinFET technology in 2012.
Intel was the company that made the first generation of 22-nm node FinFETs (Naif
2021). Figure 7.8 depicts this tri-gate 22-nm node FinFET.

Gate-All-Around Nanowire TFET

A gate-all-around (GAA) TFET considerably enhances the gate control that a double-
gate TFET already provides. The nanowire is suitable for continuously getting
smaller transistors due to its small size. The diameter of the nanowire is the most
crucial physical factor in a nanowire TFET. To enhance the gate control, the diameter
of the nanowire should be reduced resulting in a higher I on and a steeper subthreshold
swing. The structure of a GAA TFET is depicted in Fig. 7.9. It consists of a channel
length of 100 nm, drain and source of 20 nm length, oxide thickness (t ox ) of 2 nm,
and a radius of 10 nm (Usha and Vimla 2021).
7 TFET: From Material to Device Perspective 191

Fig. 7.9 GAA TFET structure (Usha and Vimla 2021)

Tunneling Boosters: Si–Ge, Doping Effect, Ultrathin Body

A TFET device must possess certain qualities such as high I on , low I off, and minimum
subthreshold swing for achieving better switching performance. The device charac-
teristics can change with a slight modification in its physical parameters. The large
energy bandgap of a conventional Si TFET causes it to have a low on current and
small subthreshold swing in addition to low off current also which is required. One
of the most popular approaches for utilizing a small bandgap of germanium while
maintaining the I off within an acceptable amount is to employ germanium coupled
with silicon in a heterojunction. Due to the effective bandgap of both silicon and
germanium, the I on produced in a Si–Ge heterojunction-based TFET is higher than
Si and Ge TFET. In Si–Ge heterojunction-based TFETs, a low I off is achieved by
taking advantage of a silicon-wide bandgap. Additionally, germanium is used to
increase the I on because of its narrow bandgap (Saurabh 2017; Toh et al. 2008; Shih
and Chien 2011).
As the source doping concentration rises, the electric field in the source–channel
junction increases, which results in the bandgap narrowing and the energy bandgap
decreasing. As a result, the I on current increases. The abrupt source doping concen-
tration affects the tunneling current as well. The more abrupt the doping and the
more I on current it produces, the stronger the electric field at the source channel
junction. It should be noted that source doping concentration has no impact on the
I off current. The subthreshold swing can be reduced and I on can be increased even
for a non-abrupt source doping profile by selecting the gate–source overlap (Saurabh
2017; Hyung and Chi 2009).
Drain current and subthreshold swing, two electrical properties of TFETs, are
dependent on body thickness. In a TFET, silicon body thickness affects the amount
of silicon that is available for BTBT, which raises the drain current. However, body
thickness also affects gate control. As a result, as body thickness increases, the
gate control degrades, and the drain current decreases. Optimal body thickness is
necessary for maximum drain current. I on current decreases for the dual-gate TFET
with a 5 nm body thickness due to the thin body and small Si volume at tunneling.
The Si volume for BTBT increases as body thickness rises to 10 nm. Due to the gate
control being successfully reached in the middle of the thin Si layer, the resulting I on
increases almost linearly. Additionally, the gate-to-channel coupling is effective as
192 P. K. Kumawat et al.

Si body thickness exceeds 10 nm, and up to 20 nm, I on current increases as a result

of effective gate–channel coupling. Beyond 20 nm, however, I on decreases due to
weaker gate control (Saurabh 2017; Toh et al. 2007; Luisier and Klimeck 2009).

Carbon Nanotube and Graphene TFETs

Since tunnel FET research is still in the exploratory stage, scientists are experimenting
with a wide variety of material systems including various carbon allotropes to realize
TFETs. Carbon nanotube (CNT) and graphene have small and moderate bandgaps
that are suitable for use in TFETs.

Carbon Nanotube (CNT) TFET

In contrast to the conventional MOSFET structures that uses bulk Si as the channel
material, a carbon nanotube FET (CNTFET) uses a single or an array of carbon
nanotubes. Either a ballistic or diffusive conduction mechanism can be used in a
CNT. When the electron is transmitted without interference from defects, impuri-
ties, or phonon scattering, this is called as ballistic transport. Ballistic transport is
possible if the length of a CNT is shorter than the mean free path length in the mate-
rial. Although the mean free path of CNT is incredibly long, as a result, ballistic
transport can be seen in CNTs with lengths close to 100 nm at room temperature.
The conduction mechanism, which is a key factor in determining electrical properties
like I on and subthreshold swing, is crucial in CNT transistors making the ballistic
transport important. Additionally, there is no energy loss in the channel if the trans-
port mechanism in a transistor is solely ballistic (Saurabh 2017; Frank et al. 1998;
Poncharal et al. 2002).
CNT has a small effective carrier mass and is a direct bandgap material. As a result,
a CNT TFET has higher tunneling than a TFET built using a silicon-based indirect
bandgap material. To preserve the carriers’ transverse momentum in indirect bandgap
materials, additional processes like phonon emission or absorption are necessary that
reduces the BTBT rate. Based on their diameter and chirality, CNTs have a moderate
bandgap that can vary over a broad range. A CNT gate voltage can be precisely
controlled over the bands using one-dimensional electronic transport. As a result, a
CNT TFET can have its valence band elevated above its conduction band by using
a small gate voltage. CNT’s small diameter increases BTBT causing the on-state
current to be larger (Koswatta et al. 2009). A schematic view of CNT TFET is
depicted in Fig. 7.10. When phonon scattering is taken into account with ballistic
mode of operation, the simulation findings (Koswatta et al. 2009) demonstrate that
the subthreshold swing is less than 60 mV/dec at room temperature (Saurabh 2017).
7 TFET: From Material to Device Perspective 193

Fig. 7.10 Schematic view of CNT TFET (Saurabh 2017; Koswatta et al. 2009)

Graphene TFETs

Since graphene’s bandgap is around zero, obtaining a minimum I off and a high I on
is the most challenging problem for TFETs based on graphene. As a result, the
main objective of research on graphene TFETs is to create a controlled bandgap
that will allow transistors to be switched off. Graphene does have some drawbacks
but it also has some benefits. Greater gate control and reduced short-channel effects
are made possible by graphene atomic layer thickness. With a low effective mass,
graphene has extremely good carrier mobility. Different kinds of heterostructures can
be formed using graphene, and graphene-based heterostructures can produce small
effective bandgaps. Graphene-based TFETs include graphene nanoribbons (GNR)-
based TFET, bilayer graphene TFET, graphene-on-based TFET, and zero-bandgap
graphene TFET. All of these structures utilized various methods to create a usable
bandgap. Only TFETs based on GNR will be discussed in this section (Saurabh 2017).
A lot of research is being done on the potential applications of graphene nanorib-
bons (GNR) for TFETs. However, it is very difficult to fabricate GNR with deter-
ministic characteristics like width, edge disorder, and roughness. The crucial role
that edge bond relaxation plays in determining the electrical properties of a GNR
TFET is its most distinctive characteristic. The abrupt change in the characteris-
tics of the carbon–carbon bonds at the GNR edges is where the edge bond relax-
ation first appears. Furthermore, despite significant advancements in graphene-based
electronics, the increase in I off at higher supply voltages makes it still very diffi-
cult to develop graphene-based TFETs that can outperform conventional MOSFETs
(Saurabh 2017; Zhao et al. 2009). Figure 7.11 depicts a schematic view of GNR-based
TFET where L = 30 nm and t ox = 1.5 nm.
194 P. K. Kumawat et al.

Fig. 7.11 Schematic view of a GNR-based TFET (Zhao et al. 2009)

Digital Circuits and Current Mode Logic

Digital Circuits

Power dissipation, delay, rise and fall times, and the area of the designed circuit are
the main factors that are used to determine the performance of digital circuits. These
characteristics are derived for TFET-based circuits and put up against its rival CMOS
circuits to assess the advantage of tunnel FET over MOSFET for digital applications.
The most fundamental digital circuit is an inverter. So, researchers have focused more
on the characteristics of inverters made with TFETs.

TFET Inverters

A PTFET forms the pull-up network in the TFET inverter circuit, and NTFET
forms the pull-down network similar to CMOS as depicted in Fig. 7.12. An inverter
using a PTFET with a lower driving strength exhibits asymmetrical behavior in its
voltage transfer characteristics. In general, NTFETs have better driving strength as
compared to PTFETs. Multiple PTFETs can be used in a pull-up network to resolve
this problem. Multiple PTFETs make the symmetrical transfer characteristics and
switch at V dd /2. The current in the PTFET is increased using device-level methods
(Baravelli et al. 2014).
Even when the V dd = 0.2 V, a strained Si nanowire TFET-based inverter shows a
sharp transition in the voltage transfer characteristics (VTC). However, for high input
7 TFET: From Material to Device Perspective 195

Fig. 7.12 Circuit diagram of TFET inverter and transient response showing overshoot and
undershoot (Saurabh 2017; Dey et al. 2012)

voltage, the output voltage is greater than 0 V and for low input voltage, the output
voltage is less than V dd for an inverter. This decline in inverter properties is caused
by the TFET ambipolar behavior (Dey et al. 2012). The VTC of an inverter shows
rail-to-rail transitions if the NTFET and PTFET ambipolar currents are suppressed
using the appropriate device optimization techniques. The VTC of the TFET inverter
can significantly degrade when compared to a CMOS inverter as a result of TFET
delayed onset of saturation (Saripalli et al. 2011). Transients of undershoot and
overshoot are frequently seen in the transient response of a typical TFET-based
inverter. Simulations and experiments have shown (Dey et al. 2012) that a TFET
inverter exhibits overshoot and undershoot during transient responses. The inverter
overshoots and undershoots when the input changes from low to high or from high
to low (Saurabh 2017; Mookerjea et al. 2009).
The competitive advantages of TFET inverters over CMOS inverters have been
evaluated by several researchers. The majority of studies show that advanced
MOSFET-based CMOS inverters are faster at higher supply voltages while TFET
inverters are quicker at lower supply voltages. For example, at low supply voltage
V dd = 0.25 V, TFET inverter outperforms FinFET inverters by 10 and 100 times
faster, respectively. If the supply voltage increases (V dd > 0.4 V), TFET inverters are
not superior to inverters realized using FinFET in terms of competitive advantage
(Baravelli et al. 2014).

Applications in Digital Circuits

The unidirectional current flow in TFET creates some problems with the conventional
use of TFETs for pass-transistor logic even though they can be used to implement
pass-transistor logic because these issues can be demonstrated using a circuit that
uses PTFET and NTFET with an input connected to their source and output connected
to their drain terminal of transistors. The select signal is connected to the gate of an
NTFET, and the invert of the select signal is connected to the gate of a PTFET as
shown in Fig. 7.13.
196 P. K. Kumawat et al.

Fig. 7.13 Pass-transistor circuit diagram using TFET (Saurabh 2017)

The conduction of transistor during the select signal highly depends on the polarity
of the voltage V ds (V ds = (V out − V in )). For a positive value of V ds , the NTFET
conducts while for a negative value of V ds , the PTFET will conduct. Although, if
the MOSFET is used instead of the TFET in this circuit, for the high value of select
signal, PMOS and NMOS will both conduct and will provide a robust drive current
and robust 0 and 1 logic. As a result, it is anticipated that the implementation of pass-
transistor logic using TFET will be slower than that of pass-transistor logic using
MOSFET. By connecting two NTFETs in parallel with their drains facing opposite
directions, the issue with using TFETs to implement pass-transistor logic can be
avoided. If the signal select is high, the NTFET-top will conduct if V ds_NTFET-Top is
greater than 0 V, and the NTFET-bottom will conduct if V ds,NTFET-Bottom is greater than
0 V. Thus, a bidirectional switch can be achieved. However, including an additional
NTFET increases the circuit area and input capacitance (Saurabh 2017; Mukundrajan
et al. 2012) (Fig. 7.14).
Multiplexers can be implemented using pass-transistor logic, and a TFET unidi-
rectional current flow can be used to achieve a compact implementation. When
implemented using conventional MOSFETs, a topology that combines the pull-up
network and pull-down network would typically result in a short circuit. However,
the unidirectional current flow in a TFET allows for this to happen. As a result,
the compact multiplexer implementation can use eight rather than ten transistors
(Saurabh 2017; Morris et al. 2014). Apart from this, TFETs have been widely used
in memories like SRAM and analog circuits also.
7 TFET: From Material to Device Perspective 197

Fig. 7.14 Pass-transistor logic circuit using two NTFETs (Saurabh 2017)

Current Mode Logic (CML)

Compared to static logic, CML circuits offers a lower voltage swing. The schematic
for a CML circuit using TFETs is depicted in Fig. 7.15. The two sections of the
schematic are a pull-up and a pull-down networks. The pull-up network of CML
consists of two PTFETs. Instead of two PTFETs, two resistors can be used, but
PTFETs in pull-up network exhibit significantly less power and has a smaller surface
area comparatively. Pull-up networks in CML primarily serve as loads to control the
DC voltage drop at the output. The resistance of PTFET can be changed by simply
adjusting the gate bias that will change the output voltage accordingly. At the bottom,
one NTFET is integrated to serve as a current source and regulate the output voltage
swing. In a CML circuit, the main functional component is the NTFET-based pull-
down network. Different combinations of a group of TFETs can be used to implement
the various logic functions. Note that differential pairs must be used as the pull-down
network inputs.
A current mode inverter/buffer based on a TFET is depicted in Fig. 7.15 where two
inputs IN and INb control a single pair of transistors. The constant driving current is
supplied by transistor M5 which is tunable by gate voltage V bias . The outputs O/P1
and O/P2 are charged and discharged using transistor M5 as well as transistors M3
and M4. When logic 1 is applied at IN, M1 is activated, and the constant current I c
travels along the left side of the circuit. This causes O/P1 to discharge to a specific
value between V dd and GND, while O/P2 alternately charges to quasi V dd . It should
be noted that logic 1 is relatively close to V dd while logic 0 is typically defined as
half V dd . As the O/P1 voltage is below logic 1, it is considered to be logic 0 in
this situation. The schematic achieves the inverter function if the inverted O/P2 is
extracted as the inverted output and O/P1 is extracted as the output. However, if O/
P1 is treated as the inverted output and O/P2 is treated as the output, the circuit acts
as a buffer (Bi et al. 2017).
198 P. K. Kumawat et al.

Fig. 7.15 CML circuit and CML using TFET (Bi et al. 2017)

TFET-Based Rectifiers and Charge Pumps

Energy-harvesting converters produce a small output voltage that values in a typical

environment. These values must be increased for use by electronic systems due to the
small temperature gradients and low radio frequency power obtained by antennas.
In scenarios with extremely low voltage, TFETs exhibit promise as intriguing
components to include in the necessary power conversion circuits.

TFET-Based Rectifiers

The gate cross-coupled rectifier topology has received attention because of its easy
implementation and works effectively in low voltage/power applications. According
to the authors’ findings (Cavalheiro 2017), the GCCR with GaSb–InAs heterojunc-
tion TFET (HTFET) devices offers superior power conversion as compared to other
rectifier topologies. The power conversion efficiency (PCE) is greater than 50%
between −40 and −25 dBm. By lowering the reverse-biased losses of individual
transistors at the rectifier stage, it is possible to increase the voltage or power range
of rectifiers despite good performance demonstrated at low power operation. At
higher voltage levels, the PCE falls not only as a result of the on-state transistors’
increased conduction losses but also as a result of the not fully closed transistor’s
on-state operation and the subsequent flow of reverse current (Cavalheiro et al. 2017)
(Fig. 7.16).
When compared to thermionic devices, TFETs in rectifiers have a small reverse
current and higher drive current at low supply voltages which results in high PCE at
lower RF voltage. For each TFET device in GCCR, the bulk of the period cycle is
spent in off state. At low reverse bias voltage, the magnitude of the reverse current
7 TFET: From Material to Device Perspective 199

Fig. 7.16 a Gate cross-coupled rectifier (GCCR) using TFET and b region I and II operation
(Cavalheiro 2017; Cavalheiro et al. 2017)

rises and then falls at higher values of reverse bias defining the negative differential
resistance region of the TFET. While thermionic device exhibits a reverse current,
under these circumstances, it gets stronger as the reverse bias gets stronger. The
TFET structure similar to the intrinsic p-i-n diode is in forward bias when reverse
bias is applied. The performance of TFET-based rectifiers is significantly decreased
because the large increase in reverse current in TFETs occurs at large increases in
reverse bias, which are both associated with high RF voltages. The reverse losses in
the heterojunction TFET-GCCR exponentially increase as the RF voltage magnitude
increases. Due to this, TFETs can only operate at low voltage in rectifiers (Cavalheiro
et al. 2017; Liu et al. 2014). As the solution to the significant losses caused by TFETs
in rectifiers, during the off-state condition, apply a low value of V gs . By applying
V gs equal to V ds , the reverse current of the HTFET (L g = 40 nm) is attenuated over
a large range of reverse bias.
To decrease the losses in rectifiers, a new topology is therefore required.
Researchers proposed a different topology using TFET devices in which the gates
of transistors T1 and T3 are biased with RF+ when RF+ is greater than RF− signal
applied (Cavalheiro 2017). Similarly, a gate of T2 and T4 is biased with RF− when
RF− < RF+ . The transistors T1 and T3 as well as T2 and T4 share the same gate to
achieve this behavior. The gates of T1 and T3 must be biased by two auxiliary TFET
devices T5 and T6, and the gates of transistors T2 and T4 must be biased by two
auxiliary transistors T7 and T8. The researcher proposed a topology to maintain the
same V ds bias for the four primary transistors T1 to T4 (Fig. 7.17).
In an ideal rectifier, the primary transistors T2 and T3 and the auxiliary transistors
T5 and T8 are in the on state in the region 1 of operation when RF+ > RF− , whereas
other transistors are in off state. T1, T4, T6, and T7 are characterized as being in on
the state in region 2 of operation when RF+ > RF− , while other transistors are in the
off state.
Ideally, the value of voltage V gs is zero at the reverse-biased condition in regions
1 and 2. In an ideal situation, forward bias magnitude of V gs is same as it is there for
traditional GCCR topology. This situation considerably reduces the reverse current,
and resultant reverses the losses of the topology. It is significant to notice that at
this moment, auxiliary transistors in this rectifier topology running in their off-state
condition show a nonzero V gs value suggesting that the reverse current in these
200 P. K. Kumawat et al.

Fig. 7.17 TFET rectifier (Cavalheiro 2017; Cavalheiro et al. 2017)

transistors is predicted. The ratio of widths between the main and auxiliary devices
can be increased to reduce the reverse losses caused by the auxiliary transistors and
enhance the PCE of the rectifier stage (Cavalheiro 2017; Cavalheiro et al. 2017).

TFET-Based Charge Pump

Numerous methods including charge pumps have been researched to help low-power
energy harvesting devices to improve their output voltage. Higher power conversion
efficiency is made possible by TFET devices when compared to employing a standard
technology in the charge pump circuit.
A typical charge pump using TFETs is shown in Fig. 7.18 with a gate cross-
coupled (GCCCP) architecture. When operating at low voltages, this GCCCP charge
pump performs better than other charge pumps. Two operational regions make up the
GCCCP converter’s operating principle. CLK 1, low-to-high transition in a region I
causes node int1 voltage to increase to 2V dd − V ds1 . At node int2, voltage is decreased
and reaches V dd − V ds2 . At the same time, transistors T1 and T4 operate in an off
state at reverse biased in this region, and the other two transistors are in on state and
forward biased. In region II, T1 and T4 are in a forward-bias condition and other
transistors are in a reverse-bias condition, resulting in decrease in voltage at node
int1 for the CLK 1 at high-to-low transition and increase in voltage at node int2 for
the CLK 2 at low-to-high transition (Cavalheiro 2017; Cavalheiro et al. 2017).
It is crucial to reduce the reverse current generated by TFETs when they are
operating in their off state, because the transistors used in charge pumps operate at
7 TFET: From Material to Device Perspective 201

Fig. 7.18 a Conventional charge pump, b charge pump using TFET device, c I and II regions
(Cavalheiro et al. 2017)

forward and reverse bias throughout successive periods (Cavalheiro 2017). To lower
the reverse losses of the converter and increase conversion efficiency at a large range
of voltage operations, a change in the conventional charge pump topology is needed.
In heterojunction TFETs (HTFET), gate bias can control the magnitude of reverse
current. In the reverse-bias condition of an HTFET, the reverse current magnitude
is independent of the V gs value. To more effectively reduce this reverse current, the
internal resistance of the device should be increased in the reverse-bias condition for
a low V ds value (less than 0.7 V), or this current can be reduced by applying V gs =
0 V at reverse-bias condition. These are the limitations of using HTFET devices in
charge pumps during reverse current conduction. Also, power conversion efficiency
decreases if V ds is higher than 0.7 V.
By varying the V gs value of the reverse-biased tunnel FETs, changes to the conven-
tional GCCCP topology can enhance PCE for lower voltage operations. In (Caval-
heiro et al. 2017), the researchers proposed a change to the typical GCCCP topology.
In reverse-biased condition, two p-type transistors gate control signals are redirected
to the bottom of the two coupling capacitors and drive the V gs of T3 and T4 to V ds1
and V ds2, respectively. Additionally, under reverse-bias conditions, T1 and T2 do not
show attenuated reverse current conduction. Therefore, a new topology is required.
Setting the V gs = 0 V of heterojunction TFETs operating under reverse-biased
conditions or off state may be a feasible circuit-level methods to reduce the reverse
current. As demonstrated in Fig. 7.19, auxiliary transistors and capacitors can be
employed to implement this behavior. The n-type transistor (T1) is connected and
biased by the auxiliary transistor T aux and capacitor C aux as shown in Fig. 7.18. While
the p-type transistor (T3) is connected and biased by two auxiliary inverters (T aux ) and
capacitor C aux, and a similar method is applied for other T2 and T4 transistors which
(Cavalheiro et al. 2017) provides a demonstration of the full simulation process.
When the transistor T1 is forward biased, the proposed solution is applied at V gs =
0 V, and when it is reverse biased, it is applied at a positive V gs value. The use of
p-TFET devices is suggested for a similar solution. The gate voltage of the p-device
T3 must be fixed in this situation to be equal to the lowest voltage value at nodes int1
and int2 that calls for the use of an auxiliary inverter. The highest voltage of nodes
int1 and int2 is applied to the inverter’s input after biasing it with that voltage. When
202 P. K. Kumawat et al.

Fig. 7.19 Solutions for reverse current conduction using transistors in the GCCCP topology
(Cavalheiro 2017)

the p-device is reverse biased, the suggested method applies a V gs magnitude near
0 V, and when it is forward biased, it applies a negative V gs (Bi et al. 2017).

Conclusion

In this chapter, we improved our knowledge of TFETs. We looked at the basics of

TFET device structure, operating principle, and types of TFET. After this section,
the tunneling boosters: Si–Ge, doping effect, and ultrathin body device structures
have been systematically studied. In carbon nanotube and graphene TFET studies,
both carbon nanotubes and graphene can be utilized in channels in place of bulk
silicon to improve tunneling in TFET. In the section on digital circuits, TFET-based
inverters have been explained and the applications of digital circuits using pass-
transistors TFET are explained. Current mode logic circuits have also been system-
atically studied. At the end of this chapter, TFET-based rectifiers and charge pumps
are explained.

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Chapter 8
Negative Capacitance Field-Effect
Transistor (NCFET): Strong Beyond
CMOS Device

Sukanta Kumar Swain, Abhishek Raj, and Shashi Kant Sharma

Abstract Field-effect transistors may be able to overcome the so-called “Boltzmann

tyranny” of power dissipation with the incorporation of ferroelectric negative capac-
itance (NC) into their design. Negative capacitance field-effect transistor (NCFET)
is quickly becoming a popular alternative technology that promises to increase the
power efficiency of transistors by many times while still being compatible with the
current CMOS fabrication method. The transistor’s gate stack of an NCFET contains
a ferroelectric (FE) layer that exhibits a negative capacitance effect that amplifies
the internal voltage. However, it remains a challenging task to realize the stable
negative capacitance in the non-hysteretic non-transient regime. The problem arises
due to the lack of understanding regarding the fundamental origin of the negative
capacitance (NC), specifically how the emergence of the domain state can be utilized
to implement the NCFET. The emphasis in this book chapter is to discuss a novel
architecture for field-effect transistor based on ferroelectric domains that feature a
static negative capacitance that is stable in both directions. The performance of field-
effect transistors can be significantly improved by applying a dielectric coating on
the ferroelectric capacitor, enabling the tuning of negative capacitance.

Keywords Negative capacitance field-effect transistor (NCFET) · Ferroelectric

materials · Hysteresis · CMOS fabrication · Domain states

Introduction

In IC technology, each generation has smaller and more complex circuits than
previous generation. In due course of time, the functional density has increased while
geometry size has decreased. Existing CMOS technology has a challenge that it can’t
lower the operating voltage even though it can make transistor features smaller and

S. K. Swain · A. Raj · S. K. Sharma (B)

Department of Electronics and Communication Engineering, Indian Institute of Information
Technology, Ranchi, Jharkhand, India
e-mail: [email protected]

© The Author(s), under exclusive license to Springer Nature Singapore Pte Ltd. 2024 205
S. Singh et al. (eds.), Beyond Si-Based CMOS Devices, Springer Tracts in Electrical and
Electronics Engineering, https://doi.org/10.1007/978-981-97-4623-1_8
206 S. K. Swain et al.

smaller. This is due to fundamental limit of subthreshold swing of 60 mV/dec (Gupta

et al. 2017). Technology scaling and supply voltage reduction have been important
factors in increasing energy efficiency. VDD scaling is limited by threshold voltage
because below threshold voltage, it leads to the loss in device performance. Emerging
CMOS technologies with steep subthreshold slope provides a unique chance for tech-
nology to scale down the supply voltage without scarifying the performance. Negative
capacitance field effect transistor is one of such emerging technology.
NCFET is similar to FeFET that uses a ferroelectric layer in the gate stack of the
transistor. The present CMOS fabrication technique is also completely compatible
with NCFET that makes it highly adoptable by semiconductor industry. It aims to
increase the “steepness” of MOSFET transistors to push the subthreshold swing
beyond its fundamental limit. To achieve this, a ferroelectric (FE) material is utilized
in lieu of the traditional material. NCFET is considered as a better switching device
for current electronics especially at lower supply voltages.

Negative Capacitance Field-Effect Transistor (NCFET)

The operation of NCFETs is predicated on the ferroelectric polarization-induced

passivation of internal gate voltage amplification. The surface voltage of an NCFET
is higher than that of a regular MOSFET. Even ferroelectric materials can still become
polarized without electric field because they have permanent or natural dipoles. In
NCFETs, a thin layer of ferroelectric (FE) materials is incorporated in place of
the dielectric layer. Negative capacitance essentially refers to the change in charge
that appears due to the applied voltage in the opposite direction. As depicted in
Fig. 8.1a, the polarization is vertical when the biasing is zero and it reverses when
the gate voltage exceeds the coercive field (E c ). In contrast to a traditional capacitor, a
ferroelectric’s energy-curvature around a charge has a negative capacitance because
it follows an inverted parabolic form.
As depicted in Fig. 8.2a, the capacitance is exclusively negative at the barrier
region near QF = 0 for ferroelectric materials. As the voltage is applied across the
ferroelectric capacitor, the energy landscape tilts and the polarization moves to the
nearest local minimum. Figure 8.2b shows this change for a voltage which is less than
the coercive voltage V c . If the voltage is higher than V c , one of the minima goes away,
and QF moves to the other minimum (see Fig. 8.2c). It can be[ noted that]in Fig. 8.2c,
the polarization state passes through the region where C = d2 U /dQF2 < 0. When
a ferroelectric material switches from one stable polarization to the other, it goes
through a region where the differential capacitance is negative.
Subthresold swing tells that how steeper the current is increasing with voltage.
Lower will be the value of subthreshold swing, steeper will be the curve. In
conventional MOSFETs, Subthreshold swing can be expressed as follows:
8 Negative Capacitance Field-Effect Transistor (NCFET): Strong Beyond … 207

Fig. 8.1 Operation of NCFET a polarization at zero bias b polarization when V g > V C

Fig. 8.2 a Energy landscape U of a ferroelectric capacitor when no voltage is applied. The capac-
itance C appears negative when QF = 0. b, c Evolution of the energy landscape when the voltage is
applied across the ferroelectric capacitor that is smaller (b) or greater (c) than the coercive voltage V c.
If the voltage is greater than the coercive voltage, the ferroelectric polarization descends through the
negative capacitance states. P, Q, and R shows different polarization states in the energy landscape
(Khan et al. 2015)

[ ( )−1 ] ( )
d log10 IDS Cs
SS = = 60 1 + (8.1)
dVgs COX

From Eq. (8.1), it is observed that it contains two capacitances, one is gate capac-
itance and the other one is substrate capacitance. If C OX < 0 and |COX | < |CS |, the
208 S. K. Swain et al.

subthreshold will be less than 60 mV/dec and we can obtain the negative capaci-
tance. NCFET structure is similar to MOSFET except a thin layer of ferroelectric
material. There are two primary types of NCFET based upon the types of gate struc-
tures, i.e., metal ferroelectric insulator semiconductor FET (MFISFET) and metal
ferroelectric metal insulator semiconductor FET (MFMISFET). MFIS is a kind of
field-effect transistor with a gate structure that contains a thin layer of ferroelec-
tric material, whereas MFMIS has a metal layer sandwiched between the insulator
and ferroelectric where ferroelectric polarization is maintained uniformly along the
channel.

Device Structures: MFISFET and MFMISFET

Metal Ferroelectric Insulator Semiconductor FET

The metal ferroelectric insulator semiconductor FET (MFISFET) structure does not
have an intermediate metal layer as shown in Fig. 8.3a. The stabilization of the
ferroelectric material is unaffected by gate leakage in the MFIS structure (Lue et al.
2002; Pahwa et al. 2018). By choosing the right oxide for the internal MOSFET gate
and ferroelectric material, the steady-state negative capacitance effect can be kept
stable. The MFISFET solves problem of crystal mismatch between the ferroelectric
material and the semiconductor substrate by putting the ferroelectric material right
into the gate stack. The device works better and is more stable because of this straight
integration. The MFIS structure is more advantageous for transistor applications due
to this feature.
Metal Ferroelectric Metal Insulator Semiconductor FET
MFMISFET comprises a gate stack on semiconductor substrate where source and
drain are connected by conducting channel as shown in Fig. 8.3b. A floating metal
electrode is inserted between the ferroelectric and insulator layers to prevent the
charge leakage between channel and MFM capacitance (Lue et al. 2002; Pahwa
et al. 2018; Lee et al. 2020). The top MFM capacitor plate is connected with gate

Fig. 8.3 Device structures for a MFISFET b MFMISFET

8 Negative Capacitance Field-Effect Transistor (NCFET): Strong Beyond … 209

electrode for external voltage source, whereas bottom electrode is electrically isolated
to preserve entire charge and maintain uniform electric field across gate stack and
semiconductor. It also neutralizes the parasitic charge at the interference during
fabrication process.
Due to the presence of intermediate metal layer, the potential of the ferroelec-
tric layer must be uniform and the continuous boundary condition for electric
displacement can be written as follows:

D = εO EF + P(EF ) = εI εO EI = εSi εO ESi , (8.2)

where E F , E I , and E Si are the electric fields in the ferroelectric layer, insulator, and
semiconductor, respectively. The polarization P is defined as the sum of polarization
in each domain:
P1 + P2
P= (8.3)
2
The boundary condition indicates that uniform depolarization is applied in
ferroelectric layer. This implies that it produces an antiparallel configuration, i.e.,
P1 = −P2 that leads to zero depolarization field. Gauss’s law tells the relation
εSi εO ESi = −QS (ψS ), where QS (ψS ) is space charge in the semiconductor and
ψS is surface potential.
Equation can be written as follows:

P(EF ) = −QS (ψS )

VI VI
εI εO = εSiO2 εO = −QS (ψS ), (8.4)
tI EOT

where V F and V I correspond to the voltage drops in ferroelectric layer and insulator
respectively. The total gate voltage can be given by:

VG = ψS + VI + VF

The total capacitance obtained in the layer can be expressed as:

1 1 1 1
= + + , (8.5)
Ctotal CI CF Csemiconductor
ε ε ∈ ∈
where CI = SiO2
EOT
OAI
, CF = F tFOAF .
When comparing MFIS with MFMIS, MFIS offers greater ON-state current than
MFMIS. However, this is not the case for all ferroelectric materials (Pahwa et al.
2018). The smooth hysteresis behavior can better be obtained in MFIS as compared
to MFMIS.
210 S. K. Swain et al.

Landau–Khalantikov Theory of Non-linear Dielectrics

The Landau–Khalatnikov theory of non-linear dielectrics is a theoretical framework

used to describe the behavior of materials that exhibits non-linear response to elec-
tric fields. This theory is based on the concept of an order parameter that represents
the average orientation or configuration of microscopic dipoles within the mate-
rial (Kim and Kwon 2021; Nandan et al. 2020; Bhushan et al. 2012). The theory
assumes that the free energy of the system can be described by an expansion in
powers of the order parameter. The Landau–Khalatnikov theory provides a math-
ematical description of the relationship between the applied electric field, polar-
ization, and dielectric response of the material. It has been widely used to explain
and predict the behavior of ferroelectric and other non-linear dielectric materials in
various applications including capacitors, sensors, and memory devices.
The Landau–Ginzburg–Devonshire theory can be used to describe and predict
the characteristics of phase transitions and polarization switching in ferroelectrics.
In most cases, the bulk ferroelectric state is fully determined by the temperature,
polarization, electric field, stress, and strain. The polarization P is taken as the ferro-
electric order parameter. Ferroelectricity is characterized by a first- or second-order
phase transition in which the free energy G is a thermodynamic function of the order
parameter. The G(P) can be expressed as follows:

1 1 1
G = G0 + αP 2 + βP 4 + γ P 6 − EP,
2 4 6
where E is the intensity of electric field, G0 is the energy density, P is the polarization,
and α, β, and γ are constants (Landau coefficients). Here, α can be written as α =
α0 (T − T0 ) where α 0 > 0. In general, α and β can be +ve/−ve but γ is always +
ve for stability reason. Dynamics of G involves with time can be given by Landau–
Khalatnikov (L–K) theory:

dp ∂G
δ =− ,
dt ∂P
where δ is the polarization damping factor.
In steady state

dp ∂G
δ =− =0
dt ∂P

=> E = 2αP + 4βP 3 + 6γ P 5

L–K explanation of phase transition:

For E = 0

G = αP 2 + βP 4 + γ P 6
8 Negative Capacitance Field-Effect Transistor (NCFET): Strong Beyond … 211

α is +Ve, for T > T 0

α is −Ve, for T < T 0 at E = 0, there exist three real roots.
In this case, the polarization features can be explained by a reaction–drift–diffu-
sion model. Phase transition properties and polarization switching in ferroelectrics
can be theoretically analyzed using the Landau–Ginzburg–Devonshire thermody-
namic theory. This theory can be used to determine the ferroelectric characteristics
concept of the Ising-type model within the framework of the effective field theory, but
Landau–Khalantikov equation differs from Landau–Ginzburg–Devonshire theory
due to the presence of diffusion term. The classical Landau–Khalatnikov equation
is an ordinary differential equation with respect to time, but it can be used to study
hysteresis phenomena in ferroelectric bulk materials and thin films. This relation-
ship can be expressed mathematically with time-dependent Landau–Khalatnikov
equation:

dP
E = αP + βP 3 + γ P 5 + ρ , (8.6)
dt
where α, β, and γ are the material parameters, and ρ is the kinetic coefficient of
ferroelectric polarization. Landau–Khalantikov (L–K) and miller models are used to
analyze the polarization and voltage across ferroelectric materials. In this section,
we discuss L–K equation which is dynamical version of Landau–Devonshire theory.

VFE = 2αP + 4βP 3 + 6γ P 5 (8.7)

Positive and Negative Capacitances

Figure 8.4 illustrates the simplified capacitance model for voltage amplification
concept. It can be written as a series combination of ferroelectric capacitor (C FE ) and
MOSFET capacitance (C MOS ). The mathematical relationship between gate voltage
(V G ) and MOSFET voltage (V MOS ) can be written as:

CFE
VMOS = VG (8.8)
CFE + CMOS

From Eq. (8.8), it is evident that when C FE is positive, V MOS will be lesser or
equal to V G . When C FE is negative, the equation can be written as:

−|CFE |
VMOS = VG (8.9)
−|CFE | + CMOS

Therefore, the voltage amplification can be written as:

212 S. K. Swain et al.

Fig. 8.4 Capacitance model

of NCFET

∂VMOS |CFE |
AV = = (8.10)
∂VG |CFE | − CMOS

Av could be greater than 1 when C MOS is larger than zero which means that small
change of V G will induce a large change in V MOS , and hence, the swing of NCFET
can be smaller than 60 mV/dec. The ferroelectric capacitance and MOS capacitance
should be comparable to achieve larger voltage gain but to avoid hysteresis, Av should
not be infinite and therefore C mos cannot be equal or greater than C FE . This is the
key concept in designing a stable NCFET. The subthreshold swing of NCFET can
be obtained as:
60 mV ( )
NCFET SS = MOSFET SS ∗ A−1
V = ∗ 1 + Cdep /Cox ∗ A−1
V (8.11)
dec
By substituting Av from Eq. (8.10):
( )
60 mV Cdep
NCFET SS = MOSFET SS ∗ A−1 = ∗ 1 + Cdep /Cox − , (8.12)
V
dec |CFE |

where C MOS is the series combination of C OX and C dep .

From Eq. (8.5), it is evident that C dep /C ox increases the subthreshold swing, mean-
while C dep /C fe reduces the subthreshold swing. It is important that subthreshold
swing can be less than 60 mV/decade where C FE must be smaller than C OX . For
MOSFET design, subthreshold swing can be decreased by increasing the gate voltage
and reducing C dep . For NCFET, the reduced C dep cannot reduce the swing below
8 Negative Capacitance Field-Effect Transistor (NCFET): Strong Beyond … 213

60 mV/dec. To avoid hysteresis, C FE must be larger than C MOS . This means that
subthreshold cannot be negative. Therefore, following equivalent condition should
be considered:
[ ]
Cdep
Cdep /Cox − > −1 (8.13)
|CFE |

Non-hysteretic Negative Capacitance FET

In negative capacitance FET, hysteresis behavior is one of the critical issues in ferro-
electric material which is not preferred for logic applications; therefore, NCFET
operates in non-hysteresis regime. When the gate capacitances and ferroelectric
are matched, non-hysteretic negative capacitance operation is achieved over the
entire range of the gate voltage. It has been proved theoretically that ferroelectric
capacitance |CFE | is proportional to Pr /(E c .t FE ) where t FE is the ferroelectric thick-
ness. When |CFE | decreases due to gate voltage V gs , then there is a transition from
|CFE | ≥ CMOS to |CFE | < CMOS that results in the appearance of hysteresis. It can be
concluded that hysteretic can be increased/decreased by Pr /E c or thickness of ferro-
electric. Hence, it experimentally demonstrated by Zhou et al. that hysteresis can be
eliminated by increasing the remnant polarization (Pr ) to coercive polarization (E c )
ratio with integration of HfZrOx (HZO) ferroelectric material (Lu et al. 2012; Zhou
et al. 2018).

Negative Capacitance in Ferroelectric

Negative capacitance in ferroelectric materials is a phenomenon where the effective

capacitance of the material becomes negative under certain conditions. In conven-
tional materials, capacitance is always positive which means that the charge stored
in the material increases with an increase in the voltage. However, in ferroelec-
tric materials, the polarization can exhibit a unique behavior. Ferroelectric materials
possess a continuous polarization that can be switched by an external electric field.
When a positive voltage is applied to a ferroelectric capacitor, the polarization aligns
with the field that increases the charge stored and results in positive capacitance. As
the voltage exceeds a certain threshold, the polarization starts to decrease instead
of increasing it further and results in reduced stored charge. This unusual behavior
arises due to the intrinsic properties of the ferroelectric material. Negative capaci-
tance can occur in “negative capacitance regime.” When the voltage is higher than
the coercive voltage, the polarization flips to the opposite direction. In this regime,
the ferroelectric material acts as if it has a negative capacitance that effectively ampli-
fies the voltage across the capacitor instead of attenuating it. This behavior can be
214 S. K. Swain et al.

harnessed to overcome the fundamental limitations of conventional dielectrics and

enhance the performance of electronic devices. The negative capacitance effect in
ferroelectrics is still an active area of research and has the potential to revolutionize
various technological applications in electronics and energy storage.

How to Stabilize a Negative Capacitance?

Stabilizing negative capacitance in a ferroelectric material is a difficult job that

requires careful engineering and an understanding of the physics behind it. Several
plans have been suggested to bring about this stabilization. One way is to use a
hybrid structure that combines a ferroelectric material with a dielectric material that
has positive capacitance. The positive capacitance of the dielectric can counterbal-
ance the negative capacitance of the ferroelectric leading to an overall stabilized
capacitance. Another way is to use structures called superlattices that are made up
of many layers of different materials. By changing the thickness and composition of
these layers, it is possible to make an efficient negative capacitance. Additionally,
the device architectures and designs can be improved to reduce parasitic effects and
guarantee a stable negative capacitance. Active control mechanisms such as feedback
circuits can also be employed to stabilize the negative capacitance (Yuan et al. 2021).
Use of channel materials with a lower density of states could be advantageous for
stabilizing the NCFET devices. In short, channel devices where the channel potential
is inhomogeneous, the drain voltage can locally affect NC stabilization. This can lead
to the formation of domains and inhomogeneous ferroelectric polarization. However,
simulations indicate that even at high drain voltages, hysteresis-free stabilized NC is
still achievable. Interestingly, increasing the drain voltage in an NCFET results in a
reduction in the channel potential which is beneficial for channel length scaling, and
it also induces negative drain-induced barrier lowering. Moreover, this phenomenon
results in negative differential resistance at the output characteristics which can be
useful in various analog applications.
In summary, stabilizing negative capacitance requires a combination of material
engineering, device design, and control strategies to overcome the instabilities so that
the desired behavior in ferroelectric materials can be maintained. Ongoing research
in this field aims to further refine these approaches and explore new avenues for
achieving stable negative capacitance for future technological applications.

Ferroelectric–Dielectric System

In a ferroelectric–dielectric system, the ferroelectric material provides the ability to

switch the polarization in response to an applied electric field leading to non-linear
behavior and memory effects. Ferroelectric materials have a feedback loop in their
polarization electric field properties that stores and holds charge even when there is no
8 Negative Capacitance Field-Effect Transistor (NCFET): Strong Beyond … 215

applied field. On the other hand, a dielectric material responds linearly to an electric
field and it usually have a high dielectric constant. Dielectric materials are used to
increase the overall capacitance of the system enabling efficient charge storage and
higher energy density.
By combining ferroelectric and dielectric materials, ferroelectric–dielectric
systems can exhibit unique properties. For instance, the high dielectric constant
of the dielectric material enhances the charge storage capacity of the ferroelectric
material that results in increased energy storage capabilities. Moreover, the ferro-
electric component introduces non-linear behavior and memory effects allowing for
novel applications such as non-volatile memory devices, tunable capacitors, and
energy harvesting systems. The design and optimization of ferroelectric–dielectric
systems involve careful selection of the constituent materials, its composition, and
the interface between them. The compatibility of lattice structures, thermal expansion
coefficients, and polarization alignment are crucial factors to ensure the proper func-
tioning of the system. Additionally, engineering techniques such as interface engi-
neering, strain engineering, and doping can be employed to tailor the properties and
enhance the performance of ferroelectric–dielectric systems. Ferroelectric–dielectric
systems hold a great promise for various applications including electronics, energy
storage, sensors, and actuators. Ongoing research in this field focuses on improving
the stability, reliability, and efficiency of these systems and will help to explore new
materials, combinations, and device architectures to unlock their full potential.

Modeling of NC-FinFET

NC-FETs are the emerging devices to achieve higher ION and steep subthreshold.
In this section, compact model of NC-FinFET device is analyzed. Landau–Khalat-
nikov (L–K) equation is used to analyze the compact model of FE materials. The
relationship between electric field and polarization in FE material can be expressed
as:

E = 2αP + 4βP 3 + 6γ P 5 ,

where α, β, and γ are material parameters. When capacitance is in negative regime,

unstable region is observed as shown in red dots of Fig. 8.5. The drain current of
NCFET can be expressed as:

∫VDS
iDS = qm dvch
0
216 S. K. Swain et al.

Fig. 8.5 Energy landscape

and polarization of FE
(Duarte et al. 2017)

Amplified drain current can be obtained when FE layer is used, it is proportional

to thickness of FE layer. When thickness of FE layer is too thick, the device is not
stable and anti-clockwise hysteresis comes into picture.

Compact Model for FinFET

An equivalent circuit diagram of NC-FinFET is presented in Fig. 8.6. NC-FinFET

devices are characterized for both internal and external gate nodes where internal
gate nodes measure the baseline FinFET and external gate nodes for the FE layer.
The FinFET characteristics depends on external gate voltage V ge and voltage
across ferroelectric layer V fe , where V fe depends on charge in the ferroelectric layer.
Mathematically, the electric field in ferroelectric layer can be expressed as a function
of polarization:

Efe = αP + βP 3

Critical electric field E C can be derived as:

∂Efe
=0
∂P

=> α + 3βPC2 = 0,

where remnant polarization is represented as E fe = 0

αP0 + βP03 = 0
8 Negative Capacitance Field-Effect Transistor (NCFET): Strong Beyond … 217

Fig. 8.6 Compact model flowchart

By solving Eq. (8.1) and (8.2), α and β can be obtained as a function of E c and
P0 :
√
3 3
α=− (EC /P0 )
2
√ ( )
3 3 EC /P03
β=−
2

Self-consistent Simulation Model

The voltage across ferroelectric layer depends on total ferroelectric layer charge. The
total charge with FE layer can be expressed as:

Qge = Qgi + Cgsf .Vgis + Cgdf .Vgid ,

where C gsf and C gdf are the parasitic gate to source and gate to drain capacitance,
respectively. Figure 8.7 represents the BSIM-CMG compatible NC-FinFET models.
It includes subthreshold swing, V T based on the internal charge Qint , and drain
coupling as well as parasitic capacitance.
218 S. K. Swain et al.

Fig. 8.7 Framework of BSIM-CMG compatible NC-FinFET model (You et al. 2018)

Negative DIBL

In deep submicron process, the channel length is extremely small. When drain voltage
V D increases, the gate voltage reduces, and hence, the threshold voltage reduces.
The mechanism is called as DIBL effect. From the hysteresis behavior, subthreshold
swing and DIBL are extracted in forward sweep. The subthreshold swing is defined
as minimum inverse slope near the threshold voltage. From the fundamental theory
of semiconductor physics, subthreshold swing can be expressed as:
( )
dVGS dVGS dØS CS KB T
SS = = = 1+ × ln 10,
d log10 ID dØS d log10 ID CG q

where ØS is the surface potential, K B is the Boltzmann constant, and q is electronics

charge.
DIBL can be expressed as:

Vth,high − Vth,low
DIBL = ,
VD,high − VD,low

where V th is the threshold voltage, V D is the drain voltage. The fundamental theory
of threshold voltage V Th can be written as:

QG
Vth = Øms + 2Øbi + ,
CG
8 Negative Capacitance Field-Effect Transistor (NCFET): Strong Beyond … 219

where Øms is the work function difference between semiconductor and metal gate,
Øbi is the built-in potential. In ferroelectric FETs, Øms and Øbi are not affected by
ferroelectric layer. Hence, V th depends on QG and C G . If the value of C G is very
large, DIBL becomes 0 mV/V and subthreshold swing becomes 60 mV/decade. For
subthreshold swing lesser than 60 mV/dec, the DIBL moves toward the negative
value. The negative DIBL effect is opposite from DIBL effect in conventional FETs
(Yu et al. 2021; Huang et al. 2021).

Negative Output Differential Resistance

Negative output differential resistance (NDR) is a phenomenon observed in certain

devices such as the negative capacitance field-effect transistor (NCFET). To under-
stand NDR in an NCFET, let’s first briefly discuss the concept of negative capacitance.
Negative capacitance is a property where the voltage across a capacitor decreases
when the charge on it increases. This effect is achieved by connecting a ferroelectric
material in parallel with a regular capacitor. When a voltage is applied across the
ferroelectric material, its polarization opposes the voltage resulting in a net decrease
in the voltage across the combination of the ferroelectric and regular capacitors.
In an NCFET, the gate stack includes a ferroelectric material. The presence of
negative capacitance in the gate stack can lead to NDR in the output characteris-
tics of the transistor. Typically, in a regular FET, the output resistance (differen-
tial resistance) increases with increasing drain–source voltage (V ds ). However, in
an NCFET under certain conditions, the output differential resistance can become
negative. Negative differential resistance means that as the voltage difference across
the output terminals of the device increases, the current flowing through it decreases.
This behavior is in contrary to the normal behavior of most electronic devices where
an increase in voltage difference leads to an increase in current.
The negative output differential resistance in an NCFET arises due to the coupling
between the ferroelectric material and the transistor channel. The ferroelectric mate-
rial acts as a voltage booster reducing the effective voltage across the channel and
causing a decrease in the channel current. This behavior can be exploited in certain
applications such as low-power digital logic where NDR can enable power-efficient
operation by reducing power dissipation during logic transitions.
It’s important to note that the NDR effect in NCFET is still an area of active
research and its practical implementation and applications are under exploration. The
specific operating conditions and device parameters play a crucial role in achieving
and controlling negative output differential resistance in NCFETs.
220 S. K. Swain et al.

Impact of Material Parameters

Ferroelectric material can be defined as the dielectric materials that maintain polar-
ization even in the absence of electric field. Direction of the dipole moment can
be changed by applying electric field. Ferroelectric material polarization depends
on temperature. All materials that are ferroelectric are also pyroelectric. Among 32
crystals, only 20 have direct piezoelectricity which produce polarization by mechan-
ical stress and only 10 crystal structures have the properties of spontaneous electric
polarization. The change in temperature with polarization is known as pyroelectricity.
Some pyroelectric materials are ferroelectric materials whose switching dipole can be
reversed by external electric field (Kim et al. 2018). As a result, ferroelectric mate-
rials have many interesting properties that rely on the electric field, temperature,
strain, and other factors (Fig. 8.8).
Materials with non-centrosymmetric crystalline structures have the ferroelec-
tricity properties and these materials can be put into different groups based on how
ferroelectricity works in them. The basic properties of ferroelectric materials can be
listed as:
1. It is capable of spontaneous polarization.
2. Ferroelectric materials have pre-existing or fixed or natural dipoles.
3. At zero electric field, there is no net polarization because the areas or domains
made up of the individual dipoles are not randomly oriented.
4. When an external electric field is introduced, the dipoles in the domains are
aligned with the direction of the electric field.
Many ferroelectric materials such as PbTiO, BaTiO, Pb(ZrTi)O, HfZrO, etc.,
exhibit negative capacitance. In NCFET technology, the L–K equation is the most
effective tool to understand the ferroelectric switching properties. The equation is

Fig. 8.8 Timeline of ferroelectric materials and ferroelectric semiconductor devices (Mikolajick
et al. 2021)
8 Negative Capacitance Field-Effect Transistor (NCFET): Strong Beyond … 221

Table 8.1 Landau coefficient for ferroelectric materials (Rahi et al. 2021)
Materials α Value (m/F) β Value (m5/F/Coul2) γ (m9/F/Coul4)
BaTiO3 − 1.0 × 107 − 8.9 × 109 4.5 × 1011
HfZrO − 7.0 × 108 1.0 × 1012 0.0
SBT − 1.3 × 108 1.3 × 1010 0.0
P(VDF-TrFE) − 1.98 × 109 − 3.75 × 1011 3.16 × 1013
HZO − 7 × 108 1.0 × 1012 0.0
Y-HfO2 − 1.23 × 108 3.28 × 1010 0.0
Pb(Nb0.04Zr0.28Ti0.68)O3 − 5.37 × 107 − 3.0 × 107 2.47 × 108

used to explain how the polarization P and voltage across FE material is related. The
voltage across the FE capacitor, i.e., V FE can be expressed as:
( )
VFE = αQFE + βQFE
3
+ γ QFE
5
,

where α, β, and γ are the material of Landau coefficient, QFE is the polarization
charge. So based on the Landau coefficient (α, β, and γ ) for ferroelectric materials,
the thickness plays a major role for explaining the polarization and voltage across
the FE material as shown in Table 8.1.

Switching Delay

The switching delay in NCFETs refers to the time it takes for the transistor to transit
between different states or switch from one logic level to another. This delay is
primarily influenced by the capacitance and resistance components in the transistor’s
structure.
In an NCFET, the switching delay consists of two main components: (i) Gate
delay (ii) drain/source delay. The gate delay is the time it takes for the gate voltage to
reach the threshold voltage causing the transistor to start conducting. It is influenced
by the gate capacitance and the resistance of the gate terminal. The gate capacitance
is primarily determined by the physical dimensions and the dielectric material of
the transistor’s gate oxide. The drain/source delay refers to the time it takes for the
drain or source terminal to respond to changes in the gate voltage and transition from
one logic level to another. It is influenced by the drain/source capacitance and the
resistance of the drain/source terminals. The drain/source capacitance is determined
by the physical dimensions and the doping levels of the drain/source regions.
The switching delay in NCFETs can be influenced by various factors including the
device dimensions, biasing conditions, supply voltages and load conditions. Manu-
facturers and circuit designers employ various techniques to minimize the switching
delay in NCFET-based circuits such as optimizing device structures, employing
advanced fabrication processes, and using specialized circuit design methodologies.
222 S. K. Swain et al.

It’s worth noting that the specific values and characteristics of switching delays
in NCFETs can vary depending on the transistor’s design, process technology, and
operating conditions. Therefore, it is important to consult the transistor datasheets
or device models provided by the manufacturer for more precise information on the
switching delay characteristics of a particular NCFET.

Modeling of NCFET at System Level

This section presents an overview of how NCFET is modeled at system level.

Figure 8.9 presents the methodology where all the layers from physical to system
level in NCFET are highlighted. The behavior of different thickness of transistor
is modeled as per industry standard compact model (BSIM-CMG) (Nandan et al.
2020; Dasgupta et al. 2020). Based on this concept, cell libraries that can operate at a
wide range of operating voltages at different thickness of ferroelectric layer from 1 to
4 nm can be put together to a single core tile to GDSII level. After that, performance
timing and power signoffs can be analyzed. Power signoff tools are used to compare
power and performance of different NCFET configurations and are used to obtain
frequency-dependent scaling factor for dynamic and leakage power. These factors
serve as an abstraction at the system level and can be used to predict the power of
NCFET-based processor. Finally, these factors are used to simulate the models with
multi-core processor.

Low Power Logic

Low power logic using negative capacitance field-effect transistors (NCFETs) is a

promising approach to overcome the power performance limitations of conventional
transistors. NCFETs leverage the concept of negative capacitance to achieve sub-
thermal slope operation enabling significant reduction in power consumption. By
utilizing NCFETs in low power logic circuits, several benefits can be achieved.
Firstly, the sub-thermal slope operation enables improved energy efficiency as lower
voltages are needed for switching. This reduces power consumption and prolongs
battery life making NCFET suitable for portable devices and energy-constrained
applications. Furthermore, the negative capacitance effect can mitigate the impact of
short-channel effects and leakage currents that becomes more pronounced in scaled-
down transistors (Bheemana et al. 2021). NCFETs offer enhanced control over the
channel potential enabling better transistor performance and reduced leakage power
dissipation.
The development of low power logic NCFET faces challenges related to materials,
process integration, and circuit design. Identifying and optimizing suitable ferro-
electric materials with stable negative capacitance behavior is crucial. Additionally,
precise control of the ferroelectric layer and its interaction with the transistor stack
8 Negative Capacitance Field-Effect Transistor (NCFET): Strong Beyond … 223

Fig. 8.9 General overview of design methodology from physical to system level to investigate
NCFET (Rapp et al. 2019)

is necessary to maintain the desired negative capacitance effect. Circuit design tech-
niques such as logic gate optimization and power management strategies need to
be developed specifically for NCFET-based architectures. Research efforts in low
power logic NCFETs are ongoing aiming to demonstrate their practical viability and
scalability. By leveraging the advantages of negative capacitance, NCFETs have the
potential to revolutionize low-power electronics enabling energy-efficient computing
systems, IoT devices, and other applications that prioritize power savings.

NCFET Memory, DFF, and Processor

As mentioned earlier, NCFET replaces the traditional high-K layer in transistors

with a ferroelectric layer. The key difference lies in the thickness of the FE layer.
Due to its full CMOS compatibility, FeFET is regarded as one of the most emerging
technologies in memory applications. It has already been demonstrated that FeFET-
based memories provide read–write latencies within 1 ns. One significant advantage
of FeFET is its high density as each FeFET cell consists of only one transistor.
224 S. K. Swain et al.

Fig. 8.10 Shows two transistor FeFET-based non-volatile memory

For stored logic “0” and “1,” the information is available inside the FE layer
dipole. When an electric field is applied, the direction of the dipole switches from
bottom to top or top to bottom. The sensing circuit can differentiate between logic
“0” and “1” based on the dipole direction. NCFET-based memory cells have the
potential for non-volatile retention capability due to FE polarization, high current
ratio, and low power operation (Takasu 2001). Non-volatile storage can be useful for
designing non-volatile processors to store system data in the case of power failure
(Fig. 8.10).
The objective of designing a two-transistor NCFET memory is to achieve stable
and non-volatile memory states with disturbance-free read operations. It minimizes
the area requirements by integrating the read and write paths. The write path incor-
porates a standard MOSFET that is controlled by the write select line. On the other
hand, the read path consists of an NCFET with the read select line connected to the
drain and the sense line tied to the source.
NCFET-Based DFF
A negative capacitance field-effect transistor (NCFET)-based D flip-flop (DFF) lever-
ages the unique properties of negative capacitance to enhance its operation. The
operation of a D flip-flop (DFF) based on negative capacitance field-effect transistor
(NCFET) technology is similar to a conventional DFF, but with the advantage of
improved performance due to the negative capacitance effect.
A D flip-flop is a sequential logic circuit that stores a single bit of data and can be
triggered to change its output based on a clock signal. The DFF consists of two cross-
coupled NCFET-based latch circuits, typically implemented using complementary
NCFETs (both n-type and p-type NCFETs). Here’s a step-by-step explanation of the
operation:
I. Latch Initialization: Initially, the DFF is in an unknown or reset state. The
outputs (Q and Q) are in an indeterminate state.
II. Data Input (D): The desired data to be stored is applied to the D input of the
DFF.
8 Negative Capacitance Field-Effect Transistor (NCFET): Strong Beyond … 225

III. Clock Signal (CLK): The clock signal is applied to the clock input of the DFF.
The clock signal determines when the DFF should capture the input data.
IV. Data Capture: When the rising edge (or falling edge, depending on the specific
implementation) of the clock signal occurs, the input data (D) is captured and
stored within the DFF.
V. Output Stability: Once the data is captured, the output (Q and Q) remains stable
until the next clock edge.
VI. Feedback Loop: The cross-coupled NCFETs in the latch circuit creates a feed-
back loop allowing the stored value to be maintained until a subsequent clock
edge triggers a change.
The primary advantage of utilizing NCFETs in the DFF is the negative capac-
itance effect which can enhance the performance by reducing power consumption
and improving the subthreshold slope (Li et al. 2017). The negative capacitance
effect counteracts the inherent positive capacitance of the NCFET resulting in an
effective negative capacitance value (Moaiyeri et al. 2021). This effect enables the
DFF to operate with steeper subthreshold slopes reducing energy consumption with
improved overall performance.
It’s important to note that the specific circuit design and implementation details of
an NCFET-based D flip-flop can vary depending on the research or design approach.
NC-FET-Based Processor
A negative capacitance field-effect transistor (NCFET)-based processor refers to a
central processing unit (CPU) architecture that utilizes NCFETs as the fundamental
building blocks for its transistors. The integration of NCFETs in a processor aims
to leverage the unique characteristics of negative capacitance to enhance the perfor-
mance and energy efficiency of the CPU. Furthermore, the use of NCFETs can also
potentially enable higher operating frequencies as the negative capacitance effect can
counteract the inherent capacitive delays in the transistor enabling faster switching
speeds (Rapp et al. 2019; Amrouch et al. 2018).
However, it’s important to note that research into NCFET-based processors is
still ongoing, and several challenges need to be addressed for their practical imple-
mentation. These challenges include optimizing device architectures, understanding
stability and reliability issues of negative capacitance materials, and integrating
NCFETs into existing fabrication processes. Researchers and scientists are actively
investigating NCFET-based processor designs to explore the potential benefits of
negative capacitance on CPU performance and energy efficiency. Ongoing research
in this field aims to develop practical implementations and overcome the remaining
hurdles to realize high-performance processors based on NCFET technology.
226 S. K. Swain et al.

Logic-In-Memory and Security Applications

Logic-in-Memory (LiM) reduces the amount of data transfers between the system
memory and the computational core. The idea was first outlined in 1970 but is now
gaining more attention because non-volatile memories can be integrated better with
CMOS transistors as compared to older memory technologies. LiM relies on various
applications like cryptographic algorithm implementation, security applications,
phase change memories, and so on.
Depending on the computation, LiM can be divided into different groups such as
memory processing, memory computing, coarse-grain LiM, and fine-grain LiM. In
coarse-grain LiM, non-volatile memory is placed nearer to the processor to be used
with same latency. In fine-grain LiM, non-volatile memory is integrated with the logic
design and used within the computing process. Based on emerging technologies, LiM
structures integrate non-volatile storage elements with their logic itself. There are
two categories of LiMs: ternary content addressable memories (TCAM) and basic
logic function units. TCAMs carry out parallel searches for specific pieces of data
against a table of stored data and report whether a match occurs or not. In basic logic
functions, both non-volatile storage elements and variable resistors are employed.
They can perform basic logic tasks like NAND, NOR, etc.
Logic-in-Memory (LiM) refers to a computing paradigm where memory elements
are combined with logic operations enabling the computations directly within the
memory units. LiM can offer advantages such as reduced data movement, improved
energy efficiency, and increased system performance. In the context of negative
capacitance field-effect transistors (NCFETs), LiM refers to the integration of logic
functionality within NCFET-based memory cells.
By combining memory and logic operations in a single NCFET device, LiM
enables data processing and storage to occur simultaneously that minimizes the need
for data transfer between separate memory and logic units. This reduced latency
and energy consumption is associated with data movement across different parts of
a computing system. Research in NCFET-based LiM focuses on developing circuit
architectures and design methodologies that enables efficient integration of logic
and memory functions within NCFET devices. This includes exploring the use of
NCFETs as both memory storage elements and computational elements and devel-
oping suitable control and addressing schemes. NCFET-based logics in memory
architectures have the potential to enable tasks such as data search, pattern recog-
nition, and data processing directly within the memory bypassing the need for data
transfer to a separate processing unit. This can significantly reduce the data move-
ment bottleneck and enhance overall system performance in applications such as
databases, machine learning, and artificial intelligence.
Security Applications: NCFETs also offer potential advantages in security appli-
cations due to their unique characteristics such as hardware security and physically
unclonable functions (PUF). In hardware security, NCFETs can be leveraged to
enhance hardware security by providing improved resistance against side-channel
8 Negative Capacitance Field-Effect Transistor (NCFET): Strong Beyond … 227

attacks. Side-channel attacks exploit information leaked through power consump-

tion, electromagnetic emissions or timing variations to gain unauthorized access to
secure information. The steep subthreshold slope and reduced power consumption
of NCFETs can help to mitigate such attacks and enhance the security of sensi-
tive data. In physically unclonable functions (PUFs), the security primitives exploit
the inherent randomness and unique characteristics of physical devices to generate
unclonable cryptographic keys. The properties of NCFETs such as process varia-
tion and subthreshold behavior can be utilized to create PUFs that generate unique
and unpredictable responses making them suitable for authentication and secure key
storage applications.

Negative Capacitance in Organic/Ferroelectric FET

Negative capacitance in organic materials refers to the phenomenon where the effec-
tive capacitance of the material becomes negative under specific conditions. Organic
materials such as certain polymers and organic semiconductors have attracted signif-
icant interest due to their unique electronic properties with potential applications in
flexible electronics and organic electronic devices (Jo et al. 2015). In the context
of negative capacitance, organic materials offer an intriguing opportunity to achieve
enhanced device performance with energy efficiency. By incorporating ferroelectric
or ferroelectric-like properties into organic materials, it is possible to induce nega-
tive differential capacitance where the capacitance decreases with increase in voltage.
This negative capacitance effect can be utilized to overcome the power limitations in
organic electronic devices by effectively amplifying the voltages across the devices
resulting in reduced power consumption and improved performance.
Lee et al. (2018) investigated the negative capacitance effect in organic ferroelec-
tric polymers. They demonstrated that by incorporating a ferroelectric polymer layer
such as poly (vinylidene fluoride-co-trifluoroethylene) (PVDF-TrFE) into the gate
stack of an organic field-effect transistor (OFET), negative capacitance was observed.
The negative capacitance in the ferroelectric polymer layer compensated for the posi-
tive capacitance of the gate dielectric resulting in an effective negative capacitance
that improved the switching characteristics of the OFET. Transistor channel was
made up of MoS2 which is a 2D material with high electron mobility that can control
the gate voltage due to the thickness of several atomic layers.
According to the capacitance series model, top gate NCFET can be considered
as a series combination of ferroelectric capacitance and interface capacitance as
shown in Fig. 8.11. The interface capacitance mainly comes in between metal contact
and P(VDF-trFE). During the fabrication of the organic ferroelectric capacitor, a
copolymer of polyvinylidene fluoride (PVDF) and trifluoroethylene (TrFE) with a
75/25 ratio was used that exhibited outstanding polarization characteristics. The
extracted parameters for the organic ferroelectric material P(VDF0.75 TrFE0.25 ) are as
follows:
228 S. K. Swain et al.

Fig. 8.11 Schematic diagram of top gate NCFET b. Equivalent capacitance model of top gate
NCFET

α = α0 (T − TC ), α0 = 1.20 × 1011 Jm/C2 K,

T = 300 K, TC = 413 K, β = 1.20 × 1024 Jm5 /C 4 , γ = 0,

where T is the room temperature and T c is the Curie temperature for

P(VDF0.75 TrFE0.25 ).
The ferroelectric capacitance C FE is expressed as:
[ ]−1
d2 y 1
CFE = =
dx2 2α + 12βP 2 + 30γ P 4

For the dielectric capacitor, the static terms α, β, and γ are positive. Hence, the
capacitance cannot be negative. However, the coefficient α is inversely proportional
to the permittivity, i.e., ε ∝ 1/α0 (T − TC ), where 1/α 0 is the curie Weiss constant.
The realization of negative capacitance in organic materials requires careful mate-
rial design and understanding of the underlying physical mechanisms with suitable
optimization of device structures to ensure stable and reliable operation. Ongoing
research in this field aims to explore and exploit the potential of negative capacitance
in organic materials for various applications including organic transistors, memories,
and energy harvesting devices.

Ferroelectric FET

A ferroelectric field-effect transistor (FeFET) is a type of transistor that incorporates a

ferroelectric material in its structure. Unlike conventional transistors, FeFETs utilizes
the unique properties of ferroelectric materials to enable non-volatile memory and
potential applications in neuromorphic computing. It operates based on the polar-
ization switching of the ferroelectric material. The ferroelectric layer is positioned
between the transistor’s gate electrode and the channel region. By applying an elec-
tric field to the gate electrode, the polarization of the ferroelectric material can be
switched resulting in a change in the threshold voltage of the transistor. This polar-
ization switching effect allows FeFETs to store information even when the power is
turned off making them suitable for non-volatile memory applications.
8 Negative Capacitance Field-Effect Transistor (NCFET): Strong Beyond … 229

FeFETs offer advantages such as high endurance, low power consumption, and
fast switching speeds. They can achieve high on/off current ratios that contributes
to robust memory characteristics. Additionally, FeFETs have the potential for multi-
bit storage enabling higher data density in memory applications. Moreover, FeFETs
show promise in neuromorphic computing as the polarization switching behavior
resembles the synaptic behavior in biological systems. This makes FeFETs attrac-
tive for implementing artificial neural networks and accelerating machine learning
algorithms. However, material selection, device fabrication, and stability of the polar-
ization switching remain a challenge. Researchers are exploring various ferroelec-
tric materials such as hafnium oxide, lead zirconate titanate, and bismuth ferrite to
optimize FeFET performance.
In summary, FeFETs utilizes the polarization switching of ferroelectric mate-
rials to enable non-volatile memory and show potential for neuromorphic computing
applications. With ongoing research and development, FeFETs may offer advanced
memory technologies and contribute to the advancement of next-generation
computing systems.

Conclusion

The negative capacitance field-effect transistor (NCFET) is a revolutionary device

that has garnered significant attention in the field of electronics. By leveraging the
concept of negative capacitance, NCFETs have the potential to overcome the limita-
tions of conventional transistors and enable significant advancements in low-power
and high-performance circuitry. The negative capacitance effect in NCFETs offers
several advantages. Firstly, it can address the power dissipation challenges faced
by conventional transistors that suffers from subthreshold slope limitations. It can
effectively reduce the subthreshold swing and enable steeper turn-on and turn-off
characteristics resulting in improved energy efficiency. This characteristic makes
NCFETs particularly attractive for low-power applications such as mobile devices
and Internet of Things (IoT) devices.
Furthermore, NCFETs can potentially boost the performance of integrated
circuits. The negative capacitance can counteract the inherent energy losses and
thermal limitations in electronic devices. By stabilizing the negative capacitance
using suitable engineering techniques, NCFETs can maintain a highly effective
capacitance and deliver improved speed and performance compared to conven-
tional transistors. The development of NCFET possess several challenges. One
major hurdle is the integration of ferroelectric materials into the transistor fabri-
cation process. Ferroelectric materials have different properties and requirements
compared to traditional dielectric materials necessitating the development of new
manufacturing techniques and the optimization of material interfaces. Achieving
high-quality, stable ferroelectric thin films with appropriate switching properties is
critical for the successful implementation of NCFETs.
230 S. K. Swain et al.

Another challenge lies in understanding and managing the complex dynamics of

the negative capacitance effect. The interaction between the ferroelectric material and
the transistor structure needs to be carefully characterized and modeled to ensure reli-
able and predictable device behavior. Additional issues related to device scalability,
reliability, and variability need to be addressed for practical NCFET implementation.
Despite these challenges, research and development efforts in NCFETs are rapidly
advancing. Significant progress has been made in identifying suitable ferroelectric
materials exploring innovative device architectures with improved understanding of
the underlying physics. Advancements in computational modeling and simulation
techniques are aiding in the design and optimization of NCFETs.
In conclusion, the negative capacitance field-effect transistor (NCFET) represents
a promising avenue for future electronics devices. By leveraging the unique prop-
erties of ferroelectric materials and the negative capacitance effect, NCFETs offer
the potential for significant improvements in energy efficiency and performance.
Further research and development in this field are crucial to overcome the remaining
challenges and unlock the full potential of NCFETs for a wide range of applications
including mobile devices, data centers, artificial intelligence, and beyond.

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0075
Chapter 9
Nanoelectromechanical Switches: As
a Steep Switching Device

Noel Prashant Ratchagar and Amitesh Kumar

Abstract This chapter provides a comprehensive analysis of nanoelectromechan-

ical systems (NEMS) switches as highly efficient switching devices. It explores
the development of early automatic systems to modern silicon-based technologies.
It highlights the advantages of NEMS switches over conventional semiconductor
devices, highlighting features like low-power consumption, high ON-current, and
ideal subthreshold slope. The chapter delves into various actuation mechanisms,
fabrication techniques, and discusses development challenges such as scalability
and integration. The text also explores the capabilities of NEMS switches in terms of
energy efficiency, precision sensing, and improved performance in communication.
It highlights the significant impact these switches can have on nanoelectronics.

Keywords Nanoelectromechanical systems · NEMS switches · Steep switching

devices · Low-power consumption · ON-current · Actuation mechanisms ·
Fabrication techniques · Computing · Sensing · Communication

Introduction

The first automatic switching system was developed in the early twentieth century
to address the problem faced by a telephone operator to connect the tele-
phone lines manually (http://telephonetribute.com/switches_survey_intro_chapter_
1.html). Mechanical switches were small, convenient, and efficient. Since the tran-
sistors were invented, silicon-based switching devices attracted dramatic attention
because they have increased speed. However, they suffered physical constraints

Both authors are first authors.

N. P. Ratchagar
Department of Electronics and Communication Engineering, Presidency University, Bangalore,
India
A. Kumar (B)
Department of Electrical Engineering, National Institute of Technology, Patna, India
e-mail: [email protected]

© The Author(s), under exclusive license to Springer Nature Singapore Pte Ltd. 2024 233
S. Singh et al. (eds.), Beyond Si-Based CMOS Devices, Springer Tracts in Electrical and
Electronics Engineering, https://doi.org/10.1007/978-981-97-4623-1_9
234 N. P. Ratchagar and A. Kumar

such as short channel effects (Baker 1998; Davari et al. 1995). Petersen, in 1978,
developed the first micro-sized mechanical switch with an electrostatically actuated
cantilever (Petersen 1978). Since then, microelectromechanical system (MEMS)/
nanoelectromechanical system (NEMS) switches are considered one of the ideal
switching devices as they have the advantages of both the mechanical and silicon-
based switch. The MEMS/NEMS switches possess excellent features of low-power
consumption, high ON-current, and near-ideal switching characteristics. Numerous
applications like logic operations, memory devices, and power switching has been
reported.

State of Art for Switching

MEMS/NEMS switches are widely used because of its strengths including good
isolation, low-power consumption, high linearity, and utility in wide bandwidth
(Rebeiz 2003). These switches can be classified into different categories depending
on the actuation mechanism, movement of the suspended structure, type of movable
part, and number of electrodes as given in Table 9.1 (Song and Yoon 2016).

Table 9.1 Different categories of switches

Classification Category Remark
Actuation mechanism Electrostatic Fast, low-power consumption
Piezoelectric Low voltage, complicated
Electromagnetic High force, suitable for power switching
Thermoelectric Low voltage, slow
Combination High performance, complicated
Movement Vertical Widely used
Lateral Large size, one mask fabrication
Torsional Low voltage, complicated
Movable structure Membrane Stable, low voltage, large area
Fixed–Fixed High restoring force
Cantilever Widely used, simple
Number of electrodes 3-electrodes Widely used, simple
4-electrode Not depend on source voltage
9 Nanoelectromechanical Switches: As a Steep Switching Device 235

Nano-relay Principles

A NEMS switch is usually operated through a three-terminal configuration, including

a suspended cantilever beam with two lower electrodes (Rottenberg et al. 2012). The
beam, actuation electrode, and contact electrode are “source”, “gate”, and “drain”,
respectively, as in Fig. 9.1. In OFF = state, there is no contact between the source
beam and drain electrode so that the current is zero. When a voltage is applied to the
gate electrode, the beam comes in contact with the drain electrode causing a high and
constant current flow. The threshold voltage above which the source beam comes in
contact with the drain electrode causing current to flow is “pull-in voltage.”
From the operational point of view, the switching can happen according to four
different actuation principles: (i) Electrostatic, (ii) Piezoelectric, (iii) Electromag-
netic, and (iv) Thermoelectric (Liu 2011).

Electrostatic Actuation

NEMS relays using electrostatic actuation are simple in comparison with the other
actuation techniques and are extensively used due to its extremely low-power
consumption and relatively short switching speed (Senturia 2001). These switches
are based on two conductive electrodes, one fixed and other movable, like a parallel-
plate capacitor. When a potential is applied across the electrodes, the electrostatic
force attracts the movable electrode toward the fixed electrode.
In the first condition, the terminals A and B are disconnected and hence the relay
is in OFF-state. In the second condition, a bias voltage greater than the pull-in voltage
is applied between the fixed electrode (E1) and movable electrode (E2) creating a
contact between terminals A and B turning the relay ON.

Piezoelectric Actuation

Piezoelectric effect is the ability of a material to generate electric field in response

to mechanical stress and the ability to deform a material in response to electric field

Source Gate Drain Source Gate Drain

Substrate Substrate

Fig. 9.1 Schematic of NEMS switch with three electrodes–source, gate, and drain
236 N. P. Ratchagar and A. Kumar

is reverse piezoelectric effect. The reverse piezoelectric effect is used in piezoelec-

tric actuated switches. The most commonly used piezoelectric materials for NEMS
switches are Lead Zirconate Titanate (PZT), and Aluminum Nitride (AiN) (Niezrecki
et al. 2001).
The suspended beam must be coated with a thin film of piezoelectric material. As
the piezoelectric film is coated on the top surface of the beam, the deformation due
to the piezoelectric effect results in downward displacement.
In the first condition, there is no connection between the terminals A and B and
hence the relay is OFF. In the second condition, a bias voltage greater than the pull-in
voltage is applied across the electrodes E1 and E2 causing the piezoelectric material
to expand. This expansion makes the beam to bend downward creating a contact
between terminals A and B turning the relay ON.

Electromagnetic Actuation

Electromagnetic switches convert the magnetic field into mechanical movement

based on magnetostrictive effect. Here, the beam bends because of the interaction
between the magnetic-sensitive material and the induced magnetic field (Cho et al.
2005). The beam is coated with a ferromagnetic material to make it sensitive to vari-
ations in magnetic field. A coil is wound across the beam and a magnetic field is
generated by flowing current through the coil.
In the first condition, there is no connection between the terminals A and B and
hence the relay is OFF. In the second condition, a current is sent through the coil
building up a magnetic field around the switch. This magnetic field makes the beam
to bend creating a contact between terminals A and B turning the relay ON.

Thermoelectric Actuation

The principle behind the thermoelectric actuation is thermal expansion. When an

electric current is passed through a material, the material expands depending on the
thermal expansion coefficient causing a deformation in the material (Daneshmand
et al. 2009). The temperature required to deform the material can be easily obtained
with Joule heating caused by current flowing a resistive component (Wang et al.
2003). In order to generate heat to deform the suspended beam, micro-heaters are
embedded on the beam. Usually, materials with higher resistivity such as polycrys-
talline silicon are used rather than typically used metals. By this way, it is sufficient
to have a low current to obtain desired temperature.
In the first condition, there is no connection between the terminals A and B and
hence the relay is OFF. In the second condition, a bias voltage greater than the pull-
in voltage is applied across the microheater’s electrodes E1 and E2 generating heat
9 Nanoelectromechanical Switches: As a Steep Switching Device 237

on the beam causing a thermal expansion. This expansion makes the beam to bend
downward creating a contact between terminals A and B turning the relay ON.

Fundamentals of NEMS Fabrication

NEMS are basically systems that has integrated mechanical nanostructures and
electronics. The fabrication of these systems uses the basic processing techniques
used in CMOS manufacturing. The processes fall under three categories (i) Bulk
micromachining, (ii) Surface micromachining, and (iii) High aspect ratio silicon
micromachining.
Bulk micromachining involves removal of a significant portion of the substrate
material (Kovacs et al. 1998). Surface micromachining involves addition of thin
layers of structural or sacrificial materials and patterning them (Bustillo et al. 1998).
High aspect ratio micromachining combines the deep dry etching with surface micro-
machining to realize high aspect ratio structures (Ayazi and Najafi 1999). The major
steps involve three processes: Deposition, Lithography, and Etching.

Deposition

Materials can be deposited using various techniques like oxidation, physical vapor
deposition, chemical vapor deposition, electroplating, and sol–gel deposition. Phys-
ical vapor deposition includes evaporation and sputtering. Evaporation technique is
used to deposit metals on a surface from a target by heating under high vacuum.
Sputtering is done by knocking off atoms from a target with an inert gas plasma.
In chemical vapor deposition, the material is deposited on the substrate through a
chemical reaction that takes place when a precursor material is sent into a furnace.
In sol–gel deposition, a colloidal suspension of solid particles is first dispersed on
the substrate and then the solvent is removed.

Etching

Various etching techniques for achieving isotropic or anisotropic profiles are devel-
oped using either wet or dry etching. The most common wet etchant for silicon is
HNA (combination of hydrofluoric acid, nitric acid, and acetic acid) resulting in an
isotropic profile. For anisotropic profile using wet etchants, potassium hydroxide
(KOH), tetramethylammonium hydroxide (TMAH), and ethylenediamine pyrocate-
chol (EDP) are used. For other materials like silicon dioxide hydrofluoric acid (HF)
is used; for silicon nitride, phosphoric acid (H3 PO4 ) is used; for gold, potassium
chloride (KCl) is used; and for organics acetone (C3 H6 O) is used. For dry etching,
238 N. P. Ratchagar and A. Kumar

plasma and chemical vapors are used. Xenon difluoride (XeF2 ) is used for silicon, a
combination of trifluoro methane (CHF3 ) and oxygen (O2 ) for silicon dioxide, sulfur
hexafluoride (SF6 ) for silicon nitride and O2 plasma for organics.

Lithography

During fabrication of devices, usually, a pattern is transferred at some point of the

time. This technique of pattern transfer is lithography. In lithography, a photosensitive
polymer material, called photoresist, is coated on the substrate and the photoresist is
exposed to ultraviolet light through a photomask. Many types of lithography tech-
niques are available like optical lithography, X-ray lithography, and electron-beam
lithography. Electron-beam lithography has a unique feature of directly writing a
pattern on the resist without the necessity of a mask.

Devising and Synthesis of MEMS and NEMS

In order to design and fabricate MEMS and NEMS devices effectively, recent
advancements in devices, drivers/controllers, and ICs as well as fabrication tech-
nologies provide sufficient benefits and capabilities. The most critical issue is to
design high-performance systems satisfying specific criteria and requirements like
functionality, compatibility, power and thermal management, etc. (Lyshevski 2000).
Lyshevski S. E. devised a step-by-step procedure to design microdevices which are
as follows (Lyshevski 2002):
1. Define application and environmental requirements
2. Specify performance specifications
3. Devise micro-/nano-devices, driving/sensing circuitry and controlling/
processing ICs
4. Develop fabrication process using micromachining techniques compatible with
CMOS technology
5. Perform electromagnetic, energy conversion, mechanical, thermal, vibroa-
coustic, and sizing/dimension estimates
6. Perform heterogeneous electromagnetic, mechanical, thermal, vibroacoustic
design with performance analysis, and outcome prediction
7. Verify, modify, and refine design with ultimate goals and objectives to optimize
the performance.
9 Nanoelectromechanical Switches: As a Steep Switching Device 239

Fig. 9.2 Lumped model of

the cantilever NEMS relay
Spring k
Fk
Mass m
Fe Fa
Se Sa

Modeling of NEMS Devices and Structures

Modeling a device or a structure happens at many levels. Four modeling levels, (i)
System, (ii) Device, (iii) Physical, and (iv) Process, are identified (Senturia 2001).
System level deals with block diagram representations and lumped-element circuit
models. At the process level, the process sequence and photomask designs for device
fabrication is created. The behavior of the real devices in the 3D continuum is
addressed in the physical level, while device level captures the physical behavior
of a component of the system.
A NEMS switch can be modeled as a simple lumped spring-mass system as in
Fig. 9.2 (Rottenberg et al. 2012). The movable beam structure is modeled by a rigid
plate with mass m supported by a linear spring of stiffness constant k. It is actuated by
a stationary parallel-plate capacitor of area S e separated by a gap d 0 . An additional
parasitic nano-force of attraction F a is assumed. The forces are exerted across the
actual gap d to the mobile plate through an actuator of area S a .

Nanosystems, Quantum Mechanics, and Mathematical

Models

In recent years, advancements in micro-/nano-technology and quantum informa-

tion technology have enabled the manipulation of photons, electrons (holes), and
even phonons at the level of single quanta. Exploring the interaction among optical,
electrical, and mechanical degrees of freedom has led to the exploration of various
applications in nano-opto-electro-mechanical systems (NOEMS). These applica-
tions include the control of photons, charges, and phonons, facilitating informa-
tion processing at both classical and quantum levels. The ongoing development
of quantum technology has resulted in numerous achievements, particularly in the
up-conversion and bidirectional conversion between microwave and optical signals.
Mechanical Modeling
√
2
kmeff
meff Z̈ + Ż + kZ = Fele (Z) + Fvdw (Z)
Q
240 N. P. Ratchagar and A. Kumar

Mechanical modeling involves the consideration of parameters such as displace-

ment (Z) of the gate, effective mass (meff ), quality factor (Q) within the [0–1] range
for digital logic applications (Rebeiz 2003), spring constant (K), and Vanderwaal’s
force (F vdw ). In the nanoscale relay context, undesirable forces like Van der Waals’
and Casimir forces can significantly impact the pull-in stability of NEM relays (Peng
et al. 2023; Han et al. 2020; Xu et al. 2021).

Electrostatic Nano-relay Modeling, and Optimization

Modeling electrostatic nanorelays in NEMS involves capturing the electrostatic inter-

actions and mechanical behavior of these devices. Here’s an overview of the key
considerations and steps in the electrostatic nano-relay modeling process (Alrudainy
et al. 2014; Pakhare et al. 2023a; Li et al. 2023; Esfarjani and Mansoori 2005):
1. Electrostatic Forces:
• Coulomb’s Law: Incorporate Coulomb’s law to calculate the electrostatic
forces between charged components within the relay.
• Parallel-Plate Capacitor Model: Utilize the parallel-plate capacitor model
to represent the electrostatic interaction between movable and stationary
components.
2. Mechanical Dynamics:
• Mass-Spring-Damper System: Represent the mechanical structure of the
relay as a mass-spring-damper system, where the moving part (mass) is
connected to a spring and experiences damping forces.
• Equations of Motion: Derive the equations of motion considering the
mechanical forces, including the electrostatic forces and any other external
forces acting on the system.
3. System Parameters:
• Geometry and Dimensions: Define the geometric parameters of the relay,
including the separation distance between the relay components and the
dimensions of the movable part.
• Material Properties: Consider the mechanical and electrical properties of
the materials used in the relay, such as stiffness, damping coefficients, and
permittivity.
4. Dynamic Response Analysis:
• Resonance Frequencies: Investigate the resonance frequencies of the relay
system to understand its natural modes of vibration.
• Transient Analysis: Simulate the dynamic response of the relay under
different operating conditions, such as actuation and release, to analyze its
transient behavior.
9 Nanoelectromechanical Switches: As a Steep Switching Device 241

5. Electromechanical Coupling:
• Feedback Mechanisms: Consider the feedback loop between the mechanical
and electrical domains to model how the mechanical motion influences the
electrical properties and vice versa.
• Voltage-Displacement Relationship: Establish the relationship between the
applied voltage and the displacement of the relay components.
6. Pull-In and Release Analysis:
• Pull-In Voltage: Determine the voltage at which the relay transitions from
the open to the closed state, known as pull-in voltage.
• Release Characteristics: Study the release characteristics of the relay to
understand its stability and reliability in returning to the open state.
7. Noise and Stochastic Effects:
• Thermal Noise: Account for thermal fluctuations and noise effects on the
relay’s performance, particularly at the nanoscale where these factors can be
significant.
8. Validation and Calibration:
• Experimental Validation: Validate the model by comparing its predictions
with experimental data obtained from physical prototypes.
• Parameter Calibration: Adjust model parameters based on experimental
results to improve the accuracy of the simulation.
Electrostatic nano-relay modeling is a complex interdisciplinary task, requiring
expertise in electromagnetics, mechanics, and control systems. Advanced simulation
tools and numerical methods are often employed to perform dynamic analyses and
optimize the design of these nanoscale devices.
Electrical Modeling
In contrast to CMOS, a digital circuit based on NEM relays necessitates the design
of a large, intricate logic gate where only one mechanical delay occurs at each stage.
However, this design approach results in a substantial rise in the overall on-state
resistance, consequently causing an increase in electrical delay time (Rana et al.
2014).
242 N. P. Ratchagar and A. Kumar

On-state electrical characteristics of NEM relay

Examining the on-state electrical characteristics of NEM relays reveals the on-
state resistance, illustrated in the figure above.

Dynamic Modeling

Dynamic modeling of nanoelectromechanical systems (NEMS) involves the study of

the system’s behavior over time, considering the dynamic response of its mechanical
and electrical components. This type of modeling is essential for understanding and
predicting the dynamic performance of NEMS devices under various conditions.
Here are key aspects of NEMS dynamic modeling (Pakhare et al. 2023b; Thesis
2014):
1. Mechanical Dynamics:
• Resonance Frequencies: Characterizing the natural frequencies and modes
of mechanical oscillations in NEMS devices.
• Damping Effects: Considering the impact of damping on the mechanical
motion and how it affects the overall response.
2. Electrical Dynamics:
• Circuit Elements: Modeling the electrical components, such as capacitors
and resistors, and their interactions with the mechanical elements.
• Electromechanical Coupling: Understanding how the mechanical motion
influences the electrical properties and vice versa.
3. Coupled System Dynamics:
• Interaction Forces: Analyzing the forces between mechanical and electrical
elements, including electrostatic and electromechanical forces.
• Transient Responses: Examining the system’s behavior during transient
events, such as sudden changes in input or mechanical perturbations.
4. Nonlinear Effects:
9 Nanoelectromechanical Switches: As a Steep Switching Device 243

• Nonlinearities in Mechanical Response: Accounting for nonlinearities that

may arise due to large mechanical displacements or material properties.
• Electromechanical Nonlinearities: Considering nonlinear effects in the
interaction between mechanical and electrical components.
5. Control Strategies:
• Feedback Control: Implementing control strategies to regulate and stabilize
the dynamic behavior of NEMS devices.
• Actuation and Sensing: Incorporating models for the actuation and sensing
mechanisms to understand their impact on dynamic responses.
6. Noise and Fluctuations:
• Thermal Noise: Considering the influence of thermal fluctuations on the
mechanical and electrical components.
• Noise Sources: Analyzing sources of noise and their impact on the dynamic
behavior, especially at the nanoscale.
7. Verification and Validation:
• Experimental Correlation: Validating the dynamic models through experi-
mental measurements to ensure accuracy and reliability.
• Parameter Estimation: Iteratively refining model parameters based on
experimental data for better alignment with real-world behavior.
Dynamic modeling of NEMS is crucial for optimizing device performance,
designing control systems, and understanding the limitations and challenges associ-
ated with the dynamic operation of nanoscale systems.

Quasi-static Modeling

Quasi-static modeling of NEMS, or nanoelectromechanical systems, involves

analyzing their behavior under slow and gradual changes, assuming equilibrium
at each step. This approach is useful because it simplifies the dynamic analysis and
allows for a more manageable representation of the system’s response (Models et al.
2015; Fedotov et al. 2021).
In quasi-static modeling, you typically consider the mechanical and electrical
aspects separately. For the mechanical part, you’d focus on things like the mechanical
resonator’s deformation, while for the electrical part, you’d look at the changes in
the electronic properties.
244 N. P. Ratchagar and A. Kumar

Technological Challenges for NEMS Computing

Nanoelectromechanical systems (NEMS) computing indeed faces various techno-

logical challenges, although the potential benefits are substantial. Here are some key
challenges (Darban et al. 2023; Chaitanya et al. 2023; Wang et al. 2023):
1. Fabrication Precision: NEMS devices operate at the nanoscale, requiring
extremely precise fabrication techniques. Any deviations or imperfections during
fabrication can significantly impact their performance and reliability.
2. Material Issues: The choice of materials for NEMS components is critical. Iden-
tifying materials with suitable mechanical, electrical, and thermal properties at
the nanoscale is challenging. Moreover, these materials must be compatible with
the fabrication processes and exhibit minimal fatigue over numerous mechanical
cycles.
3. Integration with Electronics: Integrating NEMS devices with conventional elec-
tronic circuits poses challenges. Ensuring seamless communication and interface
between the mechanical and electronic components while maintaining reliability
is a complex task.
4. Damping and Energy Dissipation: NEMS devices are prone to energy dissipation
and damping effects, limiting their efficiency. Managing these issues is crucial
for achieving long-term stability and energy-efficient operation.
5. Temperature Sensitivity: NEMS devices may be sensitive to temperature varia-
tions. Controlling and mitigating the impact of temperature fluctuations on their
performance is essential for practical applications.
6. Noise and Signal Integrity: At the nanoscale, noise becomes a significant concern.
Managing noise levels and ensuring high signal integrity in NEMS-based systems
is crucial, especially in computing applications where accurate information
processing is essential.
7. Scalability: The scalability of NEMS technology for large-scale computing
applications is an ongoing challenge. Ensuring that the technology can be reli-
ably scaled up without compromising performance or increasing fabrication
complexity is a significant hurdle.
8. Reliability and Durability: NEMS devices need to withstand mechanical stress
and environmental conditions over extended periods. Ensuring their reliability
and durability in real-world applications, where they might be subject to various
external factors, is a critical consideration.
9. Cost and Manufacturing Challenges: The current fabrication processes for NEMS
devices can be expensive and complex. Addressing these cost and manufacturing
challenges is crucial for making NEMS technology commercially viable.
9 Nanoelectromechanical Switches: As a Steep Switching Device 245

Low-Voltage Operation

Operating nanoelectromechanical systems (NEMS) at low voltages is an interesting

aspect with potential advantages such as reduced power consumption and heat gener-
ation. However, it comes with its own set of challenges. Here are some considerations
for the low voltage operation of NEMS (Darban et al. 2023):
1. Pull-in Voltage: NEMS devices often operate close to their pull-in voltage, the
voltage at which the mechanical structure collapses due to the electrostatic force.
Operating at low voltages while maintaining stability and avoiding unintentional
pull-in is crucial.
2. Signal-to-Noise Ratio: At lower voltages, the signal-to-noise ratio can become
a concern. The signals generated by the mechanical movement of NEMS may
become weaker and more susceptible to noise, impacting the reliability of data
processing.
3. Switching Speed: Lowering the operating voltage can affect the switching speed
of NEMS devices. It is important to find a balance between voltage reduction
and maintaining acceptable switching times for practical applications.
4. Material Properties: The choice of materials for NEMS components is critical
when operating at low voltages. Some materials may not exhibit the desired
mechanical properties or may be more susceptible to wear and tear at lower
voltages.
5. Electrostatic Force: The electrostatic force that drives the mechanical movement
of NEMS is directly related to the applied voltage. Lowering the voltage may
reduce the force, affecting the overall performance of the device.
6. Energy Efficiency: While low voltage operation can reduce power consumption,
it’s essential to consider the overall energy efficiency of the system. This includes
factors such as the energy required for actuation and signal processing.

Reliability of Contact Technology

Reliability of contact technology is a crucial aspect in the performance of nano-

electromechanical systems (NEMS). Contacts in NEMS devices play a vital role in
electrical signal transmission, actuation, and sensing. Here are some considerations
regarding the reliability of contact technology in NEMS (Hou et al. 2023; Kaynak
et al. 2023; Reynaud et al. 2023):
1. Wear and Tear: NEMS devices often involve moving mechanical parts, and the
contacts may experience wear and tear over time. The reliability of the contact
technology depends on the ability of the materials used to withstand repeated
mechanical movements without significant degradation.
2. Material Selection: The choice of materials for the contacts is critical. Mate-
rials should have suitable mechanical, electrical, and tribological properties to
246 N. P. Ratchagar and A. Kumar

ensure reliable and stable contact performance. Minimizing wear, corrosion, and
adhesion between contact surfaces is essential.
3. Stiction and Adhesion: At the nanoscale, stiction and adhesion between
contacting surfaces become significant factors. These phenomena can lead
to unwanted sticking of the contacts, affecting their reliability and causing
operational issues.
4. Contact Resistance: Maintaining low and stable contact resistance is essential
for efficient signal transmission. The reliability of contact technology is compro-
mised if contact resistance fluctuates or increases over time due to factors like
oxidation or contamination.
5. Environmental Sensitivity: NEMS devices may be deployed in various envi-
ronments, and the reliability of contact technology should be robust against
environmental factors such as humidity, temperature variations, and chemical
exposure.
6. Switching Speed and Endurance: NEMS devices often involve rapid switching
or actuation. Ensuring that contact technology can sustain high switching speeds
and endure a large number of cycles without failure is crucial for long-term
reliability.
7. Cleaning and Maintenance: Developing methods for cleaning and maintaining
contacts in NEMS devices is important. This includes addressing issues such as
removing contaminants or restoring proper functionality in case of performance
degradation (Kaynak et al. 2023).

NEMS-Based Architectures

NEMS-based architectures refer to computing or electronic systems that leverage

nanoelectromechanical systems (NEMS) as fundamental components. NEMS
devices are typically built at the nanoscale and utilize mechanical motion for various
functions, such as computation, sensing, and communication (Kaynak et al. 2023;
Reynaud et al. 2023).

Conventional Architectures

Here are some potential conventional architectures and applications where NEMS
can play a significant role:
1. NEMS Computing:
• Memory Devices: NEMS-based memory devices can offer high-density
storage with low-power consumption. Examples include NEMS-based non-
volatile memory or NEMS-based resistive switching devices.
9 Nanoelectromechanical Switches: As a Steep Switching Device 247

• Logic Gates: NEMS devices can be used as building blocks for logic gates,
enabling the development of NEMS-based logic circuits with potentially lower
power consumption compared to traditional electronic circuits.
2. NEMS Sensing and Actuation:
• Sensors and Actuators: NEMS devices can be employed as sensitive sensors
for detecting various physical quantities such as pressure, mass, and acceler-
ation. They can also act as actuators for precise mechanical movements.
• Inertial Sensors: NEMS-based accelerometers and gyroscopes can be used
in applications like navigation systems, robotics, and inertial measurement
units.
3. Communication Systems:
• Radio Frequency (RF) Devices: NEMS resonators and switches can be utilized
in RF applications, offering potential advantages in terms of size, power
consumption, and frequency stability.
• NEMS-Based Communication Networks: NEMS devices could enable novel
communication architectures, potentially leading to more efficient and
compact communication systems.
4. Energy Harvesting:
• NEMS-Based Energy Harvesters: NEMS devices can convert mechanical
vibrations into electrical energy. This capability can be harnessed for energy
harvesting in applications where small-scale, sustainable power sources are
required.
5. Biomedical Applications:
• NEMS-Based Biosensors: NEMS devices can be used for highly sensitive
biosensing, enabling the detection of biomolecules with high precision. This
has applications in medical diagnostics and healthcare.
• Drug Delivery Systems: NEMS-based devices can be engineered for
controlled drug delivery, offering precise release mechanisms at the nanoscale.
6. NEMS Integration with CMOS:
• Hybrid Integration: Combining NEMS devices with traditional Complemen-
tary Metal–Oxide–Semiconductor (CMOS) technology can lead to hybrid
architectures, benefiting from the strengths of both technologies.
7. Quantum Computing:
• NEMS-Based Qubits: NEMS devices could play a role in the development
of quantum computing by providing stable and controllable qubits at the
nanoscale.
The successful implementation of NEMS-based architectures relies on over-
coming fabrication challenges, improving reliability, and addressing issues related to
248 N. P. Ratchagar and A. Kumar

scalability. Ongoing research in this field aims to unlock the full potential of NEMS
technology in various applications.

Adiabatic Architectures

Adiabatic computing refers to a computing paradigm where the system undergoes a

slow, energy-conserving process to perform computations. Adiabatic architectures
aim to minimize energy dissipation during computation, making them attractive
for low-power applications. When integrated with nanoelectromechanical systems
(NEMS), adiabatic architectures can offer unique advantages. Here are some aspects
to consider (Smith et al. 2023; Ali et al. 2023; Vanlalchaka et al. 2023):
1. Energy Efficiency:
• Adiabatic Processes: Adiabatic NEMS architectures leverage slow and
energy-conserving processes, minimizing energy dissipation. This is partic-
ularly crucial in nanoscale devices where energy efficiency is a paramount
concern.
2. NEMS as Energy Storage Elements:
• Mechanical Resonators: NEMS devices, such as mechanical resonators, can
store and release mechanical energy during adiabatic processes, acting as
energy storage elements in the system.
3. Computation with Mechanical Motion:
• NEMS Logic Gates: NEMS devices can be integrated into adiabatic logic
gates where mechanical motion is utilized for computation. This could involve
utilizing the mechanical degrees of freedom of NEMS for adiabatic switching
and signal processing.
4. Adiabatic Quantum Computing:
• Quantum Adiabatic Computing: NEMS-based architectures could contribute
to adiabatic quantum computing. Adiabatic quantum algorithms aim to find
the ground state of a quantum system, and the mechanical properties of NEMS
could be exploited for adiabatic quantum annealing.
5. Potential for Hybrid Systems:
• Integration with Other Technologies: Adiabatic NEMS architectures may
be part of hybrid systems, combining the advantages of NEMS with other
emerging technologies or existing computing paradigms.
6. Challenges in Implementation:
9 Nanoelectromechanical Switches: As a Steep Switching Device 249

• Precision Control: Achieving precise control over adiabatic processes in

NEMS devices is challenging due to the potential sensitivity of mechanical
components to environmental factors.
• Fabrication Complexity: Integrating adiabatic principles with NEMS requires
advanced fabrication techniques to ensure the reliable and precise construction
of nanoscale devices.
7. Applications in Signal Processing:
• Signal Processing Circuits: Adiabatic NEMS architectures may find appli-
cations in signal processing circuits, where the slow, adiabatic nature of the
processes can be advantageous for specific computational tasks.
8. Reduced Heating Issues:
• Minimized Heat Generation: Adiabatic processes naturally minimize heat
generation during computation, which is beneficial in NEMS devices to
prevent thermal effects and enhance device reliability.
Research in the field of adiabatic NEMS architectures is ongoing, and advance-
ments in fabrication techniques, control methodologies, and materials science are
essential to realizing the full potential of this approach. As technology progresses,
these architectures may play a significant role in developing energy-efficient and
high-performance nanocomputing systems (Smith et al. 2023) [44].

Conclusions

In conclusion, nanoelectromechanical systems (NEMS) switches represent a

promising avenue for advancing electronic and computing technologies. These
miniature switches, operating at the nanoscale, offer unique advantages and capabil-
ities. NEMS switches stand at the forefront of nanoelectronics, offering a pathway to
enhanced performance, reduced energy consumption, and innovative functionalities
in electronic systems. The ongoing exploration of their capabilities and the resolution
of associated challenges will likely lead to transformative applications in the coming
years.

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Chapter 10
The Device-Circuit Co-design Perspective
on Phase-Transition and Hybrid
Phase-Transition (Hyper-) FETs,
Phase-FETs, and MOSFET

Abhishek Choubey, Shruti Bhargava Choubey, Durgesh Nandan,

and Kumar Gautam

Abstract Phase-Transition and Hybrid Phase-Transition (Hyper-) FETs, Phase-

FETs, and MOSFETs are the advanced semiconductor technologies that are the
subject of this book chapter’s exploration of the integrated device-circuit co-design
viewpoint. It highlights the revolutionary potential of these new transistors by offering
a thorough examination of their special qualities, advantages, and difficulties. The
significance of using an integrated approach to device and circuit design is empha-
sized in the debate. The chapter explores the unique functions that various types
of FETs will play in influencing integrated circuits in the future and looks into the
synergy between them. It also looks at how these innovative transistors coexist with
conventional MOSFETs, providing insights into the prospects and difficulties in the
changing semiconductor industry. Located at the intersection of circuit and device
design, this chapter promotes a multidisciplinary and cooperative approach. It offers
practitioners, engineers, and academics a framework for guidance and important
insights into the complexities of semiconductor innovation.

Keywords Phase-transition FETs · Hybrid phase-transition FETs · Device and

circuit synergy · Semiconductor technologies · MOSFETs

A. Choubey (B) · S. B. Choubey

Sreenidhi Institute of Science & Technology, Hyderabad, Telangana, India
e-mail: [email protected]
D. Nandan
School of Computer Science & Artificial Intelligence, SR University, Warangal, India
K. Gautam
AI Graduate School, Gwangju Institute of Science and Technology, Gwangju, Korea

© The Author(s), under exclusive license to Springer Nature Singapore Pte Ltd. 2024 253
S. Singh et al. (eds.), Beyond Si-Based CMOS Devices, Springer Tracts in Electrical and
Electronics Engineering, https://doi.org/10.1007/978-981-97-4623-1_10
254 A. Choubey et al.

Introduction

The term “device-circuit co-design” refers to a design technique in which an elec-

tronic component and the circuit is integrated, developed, and optimized at the same
time. As the relationship between device performance and circuit design strengthens,
this method is becoming more vital. Device designers have historically prioritized
the performance of individual electronic components, while circuit designers have
prioritized the overall purpose and performance of the circuit. Due to the miniatur-
ization and increased complexity of electronic systems, it is now imperative to think
about both aspects of the design at the same time (Maxey et al. 2022).
To achieve the optimal performance of both the devices and the circuits,
device-circuit co-design encourages close collaboration between device and circuit
designers. Complex computer-aided design (CAD) software is needed for this
purpose as it is the only method to simulate and optimize the devices and the circuits
(Li et al. 2021). The capacity to simultaneously improve the electronic system’s
performance and power efficiency is a major benefit of device-circuit co-design.
System performance can be improved and power consumption can be reduced by
joint optimization of the devices and circuits. Also, unlike more conventional design
methods, device-circuit co-design encourages the investigation of novel device tech-
nologies and circuit topologies. For instance, novel circuit topologies tailored to the
special features of developing device technologies like memristors and spintronics
may be necessary. Overall, device-circuit co-design is a key strategy for achieving
performance and power consumption optimization in the design of next-generation
electronic systems.1
The implementation of high-density, high-speed, low-power VLSI systems has
been made possible by CMOS technology’s consistent scaling. More complex carrier
transport phenomena’s are required to completely explain the behavior of 3D multi-
gate FETs that has evolved from planar, classical, single-gate FETs over the previous
decade. According to the International Technology Roadmap for Semiconductors
(ITRS) (Wang et al. 2022), multi-gate FET technology is expected to replace FD-
SOI and other scaled planar bulk technologies in this decade. Both Intel and TSMC
have already announced their transition to such devices (Liu et al. 2022). From
manufacturing standpoint, the FinFET (O’Brien et al. 2021) stands out as the most
promising contender for widespread implementation. Significant efforts have been
spent over the past few years on how to better and more cheaply integrate FinFET
technology into the standard CMOS process (Cho et al. 2015). Recently, a lot of
emphasis have been given to study digital circuits (Wang et al. 2022), analog/RF
circuits, and SRAMs (Acerce et al. 2015) as well as the analysis and design of
FinFET devices (Bellino et al. 2019).
To store and alter the information, phase transition devices use phase change
materials. These materials have the unique ability to undergo a phase transition when
subjected to an electric current or heat often between a crystalline and amorphous
phase. Non-volatile memory in which digital information is stored and remains even

1 “Roadmap—IEEE IRDS™ .” https://irds.ieee.org/editions.

10 The Device-Circuit Co-design Perspective on Phase-Transition … 255

when power is disconnected is the most prevalent usage of phase transition devices.
To keep information safe and secure, phase change memory (PCM) makes use of
chalcogenide glasses and other phase changing materials. PCM devices are faster
and more durable than conventional flash memories.
Neuromorphic computing that attempts to create a computer system that acts and
functions like human brain also makes use of phase transition devices. This tech-
nology can perform tasks like pattern recognition and machine learning by mimicking
the actions of neurons and synapses. In logic and computing, phase transition devices
could be utilized to create reprogrammable analog circuits and reconfigurable logic
gates (Zimmers et al. 2013). When compared to conventional electronics, phase tran-
sition devices are faster, use less energy and can be used in a wider variety of applica-
tions. When more than one phase or mechanism contributes to the switching behavior
of a material, we say that the material is undergoing a hybrid phase transition. As a
result, they may exhibit novel and intriguing features not seen in conventional phase
transition devices.
The resistive random access memory (RRAM) is an example of a hybrid phase
transition device since it switches resistance using both filamentary and interface
processes. In interface switching, the resistance of the device is changed by adjusting
the interface between two materials, whereas in filamentary switching, a conductive
filament is generated within the device by the movement of ions.
Combining the ferroelectric effect (the capacity of some materials to flip their
polarization in response to an electric field) with resistive switching, the ferroelectric
resistive switching (FE-RS) device is another example of a hybrid phase transition.
The resistance of an FE-RS device can be affected by the polarization of the ferro-
electric materials leading to a complicated switching behavior that can be modulated
by an external voltage. Active research is being conducted on hybrid phase transition
devices because of their potential to pave the way for more powerful computer and
memory technologies. However, their intricacy also creates difficulties in analyzing
their actions and improving their efficiency.

Circuits Using Hyper-FETs

A hyper-thin metal-oxide-semiconductor field-effect transistor (MOSFET) is used in

hyper-FET (HFET) circuits to achieve high-speed and high-frequency performance.
To facilitate rapid switching and high-frequency operation, HFETs have a channel
length of the order of tens of nanometers or less. In addition, they function well
at low voltages that makes them applicable to a wide variety of low-power uses.
Radiofrequency (RF) amplifiers, mixers, and oscillators are only some of the many
applications for high-frequency HFET circuits. They are also utilized in memory
and clock distribution networks found in high-speed digital circuitry. To boost the
efficiency of digital circuits, the hyper-FET field-effect transistor (FET) has been
proposed. Hyper-FET circuits takes an advantage of a redesigned FET structure to
256 A. Choubey et al.

cut down on power consumption and increase switching speeds (Goodwill et al.
2019).
The current flow between the source and drain terminals of a conventional FET is
regulated by the gate voltage. However, with a Hyper-FET, the effective resistance
of the channel between the source and drain is also affected by the gate voltage.
This allows the Hyper-FET to turn on and off more quickly than a standard FET
while consuming less energy. Digital circuits such as logic gates, memory cells,
and other forms of digital logics can all make use of hyper-FETs. Hyper-FETs’
with increased efficiency and speed in digital circuits have the potential uses in
fields like high-speed computing and telecommunications. However, hyper-FETs
are still a developing technology, and there are obstacles to overcome to put them
into practice. Hyper-FETs, for instance, can be more expensive to create since their
fabrication process is more sophisticated than that of conventional FETs. More-
over, Hyper-FETs’ performance can be impacted by variances in the manufacturing
process making it challenging to mass-produce devices with consistent performance
(Polozov et al. 2020).
While Hyper-FETs have the potential to significantly boost the efficiency of digital
circuits, they nevertheless face several obstacles before they become the industry
standard. The ability to operate at high frequencies with low-power consumption
is a major benefit of HFET circuits. Because of this, mobile devices and wireless
communication systems can benefit greatly from their utilization. When it comes
to obtaining high-speed, high-frequency performance in a wide range of electronic
applications is crucial.

Metal–Insulator Transitions and Their Varieties

Transitions from one type of material to another such as metal to insulator or insulator
to metal are known as metal–insulator transitions (MITs). Multiple MIT varieties
have been identified in a wide range of materials. Some instances are as follows:
1. In materials having partially full electron bands and high electron correlations,
a phase transition known as a Mott transition can take place. When the electrons
become more localized due to changes in temperature or other environmental
variables, the material changes from metallic to insulating state.
2. When the disorder in a material becomes severe enough to confine electrons in
localized states, a phenomenon known as Anderson localization develops. This
causes the electrons to get trapped that changes the material’s properties from
metallic to insulating.
3. When electrons in a material undergo a charge density wave (CDW) transition,
the electrons rearrange themselves in a periodic pattern that distorts the crystal
lattice. The CDW can either strengthen or weaken as a function of temperature or
other environmental conditions causing the material to transform from metallic
to insulating state.
10 The Device-Circuit Co-design Perspective on Phase-Transition … 257

4. Spin density wave (SDW) transition occurs when electrons in a material acquire
a periodic magnetic moment. The SDW can go from being strong to weak
causing a shift in phase from metallic to insulating as the temperature or other
environmental conditions are altered.
Some of the many varieties of MITs observed in different materials are listed
above. Depending on the material and environmental conditions, the precise process
behind each type of MIT can differ. To create new materials with desirable electrical
properties for various applications such as electronics and energy storage, it is crucial
to get a deeper understanding of these transitions (Vu et al. 2020).

Anderson’s Localization

When waves (such as electrons or photons) become confined or localized in a disor-

dered system rather than traveling through the system as a whole, a phenomenon
known as Anderson localization occurs. This happens when there is so much chaos
in the system that waves can’t propagate across it without being scattered or absorbed.
Philip W. Anderson, a scientist, coined the term for this occurrence in 1958.
Electronic transport in disordered solids, optical transmission in photonic crystals,
and acoustic waves in random media are all examples of physical systems in which
Anderson localization has been seen. In insulation state where no waves may prop-
agate through the system is a possible outcome of Anderson localization. Due to
the consequences of the disorder, this can happen even in systems that are generally
thought to be conductive or transparent. This has serious ramifications for the effi-
ciency and performance of systems that rely on wave propagation such as electronic
equipment. The study of Anderson localization and its potential applications is a
vibrant topic of condensed matter physics. Localized waves have interesting quali-
ties that could be put to use in the development of new electrical and optical devices
(Xiang et al. 2020).

Peierls’ Phase Change

Condensed matter physicists see the Peierls transition when distortion of a one-
dimensional crystal leads to a periodic modulation of the atomic locations along
the crystal axis. The interaction between the crystal’s electrical and lattice degrees
of freedom causes this phase change. In 1955, Rudolf Peierls postulated the Peierls
transition as a mechanism to explain the dramatic drop in electrical conductivity seen
in certain materials such as metals when cooled to very low temperatures. Peierls
demonstrated that the creation of a charge density wave as a result of the distortion
of the crystal lattice might account for the observed drop in conductivity.
258 A. Choubey et al.

One-dimensional systems like polyacetylene and inorganic materials like TaS3 and
NbSe3 have been seen to undergo the Peierls transition. Changing the environment’s
temperature, pressure, or doping can all trigger the changeover.
Important consequences for material characteristics are associated with the Peierls
transition. For instance, a material’s electrical conductivity can drop, its resistivity
can rise, and its magnetic and thermal properties can shift due to the creation of a
charge density wave. The electrical and mechanical properties of carbon nanotubes
and other one-dimensional structures can be affected by the Peierls transition that
plays a significant role in the physics of these structures. The Peierls transition has
far-reaching consequences for the properties and uses of one-dimensional materials
making it a key concept in the field of condensed matter physics (Wu et al. 2021).

Mott’s Phase Change

In condensed matter physics, the Mott transition describes the phase change from
metal to insulator caused by strong electron–electron interactions. Sir Nevill Mott
who originally documented this change in 1949 gets the credit for naming it after
himself. When a material’s electrons are in a metallic state, they can move freely and
the material can conduct electricity. However, in some materials, the electrons might
become localized due to the strong interactions between them and so trapped. This
can cause the material to take on the properties of an insulator rendering it highly
resistant to the flow of electricity.
When the energy barrier associated with electron hopping between neighboring
sites is overcome by the intensity of the electron–electron interactions, the Mott
transition takes place. This can happen when the environment undergoes a shift in
temperature, pressure, or doping.
Important consequences for material characteristics are associated with the Mott
transition. The material’s magnetic, thermal, and transport properties may all be
affected. The transition has close ties to the phenomenon of high-temperature super-
conductivity making it significant in the physics of high-temperature superconduc-
tors. The Mott transition is a fundamental idea in condensed matter physics with
far-reaching consequences for how materials behave and their potential uses in
electronics and other technologies (Zhang et al. 2021).

MOSFET’s Scaling Limits and Device Parameters

Metal–oxide–semiconductor field-effect transistors (MOSFETs) are ubiquitous in

modern electronics including central processing units (CPUs), memory chips, and
power amplifiers. A gate, source, and drain make up the device with the gate sitting
on an insulating layer above the channel. The current across the channel of a
MOSFET is regulated by the gate voltage making it a voltage-controlled switch.
10 The Device-Circuit Co-design Perspective on Phase-Transition … 259

The threshold voltage, gate capacitance, and channel length are three of the most
important device factors that affect a MOSFET’s performance. The device’s speed,
power consumption, and dependability are all heavily dependent on these values.
However, when device dimensions decrease, scaling limitations start to become
apparent. These restrictions on MOSFETs are typically associated with the device’s
physical dimensions and the rising power density that results from the device’s minia-
turization. Smaller devices have shorter channels and smaller gate capacitances
allows faster switching at reduced power costs. However, the performance of the
device is limited by quantum mechanical processes like tunneling and short channel
effects when the channel length approaches the limit of a few nanometers.
To get over these scaling barriers, scientists are looking into novel device topolo-
gies and materials for constructing state-of-the-art MOSFETs. Germanium and III-V
semiconductors are two examples of novel materials being researched for their poten-
tial to replace silicon in the future MOSFETs. There are alternatives to conventional
planar MOSFETs that may provide a better performance, such as nanowire and
FinFET architectures. Some of the most important factors in a MOSFET’s perfor-
mance are its device parameters such as its threshold voltage, gate capacitance, and
channel length. To keep up with the high rate of technical progress in modern elec-
tronic devices, scaling restrictions relating to quantum effects and power density will
need to be overcome as device dimensions continue to reduce (Goh and Jeon 2018).

Anderson and Pierels Insulators Field Effect

Due to the scattering of electrons by randomly located impurities or defects, elec-

tronic transport in Anderson insulators is controlled by the Anderson localization
effect. This localization effect causes electrons to become confined to discrete parts
of the material where they are unable to conduct electricity. Because of this, the mate-
rial exhibits insulating properties and high electrical resistance. A periodic modifi-
cation of the crystal lattice which is often due to the development of a charge density
wave that gives rise to the insulating behavior seen in Peierls insulators. When the
electronic band structure of a material is modulated in this way, a band gap forms
blocking the flow of electrons as a current. The occupied states in the valence band
are effectively separated from the unoccupied states in the conduction band by the
band gap. Therefore, the material acts as an insulator since a voltage placed across
it does not result in a flow of electrons.
The field effect that describes the regulation of electronic characteristics by an
external electric field controls the electronic transport in both classes of insula-
tors. The localization length is the characteristic length scale across which electrons
become trapped due to Anderson localization in Anderson insulators, and it can be
altered by an electric field. The electronic transport characteristics and localization
length of a material can be manipulated by changing the electric field applied to it.
The electronic transport properties of Peierls insulators can be altered by an electric
field by modulating their band gap or charge density waves. The insulating properties
260 A. Choubey et al.

of a Peierls insulator can be adjusted by changing the size of the band gap using a
gate voltage. As a whole, the field effect provides a potent tool for manipulating the
electronic characteristics of Anderson and Peierls insulators opening the door to the
creation of novel materials with tunable electronic transport properties for use in a
variety of electronics and energy-related applications (Paoletta and Demkov 2021).

Anderson Insulators and the Field Effect

Due to the scattering of electrons by randomly located impurities or defects, elec-

tronic transport in Anderson insulators is controlled by the Anderson localization
effect. This localization effect causes electrons to become confined to discrete parts
of the material where they are unable to conduct electricity. However, the field effect
allows the electrical properties of Anderson insulators to be altered by applying an
external electric field. The Anderson localization length, the characteristic length
scale across which electrons become trapped can be altered by an external electric
field. The electronic transport characteristics and localization length of a material
can be manipulated by changing the electric field applied to it.
The Anderson insulator is often sandwiched between two metal electrodes in a
metal-insulator-metal (MIM) configuration to investigate the field effect in Anderson
insulators. By applying a voltage to the metal electrodes, an electric field is created
across the insulating layer and the device’s current–voltage properties can be deter-
mined. To facilitate electron tunneling through the Anderson insulator and into the
metal electrodes, an electric field shortens the localization length of the insulator.
As a result, the device’s current–voltage characteristics shift allowing researchers
to better examine the field effect in Anderson insulators. New materials for elec-
tronic and energy applications could be greatly aided by understanding the field
effect in Anderson insulators. The electrical transport capabilities of a material can
be controlled by modifying the localization length using an electric field paving the
way for the creation of novel materials with purpose-built characteristics.

Gate-Like Behavior in Peierls Insulators

When compared to Anderson insulators, Peierls insulators have a unique form of

insulating behavior and the gating effect allows for the electronic properties to be
controlled by an external electric field. The insulating behavior of Peierls insulators
is due to a periodic modulation of the crystal lattice which is normally brought about
by the production of a charge density wave. When the electronic band structure of a
material is modulated in this way, a band gap forms blocking the flow of electrons
as a current. The occupied states in the valence band are effectively separated from
the unoccupied states in the conduction band by the band gap.
10 The Device-Circuit Co-design Perspective on Phase-Transition … 261

A metal–insulator-semiconductor (MIS) configuration can be used to investigate

the gating effect in Peierls insulators by placing the insulator in the middle of a metal
electrode and a semiconductor layer. The band gap size and charge density wave
modulation of a Peierls insulator can be altered by providing a voltage to the metal
electrode creating an electric field across the insulating layer. By altering the potential
energy landscape of the material, the electric field can efficiently move the energy
levels of the valence and conduction bands hence altering the magnitude of the band
gap. When the electric field is high enough, the band gap narrows and electrons can
flow freely between the metal electrode and the semiconductor layer.
New materials for electronic and energy applications may be greatly aided by
understanding the gating effect in Peierls insulators. Controlling the insulating
behavior and modulating the electronic transport qualities can be achieved by control-
ling the band gap size and the charge density wave modulation via the application
of an electric field. This has the potential to pave the way for the creation of new
materials with purpose-built characteristics such as those used in high-performance
electrical devices or energy harvesting (Han and Orshansky 2013).

Theory of the Mott Field Effect Transistor

An electronic device called a Mott field-effect transistor (FET) employs the Mott
transition to regulate the current passing through a material. In the Mott transition,
the electronic structure of a material undergoes a change that causes the substance
to go from an insulating to a metallic phase. The material in a Mott FET is typically
a transition metal oxide with a tightly correlated electron system that experiences a
Mott transition as a result of a change in an external parameter. A thin insulating layer
such as silicon dioxide separates the gate electrode from the material in a field-effect
transistor (FET) structure.
The electrical characteristics of a material can be altered by applying a voltage to
the gate electrode creating an electric field across the insulating layer. In particular,
the fermi level can be moved within a material due to the electric field inducing a
change in the energy levels of the electrons. The material undergoes a Mott tran-
sition from an insulating to a metallic state when the fermi level crosses the Mott
gap allowing electrons to flow as a current. The Mott FET is useful in low-power
logic circuits, high-speed electronic devices, and more. It can even function at room
temperature. Understanding the intricate electrical properties of strongly correlated
electron systems is difficult and the theoretical description of the Mott FET is still
an active area of research (Bahmani et al. 2020).
262 A. Choubey et al.

Mechanism for Operation

By applying an external electric field through the gate electrode, a Mott FET can
manipulate the electrical characteristics of a tightly correlated electron system. An
electric field controls the flow of electrons in a Mott FET making it a form of field-
effect transistor. Between two metal electrodes and an insulating layer separating it
from a gate electrode is where the Mott FET’s strongly correlated electron material,
like a transition metal oxide, is located. The electrical characteristics of a material
can be altered by applying a voltage to the gate electrode, creating an electric field
across the insulating layer.
The Mott gap is the energy difference between the valence band and the conduction
band in strongly correlated electron materials. Strong Coulomb repulsion between
electrons in the material causes the Mott gap because the electrons are prevented
from freely migrating and the material is in an insulating condition. When the gate
voltage is raised, an electric field is created across the insulating layer causing the
electrons within the material to change energy levels. The material undergoes a Mott
transition from an insulating to a metallic state when the gate voltage hits a critical
value causing the fermi level to cross the Mott gap. As a result, an electric current
can flow through the material turning the device on.
The Mott FET can be toggled between its conducting “on” state and it is insulating
“off” state (where no current flows through the device) by adjusting the gate voltage.
Because of this, low-power logic circuits and other high-speed electronic devices can
be created using the Mott FET as a switch. In conclusion, the electronic properties
of a tightly correlated electron system are manipulated by an external electric field
generated by a gate electrode in a Mott FET’s operating mechanism. The Mott FET
may control the current through the device and function as a switch in electrical
circuits by producing a Mott transition in the material (Abrar et al. 2022).

Length of Screening

The electrical characteristics of the strongly correlated electron material in a Mott

FET are influenced by the electric field created by the gate electrode over a distance
called the screening length. The performance of a Mott FET is significantly impacted
by the screening length which influences how much the gate voltage can alter the
material’s electrical characteristics and trigger a Mott transition.
The screening length of a Mott FET is determined by the Mott gap, the carrier
density of the material, and the dielectric constant of the insulating layer. A material’s
carrier density dictates how quickly charge carriers can redistribute in response to an
external electric field, while the dielectric constant of the insulating layer controls
the degree to which the electric field created by the gate voltage is screened. In
a typical Mott FET, the screening length is only a few nanometers at most. The
electric field cannot travel very far into the material because of the strong Coulomb
10 The Device-Circuit Co-design Perspective on Phase-Transition … 263

repulsion between the electrons. Therefore, to induce a Mott transition and adjust
the material’s electrical characteristics, the gate electrode must be placed very close
to the material. Recent studies have focused on increasing the screening length of
Mott FETs by manipulating the electrical characteristics of the strongly correlated
electron material and optimizing the gate insulator material and thickness. Increases
in screening length can boost device performance and pave the way for innovative
uses of Mott FETs in electronics.

Behavior Below the Threshold

When the gate voltage of a Mott FET is less than the threshold voltage, the voltage
needed to cause a Mott transition in the strongly correlated with electron material and,
the transistor exhibits subthreshold behavior. The Mott FET operates like a standard
field-effect transistor below its threshold voltage with the gate voltage regulating the
flow of electrons through the material. In the off state of a Mott FET where the gate
voltage is less than the threshold voltage, no current flows through the device. The
channel conductance rises as the gate voltage rises because the electrical character-
istics of the material are gradually changed. The following equation describes the
Mott FET’s subthreshold behavior.

ID = I0 × exp[(VG − VT )/nVT ] (10.1)

The subthreshold slope factor n is defined as follows: where I D is the drain current,
I 0 is a constant, V G is the gate voltage, V T is the thermal voltage, and n is the
subthreshold voltage. An essential parameter that controls how steep the transistor’s
behavior is in the subthreshold region is the subthreshold slope factor n. The density of
states and the Coulomb interaction between electrons in a Mott FET are responsible
for the subthreshold slope factor. Because of the strong Coulomb contact between
electrons, Mott FETs often have a larger subthreshold slope factor than traditional
field-effect transistors. Mott FETs are useful in low-power electronics because of
their subthreshold behavior that allows them to function at low voltages and currents.
Power consumption in electronic circuits can be decreased and energy efficiency
increased by fine-tuning the Mott FET’s subthreshold behavior.

Properties of the Interface

The performance of a Mott FET relies heavily on the interface parameters between
the gate dielectric and the strongly correlated electron material. Several device char-
acteristics including threshold voltage, subthreshold slope, and gate leakage current
are sensitive to interface quality. The creation of a high-quality interface between the
gate dielectric and the strongly correlated electron material is a significant difficulty
264 A. Choubey et al.

in the construction of Mott FETs. This is because it is challenging to create good

electrical contact with the gate dielectric when using strongly correlated electron
materials as these materials are often insulators or semiconductors with a significant
band gap. Researchers have devised a variety of methods for designing the interface
properties of Mott FETs to help with this problem. The gate dielectric can be made
from thin sheets of high-dielectric-constant dielectric materials like hafnium oxide or
zirconium oxide. To effectively modulate the electrical characteristics of the strongly
correlated electron material, these can provide a high capacitance per unit area.
One alternative is to alter the strongly correlated electron material itself by doping
or alloying it to change its electronic characteristics. This can boost the device’s inter-
face qualities by enhancing the contact between the material and the gate dielectric.
Surface properties of the material and the gate dielectric such as surface roughness
and chemical composition must be controlled in addition to the choice of the gate
dielectric and material engineering. As a result, the gate leakage current can be
reduced and the density of interface states can be lowered (Alam et al. 2021).
The overall performance of a Mott FET is heavily dependent on the interface
parameters between the gate dielectric and the strongly correlated electron material.
High-performance, low-power, and reliable Mott FETs can be built by focusing on
the interface.

Mott FET Experiments

The features and performance of Mott FETs have been the focus of extensive study
in recent years with several experimental investigations examining various aspects of
these devices. Some case studies of experiments involving Mott FETs are as follows:
1. One of the most difficult aspects of making Mott FETs is creating a good inter-
face between the gate dielectric and the strongly correlated electron material. To
overcome this difficulty, scientists have come up with several solutions including
the use of high-dielectric-constant gate dielectrics, surface treatments, and mate-
rial engineering strategies. Pulsed laser deposition, sputtering, and molecular
beam epitaxy are just a few examples of the state-of-the-art deposition processes
generally used in the manufacture of Mott FETs.
2. The threshold voltage of a Mott FET is a function of the Mott transition and
the gate voltage both of which can be tuned. Researchers have shown that a
Mott FET’s threshold voltage may be adjusted by manipulating the device’s gate
voltage, the operating temperature, or the doping concentration. Researchers have
demonstrated that the threshold voltage of vanadium dioxide (VO2 ) Mott FETs
may be changed by a factor of more than 10 by adjusting the gate voltage.
3. An essential parameter for low-power electronics is the subthreshold behavior of
a Mott FET. Due to the strong Coulomb contact between electrons, experimental
studies have revealed that the subthreshold slope factor of a Mott FET is often
greater than that of a normal field-effect transistor. Using high-dielectric-constant
10 The Device-Circuit Co-design Perspective on Phase-Transition … 265

gate dielectrics or manipulating the device’s interface properties have both been
shown to increase the subthreshold slope.
4. Due to their unusual electrical features, Mott FETs can function at very high
frequencies. High transconductance and low output capacitance have been seen in
experimental studies of Mott FETs operating at a frequency of several gigahertz.
Optimizing the device structure and interface properties is essential for high-
frequency performance in Mott FETs.
Experiments on Mott FETs have shown that they can be used in low-power
and high-performance circuits. However, further study is required to improve their
performance and dependability and to create commercially viable mass-produced
fabrication methods.

MOSFET with a Solid-Dielectric Gate

When the gate dielectric is a solid insulator like silicon dioxide or hafnium oxide, the
resulting device is called a solid dielectric gated Mott FET. For low-power applica-
tions like portable electronics and sensors, a solid dielectric gate is used in a Mott FET
to provide precise control of the gate voltage. The fundamental difference between a
regular MOSFET and a solid dielectric gated Mott FET is the type of channel mate-
rial, although the basic functionality is the same. The channel material in a Mott FET
is a transition metal oxide or other strongly correlated electron material that under-
goes a Mott-insulating phase transition over a threshold gate voltage. This phase
transition causes an abrupt alteration in the electrical conductivity of the material
allowing the device to toggle between its active and inactive states.
Material qualities of the channel material, quality of the interface between the
channel material and the gate dielectric, and device structure design are only a few
of the elements that affect the performance of a solid dielectric gated Mott FET.
Utilizing high-dielectric-constant gate dielectrics, engineering the device’s interface
properties, and producing the channel material with high quality and purity are only
some of the methods used by researchers to obtain high-performance Mott FETs. A
solid dielectric gate in a Mott FET allows for low-voltage operation which in turn
reduces power consumption and boosts the device’s energy efficiency. The use of a
solid dielectric gate permits the construction of devices with very small dimensions
which opens up the possibility of scaling.
Low-power electronics and sensing applications stand to benefit greatly from
the use of solid dielectric gated Mott FETs. The Mott transition and low-voltage
operation are just two of the special features that set it apart from regular MOSFETs.
However, more study is required to improve the device’s efficiency and dependability
as well as to create mass-production-ready fabrication methods.
266 A. Choubey et al.

FET with Correlated Oxides

The field-effect transistor (FET) known as a correlated oxide FET employs a channel
material composed of strongly correlated electrons. Correlated oxide FETs use mate-
rials with strong electron–electron interactions, such as transition metal oxides which
exhibit several interesting physical properties including high-temperature supercon-
ductivity and enormous magnetoresistance in contrast to conventional FETs that uses
semiconductors like silicon or gallium arsenide.
Correlated oxide field-effect transistors (FETs) function on the principle of the
Mott transition that occurs when a strongly correlated electron material changes phase
from insulator to metal when subjected to a threshold gate voltage. The electric
field of the gate causes a redistribution of electrons in the material leading to the
development of a conductive channel that facilitates the phase transition. Use of
correlated oxide materials in FETs has some benefits, one of which is the possibility
of high mobility that can result in excellent device performance. Furthermore, these
materials can display a range of intriguing physical features including magnetism
and superconductivity that may find value in fields like spintronics and quantum
computing.
However, there are also certain obstacles associated with the use of correlated
oxide materials in FETs. The characteristics of such materials are generally highly
susceptible to impurities and flaws making their synthesis and processing chal-
lenging. The performance and dependability of the devices may also be impacted
by the Mott transition’s side effects such as heating and instability. Despite of these
obstacles, great progress has been achieved in the development of high-performance
and reliably correlated oxide field-effect transistors (FETs). Researchers have
demonstrated correlated oxide FETs with high mobility and low-power consump-
tion suggesting that these devices have great potential for future electronics and
computing applications.

Organic Mott FET

Field-effect transistors (FETs) that use organic materials as channel materials and
function via the Mott transition are known as organic Mott FETs. Most organic Mott
FETs use polymers or tiny molecules with strong electron–electron interactions as the
organic materials. A critical voltage applied to the gate induces a transition from an
insulating to a metallic state in organic material similar to the operation mechanism
of a typical Mott FET. However, the organic material’s unique features can affect
behavior and performance in ways that are distinct from those of traditional inorganic
Mott FETs.
Since organic materials may be produced using simple processes like spin-coating
or inkjet printing, organic Mott FETs provide the promise of low-cost and flex-
ible device construction. Also, organic materials can show great carrier mobility
10 The Device-Circuit Co-design Perspective on Phase-Transition … 267

which makes them interesting as potential components in high-performance elec-

trical systems. Low stability and dependability are problems that organic Mott FETs
have to deal with because organic materials are so vulnerable to environmental condi-
tions like temperature and humidity. Device performance can also vary because
organic material properties are highly context-dependent. Despite these obstacles,
great progress has been achieved in the development of high-performance and stable
organic Mott FETs. The potential of organic Mott FETs in the future electronic and
computer applications is still being investigated with researchers optimizing mate-
rials and device architectures and creating novel processing and characterization
techniques for organic materials (Xia et al. 2018).

MOSFETs Gated by Ionic Liquids

To generate a Mott transition in the channel material, ionic liquid-gated Mott FETs
use an ionic liquid as the gate dielectric. At zero gate voltage, the channel material
is often a strongly correlated electron material like a transition metal oxide. Instead
of using a solid dielectric like silicon dioxide for the gate in a conventional Mott
FET, an ionic liquid is utilized. The insulating channel material undergoes a phase
transition from the insulating to the metallic state when the ionic liquid is brought
into contact with it and a gate voltage is provided.
Compared to more conventional solid dielectrics, ionic liquid gate dielectrics
have several benefits. Due to their strong ionic conductivity, ionic liquids can be
used for effective channel gating at low voltages. Ionic liquids are well-suited for use
in electronic devices because they may be engineered to have desirable chemical and
physical properties such as high stability and low viscosity. High on/off current ratios
and low subthreshold swings are just two of the intriguing performance properties
of ionic liquid-gated Mott FETs making them good candidates for application in
low-power electronics and sensors. However, there are still obstacles to overcome
in the advancement of these devices such as the optimization of the ionic liquid
characteristics and the decrease of device variability caused by the Mott transition’s
sensitivity to impurities and defects in the channel material.

Mechanism for Gating

The electrons in the channel material of an ionic liquid-gated Mott FET are redis-
tributed when a gate voltage is delivered through the ionic liquid which is the gating
mechanism. The ionic liquid acts as a gate dielectric, collecting charge carriers at
the channel/dielectric contact. The gate voltage can cause a Mott transition in a Mott
insulator channel material by altering the occupied of the d orbitals. Strong electron–
electron interactions lead to a partially filled band with localized electrons at zero gate
voltage in a Mott insulator. The electrons in the partially filled band are redistributed
268 A. Choubey et al.

when a gate voltage is applied due to the accumulation of charge carriers in the ionic
liquid at the interface with the channel material. The electrons may become less
tightly bound resulting in a change to a metallic phase. Because of the ionic liquid’s
strong ionic conductivity and its ability to accumulate charge carriers immediately at
the interface with the channel material, the gating mechanism in ionic liquid-gated
Mott FETs is very effective. Inducing the Mott transition typically requires a small
gate voltage that can enhance device efficiency and reduce power consumption.
However, impurities and flaws in the channel material might influence the effi-
ciency and stability of the Mott transition that can be a problem for ionic liquid-gated
Mott FETs. To enhance the efficiency and dependability of these gadgets, scientists
are attempting to fine-tune both the channel material and the ionic liquid’s qualities.
When doing experiments with a field-effect transistor (FET), an ionic liquid is
used as the gate dielectric. When a gate voltage is supplied via the ionic liquid, the
conductivity of the channel material is altered. The channel material in these studies
is commonly a transition metal oxide, which exhibits a Mott-insulating phase at zero
gate voltage since its electrons are tightly correlated. A Mott transition is induced in
the channel material when an ionic liquid is brought into contact with it and a gate
voltage is applied. The high on/off current ratios and minimal subthreshold swings
demonstrated by ionic liquid-gated FET devices suggest their potential utility in
low-power electronics and sensors. Experiments that make use of ionic liquid-gated
FETs include, but are not limited to:
1. Mott transitions in transition metal oxides have been studied using ionic liquid-
gated field effect transistors (FETs). These oxides include V2 O5 , MoO3 , and
TiO2 .
2. Researchers are striving to create novel ionic liquid gate dielectrics with desirable
qualities including high stability and low viscosity to enhance the functionality
of ionic liquid-gated field effect transistors (FETs). Research in this area focuses
on the creation and characterization of novel ionic liquids for use in FET devices.
3. Controlling the characteristics of the channel material and the ionic liquid gate
dielectric, scientists are attempting to improve the performance of ionic liquid-
gated FET devices. Characterizing the on/off current ratio, subthreshold swing,
and gate leakage current are all part of these investigations as it is optimizing
device settings for maximum efficiency. When it comes to investigating Mott
insulators and creating novel electrical devices with enhanced performance
characteristics, ionic liquid-gated FET studies offer a viable method.

Mott Transistors with Alternative Gate Architectures

Traditional Mott FETs use an ionic liquid gate although different gate designs are
possible. Some examples of non-traditional gate architectures that have been studied
are:
1. For MIS gates, a metal gate is used with an insulating layer separating it from the
Mott insulator channel. The conductivity of the channel material is altered when a
10 The Device-Circuit Co-design Perspective on Phase-Transition … 269

voltage is given to the metal gate inducing a charge in the insulating layer. Using
other insulating layers, including hafnium dioxide, MIS gate Mott transistors
have been studied and have shown promising performance characteristics.
2. The use of a solid electrolyte substance as the gate dielectric characterizes solid-
state electrolyte gates. The channel material’s conductivity is altered by the appli-
cation of the gate voltage through the solid electrolyte. High on/off current ratios
and low subthreshold swings have been seen in solid-state electrolyte gate Mott
transistors fabricated from a variety of solid electrolyte materials such as lithium
lanthanum titanate.
3. For graphene gates, the graphene sheet itself serves as the gate electrode.
Bypassing the gate voltage through the graphene layer, the channel material’s
conductivity can be altered. Research into graphene gate Mott transistors using
several types of graphene, such as graphene oxide has yielded encouraging
results.
4. In the case of ferroelectric gates, the gate dielectric is itself ferroelectric. The
channel material’s conductivity is altered as a result of the gate voltage being
delivered via the ferroelectric material creating a polarization charge in the ferro-
electric. High on/off current ratios and low subthreshold swings have been seen
in ferroelectric gate Mott transistors fabricated from a variety of ferroelectric
materials, including lead zirconate titanate.
Overall, experimenting with different gate designs is a potential route toward
creating Mott transistors with enhanced performance characteristics and tunable
attributes.

Mott Transistor with Heterojunction Modulation

To improve performance, a specific type of Mott transistor known as a hetero-

junction modulation-doped Mott transistor (HMDMT) uses a hetero-junction struc-
ture. An HMDMT is characterized by the presence of a hetero-junction at the inter-
face between the Mott insulator and two other layers of material. To increase carrier
mobility and decrease scattering, a modulation-doped structure is created by strongly
doping one of the layers with impurities. HMDMTs have improved channel conduc-
tance control over conventional Mott transistors. This is accomplished by controlling
the conductance of the Mott insulator channel via the gate voltage that in turn controls
the carrier density in the strongly doped layer adjacent to the Mott insulator. Modu-
lation doping can also shorten the screening length which in turn can enhance the
device’s subthreshold behavior.
Several material mixtures for HMDMTs have been studied including SrTiO3 /
LaAlO3 , LaAlO3 /SrTiO3 , and NdAlO3 /SrTiO3 . These devices have shown encour-
aging performance features including reduced subthreshold swings, strong gate
control, and high on/off current ratios. HMDMTs may find use in fields like quantum
computers, sensors, and low-power devices.
270 A. Choubey et al.

Conclusion

In this chapter discusses the distinct roles that various types of FETs will play in
future integrated circuits, as well as their synergy. Additionally, it addresses the
coexistence of these novel transistors with traditional MOSFETs, offering insights
into the opportunities and challenges facing the rapidly evolving semiconductor
industry.

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Chapter 11
Feedback Field-Effect Transistors/Zero
Subthreshold Swing and Zero Impact
Ionization FET

Rapolu Anil Kumar, Kondavitee Girija Sravani, Karumuri Srinivasa Rao,

and Aime Lay-Ekuakille

Abstract Feedback Field-Effect Transistors (FBFETs) function through a positive

feedback loop, where electrons and holes in the channel region impact the energy
states of the potential barrier and wall. This positive feedback mechanism results in
notable characteristics for FBFETs, including an impressive subthreshold swing of
approximately 0 mV/decade at 300 K, a high on-/off-current ratio of around 10^10,
and a well-defined saturation region. The power consumption in both the turn-on and
turn-off states remains remarkably low until the device is actively operating. Further-
more, the hysteresis induced by carriers accumulated in the potential wall allows
FBFETs to serve as memory devices. Additionally, FBFETs exhibit the potential to
significantly reduce power consumption in neuromorphic devices, by approximately
100 times. This study delves into the analysis of the FBFET’s device structure and
operational principles, providing a comprehensive overview of its applications.

Keywords Positive feedback loop · Highly responsive switching device ·

Feedback field-effect transistor · Low-power applications · Neuromorphic
computing · Integrate-and-fire paradigm

R. A. Kumar · K. Girija Sravani (B) · K. Srinivasa Rao

Department of ECE, VLSI-Microelectronics Research Center, KL University, Vaddeswaram,
Guntur, Andhra Pradesh 522502, India
e-mail: [email protected]
A. Lay-Ekuakille
Department of Innovation Engineering, University of Salento, Via Monteroni, Ed “Corpo O”,
73100 Lecce, Italy

© The Author(s), under exclusive license to Springer Nature Singapore Pte Ltd. 2024 273
S. Singh et al. (eds.), Beyond Si-Based CMOS Devices, Springer Tracts in Electrical and
Electronics Engineering, https://doi.org/10.1007/978-981-97-4623-1_11
274 R. A. Kumar et al.

Introduction

A specific kind of Field-Effect Transistors (FETs) called feedback field-effect tran-

sistors (Feedback FETs) has been developed and improved for use in control systems
and feedback loop applications. These transistors are essential parts of many elec-
tronic circuits and systems because of their design, which makes it easier to precisely
control and regulate electrical signals (Lee et al. 2020). By modulating the flow of
charge carriers between the source and drain terminals with a voltage applied to the
gate terminal, feedback FETs take use of the core concepts of FET functioning. But
what really distinguishes feedback FETs is their smooth integration into feedback
loops, offering useful characteristics like minimal distortion, excellent linearity, and
steady amplification.
Electronic circuits using feedback FETs may be used to build precise signal manip-
ulation applications such as oscillators, filters, closed-loop control systems, auto-
matic gain control (AGC), and others. When preserving signal precision, stability,
and predictability is crucial, these transistors are very useful. In this investigation
of feedback FETs, we will examine their fundamental working principles, different
kinds and configurations, and the diverse range of applications in which they are
highly effective. Gaining a grasp of feedback FETs will help us to create complex
electrical systems that can function consistently and precisely in a variety of engi-
neering and technological domains (Wan et al. 2012a). Subthreshold Swing (SS) at
Zero and Ionization Field-Effect Transistor (FET) with Zero Impact are two important
concepts in the field of semiconductor devices and transistor technology.

(i) Zero Subthreshold Swing (SS):

A critical factor in transistor functioning, particularly in low-power electronics

and digital circuits, is subthreshold swing (SS). The efficiency with which a tran-
sistor transitions between its on and off states when the voltage across the gate is
below the threshold (Vth) is measured (Wan et al. 2013a). It is preferable to have
a lower subthreshold swing since it enables more effective functioning and lower
power consumption. It is difficult to get an estimated subthreshold swing in typical
MOSFETs close to the theoretical limit, which is 60 mV per decade at room tempera-
ture. Subthreshold leakage current and other variables usually cause the subthreshold
swing to rise when the gate’s voltage drops below the cutoff.

(ii) Zero Impact Ionization FET (ZI-FET):

A specific kind of FET called the Ionization Field-Effect Transistor with Zero Impact
was created to solve the problem of subthreshold swing and enhance energy efficiency
in electronic equipment. The goal is to attain a subthreshold swing near the theoret-
ical limit of 60 mV/decade, which would allow for extremely effective low-power
operation (Tang et al. 2002).In order to limit the effects of impact ionization—a
phenomenon in which charge carriers in semiconductor materials collect enough
energy to form electron–hole pairs—ZI-FETs include novel materials and structural
11 Feedback Field-Effect Transistors/Zero Subthreshold Swing and Zero … 275

designs. In conventional MOSFETs, impact ionization causes poor subthreshold

swing and higher subthreshold leakage.
To reduce impact ionization, ZI-FETs may employ materials such as new
heterostructures or III-V compound semiconductors (Chandrasekaran et al. 2007).
Due to their increased electron mobility and ability to mitigate the negative effects of
impact ionization, these materials exhibit reduced subthreshold swing and enhanced
energy efficiency. ZI-FETs have great potential for use in low-power electronics,
such as Internet of Things (IoT) devices and smartphones, where cutting down on
power consumption is essential for increasing battery life and boosting overall effi-
ciency. Zero Impact Ionization Field-Effect Transistors (ZI-FETs) are a specialized
class of transistors designed to achieve low subthreshold swing and improve energy
efficiency by minimizing impact ionization effects through creative materials and
structures. Zero Subthreshold Swing (SS) is a critical parameter in transistor perfor-
mance. Future electronic device development will not be possible without these
technologies (Colinge and Lee 2014).

Fb-FET Structure and Operating Principle

A variant of the conventional Field-Effect Transistor (FET) called the Field-Effect

Transistor with Back Gate (Fb-FET) adds a second gate, sometimes referred to as
the back gate or back electrode. This arrangement is frequently seen in cutting-edge
semiconductor devices, such as integrated circuits and sensors, for a variety of uses.
In some situations, the back gate improves performance and provides more control
over the properties of the transistor (Lee and Colinge 2013).

Structure of a Standard FET

(i) Substrate: The semiconductor material, often silicon, serves as the foundation
for the Fb-FET.
(ii) Front Gate (Gate 1 or G1): The front gate is the primary electrode of gate
located on the semiconductor’s upper surface. It is isolated by a thin insulating
layer, usually silicon dioxide (SiO2 ), from the semiconductor channel.
(iii) Back Gate (Gate 2 or G2): The back gate is an additional gate electrode located
on the bottom or backside of the semiconductor substrate. It is also distinct from
the support material by an insulating layer (Dirani et al. 2016a).
(iv) Source and Drain Contacts: Source and drain terminals are used to connect
the Fb-FET to external circuitry. The channel region between these terminals
is where the transistor action occurs.
276 R. A. Kumar et al.

Operating Principle

The Fb-FET functions according to the same basic idea as a traditional FET, which
is the application of an electric field to a semiconductor channel to modulate its
conductivity. But the Fb-FET’s back gate offers much more versatility and control
over altering the transistor’s characteristics (Solaro and Fonteneau 2016).
Here’s a simplified overview of the operating principle:
(i) Biasing: The conductivity of the channel between the drain and source is
influenced by the electric field created when the front gate (G1) is electri-
cally charged in relation to the source terminal. The charge carrier flow in the
channel—typically electrons or holes—is regulated by this voltage on the front
gate.
(ii) Back Gate Influence: There is more control available at the back gate (G2). The
electric field inside the substrate may be changed by applying a voltage to the
back gate. This alteration may have an impact on how the channel produced
by the front gate voltage behaves. We may modify the transistor’s threshold
voltage, transconductance, and subthreshold slope by changing the voltage on
the back gate.
(iii) Operation Modes: Fb-FETs have many operating modes, such as depletion
mode, in which the front gate depletes the channel, and enhancement mode,
in which the front gate increases channel conductivity (Dirani et al. 2016b).
These modes may be further adjusted via the back gate, allowing for more exact
control.
The Fb-FET structure Fig. 11.1a, b is flexible choice for cutting-edge semicon-
ductor device design as it incorporates a second gate, the back gate, which offers more
control over the behavior of the transistor. Better performance, power efficiency, and
flexibility in a range of applications are made possible by this extra control.

Device Fabrication

The estimated manufacturing process used for the proposed FBFET device is depicted
in as shown in Fig. 11.2 (Wann and Hu 1993). It would have been difficult to
use conventional MOSFET manufacturing techniques since the device needed two
different gate structures, one n-type doped with materials and the other with p-type
materials. For this reason, the p-type and n-type polysilicon gates have to be made
separately. First, as shown in Fig. 11.2a, a fin-type silicon channel needed to be
created. Subsequently, as shown in Fig. 11.2b–e, a series of Deposition and Etching
procedures were done twice. Despite being a more difficult process to fabricate than
the conventional MOSFET technique, this approach was still achievable with current
technology and was not expected to be unduly complicated (Lacord et al. 2018).
Field-Effect Bipolar-Induced Field-Effect Transistor (FFFET) manufacturing is
a multi-step, somewhat complicated procedure as shown in Fig. 11.2. An abridged
11 Feedback Field-Effect Transistors/Zero Subthreshold Swing and Zero … 277

Fig. 11.1 a P-I-N feedback field-effect transistor (FBFET) with trap-charged spacers is shown
in its device structure (Colinge and Lee 2014). b Its perspective from the channel’s cross-section
(Colinge and Lee 2014)

Fig. 11.2 Method of fabrication employed to create the suggested FBFET structure (Dirani et al.
2016a): a creation of the channel and gate oxide area; b hard mask patterning of the double P-
poly gate; c double P-poly gate deposition; d hard mask patterning of the double N-poly gate; and
e double N-poly gate deposition
278 R. A. Kumar et al.

summary of the essential fabrication processes for an FBFET device is provided

below:
(i) Substrate Preparation:
. Start with a silicon wafer as the substrate material.
(ii) Gate Formation:
. Deposit a thin oxide layer (SiO2 ) on the silicon substrate.
. Define and create the n-type and p-type gate regions separately using
photolithography and doping techniques. This step involves selectively
implanting or diffusing n-type and p-type dopants into the silicon to create
the gates (Bawedin et al. 2008).
(iii) Fin Formation:
. Use lithography and etching processes to define and create the fin-type
silicon channel structure. The fin structure provides the basis for the
device’s operation.
(iv) Isolation:
. Implement isolation techniques (such as shallow trench isolation, STI)
to isolate individual FBFET devices on the silicon substrate to prevent
interference between neighboring devices.
(v) Source and Drain Formation:
. Define and create the areas of the source and drain utilizing lithography
and implanting ions or diffusion processes. These regions typically involve
doping with appropriate materials to create n-type and p-type regions as
required (Hubert et al. 2009).
(vi) Gate Dielectric Formation:
. Deposit a gate dielectric layer (usually silicon dioxide, SiO2 ) over the entire
structure, including the gate, fin, source, and drain regions.
(vii) Gate Electrode Formation:
. Deposit a polysilicon or metal gate material over the gate dielectric layer.
. Define and shape the gate electrodes using lithography and etching
techniques.
(viii) Spacer Formation:
. Form insulating spacers on the sides of the gate electrodes. These spacers
help in controlling the channel region and reducing leakage current.
(ix) Contact Formation:
. Create contact openings through a dielectric layer to allow for linkages
between the source and drain areas electrically.
11 Feedback Field-Effect Transistors/Zero Subthreshold Swing and Zero … 279

(x) Metal Interconnects:

. Deposit and pattern metal layers to attach the electrodes for the source,
drain, and gate to external circuitry.
(xi) Passivation Layer:
. Apply a passivation layer to protect the device and its interconnects.
(xii) Testing and Packaging:
. Test the fabricated FBFET devices to ensure functionality and perfor-
mance.
. Package the devices for integration into electronic circuits.
It is crucial to remember that the actual construction of an FBFET may entail
more complex procedures as well as certain materials and methods designed to meet
the required device parameters. Furthermore, the design and technology employed
in the production of FBFETs may change the sequence in which certain procedures
are performed (Rodriguez et al. 2011).

TCAD Modeling

When developing semiconductor devices, Technology Computer-Aided Design

(TCAD) modeling is a useful tool for designing and analyzing state-of-the-art instru-
ments like the Field-effect transistor with feedback (FBFET) (Rodriguez et al. 2012).
Before real prototypes are made, TCAD modeling enables researchers and engineers
to model how semiconductor devices will behave virtually. Here is how FBFETs can
benefit from TCAD modeling:
(i) Device Structure and Geometry: The first step in TCAD is to define the
FBFET’s physical structure and geometry, including the material character-
istics, doping profiles, and dimensions of the gate, source, and drain regions.
The TCAD program offers resources for modeling the FBFET virtually.
(ii) Material Properties: For each of the FBFET’s areas, we may set material char-
acteristics including mobility, carrier lifetimes, and doping concentrations.
For device behavior simulation to be correct, this information is essential.
(iii) Process Simulation: The stages in the manufacturing process that go
into making an FBFET may be simulated using TCAD modeling. This
involves processes like as deposition of different materials, oxidation, thermal
annealing, and ion implantation (Song et al. 2009). We can forecast the impact
on the device attributes by modeling these processes.
(iv) Electrical Simulation: By resolving the semiconductor equations for drift–
diffusion, continuity, and carrier transport, TCAD simulates the electrical
behavior of the FBFET. This enables us to examine the I-V characteristics,
subthreshold behavior, and more electrical attributes of the device.
280 R. A. Kumar et al.

(v) Device Optimization: By adjusting factors like gate length, gate oxide thick-
ness, and doping profiles, TCAD modeling allows us to carry out design
optimizations (Mueller et al. 2005). It is possible to assess the effects of these
modifications on device performance, which allows us to adjust the FBFET
design to suit certain applications.
(vi) Parameter Extraction: Critical device parameters that are necessary for
describing the performance of the FBFET, such as drain current, transcon-
ductance, and threshold voltage, may be extracted using TCAD.
(vii) Sensitivity Analysis: Sensitivity analysis may be carried out using TCAD
modeling to determine how changes in shape, process parameters, and mate-
rial qualities affect device performance. This is useful for evaluating how
durable the item is under actual manufacturing circumstances.
(viii) Monte Carlo Simulations: TCAD is capable of doing Monte Carlo simula-
tions, which offer insights into how differences in parameters impact device
performance statistically, to account for statistical variances in production.
(ix) Reliability Analysis: Through the modeling of processes such as hot carrier
effects, gate oxide breakdown, and electromigration, TCAD is able to predict
the long-term dependability of FBFETs. Predicting the lifespan of the item
and its gradual decline in performance is essential.
(x) Integration into Circuit Simulations: Upon developing the FBFET model with
TCAD, it may be included into circuit simulation software, such as SPICE,
to examine its performance in more extensive electronic circuits and systems.
All things considered, TCAD modeling provides a thorough method for creating
and evaluating FBFET devices as shown in Fig. 11.3. Without the need for actual
prototypes, it enables engineers and researchers to comprehend how the device
behaves, maximize its performance, and forecast how it will function in real-world
scenarios, greatly speeding up the device development process (Eminente et al. 2007).

Fig. 11.3 Silicon nanowire FBFET’s cross-sectional view for the TCAD simulation (Dirani et al.
2016b)
11 Feedback Field-Effect Transistors/Zero Subthreshold Swing and Zero … 281

Memory Operation

A Feedback FET’s (Fb-FET) memory operation is its capacity to store and hold data
or information in a non-volatile way as shown in Fig. 11.4, which qualifies it for use
in specific memory applications. To accomplish memory functionality, the Fb-FET
blends the special qualities of a feedback mechanism with the fundamentals of a
field-effect transistor. This can be achieved by using a certain operating mode known
as “floating gate mode” or “non-volatile memory mode.” This is how it operates:

(i) Floating Gate Structure: A floating gate is a part of the construction of a

conventional Fb-FET, which is utilized in memory applications, along with
the front and rear gates. Usually constructed of conductive material such as
polysilicon, the floating gate is separated from the remainder of the device by
insulating layers (Cristoloveanu et al. 2017).
(ii) Programming: A voltage pulse is applied to the front and rear gates in order
to write data into the memory cell. Charge carriers, such as electrons or holes,
are induced to tunnel through the insulating layer and onto the floating gate by
the electric field created by the first gate voltage. Usually, a strong voltage is
applied to the front gate to accomplish this procedure.
(iii) Charge Trapping: The characteristics of the insulating layer trap the charge
carriers that tunnel onto the floating gate. The device’s conductivity and
threshold voltage are impacted by the electric field this trapped charge produces
inside the device.
(iv) Reading: When the front gate voltage is set to a certain level, it becomes
possible to read the stored data and identify whether the transistor is in a “pro-
grammed” or “erased” condition. The properties of the transistor are changed
by the charging state of the floating gate, which makes it possible to sense the
stored data.

Fig. 11.4 a Example of the waveform of a DRAM without a capacitor (Lacord et al. 2018).
b Diagram of a DRAM equivalent circuit without a capacitor that has three states for the logic
values “0” and “1” (Lacord et al. 2018)
282 R. A. Kumar et al.

(v) Erasing: A voltage pulse is delivered to free the imprisoned charge from
the floating gate, erasing the recorded data and restoring the Fb-FET to its
initial condition. Hot electron injection and Fowler–Nordheim tunneling are
two methods that can do this.

Key Characteristics and Advantages of Fb-FET Memory:

Non-Volatile: Since the Fb-FET memory is non-volatile—that is, it retains data even
in the event of a power outage—it is suitable for data storage applications similar to
flash memory.
Electrically Programmable and Erasable: Electrical writing and wiping of data
makes it possible to manipulate data easily without physically altering the device.
High Density: Fb-FET memory cells can be densely packed on a chip, making them
suitable for high-capacity memory devices.
Reliability: Fb-FET memory cells are known for their reliability and long-term data
retention.
Low-Power Consumption: Reading and writing operations typically require relatively
low power compared to some other memory technologies.
Endurance: Fb-FET memory can endure numerous read and write cycles before
wearing out.
A “0” state is encoded by lowering the gate voltage to 0 V, which removes
the carrier from the channel area below the gate. Returning the gate voltage to an
extremely negative range (VGe) is necessary to maintain the “0: state, This causes
profound depletion since there aren’t any carriers available to build an inversion
layer, upsetting equilibrium. This rapid change in potential creates a steep barrier
for hole injection. A negative pulse is used to retrieve data in order to read the “0”
state. To avoid unwanted current flow, VD should be appropriately selected from
the observed VDe values in the transient and DC modes, preventing the diode from
turning on unexpectedly. Constant refreshing of the ‘0’ state is necessary because
trapped carriers generated under the gate cause a reduction in the energy barrier and
VDe, as illustrated in Fig. 11.4a, b (Wan et al. 2013a).

Failure Analysis

Failure analysis of a Feedback FET (Fb-FET) entails looking into and identifying
problems or malfunctions that happen while the device is operating (Navarro et al.
2017). Enhancing the performance and dependability of Fb-FET-based devices
requires figuring out the underlying reasons of these problems. The following steps
are usually involved in the failure analysis process:

(i) Failure Identification:

11 Feedback Field-Effect Transistors/Zero Subthreshold Swing and Zero … 283

Finding the precise malfunction or abnormality in the Fb-FET device is the first
step. There are several ways to do this, including visual examination, performance
characterization, and electrical testing.

(ii) Isolation and Localization:

Isolating and localizing the issue is the next step after failure identification. This
entails figuring out which element or section of the Fb-FET is broken. One way to
use isolation techniques is to probe several areas of the device to find the problem’s
location.

(iii) Physical Inspection:

Visual examination and microscopy are frequently employed to assess the Fb-FET’s
physical state. This can assist in locating problems like flaws, physical harm, or
surface contaminants on the equipment.

(iv) Electrical Testing:

An essential component of failure analysis is electrical testing. It entails testing a

number of Fb-FET electrical properties, including capacitance, leakage currents,
threshold voltage, and voltage-current characteristics. Potential failures may be
indicated by deviations from predicted values.

(v) Material Analysis:

The characteristics of the semiconductor materials utilized in the Fb-FET may occa-
sionally be investigated using material analysis techniques (Cristoloveanu et al.
2018). This can use methods such as scanning electron microscopy (SEM), trans-
mission electron microscopy (TEM), and energy-dispersive X-ray spectroscopy
(EDS).

(vi) Fault Isolation Techniques:

To precisely find and isolate flaws inside the device, advanced methods like as elec-
tron beam-induced current (EBIC) and focused ion beam micromachining (FIB) can
be employed.

(vii) Simulation and Modeling:

Identifying possible failure mechanisms and comprehending the behavior of the

device under various settings can be aided by computational simulations and
modeling.
(viii) Root Cause Analysis:

Finding the failure’s primary cause is crucial once the flaw has been located. Investi-
gating elements such process variances, design faults, material flaws, manufacturing
problems, or electrical overstress may be necessary to achieve this.
284 R. A. Kumar et al.

(ix) Corrective Actions:

The failure can be addressed by taking the necessary remedial action when the root
cause has been identified. This might entail altering the material, improving the
process, changing the operating conditions, or changing the design.
(x) Testing and Verification:
It is critical to retest the device after putting corrective measures into place to make
sure the issue has been fixed and that it still satisfies performance and reliability
requirements.
In order to avoid similar failures in other devices and for future reference, thor-
ough documenting of the failure analysis process is necessary. The research and
manufacture of semiconductor devices depend heavily on failure analysis, which
enhances yield, quality, and dependability of the final product (Navarro et al. 2019).
To properly identify and fix problems with Feedback FETs and other semiconductor
devices, multidisciplinary knowledge in electrical engineering, materials science,
and physics is needed.

Process Optimization

In order to increase the performance, yield, and dependability of these semicon-

ductor devices, process optimization for Feedback FETs (Fb-FETs) entails improving
and fine-tuning the fabrication processes and parameters (Kang et al. 2019). The
process of optimization is intricate and usually entails experimentation, analysis,
and successive processes. An outline of the main elements of Feedback FET process
optimization is provided below:
(i) Design Optimization:
It is essential to optimize the electrical and physical design of the device prior to
manufacture. To achieve certain performance targets, this entails modifying the front
gate, rear gate, floating gate, and other components’ sizes and features.
(ii) Material Selection:
For Fb-FET performance, selecting the appropriate semiconductor materials and
insulators is crucial. Device behavior is influenced by material characteristics like as
bandgap, dielectric constant, and electron mobility.
(iii) Process Variation Reduction:
In order to guarantee consistent device functioning, it is imperative to minimize
variances in the manufacturing process. This includes managing variables like as
etch rates, doping concentration, and film thickness.
(iv) Quality Control and Testing:
11 Feedback Field-Effect Transistors/Zero Subthreshold Swing and Zero … 285

Throughout the fabrication process, use strict quality control procedures and in-line
testing to spot any early deviations from the intended parameters. Techniques for
electrical, optical, and physical characterization might fall under this category.

(v) Gate Oxide Formation:

The performance of Fb-FETs is dependent on the thickness and quality of the gate
oxide layer. Reliability depends on optimizing the gate oxide generation method,
such as thermal oxidation or chemical vapor deposition (CVD).

(vi) Front and Back Gate Voltage Control:

To achieve the required features of the device and to ensure data retention in memory
applications, it is imperative to precisely manage the voltage levels supplied to the
front and back gates during programming and operation.

(vii) Charge Injection and Retention:

Optimizing the methods for charge injection onto and retention within the floating
gate is crucial for Fb-FET memory applications. Adjusting programming and deleting
voltages and timings may be necessary for this.
(viii) Scaling and Miniaturization:

As semiconductor technology develops, process optimization frequently entails

reducing the size of the device in order to maximize integration density and enhance
performance while preserving dependability.

(ix) Reliability Testing:

Test the long-term stability and data retention of Fb-FET devices in memory
applications using stress testing and accelerated aging.

(x) Environmental Considerations:

Take into consideration environmental elements including temperature, humidity,

and radiation that may have an impact on the functioning of Fb-FETs. When
appropriate, adjust the device’s specs to survive these circumstances.

(xi) Modeling and Simulation:

To forecast device behavior and direct optimization efforts, use computer modeling
and simulation techniques. These instruments can be used to pinpoint important
design elements and process factors.

(xii) Feedback Loop:

Create a feedback loop in which areas for improvement are identified by regularly
analyzing data from testing and production. With time, the manufacturing process is
improved and optimized thanks to this constant observation.
286 R. A. Kumar et al.

(xiii) Cost Optimization:

To make sure that the improved process is still financially feasible for large-scale
manufacturing, strike a balance between cost and performance gains.
Device designers, process engineers, and production teams must work closely
together to optimize the feedback FET process, which is a continuous endeavor (Wan
et al. 2013b). The objective is to manufacture devices that fulfill the requirements of
different applications, such as memory storage and non-volatile memory technolo-
gies, while maintaining consistent and enhanced performance characteristics (Wan
et al. 2012b).

Figures of Merits

The characteristics or metrics known as figures of merit for Feedback FETs (Fb-
FETs) are employed to assess the efficacy, efficiency, and appropriateness of these
devices for a range of applications (Lee et al. 2018). The particular application and
the intended usage of the Fb-FET determine which figures of merit are selected. The
following are typical figures of merit for Fb-FETs:
(i) Threshold Voltage (Vth):
The Fb-FET starts to conduct at a gate voltage known as the threshold voltage. It is
an essential parameter for figuring out how the device will transition.
(ii) Subthreshold Swing (SS):
The subthreshold swing gauges the Fb-FET’s on/off efficiency. It is an essential char-
acteristic for analog and digital applications that use less power. Better performance
is indicated by lower SS levels.
(iii) On/Off Ratio (I on /I off ):
The current difference between the conducting (ON state) and non-conducting (OFF
state) states of the Fb-FET is represented by the on/off ratio. For digital applications,
high on/off ratios are preferred in order to reduce leakage current during the off-state.
(iv) Transconductance (gm):
The change in drain current in response to a change in gate voltage is measured
by transconductance. In applications involving analog amplification, it is essential.
Better amplification capacity is indicated by higher transconductance (Cho et al.
2019).
(v) Charge Retention Time:
Charge retention time quantifies the amount of time that stored charges on the floating
gate may be maintained without appreciable leakage for Fb-FETs used in non-volatile
memory applications. Extended periods of retention are preferable (Duan et al. 2019).
11 Feedback Field-Effect Transistors/Zero Subthreshold Swing and Zero … 287

(vi) Write/Erase Endurance:

Write/erase endurance, in non-volatile memory applications, is the number of times

the Fb-FET can be programmed (written) and erased (cleared) without experiencing
a failure. Increased endurance is preferred.

(vii) Program/Erase Speed:

The speed at which the Fb-FET can be programmed and erased in non-volatile
memory applications is measured by this figure of merit (Woo et al. 2019). Quicker
operations are frequently favored.

(viii) Operating Voltage Range:

For both analog and digital applications, the voltage range at which the Fb-FET may
consistently function without malfunction or significant leakage is essential.
(ix) Data Retention Stability:

Data retention stability is a term used to describe how well stored information holds
up over time and in different environmental conditions in non-volatile memory
applications.

(x) Yield:

The percentage of defect-free Fb-FETs in a manufacturing process is called yield. A

high yield is necessary for production to be economical.

(xi) Power Consumption:

One important point of differentiation for battery-operated gadgets is power usage.

Reduced heat generation and longer battery life are achieved with lower power usage.

(xii) Noise Performance:

Noise performance is essential in sensitive applications such as sensors and analog

circuitry. It gauges how much undesired electrical noise is present in the output of
the gadget.

(xiii) Area Efficiency:

The ability of the Fb-FET to be incorporated into a semiconductor chip is evaluated by

area efficiency. High-density integrated circuits are generally designed with smaller
device areas in mind.
(xiv) Temperature Sensitivity:

For some uses, Fb-FETs must perform reliably throughout a wide temperature range.
Temperature sensitivity is a measure of how the gadget performs differently at
different temperatures.
288 R. A. Kumar et al.

(xv) Cost-Effectiveness:

The whole cost of producing and incorporating the Fb-FET into a product, including
expenses for materials, fabrication, and testing, is taken into account by the cost-
effectiveness figure of merit (Kwon et al. 2019).
The intended use of the device, industry standards, and the particular performance
requirements of the application all play a role in determining which figures of merit
are most significant for a certain Fb-FET application (Oh et al. 2019). When building
and improving Feedback FETs for a range of applications, including as digital logic,
analog circuits, and non-volatile memory, engineers and researchers take these figures
of merit into account.

Conclusions

Reactions with regard to resolving significant issues with conventional Field-Effect

Transistors (FETs) including subthreshold swing and impact ionization, Field-Effect
Transistors (Fb-FETs) are a potential advancement in semiconductor technology.
In particular, Fb-FETs provide a number of significant benefits when designed
to achieve zero subthreshold swing and zero impact ionization. It is important to
remember, nevertheless, that producing Fb-FETs with zero impact ionization and
zero subthreshold swing is a difficult undertaking that calls for creative designs,
materials, and manufacturing processes. In an effort to overcome these obstacles and
realize the full potential of Fb-FETs for a variety of applications, researchers and
engineers are working hard.
Feedback field-effect transistors (FETs) featuring zero subthreshold swing and
zero impact ionization hold great promise for resolving basic problems with conven-
tional FET technology. By enhancing performance, energy economy, and relia-
bility in both current and future applications, FETs have the potential to completely
transform electronic devices.

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Chapter 12
Resistive-Gate Field-Effect Transistor:
A Potential Steep-Slope Device

Abhinandan Jain, Lalit Kumar Lata, Neeraj Jain, and Praveen K. Jain

Abstract The recent development of steep-slope devices offered novel opportu-

nities for voltage scaling beyond the capabilities of CMOS. Steep-slope devices
are suggested to improve their performance. Theoretically, steep-slope devices may
allow low-voltage operation with acceptable leakage current by switching from the
off to on state with a smaller change in gate voltage. This chapter includes ReFET
that has been identified as a developing field-effect transistor due to its subthreshold
swing of less than 60 mV/dec. Due to the optimization of MOSFET components,
ReFET is a better option for upcoming low-power electric applications because the
leakage current has decreased by nearly four decades. This chapter also addresses
the challenges associated with resistive-gate field-effect transistors, in addition to
the opportunities they present. This chapter additionally covers various memory
structures, with a particular emphasis on resistive random-access memory. This
article includes a review of recent developments in the design of RRAM-based
neuromorphic computing circuits inspired by the human brain.

Keywords Steep slope · Subthreshold slope · Resistive random-access memory

(RRAM)

Introduction

In the current scenario, the major points to be noted in device fabrication are power
consumption and switching speed of the device. The low-power consumption devices
are suitable for battery-operated devices, preferably. The trade-off between switching
speed and power dissipation is one of the most crucial factors in semiconductor
devices (Tura and Woo 2010). The primary issue with vacuum tubes was their limited

A. Jain · L. K. Lata · N. Jain · P. K. Jain (B)

Department of Electronics and Communication Engineering, Swami Keshvanand Institute of
Technology, Management and Gramothan, Jaipur, Rajasthan 302017, India
e-mail: [email protected]

© The Author(s), under exclusive license to Springer Nature Singapore Pte Ltd. 2024 291
S. Singh et al. (eds.), Beyond Si-Based CMOS Devices, Springer Tracts in Electrical and
Electronics Engineering, https://doi.org/10.1007/978-981-97-4623-1_12
292 A. Jain et al.

power dissipation, which has led to the development of power-efficient bipolar tran-
sistors for switching and amplification purposes. In the 1980s, field-effect transis-
tors (FETs) based on complementary metal oxide semiconductor (CMOS) were
replaced by bipolar transistors in response to the demands for greater power effi-
ciency (Alam et al. 2019). The consequences of operating at low voltages include
an increase in leakage current in CMOS devices. CMOS also encounters numerous
challenges, including issues related to power consumption, self-heating, and scal-
ability. Several devices, such as tunnel FETs, CNTFETs, nano-electro-mechanical
FETs (NEMFETs), spin FETs, phase FETs, and negative capacitance field-effect
transistors (NC-FETs), were investigated by researchers in the past. As per Moore’s
law, when the number of transistors on a chip doubles every two years, the perfor-
mance of the device increases tremendously, but the power dissipation of the chip
also increases (Pandey et al. 2016). In the electronics industry, maintaining the power
density of massive digital circuits is a critical challenge. Utilizing a transistor with
a steep slope or a low subthreshold swing is one strategy for reducing this power
density (Yuan et al. 2016). Theoretically, steep-slope devices may allow low-voltage
operation with acceptable leakage current by switching from the off to on state with
a smaller change in gate voltage (Gnani et al. 2016).
To maintain the performance of the device, the threshold voltage reduces propor-
tionally as the power supply scales down. This scaling of threshold voltage causes
a significant increase in static power dissipation because MOSFET’s swing is
constrained to 60 mV/dec below the threshold (Chang and Haensch 2012). Low-
power and high-performance systems cannot be realized because of the supply
voltage scaling restrictions (Pandey et al. 2016). The introduction of the NC-FET
further improved the subthreshold swing of MOSFET. A nanocrystalline ferroelec-
tric (FET) material is deposited as an intermediate layer between the dielectric and
gate materials. Making sure that the voltage inside the FE–oxide interface is higher
than the gate voltage in NC-FETs lowers the MOSFET’s subthreshold swing to less
than 60 mV/dec. Consequently, by achieving the on-current (Ion ) at a reduced supply
voltage (VDD ), the power consumption would be significantly diminished (Alam
et al. 2019). The NC-FET technology functions at a significantly low voltage due
to its steeper subthreshold oscillation; furthermore, it increases the on current while
keeping the off current constant (Huang et al. 2014). There are significant challenges
with the manufacturing process of NC-FET, such as integrating ferroelectric material
into the gate stack while maintaining high-quality silicon contact (Amrouch et al.
2018).
The power density has become a significant barrier to further MOSFET scaling.
The steeper subthreshold slope is an alternate method to design a transistor to over-
come the power density problem. One example of a device that uses the quick pull-in
and quick release of mechanical beams to get a subthreshold swing of less than 60 mV/
dec is the NEMFET (Ye et al. 2016). In the NEMFET, the gate is pushed closer to
the channel to boost the gate’s ability to modulate the density of the carriers in the
channel (Tura and Woo 2010).
Positive feedback FETs (FBFETs) offer very steep switching devices with
extremely low subthreshold swings of less than 1 mV/dec. The bulk-type FBFET
12 Resistive-Gate Field-Effect Transistor: A Potential Steep-Slope Device 293

typically uses the p-i-n structure to generate an S-shaped energy band structure as a
result of the positive feedback (Lee et al. 2019). For low-power and high-performance
computing systems, tunneling field-effect transistors (TFET) are regarded as a band-
to-band enabler (Pandey et al. 2016). The tunnel FET operates in two states: on and
off. In the on state, the gate voltage surpasses the threshold voltage, and conduction
takes place because a very tiny band gap exists between the channel and the source,
allowing considerable tunneling for the current to flow. In the off state, no tunneling
occurs and very little leakage current flows due to the large potential barrier between
the source and the channel (Woo et al. 2007).
Subthreshold swing value in tunnel FET is influenced by the thickness of the gate
oxide (t ox ), the thickness of the SOI layer (t SOI ), and the steepness of the source
doping profile. As the thicknesses of the gate oxide and SOI layers in tunnel FET are
reduced, it is noticed that the subthreshold swing value also decreases (Woo et al.
2007). The reduced subthreshold swing (S avg ) offers more steepness and reduces the
voltage supply without degrading the performance (Ionescu and Riel 2011).

VT − VGOFF VDD
Savg = IT
≈
log IOFF log IIOFF
ON

Band-to-band tunneling is the one category of steep-slope devices in which it is

possible to obtain subthreshold swings of less than 60 mV/dec. NEMFET devices
with a moveable gate/body and NC-FETs with ferroelectric gates are examples of the
second category (Huang et al. 2016). A new steep-slope device in which a resistive
switching layer is deposited onto the gate layer of a field-effect transistor is called a
ReFET. In a ReFET, a resistive switching layer is used between two metals that allow
the gate layer resistance to change from a high-resistance state to a low-resistance
state (Huang et al. 2016). The threshold voltage V t of a ReFET is decreased by the
transition from a high-resistance state (HRS) to a low-resistance state (LRS). The
subthreshold swing and ION current also improved as a steep SS of 8 mV/dec of
ReFET (Chang and Haensch 2012). When the gate voltage in the resistive-gate field-
effect transistor increases, the voltage across the metal–insulator increases which
creates an abrupt transition from the HRS to the LRS.

ReFET Structure and Operating Principle

The gate structure of ReFET is different from the MOSFET gate structure. The
MOSFET gate terminal is made up of metal, while the ReFET gate structure is made
up of metal–insulator–metal layers, as shown in Fig. 12.1. The insulator material
is sandwiched between two metals and exhibits sudden resistance change behavior
between the LRS and HRS (Huang et al. 2014). To achieve an excellent ratio of on
current to off current, it is essential to minimize the leakage current of the HRS and
keep the resistance value of the LRS as low as possible. The performance of multilayer
294 A. Jain et al.

Fig. 12.1 Structure of ReFET

resistive switching devices has been seen to be significantly superior in comparison

with that of single-layer devices, according to recent publications. Various oxide
materials, such as TiOx , HfO2 , Cu2 O, and NiO, can be used as an insulator surface
in resistive-gate field-effect transistors.
Electrical Characteristics:
The electrical characteristics of ReFET depend upon the nature of the insulator
material used as a sandwich between two metals. Various electrical parameters to
evaluate the performance of FETs can be defined as:
I. Threshold voltage (V T ): The lowest gate voltage necessary to induce a deep level
of inversion and enable drain-to-source conduction.
II. I On /I off ratio: On- and off-current ratio can be defined as:

IOn Maximum drain current at above threshold region

=
Ioff Minimum drain current (when device is in off state)

III. Subthreshold swing (SS): It is described as:

[( ) ]−1 ( )
[ ]−1 [ ]−1 ∂ log IDs ∂VGS
SS = γ ' = (tg(γ )max =
∂VGs max ∂ log(IDS ) max

Here, γ ' is the maximum slope of the transfer characteristics in semilogarithm plot.
Table 12.1 compares different performance parameters of field-effect transistors.

Device Fabrication

There is a resistive-gate field-effect transistor (ReFET) made up of MOSFET and

dielectric layers (MDM) between the top and bottom electrodes. The bottom electrode
of the MDM is electrically connected in series with the gate of the MOSFET. A
resistance-switching layer and a resistance-non-switching layer result in MDM’s
12 Resistive-Gate Field-Effect Transistor: A Potential Steep-Slope Device 295

Table 12.1 Comparison table of different field-effect transistors

Materials/ ReFET Pt/ ReFET TiN/ NTFET 40 nm NTFET 40 nm NC-FET
property TiN/TaOx / TaOx /Pt Si Ge MoS2 /HfO2 /
Poly-Si/SiO2 LNO
SS 8 mV/dec 4.9 mV/dec 63 39 4.97 mV/dec
VT Suddenly – 0.43 0.2 –
reduced
I ON /I OFF – 106 1012 1011 –
Reference Huang et al. Huang et al. Bhushan et al. Bhushan et al. Wang et al.
(2016) (2013) (2012) (2012) (2020)

Fig. 12.2 Illustration of resistive-gate field-effect transistor

dielectric layers. This offers a bidirectional integrated circuit voltage limit with a
limiting voltage that can be adjusted to almost any value that is likely to be present
on an integrated circuit. As demonstrated in Fig. 12.2, a ReFET can be fabricated
by using any practical method. For instance, direct diffusion or ion implantation can
be used to create source and drain regions, and sputtering can be used to deposit the
insulating and resistive layers. Postmetal annealing should be performed to lessen
the interface traps between layers and control the quantity and distribution of oxygen
vacancies.
As seen in Fig. 12.3, Hsieh et al. (2021) demonstrated a resistive-gate field-effect
transistor based on HfO2 /HfON. Here, titanium nitride (TiN) and silicon dioxide
(SiO2 ) were first deposited on a p-type silicon wafer using physical vapor deposition
(PVD), with TiN acting as the bottom electrode of the RRAM MDM. SiO2 was used
to provide isolation. The bottom electrode pattern was defined by lithography, and the
TiN sidewall was shaped by an anisotropic dry etch. Next, atomic layer deposition
(ALD) was used to put thin layers of HfO2 and HfOx doped with nitrogen ions on the
sidewall of the TiN. The titanium (Ti) on the dielectric layers was PVD-capped, and a
PVD TiN top electrode was deposited later. Then, lithography was used to create the
contact windows for the top and bottom electrodes. With a gate stack made up of Pt/
TiN/TaOx /Poly-Si/SiO2 , Huang et al. (2014) created an n-type ReFET device. Here,
n-type ReFETs based on a gate stack of TiN/TaOx /Poly-Si were developed. TaOx
was sputtered from a Ta target using an RF reactive magnetron in an atmosphere that
296 A. Jain et al.

Fig. 12.3 HfO2 /

HfON-based resistive-gate
field-effect transistor device
structure as fabricated by
Hsieh et al. (2021)

contained a mixture of oxygen and argon. A later annealing procedure was used to
boost the oxygen content of the TaOx film. On gate oxide, a stack of Pt/TiN/TaOx /
Poly-Si was eventually deposited.

TCAD Modeling

A subset of electronic system design software is called technology computer-aided

design (TCAD). TCAD specifically simulates the physics of semiconductor devices
and processes. To develop and improve semiconductor device fabrication processes
and electrical behaviors, TCAD can be used in computer simulations. Electronic
design automation is now widely used as a workhorse technology for integral
processes in semiconductor devices and process simulation. It has evolved into a
necessary toolkit. The purpose of TCAD is to give an interactive physical descrip-
tion and examination of semiconductor devices through simulation and modeling
in order to facilitate circuit design and save R&D costs and time. With TCAD, the
properties of conventional semiconductor devices may be anticipated in a timely and
cost-effective manner (SILVACO-TCAD 2019). Although phenomenological and
semiempirical models may be used to visualize new processes, structures, and mate-
rials in order to capture physical insights and expedite the learning curve, Sentaurus
TCAD is a comprehensive set of nanoscale processes, device design, and simula-
tion tools developed by Synopsy. It facilitates industry-leading process and device
simulation facilities by providing a sophisticated GUI-driven simulation environ-
ment for managing simulation tasks and analyzing simulation outcomes. Figure 12.5
depicts the flowchart for Synopsy’s Sentaurus TCAD (Kashirskaya 2015). Industry
and academic institutions have been using another TCAD “Silvaco ATLAS” simu-
lator for more than 20 years. Silvaco ATLAS includes a database of common semi-
conductor materials. Along with the Silvaco ATLAS, other interactive tools such
12 Resistive-Gate Field-Effect Transistor: A Potential Steep-Slope Device 297

Fig. 12.4 TCAD simulation software—SILVACO ATLAS flowchart

as Tony Plot, Deck Construct, and Tony Plot 3D are also used. The device simula-
tion using these TCAD tools should specify the physical compositions and physical
models that must be solved under given electrical bias conditions. Figure 12.4 depicts
the Silvaco ATLAS flowchart.

Memory Operation

Memory is an essential component of every electronic device as it facilitates the

storage of data. Figure 12.6 shows the memory structure based on charge base
and change of resistance-based memory. DRAMs, which are utilized in computer
systems, have extensive density and capacity, but their volatility necessitates that
they be refreshed every few milliseconds. SRAM is fast, but this is also a volatile
type of memory. Flash memory is extensively used due to its cheap cost and great
density.
To enhance processing speed and other functionalities, the device’s processor
is consistently updated. Memory devices are additionally upgraded to improve
system synchronization and, consequently, system speed. Hence, many random-
access memories, including RRAM, MRAM, FERAM, and PCM, are offered. PCM,
MRAM, FERAM, and RRAM memory types largely depend on the placement of
the switching region and the behavior of their current voltage or resistance voltage
(Meena et al. 2014).
Even worse, the performance difference between processing and memory units
has widened significantly, and in the traditional von Neumann architecture, data
movement between these units begins to predominate in terms of energy consumption
and system throughput. This issue is also referred to as the von Neumann bottleneck
(Lee and Zhu 2020). In DRAM, SRAM, and flash memory, the information is stored
as charge on the capacitor, as charge at the nodes of cross-coupled inverters, and as
298 A. Jain et al.

Fig. 12.5 TCAD simulation

software—Sentaurus
flowchart

charge at the floating gate of the transistor, respectively. By scaling down dynamic
RAM, static RAM, and flash memory to 10 nm nodes or beyond, their performance,
reliability, and noise margin degrade (Zahoor et al. 2020). The memories may be
separated based on the change in resistance memory type. Memory technologies
such as phase-change memories (PCM), resistive random-access memory (RRAM),
magnetic random-access memory (MRAM), and spin-transfer torque random-access
memory (STT-RAM) are gaining significant attention because of their high speed,
high density, and nonvolatility.
12 Resistive-Gate Field-Effect Transistor: A Potential Steep-Slope Device 299

Fig. 12.6 Different types of memory structure

The magnetic RAM structure is magnetic metal/insulator/magnetic metal, as

depicted in Fig. 12.7. The MRAM cell has a high rate of operation and long endurance.
STT-RAM provides fast write/read performance, long endurance, scalability, quick
access time, and low programming voltage (Zahoor et al. 2020). PC-RAM functions
by shifting the active material’s phase from an amorphous phase to a conducting
crystalline phase. Although PC-RAM cells offer advantages such as rapid switching
speed, multilevel operation, and robust scalability, their substantial write latency
poses a drawback.
RRAM is emerging as one of the most popular nonvolatile memories due to its
rapid speed, scalability, low power consumption, and remarkable compatibility with
CMOS technology. Due to its potential usage in neuromorphic systems, RRAM is
gaining significant attention (Gao et al. 2016). RRAM is a network topology with

Fig. 12.7 Schematic of

metal–insulator–metal
structure for RRAM
300 A. Jain et al.

Fig. 12.8 Diagrams showing the switching mechanism of RRAM

two terminals. Between two metal electrodes is a dielectric layer whose resistance
may be altered reversibly between two or more states using external electrical inputs.
(Ielmini et al. 2021). The I-V hysteresis of RRAM devices fluctuates between LRSs
and HRSs and vice versa.
Anions or cations may induce the electrochemical mechanism that modifies
conduction. The formation of low-resistance conductance channels through the
migration of oxygen vacancies is what distinguishes RRAMs of the anion type. The
recombination of oxygen ions with vacancies can convert a low-resistance state to a
high-resistance state when an electric field is applied in the opposite direction (Jain
et al. 2022). The device undergoes a reduction in resistance (LRS) from its initial
state of high resistance (HRS) due to the migration of oxygen vacancies within the
metal oxide layer. This voltage is referred to as the set voltage. Owing to the recovery
of oxygen vacancies, the device switches from LRS to HRS; this voltage is referred
to as the reset voltage as shown in Fig. 12.8.
In RRAM, two switching modes exist: (i) unipolar switching mode and (ii) bipolar
switching mode. In the unipolar switching mode, the applied voltage amplitude rather
than its applied voltage determines the switching direction. Hence, set/reset is feasible
with the same polarity (Jain et al. 2022). In general, bipolar switching implies a lower
reset current than unipolar switching. Bipolar switching shows better device perfor-
mance in comparison with unipolar switching (Ye et al. 2016). In a bipolar switching
mode, the polarity of the applied voltage determines the switching direction. The set
and reset polarities are opposite to each other (Wong et al. 2012). The development of
RRAM has produced some serious concerns, such as the uncertain physics of resis-
tive switching in oxides, very poor uniformity, and significant switching parameter
variation. The RRAM’s performance may degrade as a result of switching events
between HRS and LRS, which might result in long-term damage.
12 Resistive-Gate Field-Effect Transistor: A Potential Steep-Slope Device 301

Resistive Memory Device in Brain-Inspired Computing

The human brain is one of the most complex objects of the human body and works
as central processing for human beings. It is highly efficient in performing cognitive
tasks such as the abstraction of information, recognition, processing, and decision-
making. It solves many complicated problems or tasks. The brain analyzes informa-
tion received from peripheral nerves located throughout the body before the comple-
tion of activities. Any word-related activity requires the human brain to engage in
memorization, recognition, processing, and decision-making. Making a hardware-
based artificial neural network that works like the human brain is the best way to
do neuromorphic computation that uses little energy and does not cost loads of
money. Neurons and synapses are the basic building blocks of a hardware-based arti-
ficial neural network. The electronic synapses’ performance and architecture largely
dictate the area, power, and computing efficiency of a brain-inspired chip (Gao et al.
2016).
RRAM has nonvolatile memory, a lower cost, a greater density, and is much
quicker than Flash memory, static RAM, and DRAM. Owing to the RRAM’s great
density and speed, it is employed for brain computing applications (Zidan et al.
2018). RRAM is used in brain computing applications to increase durability and
enhance selector performance to reduce sneak currents by decreasing programming
current and voltage (Zidan et al. 2018).
A hardware-based artificial neural network modeled after the human brain’s
fundamental structure consists of numerous neurons and synapses. The structure
and performance of the electrical synapses on a brain-inspired chip affect many
parameters, including its area, power, and computational efficiency (Gao et al. 2016).
Memristors naturally meet the above requirements because they are an electrically
tunable conductance connection between a presynaptic neuron (PRE) and a postsy-
naptic neuron (POST) that can sense the pulses sent by both neurons (Wang et al.
2015). Most memristive synapses work by moving metal or oxygen ions around,
which makes conducting filaments form or break apart randomly at the nanoscale.
Significant variations in performance between devices and cycles are an unavoid-
able consequence, posing a substantial barrier to the implementation of artificial
neural networks on a large scale (Wang and Zhuge 2019). Metal oxide RRAM-based
synapses have been reported to execute a variety of synaptic tasks that are useful for
creating high-performance brain-inspired chips.
Although synaptic connections’ conductivity and modulation govern the commu-
nication channels in the brain, neurons still produce spikes as indicators of infor-
mation processing in the brain. There are synapses between the receptor neurons’
dendritic terminals and the transmitter neurons’ axons. By releasing neurotransmit-
ters, these junctions regulate the transmission of messages between neurons (Tura
and Woo 2010). This feature is reproduced substantially in synthetic neural models:
Neurotransmitters connect to the postsynaptic neuron, enabling ionic current to
pass into the downstream cell. A neuromorphic computing system’s efficiency and
processing capability are proportional to the number of resistance levels.
302 A. Jain et al.

RRAM synapse limitations in the integrated circuit industry include the difficulty
of performing multilayer switching control, improving retention and uniformity,
and reducing power consumption (Gao et al. 2016). One of the most significant
challenges lies in the inadequate hardware required to implement synapses, which
are the fundamental components responsible for processing data in artificial brains.

Atomic Memristive Switch

Higher functional density, low programming voltage, and the development of

forming-free devices are just a few of the challenges that devices face as they shrink.
As inter-electrode spacing approaches the atomic level, it becomes more challenging
to maintain consistent resistive switching functionality (Guo et al. 2020). Atomic
switches are one particular type of switch. The switch may be on or off, and the voltage
applied between the electrodes controls the state of the switch (Hiroshi Kubota et al.
2022).
There are several kinds of atomic switches available. By depositing atoms in the
space between the electrodes, a molecular gap-type atomic switch reduces the amount
of ions in the electrode. This switch has two functioning states: The first is when
a metal filament is developing between the electrodes, and the second is when the
growth is complete and the filament linking the electrodes is stable (Hiroshi Kubota
et al. 2022). For the control of metal ion diffusion, an atomic switch is needed. In
reduction or oxidation, the formation or annihilation of a conductive channel between
two electrodes is regulated (Aono and Hasegawa 2010).
RRAM is present in two kinds of devices, depending on the anion or cation.
In anion-based RRAM memory, a metal oxide layer is sandwiched by two metal
electrodes, such as Pt/TiO2 /Pt (Wang et al. 2015) and Pt/NiO/Pt (Hino et al. 2011). An
ionic conductor sandwiched between two metal conductors is called a cation-based
ionic device. Cation-based ionic devices are responsible for switching operations
and atomic switches (Hino et al. 2011). There are atomic switches that control how a
metal atomic bridge forms and breaks down in a nanogap between an ionic conducting
material on a reversible electrode (Aono and Hasegawa 2010) and an atomic bridge.
The atomic switch has two distinct states: on and off.
If the size is reduced to the nanometer scale and the atomic switch is on, then
a highly conductive channel can be formed between the two electrodes. The metal
atomic bridge is annihilated when the ionized metal atoms, or cations, are redissolved
into the ionic and electronic mixed conductor material at the time of switching off
the switch (Aono and Hasegawa 2010).
12 Resistive-Gate Field-Effect Transistor: A Potential Steep-Slope Device 303

Parameter Application
Memories Atomic switches use a different type of nonvolatile and
volatile, multistate memory
For writing and erasing, atomic switches need bipolar bias
voltage (Hino et al. 2011)
Logic devices Logic circuits, such as logic gates, may be designed using
two terminal atomic switches (Hino et al. 2011)
Theoretically, all logic circuits might be designed using
atomic switches, without resorting to semiconductor
transistors (Hino et al. 2011)
Programmable switches Field-programmable gate arrays use atomic switches as
programmable switches or on or off switches (Hino et al.
2011)
Neuromorphic synaptic functions Use in a neuromorphic synaptic functions

Conclusion

This chapter provides an overview of recent developments in field-effect transistors,

with a particular emphasis on the ReFET. The ReFET is a developing field-effect
transistor due to its subthreshold swing of less than 60 mV/dec. This section also
includes a summary of memory operations and the resistive memory device in brain-
inspired computing. Due to the use of an insulator layer between metal and metal,
the switching characteristics of ReFET improved, such as its threshold voltage being
reduced and its subthreshold swing being reduced with respect to MOSFET. The
application of ReFET is for low-power electric applications. RRAM provided several
capabilities for brain-inspired computing applications. RRAM is the most competent
memory technology owing to its simple design, compatibility with existing CMOS
technology, high switching speed, and ability to be shrunk to the smallest feasible
size (Jain et al. 2023). A correct interpretation of the device switching mechanism,
which has been the subject of long-running debate among scientists throughout the
globe, is now the main obstacle to the fabrication of RRAM (Lata et al. 2022).
Although RRAM devices have a variety of physical characteristics that appeal to
neuromorphic computing primitives, there are currently a number of technological
barriers preventing their widespread implementation for memory and computing.
Programming and read variations impose significant technological restrictions that
restrict the dependable and replicable storage of data.

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Chapter 13
Spin Field-Effect Transistor: For Steep
Switching Behavior

Karumuri Srinivasa Rao, K. Rohith Sai, Kondavitee Girija Sravani,

and Aime Lay-Ekuakille

Abstract With regard to the development of semiconductor technology, SFET

becomes an instrument aimed at satisfying the needs in equipment with steep
switching characteristics. SFETs utilize the spin degree of freedom for electrons
and spin currents unlike in case of FETs that comprise of traditional. In this section,
we outline the design principles of the SFET with particular emphasis on its special
features that are related to voltage and current waveforms that lead to steep switch-
ings. Instead, leveraging on the same concept of spin injection and manipulation, the
SFET switches rapidly between ON and OFF modes. The high intrinsic spin func-
tionality leads to reduced electron scattering resulting in enhanced electron mobility
as well as rapid switching speeds. Using the concept of spin property as a basis for
electron opens up new way leading to best performances ever witnessed.

Keywords Spin · Datta-Das · Magnetisation · Manipulation · Spintronics

Introduction

The spin field-effect transistor (Spin-FET) is a masterpiece in electronic devices.

It is the answer to calls for faster, more energy-efficient, and compact electronic
components (Wang et al. 2017; Ahmad Malik et al. 2020; Liu et al. 2008; Cahay and
Bandyopadhyay 2003). Achieving astonishing levels of performance, this extraor-
dinary technology harnesses the inherent properties of electron spin, alongside its
charge, to produce a distinctively sharp switching behavior (Sverdlov et al. 2014;

K. Srinivasa Rao (B) · K. Rohith Sai · K. Girija Sravani

Department of ECE, VLSI-Microelectronics Research Center, KL University, Vaddeswaram,
Guntur, Andhra Pradesh 522502, India
e-mail: [email protected]
A. Lay-Ekuakille
Department of Innovation Engineering, University of Salento, Via Monteroni, Ed “Corpo O”,
73100 Lecce, Italy

© The Author(s), under exclusive license to Springer Nature Singapore Pte Ltd. 2024 307
S. Singh et al. (eds.), Beyond Si-Based CMOS Devices, Springer Tracts in Electrical and
Electronics Engineering, https://doi.org/10.1007/978-981-97-4623-1_13
308 K. Srinivasa Rao et al.

Pramanik et al. 2005; Osintsev et al. 2011a). For decades, electron charge manip-
ulation via field-effect transistors (FETs) has been essential to modern electronics,
serving as a foundational component of these devices (Osintsev et al. 2011b; Sverdlov
et al. 2015; Sverdlov and Selberherr 2015; Gao et al. 2010). An ever-growing need for
transistors that can switch quickly and use minimal power exists due to the shrinking
size and increasing complexity of electronic devices (Pramanik et al. 2003; Sugahara
et al. 2016; Bandyopadhyay and Cahay 2013; Sverdlov and Selberherr 2023). The
Spin-FET brings a groundbreaking perspective by making use of the natural angular
momentum of electrons, which we call “spin,” in addition to their electric charge
(Osintsev et al. 2012; Boudine et al. 2015; Liu et al. 2007; Tang et al. 2015). Unlike
regular FETs, which depend solely on the flow of charge carriers through a semicon-
ductor channel, the Spin-FET operates by leveraging the direction of electron spins as
its main control mechanism. This remarkable characteristic allows for exceptionally
sharp and rapid switching behavior. As such, it exhibits considerable promise for a
wide range of applications, such as quantum computing, ultra-fast data storage, and
high-frequency signal processing (Davidson 2007; Zografos et al. 2019; Zhu et al.
2021; Chappert and Barthélémy 2007).
We have thoroughly explored the creation of the spin field-effect transistor
(Spin-FET) and the intriguing field of spin-based electronics in this chapter (Wang
et al. 2018; Johnson 2003; Salis 2013; Mohota and Nemade 2016). We started
our adventure by delving deeply into the fundamentals of spin, covering ideas like
angular momentum and ferromagnetism. We next delved into the intricate dynamics
governing magnetization, which laid the foundation for comprehending the signif-
icance of anisotropy in spin-related phenomena as well as the Landau–Lifshitz–
Gilbert equation. Next, we discussed the idea of spin-transfer torque and its impor-
tance in the context of spin-based devices (Johnson et al. 2010). When we moved
to the field of semiconductors, we discovered the fundamentals of spin transport,
the effective spin–orbit Hamiltonian, and the fascinating spin–orbit interaction that
takes place in the semiconductor channel. Additionally, we investigated the important
subject of spin relaxation, focusing specifically on D’yakonov–Perel’ spin relaxation.
We began by introducing the Spin-FET and going over some of its basic ideas, such
as the Datta–Das Spin-FET model, nanomagnetic logic, tunnel magneto resistance,
and several spin-based logic ideas, such as the innovative idea of All-Spin Logic.
In summary, we presented the most recent developments in spin-based electronics,
such as the creation of the two-dimensional Spin-FET transistor and the novel spin
field-effect transistor with a graphene channel, to wrap up our investigation.
These astounding developments highlight how spin-based technology has the
power to fundamentally alter the field of contemporary electronics.
13 Spin Field-Effect Transistor: For Steep Switching Behavior 309

Spin Basics

Spin-FET uses a spin-polarized source (or) gate to control the flow of electrons
instead of external fields. In this transistor, the key idea is to manipulate the spin of
electrons in a way that enables efficient and precise control of current flow.
Working:
Spin Injection: To initiate the current flow, spin-polarized electrons are injected into
the device (mainly source). Spin-polarized electrons are electrons that are already in
a specific spin state.
Spin Manipulation: In this device, the spins are manipulated using spin–orbit
coupling (or) magnetic fields. Spin orbital coupling arises when interaction between
electron spin and orbital motion occurs. These manipulations are used to control the
direction and magnitude of current in the spin field-effect transistor.
Current Control: The Spin-FET can regulate the passage of electrical current by
manipulating the spins of electrons in the channel through the use of the gate terminal
and magnetic fields. Depending on the spin orientation and the applied gate voltage,
it can either permit electrons with specific spins to travel from the source to the drain
or prevent their passage.
Spin Detection: At the output of the device, a spin-sensitive detector is used to
measure the spin of the electrons. These measurements provide the information
about the current flow.

Angular Momentum and Ferromagnetism

Angular momentum:
In classical mechanics, angular momentum is a vector quantity that describes the
rotational motion of an object. It depends on two factors: the object’s moment of
inertia (a measure of how mass is distributed relative to the axis of rotation) and its
angular velocity (the rate of change of the angular position). In quantum mechanics,
angular momentum takes on a different form due to the wave–particle duality of
matter. In addition to the orbital angular momentum associated with the motion of
particles around an atomic nucleus, there exists another form of angular momentum
called “intrinsic angular momentum” or simply “spin.”
Ferromagnetism:
Ferromagnetism in spin field-effect transistors (SpinFETs) is a fascinating
phenomenon that utilizes the inherent spin properties of electrons to drive advance-
ments in data storage and processing technologies. Within a SpinFET, the magnetic
orientations of electron spins play a critical role in determining the device’s behavior.
310 K. Srinivasa Rao et al.

In materials exhibiting ferromagnetic characteristics, a significant proportion of elec-

tron spins align in a parallel manner, resulting in a robust net magnetic moment. This
alignment can be manipulated and regulated in SpinFETs through the application of
voltage or external magnetic fields, offering precise control. This controllability paves
the way for the creation of innovative spintronic devices like non-volatile memory
and efficient spin-based logic gates. Ultimately, this technology promises faster,
more energy-efficient, and versatile electronic solutions with potential applications
in both traditional computing and emerging quantum computing domains. Ferro-
magnetism in SpinFETs is thus positioned at the forefront of contemporary materials
science and electronics research, offering promising pathways for the evolution of
next-generation computing and data storage systems.

Magnetization Dynamics and the Landau–Lifshitz–Gilbert

Equation

Magnetization dynamics and the Landau–Lifshitz–Gilbert (LLG) equation serve

as fundamental principles in the exploration of magnetism and the properties of
magnetic materials. They play a pivotal role in elucidating the manner in which
magnetic moments, characterized by the magnetization vector, change over time in
reaction to external fields and various influencing factors.
Magnetization Dynamics:
M represents the total magnetized moment in a material substance per unit volume.
These tiny magnetic moments resemble dancers in a choreographed show. The
dancers are usually associated with electron’s spins which exist inside a certain mate-
rial. These moments are what make a story and how they come together, move or
alter through time. A variety of factors, such as the interaction between the moments,
temperature changes, or the input of an external magnetic field, might cause such a
change.
The Landau–Lifshitz–Gilbert Equation:
The Landau–Liftshits Gilbert equation, which depicts the evolution of the magne-
tization vector over time, is one of the most significant formulas in the study of
magnetism. Three well-known physicists created this equation in the middle of the
twentieth century: Lev Landau, Evgeny Lifshitz, Gilbert Theodore, and others. As a
result, this work has become a cornerstone of the field’s study of magnetic phenomena
and materials, providing a wealth of knowledge on how magnetization behaves in
response to external magnetic fields and related effects.
In its most basic form, the LLG equation can be expressed as follows:

dM /dt = −γ M × Heff + αM × dM /dt

To elucidate the symbols used:

13 Spin Field-Effect Transistor: For Steep Switching Behavior 311

• The rate at which magnetization vector M changes with respect to time t is

indicated by dM/dt.
• γ is one of the most important basic constants in nature representing the relation
between the magnetic moment and angular momentum of the electron.
• Magnetization vector is denoted by M, indicating magnetic moment per volume
in material.
• H eff stands for the effective magnetic field experienced by the magnetization,
encompassing contributions from external applied fields, demagnetization fields,
and exchange interactions within the material.
• α constitutes the Gilbert damping parameter, a measure of the strength of damping
or dissipation in the dynamics of magnetization.
The LLG equation holds significant implications across diverse aspects of
magnetism and spintronics. This includes its utility in comprehending ferromag-
netic materials, magnetic data storage, and the development of magnetic devices. It
elucidates the phenomenon of magnetization precession around the effective field
and how this precession gradually loses energy due to the influence of the damping
parameter α.

Anisotropy

Anisotropy in the domain of materials science and physics pertains to a property

exhibited by a material wherein it demonstrates different characteristics or behav-
iors when measured along different directions. This phenomenon can manifest
in diverse forms, encompassing magnetic anisotropy, crystallographic anisotropy,
thermal anisotropy, and other variations.
Magnetic Anisotropy:
Magnetic anisotropy characterizes magnetic materials’ property wherein their
magnetic behavior, encompassing aspects like the orientation of magnetization or
their response to an external magnetic field, varies based on the direction in which
the measurement is conducted. Understanding magnetic anisotropy holds paramount
importance in numerous applications, including data storage and magnetoelectronics.
Distinct types of magnetic anisotropy include:
Shape Anisotropy: This arises from the physical shape of a magnetic material. For
instance, a magnetic particle that is elongated and slender will exhibit dissimilar
magnetic properties along its length compared to its width.
Crystalline Anisotropy: In crystalline materials, the arrangement of atoms or ions
within the crystal lattice can give rise to anisotropic magnetic behavior. Specific
crystallographic directions may display more pronounced or weaker magnetic
properties.
312 K. Srinivasa Rao et al.

Magnetoelastic Anisotropy: This form of anisotropy emerges from the interac-

tion between magnetic and mechanical characteristics. When a material undergoes
deformation, its magnetic properties can undergo directional changes.
Stress-Induced Anisotropy: The application of stress or strain to a material can
also induce anisotropy in its magnetic behavior. This is particularly relevant in
magnetostrictive materials.

Spin-Transfer Torque

Spin-transfer torque (STT) is a concept within the field of spintronics, a branch

of electronics that leverages both electron charge and intrinsic spin properties.
STT involves manipulating electron spin orientation to control electrical current
in magnetic materials, with critical applications in magnetic data storage, including
magnetic random-access memory (MRAM) and emerging technologies.
The workings of spin-transfer torque:
Electron Spin: Electrons have inherent characteristics: charge and spin, with spin
being an intrinsic angular momentum that can assume either an “up” or “down”
orientation.
Magnetic Materials: Certain materials, like ferromagnetic or ferromagnetic ones,
exhibit magnetization, representing the collective alignment of electron spins within
the material.
Spin-Polarized Current: When an electron current traverses a magnetic material,
electrons from different sources possess specific spin orientations (“up” or “down”).
This induces a flow of spin-polarized electrons within the material.
Spin–Orbit Interaction: As these spin-polarized electrons traverse the material,
they subtly interact with atomic magnetic moments (spins) due to the spin–orbit
interaction.
Spin-Transfer Torque: In this interaction, the spin-polarized electrons can gently
exert torque on atomic magnetic moments, causing them to subtly process or alter
their orientation. This torque is tactically employed to manipulate the magnetization
direction of the magnetic material.
13 Spin Field-Effect Transistor: For Steep Switching Behavior 313

Spin in Semiconductor Technology

Spin Transport

Spin transport, a phenomenon at the forefront of modern physics and materials

science, involves the propagation of electron spin information without artificial detec-
tion mechanisms interfering with its course. In the quantum region, electrons possess
intrinsic angular momentum or spin, akin to tiny compass needles. Understanding and
harnessing this property has opened new avenues for the development of spintronic
devices. Unlike conventional electronics that rely solely on the charge of electrons,
spintronics utilize both charge and spin, making them highly energy-efficient and
promising for future technology.
The smooth transmission of spin-related data across different materials and inter-
faces by no other than outside influences is called spin transport. This is exception-
ally essential especially with regards to applications such as magnetic data storage
and spin-based computing. Materials such as the ferromagnets, semiconductors,
and topological insulators are key ingredients that make for efficient spin trans-
port. Driving spin current can take place in the number of ways that spin–orbit
interaction is one among others.
At the heart of spin transport lies a real promise to revolutionize the world of infor-
mation storage and processing devices. Spintronic devices may have higher speed,
lower power consumption, and greater data capacity than conventional devices. This
research has been going on continuously for now in search for other materials plus
strategies to enhance spin transferring efficiency and ability to control, so as to take
the world forward into another age for quantum computing and electronics with
spinning electrons. The answer lies in this area that opens new generations of our
virtual life without any artificial interference.

Effective Spin–Orbit Hamiltonian

In particular, atomic and molecular physics rely heavily on this spin–orbit Hamil-
tonian. It is responsible for capturing the fine linkage of an electron’s inherent spin
angular momentum and its orbital spin, in which the latter originates from the effects
of relativity attached to the motion of the former and its electric charges interac-
tions. It is possible to use the most effective spin–orbit Hamiltonian in order to provide
a reasonable model of this phenomenon. This Hamiltonian has several advantages
such as the ability to determine the atomic/molecular energies and properties.
The effective spin–orbit Hamiltonian can be expressed as follows:

H_SO = ξ (L · S)

Here:
314 K. Srinivasa Rao et al.

• H_SO denotes the effective spin–orbit Hamiltonian.

• ξ stands for the spin–orbit coupling constant, which varies depending on the
specific element or molecule being studied.
• L represents the orbital angular momentum operator.
• S represents the spin angular momentum operator.
Essentially, this Hamiltonian accounts for the interaction between an electron’s
orbital angular momentum (L) and its spin angular momentum (S). The strength of
this interaction is quantified by the dot product between L and S, with the value of ξ
determining the magnitude of the spin–orbit coupling for a given atom or molecule.

Spin–Orbit Interaction in the Semiconductor Channel

The spin–orbit interaction within a semiconductor channel is a fundamental

phenomenon resulting from the interplay between an electron’s spin and its orbital
movement as it traverses the crystalline structure of the semiconductor material. In
semiconductors like silicon or gallium arsenide, this interaction exerts a substan-
tial influence on the material’s electronic characteristics and assumes a vital role in
contemporary electronic devices. This interaction causes the energy levels of elec-
trons with different spin orientations to split, thereby creating distinct energy bands
for spin-up and spin-down electrons. This phenomenon holds significant relevance in
the field of spintronics, an area dedicated to manipulating electron spin for purposes
of information processing and storage. Engineers and scientists harness the spin–
orbit interaction within semiconductor channels to design spin-based transistors, spin
valves, and innovative electronic components, all of which offer promising avenues
for advancing information technology and computing. Therefore, comprehending
and managing the spin–orbit interaction is indispensable for the evolution of future
semiconductor devices, enhancing their functionality.

D’yakonov–Perel’ Spin Relaxation

D’yakonov–Perel’ spin relaxation, named after its originators I. D’yakonov and V. I.

Perel’ in the 1970s, is a phenomenon within condensed matter physics that explains
how the spin angular momentum of electrons in a solid-state system loses coher-
ence due to various scattering mechanisms. To comprehend D’yakonov–Perel’ spin
relaxation, it is crucial to grasp the concept of electron spin, which is an intrinsic
angular momentum associated with their magnetic properties. Think of electron
spin as a minuscule magnetic “arrow” pointing in either an “up” or “down” direc-
tion. Preserving and manipulating electron spin is essential for technologies like
spintronics and quantum computing.
13 Spin Field-Effect Transistor: For Steep Switching Behavior 315

In solid-state systems like semiconductors or metals, electrons encounter various

scattering processes due to imperfections in the crystal lattice or interactions with
impurities. These scattering events alter the momentum and energy of electrons,
consequently affecting their spin orientations. D’yakonov–Perel’ spin relaxation
specifically focuses on the mechanisms responsible for the loss of coherence in
electron spins when they interact with these scattering processes. The importance of
D’yakonov–Perel’ spin relaxation becomes evident in its influence on spin-related
phenomena in solid-state devices. For instance, in the field of spintronics, where
electron spin is utilized for information processing, a longer T1 time is highly
sought after to uphold spin coherence and guarantee the reliability of spin-based
operations. Consequently, scientists and engineers strive to comprehend and manage
D’yakonov–Perel’ spin relaxation, aiming to enhance the efficiency of spintronic
devices and investigate potential applications in quantum computing and data storage.

Spin-FET

A spin field-effect transistor (Spin-FET), sometimes called a spintronic field-effect

transistor, represents an innovative departure from the conventional field-effect tran-
sistor (FET) which is shown in Fig. 13.1. It harnesses not only the electrical charge
of electrons but also their inherent spin to control the flow of electrical current.
Spintronics, a sub-field within the field of electronics known as “spin transport elec-
tronics,” takes advantage of the intrinsic spin property of electrons in conjunction
with their charge. This approach presents some really promising benefits, like using
less power, processing data more quickly, and improving the capacity for storing
information compared to regular electronic devices.
Understanding the concept of a Spin-FET requires us to delve into the fascinating
realm of electron spin. Electron has an interesting attribute other than being nega-
tively charged; it is called spin. These little compass needles inside electrons do
not indicate north but instead, they point in different directions. The electron spin
is a quantum property similar to an inner rotation (a magnet itself) that results in a
magnetic moment. This makes it even more difficult in our comprehension of the
subatomic particles. Now, electrons can be in one of two possible spin states: “up”
or “down,” usually denoted with + 1/2 and − 1/2, respectively. Spin states consti-
tute an integral part of quantum physics and greatly inform us about the magnetism

Fig. 13.1 The structure of Spin-FET

316 K. Srinivasa Rao et al.

of material. Engineers and physicists use these spin states in the world of Spin-
FETs creating a way for better performing and efficient devices. This is just like
harnessing the direction in which tiny compass needles orient their needle ends to
control electron movements and that is an entirely new concept in the electronics
field.
Basically, Spin-FET is based on the notion that instead of charge, one can use
spin of electrons of semiconductor channel to control electric currents. It shares
the traditional FETs structuring scheme—source, channel, and drain—although the
operation principle is very different. Hence, in an ordinary FET, you regulate the
current by varying the charge on a gate electrode. However, a SpinFET proceeds in
another way. Unlike conventional field-effective devices, it employs a combination
of electric and magnetic fields to control spin orientation of electrons within the
channel. This ingenious use of magnetic influences introduces a novel dimension
to semiconductor device functionality. By manipulating electron spin in addition
to charge, Spin-FETs offer the potential for advanced functionalities in electronics,
including enhanced data processing and energy efficiency, paving the way for cutting-
edge applications in various technological domains.
The foremost benefit offered by Spin-FETs lies in their potential for non-volatile
operation with extremely low power consumption. These devices hold great promise
for various applications such as spin-based logic devices, magnetic memory solu-
tions, and the domain of quantum computing. It is important to note that spintronics
technologies are currently in a phase of active research and development. Practical
applications are continually unfolding as scientists and engineers look into inno-
vative approaches to leverage the distinctive characteristics of electron spin within
Spin-FETs and other spintronic devices.
To understand the Spin-FET, let us break down the key components:
Electron Spin: Electron has two properties, namely charge and spin. Spin is a
quantum mechanical property which is also said to be the angular momentum of
the electron. Electron has two types of spin up and down. This corresponds to a
magnetic moment aligned in a specific direction.
Spintronics: Spintronics is short form of spin transport electronics. This is a field
within electronics that seeks to harness both the charge and spin properties of elec-
trons for a range of applications. It distinguishes itself from conventional electronics,
which exclusively depend on devices driven by electrical charge.
Field-Effect Transistor (FET): A standard field-effect transistor (FET) is a semi-
conductor component that manages the passage of electric current through the manip-
ulation of an external electric field. It comprises three key terminals: source, drain,
and gate. The application of voltage to the gate terminal enables you to regulate the
current flow between the source and drain terminals.
Advantages:
• Low power consumption
• Data storage capability.
13 Spin Field-Effect Transistor: For Steep Switching Behavior 317

Challenges:
• Difficult to fabricate
• Spin coherence.
Types of Spin-FETs:
1. Datta–Das Spin-FET
2. Graphene-based Spin-FET.
Semiconductor heterostructures.

Datta–Das Spin-FET Model

The Datta–Das spin field-effect transistor (Datta–Das Spin-FET) is a theoretical

design for a spintronic transistor that was introduced by Supriyo Datta and Biswajit
Das in 1990. It constitutes a pivotal concept in the field of spintronics, which focuses
on utilizing the intrinsic spin property of electrons to govern and manipulate electrical
current within a semiconductor channel. Below is a comprehensive explanation of
the Datta–Das Spin-FET:
Fundamental Principle:
The Datta–Das Spin-FET is based on the concept of employing spin transport in a
semiconductor conduction. The configuration of Datta–Das Spin-FET is illustrated
in Fig. 13.2. Unlike conventional FETs that operate based on the charge of electrons,
Spin-FETs hinge upon both the charge of electrons and their spins in managing
current flow. The transistor operation hinges on manipulation of electron spin in this
design.
Structure:
Source and Drain Contacts: These serve as the conduits through which electrical
current enters and exits the semiconductor channel.
Semiconductor Channel: Comprising a semiconductor material, such as silicon,
this channel acts as the pathway for electrons to traverse between the source and
drain terminals.
Gate Terminal: Analogous to conventional FETs, the gate terminal is employed to
modulate current flow. However, in the case of Spin-FETs, it is used to manipulate
the spin orientation of electrons within the channel.

Fig. 13.2 Structure of

Datta–Das Spin-FET Fm Fm
Sc
318 K. Srinivasa Rao et al.

Magnetic Contacts or Magnetic Fields: In the Datta–Das design, one or more

ferromagnetic contacts are employed to generate a spin-polarized current. These
contacts facilitate the injection of electrons with a specific spin alignment into the
semiconductor channel.
Working:
Spin Injection: Spin-polarized electrons are introduced into the semiconductor
channel from the ferromagnetic source contacts. Spin polarization implies that a
majority of electrons possess their spins aligned in a particular direction, such as
“up” or “down.”
Spin Manipulation: Upon entry into the channel, spin-polarized electrons undergo
spin–orbit interactions and experience Zeeman splitting (induced by an applied
magnetic field or the presence of magnetic materials). These interactions enable
the manipulation of electron spin orientations.
Current Regulation: By manipulating electron spins within the channel using the
gate terminal and magnetic fields, the Spin-FET can govern the passage or obstruction
of electrons with specific spin orientations from the source to the drain, contingent
upon the spin orientation and gate voltage.
Output Detection: At the drain end, a spin-sensitive detector may be employed
to gauge the spin properties of the electrons that have traversed the channel. This
measurement yields information about the current flow through the device.
Advantages and Applications:
Enhanced Energy Efficiency: Spin-based devices can exhibit superior energy effi-
ciency compared to traditional charge-based devices, as they can operate with reduced
energy dissipation.
High-Speed Performance: Electron spin manipulation can transpire rapidly,
enabling high-speed switching.
Spintronic Logic and Memory: Spin-FETs could find utility in spintronic logic
circuits and non-volatile memory devices.
Challenges and Ongoing Research:
The Datta–Das Spin-FET concept has engendered substantial research interest in
the domain of spintronics. Nonetheless, practical implementation faces challenges,
including the preservation of spin coherence over longer distances and at higher
temperatures, as well as achieving efficient spin injection and detection.

Nanomagnetic Logic

Nanomagnetic logic, often abbreviated as NML, stands out as a burgeoning and

highly promising technology within the domain of nanoelectronics. It signifies a
13 Spin Field-Effect Transistor: For Steep Switching Behavior 319

groundbreaking approach to computing by exploiting the inherent characteristics

of magnetic materials on the nanoscale. Diverging from traditional semiconductor-
based logic gates, which rely on electrical currents, NML operates by manipulating
the magnetic alignment of individual nanomagnets to execute logical operations.
This pioneering methodology offers numerous advantages, including reduced power
consumption, non-volatility, and the potential for exceedingly compact and energy-
efficient computing devices.
At the core of nanomagnetic logic lies the nanomagnet, a minute structure typi-
cally composed of ferromagnetic materials like iron or cobalt. These nanomag-
nets can assume diverse shapes and configurations, and their magnetic state can
be controlled through external magnetic fields or interactions with neighboring
nanomagnets. By skillfully arranging and manipulating these nanomagnets, intri-
cate logic functions can be achieved, enabling the design of logic gates and circuits.
A paramount advantage of nanomagnetic logic lies in its potential for achieving ultra-
low power consumption. In stark contrast to conventional transistors that necessi-
tate a continuous flow of electrical current to maintain their state, nanomagnets
retain their magnetic orientation without the need for a constant power supply. This
inherent property renders NML exceptionally well-suited for applications where
energy efficiency holds paramount importance, such as in portable electronic devices
and environments with limited energy resources.
Moreover, nanomagnetic logic boasts non-volatility, signifying that once a
magnetic state is established, it remains steadfast even when the power source is
deactivated. This characteristic renders it particularly appealing for applications such
as non-volatile memory and instant-on computing, where data retention and rapid
startup times are critical.

Tunnel Magnetoresistance

Tunnel magnetoresistance (TMR) is a phenomenon that occurs when the elec-

trical resistance of a magnetic tunnel junction (MTJ) undergoes significant changes
based on the relative alignment of magnetization in two magnetic layers sepa-
rated by a thin insulating barrier. This effect serves as a fundamental principle in
numerous contemporary magnetic data storage and sensor technologies, including
magnetic random-access memory (MRAM) and magnetic sensors used across
various applications.
Here is a breakdown of how TMR operates:
Magnetic Tunnel Junction (MTJ): At its core, an MTJ comprises two ferromag-
netic layers separated by a thin insulating layer. One of these ferromagnetic layers
typically features a fixed magnetization direction, while the other possesses a free
magnetization direction that can be influenced by an external magnetic field.
Electron Tunneling: It is a fascinating process in which, thanks to the quirks of
quantum mechanics, electrons can pass through the insulating barrier inside the
320 K. Srinivasa Rao et al.

magnetic tunnel junction (MTJ), even though that barrier material usually prevents
such movement. Whether tunneling happens or not depends on the energy levels of
the electrons and how their spins are aligned in the magnetic layers.
Tunneling Current: When the magnetizations of the two ferromagnetic layers are
parallel (meaning their magnetic moments are aligned in the same direction), there is a
greater likelihood of electrons tunneling through the barrier. This results in a decrease
in the electrical resistance of the MTJ. Conversely, when the magnetizations are
antiparallel (with magnetic moments aligned in opposite directions), the probability
of tunneling decreases, leading to an increase in electrical resistance.
Resistance Change: The ratio of resistance between the parallel and antiparallel
configurations is referred to as the TMR ratio. This ratio can be quite substantial, often
surpassing 100% or more. This high TMR ratio renders TMR devices exceptionally
sensitive to alterations in the relative magnetic orientation of the layers.
Tunnel magnetoresistance plays a pivotal role in advancing various technologies
reliant on magnetic properties, offering fresh possibilities for data storage and sensing
applications.

Spin-Based Logic Concepts

Spin-based logic is a branch of quantum computing research that leverages the

quantum property of electron spin for information processing and computation. It
holds the potential to solve specific problems much faster than classical computers.
Here are some fundamental concepts in spin-based logic:
Spin: Spin is an inherent property of elementary particles like electrons, akin to
intrinsic angular momentum. Electrons can exist in one of two spin states: “spin up”
(often represented as ↑) or “spin down” (typically denoted as ↓).
Spin Qubit: In quantum computing, a quantum bit or qubit can be realized using
electron spin. These qubits can represent classical 0 and 1 states as well as exist in
superpositions, a core feature of quantum computing.
Spin Manipulation: Spin-based logic relies on the ability to control the spin states
of electrons. Techniques like electron spin resonance (ESR) and magnetic fields are
employed for this purpose.
Quantum Gates: Think of quantum logic gates as tools used to perform operations
on qubits, which are the building blocks of quantum computing. In the context of
spin-based logic, these gates manipulate the spin states of electrons. One common
gate is the Hadamard gate, which is often used to create superpositions.
Spin Coherence: Spin coherence relates to how long a qubit can maintain its super-
position state without losing its quantum properties due to the effects of decoherence.
It is crucial to preserve spin coherence for reliable spin-based quantum computing.
13 Spin Field-Effect Transistor: For Steep Switching Behavior 321

Entanglement: In the realm of spin-based qubits, entanglement is a fascinating

phenomenon. When qubits become entangled, the state of one qubit becomes inter-
twined with that of another, irrespective of their physical separation. This property
is vital for quantum computing algorithms.
Decoherence: Decoherence is the undesirable process by which quantum properties,
like superposition, are lost due to interactions with the surrounding environment. It
is a significant challenge in the field of spin-based logic and quantum computing in
general.
Quantum Algorithms: Quantum computers, including those based on spin qubits,
have the potential to solve certain problems exponentially faster than classical
computers. Notable examples are Shor’s algorithm, used for factoring large numbers,
and Grover’s algorithm, which excels at searching unsorted databases.
Spintronic Devices: Quantum computed goes beyond spin-based logic. Classical
computing uses the spin of electrons to store and manipulate information in so-called
spintronic devices. It also presents a possibility of saving energy as well as enhancing
the throughput of signals compared to the conventional electronic products.
Topological Qubits: Another prospect involves combining spin-based quantum
computers with topological qubits. So-called exotic qubit is based on electronic
attributes which originate non-locally and are less susceptible to the process of
decoherence.
Quantum Error Correction: Decoherence and other error sources can be corrected
using these error correction codes. At this moment, research on spin-based logic
specific error correction schemes is underway.

All-Spin Logic

This is an innovative concept in spintronics and nanoelectronics. It will enhance

the development of powerful and energy-efficient computing gadgets. Instead, this
architecture is based on the intrinsic spin of the electron itself, which can act as an
information carrier for computation. It provides for low power consumption, fast
data processing, and flexibility in scaling—all very attractive qualities that are sure
to shape the future of digital technology today.
At the core of All-Spin Logic lies a fundamental principle: manipulation and
transmission of spintronic-based information with spin valves and magnetic tunnel
junctions. These devices use the magnetic nature of materials to orient electron spins,
which results in spin currents that can be used for logic functions. Spintronics differs
from traditional charge-based electronics by using the property of conserving spin.
By utilizing this, it leads to a considerable decrease in energy consumption.
Moreover, All-Spin Logic holds significant promise for seamless integration with
emerging technologies like quantum computing and neuromorphic computing. Its
capability to store and process information using spins rather than conventional bits
322 K. Srinivasa Rao et al.

positions it ideally for quantum computing qubits, which also hinge on the princi-
ples of quantum spin states. Additionally, the neuromorphic computing paradigm,
inspired by the human brain, can harness the energy efficiency and parallel processing
capabilities that All-Spin Logic offers, paving the way for more efficient applications
in artificial intelligence and cognitive computing.

Two-Dimensional Spin-FET Transistor

Two-dimensional spin field-effect transistor is a hypothetical or emerging electronic

device that combines the principles of spintronics and 2D materials to control the
flow of electron spins for information processing. Figure 13.3 shows the structure of
2D Spin-FET.
Spintronics: Spintronics is a field that explores how to manipulate the inherent
spin of electrons alongside their charge for various electronic applications. This
approach differs from traditional electronics, which primarily rely on electron charge.
2D Materials: Two-dimensional (2D Spin-FETs); where a 2D material is used as
an electron channel. For instance, one can cite a notable instance of one layer carbon
arrangement in a hexagonal grid, known as graphene. Additionally, there exist other
2D materials such as TMDS that can act as conduits for the devices.
Spin Transport: Information is transferred and processed by using spins of electrons
in 2D Spin-FETs. Electrons have two spin states: In this case, the term “spin” will
mean upward (“up”) or downward motion (down). Thus, the spin state in such devices
can be used as a bit representation mechanism that differs from the conventional
charge-based ones.
Gate Control: Just like conventional FETs, Spin-FETs have a gate that helps in
controlling the movement of electrons in the semiconductor channel. The switching
on/off and amplification of spin current can be controlled by applying voltage to the
gate, thereby increasing channel conductance.
Applications: It is believed that 2D Spin-FETs can be applied in non-volatile memo-
ries, logic gates, and low power electronics. The particular interest in spin based QC
technologies and most importantly they are very exciting.
Challenges: The practical implementation of Spin-FETs comes with several chal-
lenges. These include maintaining electron spin coherence over longer distances and
at room temperature, achieving efficient spin injection and detection, and integrating
these devices into existing semiconductor technology.

Fig. 13.3 Structure of 2d

Spin-FET Gate

Source Channel Drain

13 Spin Field-Effect Transistor: For Steep Switching Behavior 323

Spin Field-Effect Transistor with a Graphene Channel

Let us delve into the world of a hypothetical electronic device known as a graphene-
based spin field-effect transistor (Spin-FET). This device makes clever use of
graphene, a single layer of carbon atoms arranged in a hexagonal lattice, which
possesses exceptional electronic properties, making it an exciting material for various
nanoelectronics and spintronics applications.
In a graphene-based Spin-FET, graphene plays a pivotal role as the semicon-
ductor channel, allowing electrons to move. Here is why graphene is a great fit for
spintronics:
High Electron Mobility: Graphene lets electrons zip around at incredibly high
speeds, making it perfect for high-speed electronic devices.
Adjustable Electronic Properties: You can tweak graphene’s electronic character-
istics by applying an electric field or altering its shape, giving you versatile control
over its conductivity.
Spin Transport: Graphene has shown remarkable ability in transporting electron
spins across significant distances, which makes it a strong contender for spintronic
applications.
Spin Injection: To start, spin-polarized electrons are sent into the graphene channel
from a ferromagnetic source contact. These electrons mostly have their spins aligned
in a specific direction, like “up” or “down.”
Spin Manipulation: Inside the graphene channel, various methods can be employed
to change the orientation of electron spins. This manipulation can involve spin–orbit
interactions, proximity to magnetic materials, or applying external magnetic fields.
Current Control: By manipulating electron spins within the graphene channel using
gate voltages, magnetic fields, or other techniques, the device can selectively allow
or block the flow of electrical current. It is like having a precise control knob for the
flow of electrons, thanks to the unique properties of graphene and the principles of
spin-dependent transport. This opens up exciting possibilities for advanced electronic
applications.
Spin Detection: Spin-sensitive detectors are placed at the drain end and they
provide information about the spin of electrons passing through the graphene
channel. However, it provides much useful background as regards the spin char-
acteristics that are innate in this moment.
324 K. Srinivasa Rao et al.

Conclusions

The experience is based on spin engineered electronics and creating a SpinFET,

which reveals many science theoretical solutions and technologies. At its inception,
we addressed fundamental spiral issues such as angular momentum and ferromag-
netism. Our travel was complicated and involved a path where all this knowledge
about magnetization, as well as, anisotropy are needed for the understanding of its
meaning in spin devices engineering by means of Landau–Lifschitz–Gilbert equa-
tion. In our own ways, we traveled into the labyrinth of spin–spin technology that
spanned from theories to actual practice. We exposed fundamental features of spin
transport and spin–orbit interaction phenomena crucial for contemporary electronics
in the field of semiconductor physics. In general, our study also focused on major
points like spin relaxation in Dzyaloshinski–Moriya spin relaxation. In this case, the
revolution in the mind was a new approach called Spin-FET that reflected the great
improvement of SST. To this end, we looked at its fundamental principles comprising
of Dutt–Das Spin-FET model, nanomagnetic logic, Tunnel MagnetoResistance, and
prospective concepts in spin-based logic, culminating into cutting edge advances
including All-SpinOur journey didn’t stop there we also glimpsed the latest advance-
ments in spin-based electronics, from the Two-Dimensional Spin-FET Transistor to
the game-changing spin field-effect transistor with a graphene channel. These devel-
opments underscore the transformative power of spin-based technology as it reshapes
the landscape of modern electronics. The promise is faster, more energy-efficient,
and compact electronic components, paving the way for the future of technology.

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