3D Integrated Circuits
ABSTRACT
The unprecedented growth of the computer and information technology industries is demanding
very large scale integrated (VLSI) circuits with increasing functionality and performance at minimum
cost and power dissipation. VLSI circuits are being aggressively scaled to meet this demand, which in
turn has some serious problems for the semiconductor industry.
Additionally, heterogeneous integration of different technologies into one single chip (SOC) is
becoming increasingly desirable, for which planar (2D) ICs may not be suitable.
3D ICs are an attractive chip architecture that can alleviate interconnect related problems such
as delay and power dissipation and can also facilitate the integration of heterogeneous technologies in
one chip (SOC). The multi-layer chip industry opens up a whole new world of design. With the
introduction of 3D ICs, the world of chips may never look the same again.
3D Integrated Circuits
TABLE OF CONTENTS
Chapter No. Content Page No
Abstract 1
1. Introduction
1.1 Introduction of Project 3
2. Related works
2.1 Literature survey 4
2.2 Related Background and Concepts 5
3. Methodology 6
3.1 Typical Architecture for 3D integration 7
3.2 3D IC Technologies 8
4. Key Challenges
4.1 Key challenges for 3D integration 10
Conclusion 11
3D Integrated Circuits
CHAPTER – 1
INTRODUCTION
1.1 Introduction
Moore's Law, created by Gordon Moore in 1965, has been the guiding principle for decades in
semiconductor Industry. This law predicted the unrelenting rate of silicon chip miniaturization and
performance enhancement, predicting a doubling of transistor count every two years. For the past thirty
years, chip designers have considered whether building integrated circuits with multiple layers might
create cheaper, more powerful chips.
The performance of deep-submicrometer, very large-scale integrated (VLSI) circuits is being increasingly
dominated by interconnects due to increasing wire pitch and die size. Additionally, heterogeneous
integration of different technologies on one single chip is becoming increasingly desirable, for which
planar (2-D) ICs may not be suitable.
The three-dimensional (3-D) chip design strategy exploits the vertical dimension to alleviate interconnect-
related problems and facilitate heterogeneous integration of technologies to realize a system-on-a-chip
(SOC) design. By simply dividing a planar chip into separate blocks, each occupying a separate physical
level interconnected by short and vertical interlayer interconnects (VILICs), significant improvement in
performance and reduction in wire-limited chip area can be achieved. In the 3D design architecture, an
entire chip is divided into a number of blocks and each block is placed on a separate layer of Si that is
stacked on top of each other.
Fig.1: Schematic diagram of 3D integrated circuit
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3D Integrated Circuits
CHAPTER – 2
RELATED WORKS
2.1 Literature Survey:
Below mentioned are research papers related to 3D integrated circuit, which gives the basic knowledge
about 3D ICs.
Sl.No Authors Title Year of
publication
1 V. Kumar and A. Naeemi An overview of 3D 2017
integrated circuits
2 Muhannad S Bakir, Gang 3D Integrated Circuits: 2009
Huang, Deepak Sekar, and Liquid Cooling and Power
Calvin King Delivery
3 Paul Falkenstern, Yuan Xie, Three-Dimensional 2010
Yao-Wen Chang and Yu Integrated Circuits (3D IC)
Wang Floorplan and Power/Ground
Network Co-synthesis
2.2 Related Background and Concepts
V. Kumar and A. Naeemi, "An overview of 3D integrated circuits,"EEE MTT-S International Conference
on Numerical Electromagnetic and Multiphysics Modeling and Optimization for RF, Microwave, and
Terahertz Applications (NEMO) -2017
This paper presents an overview of three-dimensional integrated circuits (3D ICs) is presented in this paper.
The key potential applications of 3D ICs that have the most impact in terms of performance, power and
area are highlighted, followed by a brief overview of the different technology approaches to implement 3D
ICs. Further, the key challenges to 3D integration are discussed here.
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3D Integrated Circuits
integration technology. The key technology enabler for 3D integration is the TSV, which can be
manufactured with the via-first, via-middle, or via-last processes. Finally, the key
challenges to 3D integration, i.e. heat removal, IC testing and yield improvement, reliability, and power
delivery are discussed.
Muhannad S. Bakir, Gang Huang, Deepak Sekar & Calvin King, 3D Integrated Circuits: Liquid Cooling
and Power Delivery – 2009
In order to address the ever increasing adverse effects of conventional silicon ancillary technologies on the
performance of CMOS nanosilicon technology, this paper describes the implementation of fully compatible
and wafer-level batch-fabricated electrical, optical and fluidic, or ‘trimodal’, interconnects. It is proposed
that the electrical I/Os be used for power delivery and signaling, the optical I/Os for massive off-stack
bandwidth and the fluidic I/Os (with integrated backside heat sink) for heat removal. The trimodal I/Os are
flip–chip compatible making them compatible with current assembly infrastructure and can be extended to
enable the stacking of high-performance (high-power) microprocessors. Liquid cooling for a 3D stack of
high-performance chips is also discussed. Challenges in power delivery are also explored for 3D systems.
The supply current flowing through the microbumps and narrow through silicon-vias (TSVs) may have
large parasitics. This may potentially lead to a large DI noise if stacked chips switch simultaneously. The
relationship between the power supply noise, decap insertion, power/ground I/O allocation and TSVs
allocation are discussed quantitatively. Schemes for reducing the power supply noise in 3D integrated
systems are also proposed and their impacts on future 3D system designs are also emphasized.
P. Falkenstern, Yuan Xie, Yao-Wen Chang and Yu Wang, "Three-dimensional integrated circuits (3D IC)
Floorplan and Power/Ground Network Co-synthesis," 2010
Three Dimensional Integrated Circuits (3D ICs) are currently being developed to improve existing 2D
designs by providing smaller chip areas and higher performance and lower power consumption. However,
before 3D ICs become a viable technology, the 3D design space needs to be fully explored and 3D EDA
tools need to be developed. To help explore the 3D design space and help fill the need for 3D EDA tools,
the 3D Floorplan and Power/Ground (P/G) Co-synthesis tool is developed in this work, which develops the
floorplan and the P/G network concurrently.
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3D Integrated Circuits
CHAPTER- 3
METHODOLOGY
3.1 Typical Architecture for 3D integration:
The most commonly studied architectures for 3D ICs are discussed here.
1. Silicon interposer (2.5D)
Although technically not a true 3D architecture, silicon interposer provides several advantages over
conventional packages. First, very fine pitch wires, similar to on-chip BEOL interconnects can be
patterned on silicon interposers. Second, due to the matched coefficient of thermal expansion between
the chip and silicon interposer, reliable fine pitch micro-bumps can be used as first level interconnect.
As a result, silicon interposers offer a significant bandwidth and energy improvement over conventional
off-chip interconnects.
Fig.2: Schematic diagram of silicon interposer
2. Stacked Memory
Multiple DRAM die are stacked on top of each other, with one logic die at the bottom for control. The
memory stack significantly increases the capacity that can be fit in a given area, whereas the logic die
handles communication with other ICs on the interposer. The two prominent memory architectures for
stacked memory are High Bandwidth Memory (HBM) and Hybrid Memory Cube (HMC) from Micron.
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3D Integrated Circuits
Fig.3: Schematic diagram of stacked memory
3. Memory on Processor
The ability to stack high density DRAM on top of the processor is extremely valuable for several
applications. By minimizing the physical distance between the two communicating ICs, the losses in the
chip-to-chip link can be minimized. Additionally, since Through Silicon Vias (TSVs) can be densely
packed to provide a large bus width, the datarate for operation can be reduced significantly compared to
the conventional IO links that typically operate at tens of GHz. This, in turn simplifies the IO circuits
considerably and minimizes the issues that creep up at higher frequencies.
4. Logic on Logic
The motivation for stacking logic on logic is to reduce the aggregate interconnect length in a large logic
circuit. For example, if a large 2D chip like a microprocessor is 2cm*2cm in dimensions, the overall
interconnect length can be reduced significantly if the microprocessor is partitioned into 4 blocks of
1cm*1cm stacked on top of each other and connected with TSVs. However, the caveat here is that the
communication between the 4 partitions should be limited.
5. Heterogeneous Integration
This is the ultimate holy grail of researchers seeking to integrate multiple technologies stacked together
in a single package. The dream is to one day combine logic, memory, RF, sensor ICs built separately in
the optimal technology within a package. There are several advantages to such a heterogeneous 3D IC
including cost, form factor, performance, IO count reduction, and lower power consumption.
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3D Integrated Circuits
Fig.4: Heterogeneous integration
3.2 3D IC Technologies:
Although 3D integration is a promising new technology with a significant number of potential
applications, it is clear that 3D integration is not trivial to implement. There are several technology
options to choose from, some of which are highlighted in this section.
1. Back-to-Back bonded
3D ICs Through silicon via is the most important component required to enable 3D integration. TSVs
are fabricated using the Bosch process, which is a two-step process including plasma etch and deposition
of passivation layer, repeated multiple times to etch deep via holes.
The following three approaches to fabricating back-to-back bonded 3D ICs have been adopted by the
industry:
Via-First: The TSVs are fabricated before the wafer is taken through any FEOL or BEOL process.
Since the TSVs are fabricated at the beginning, via holes can be etched and filled from the front side,
and wafer thinning can be done at the end to expose TSVs from the backside. The advantage is that TSV
processing will not inadvertently damage any of the devices or interconnects. However, the disadvantage
of this approach is that the TSV has to be taken through the high temperature processing steps for FEOL
and BEOL processing. The mismatch of Coefficient of Thermal Efficient (CTE) between copper and
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3D Integrated Circuits
silicon results in stress being introduced in the silicon substrate. As a result, transistor performance and
reliability are significantly compromised.
Via-Last: The TSVs are fabricated at the end, after all the FEOL and BEOL processing is completed.
Since the FEOL and BEOL processing are done prior to TSV etching, TSVs need to be etched from the
back side after wafer thinning. This process is very attractive from a CTE standpoint, since the TSVs
don’t have to endure high temperature processing.
Via-Middle: This approach combines the best of both worlds - TSVs are processed after FEOL
processing, but before the BEOL processing. This prevents the TSVs suffering through the high
temperature FEOL processing, but improves the TSV contact and BEOL/ILD reliability compared to the
via last process. This approach is popular with many companies in the industry.
2. Face-to-face bonding with micropillars
This approach is very popular for 3D ICs with two ICs in the stack. The two ICs stacked together in a
3D IC can communicate with each other through fine-pitch micro-pillars connecting the pads of one
chip to the other. The integrated 3D IC communicates with the external world through TSVs through the
bottom die. The advantage of this approach is that the parasitics for the chip to chip link are minimized
by using micro-pillars, but the technology is useful mainly for two-stack 3D ICs.
3. Monolithic 3D ICs
Monolithic 3D ICs are theoretically one of the most attractive options available because they would
allow for very short and fine-pitch vias, thus reducing the interconnect parasitics considerably.
Monolithic 3D ICs have the potential to make seamless communication between the different layers of
the 3D IC a reality. However, the high temperature FEOL processing of the second Si layer is expected
to melt the BEOL processed for the first layer. Thus, the research in this area is headed towards low
temperature FEOL processing. Another approach to stack logic on logic is to manufacture NMOS
transistors on the bottom layer and PMOS on the top layer. However, the TSVs connecting NMOS and
PMOS to form logic gates need to have extremely fine pitches in order to minimize parasitic loading on
logic gates.
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3D Integrated Circuits
CHAPTER- 4
KEY CHALLENGES
4.1 Key challenges for 3D Integration:
Given all the potential benefits of 3D integration, it is essential to understand the key challenges that are holding
the technology back from completely disrupting the semiconductor industry. The most critical challenges to the
widespread adoption of 3D integration are discussed here.
1. Heat Removal
The performance of modern electronic chips is primarily limited by their power consumption, and the
effectiveness of the cooling systems. 3D integration makes heat removal harder because the hotspots on the die
farther away from the heat sink are not easily accessible.
2. IC Testing and Yield
Another crucial challenge that impedes the widespread adoption of 3D ICs is the problem of testing them.
Although it is desirable that only the Known Good Die (KGD) are handpicked from wafer level testing and
stacked with other KGD to form different layers of a 3D IC, it is extremely expensive to assemble 3D ICs at the
die level.
3. Reliability
Depending on the process used for TSV fabrication, the reliability of transistors or interconnects on the chip can
be severely impacted. If via-middle process is used, TSVs have to go through high temperature BEOL processing,
resulting in a stress profile that could degrade transistor performance and reliability over time.
4. Power Delivery
Power is delivered to die higher up in the stack through power/ground TSVs that need to be distributed over the
area of the die. Since the performance of each die in the 3D IC is a strong function of the IR drop, a significant
number of TSVs need to be dedicated to power/ground TSVs.
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3D Integrated Circuits
CONCLUSION
From this study, we can understand that 3-D ICs are an attractive chip architecture that can alleviate
interconnect-related problems such as delay and power dissipation and can also facilitate the integration
of heterogeneous technologies on one chip. A brief overview of the 3D integration architectures,
technologies, and critical roadblocks is discussed in the report. A number of applications, including 2.5D
interposers, memory stacks, memory on logic, logic on logic, etc., can benefit tremendously from 3D
integration technology. The key technology enabler for 3D integration is the TSV, which can be
manufactured with the via-first, via-middle, or via-last processes. Finally, the key challenges to 3D
integration, i.e., heat removal, IC testing and yield improvement, reliability, and power delivery, are
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