311242 Digital Logic Design
Lecture8 . MULTI-LEVEL GATE CIRCUITS / NAND AND NOR GATES [Chap. 7]
7.1 Multi-Level Gate Circuits
Four-Level Realization of Z
7.1 Multi-Level Gate Circuits
Three-Level Realization of Z
Z = ( AB + C )[(D + E ) + FG ] + H = AB(D + E ) + C (D + E ) + ABFG + CFG + H
7.1 Multi-Level Gate Circuits
Example : Multi-Level Design Using AND and OR Gates
f (a, b, c, d ) = m(1,5,6,10,13,14 )
Two-level AND-OR gate
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7.1 Multi-Level Gate Circuits
f = acd + bcd + bcd + acd = cd (a + b ) + cd (a + b )
Three-level OR-AND-OR gate From 0s on the Karnaugh map
f = cd + abc + cd + abc
f
f = (c + d )(a + b + c )(c + d )(a + b + c)
Two-level OR-AND gate
7.1 Multi-Level Gate Circuits
Using ( X + Y )( X + Z ) = X + YZ
f = [c + d (a + b )] [c + d (a + b )]
If we multiply out d (a + b ) and d (a + b )
f = (c + ad + bd )(c + ad + bd )
f = c(d + ab) + c(d + ab) = c(d + a )(d + b) + c(d + a)(d + b)
Three-level AND-OR-AND gate
7.2
NAND and NOR Gates
NAND gate
F = ( ABC ) = A + B + C
F = (X1 X 2 K X n ) = X1 + X 2 + K + X n
7.2
NAND and NOR Gates
NOR gate
F = ( A + B + C ) = ABC
F = (X1 + X 2 + K + X n ) = X1 X 2 K X n
OR realized by using AND and NOT
7.2
NAND and NOR Gates
NAND gate realization of NOT, AND, and OR
AND realized by using OR and NOT
XY = ( X + Y )
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7.3
Design of Two-Level Circuits Using NAND and NOR Gates
DeMorgans laws
( X 1 + X 2 + K + X n ) = X 1 X 2 K X n
( X 1 X 2 K X n ) = X 1 + X 2 + K + X n
Conversion of a sum-of-products to several other two-level forms
F = A + BC + BCD = ( A + BC + BCD ) = A (BC ) (BCD ) = [A (B + C ) (B + C + D)] = A + ( B + C ) + ( B + C + D )
AND-OR NAND-NAND OR-NAND NOR-OR
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7.3
Design of Two-Level Circuits Using NAND and NOR Gates
F = A + (B + C ) + (B + C + D )
NOR-NOR-INVERT
F = ( A + B + C )( A + B + C )( A + C + D ) =
OR-AND
{[ (A + B + C )(A + B + C)(A + C + D)]}
= ( A + B + C ) + ( A + B + C ) + ( A + C + D ) = ( ABC + ABC + ACD) = ( ABC ) ( ABC ) ( ACD)
NOR-NOR AND-NOR NAND-AND
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7.3
Design of Two-Level Circuits Using NAND and NOR Gates
Eight Basic Forms for Two-Level Circuits
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7.3
Design of Two-Level Circuits Using NAND and NOR Gates
NAND-NOR
AND-OR to NAND-NAND Transformation
F = l1 + l2 + K + P + P2 + K = l1 l2 L P P2 L 1 1
(l1 ,l2 K) : literals
(P1 , P2 K) : product terms
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7.4
Design of Multi-Level NAND- and NOR-Gates Circuits
Procedure : multi-level NAND-gate circuits - Simplify the switching function - Design a multi-level circuit of AND and OR gates - Number the levels starting with the output gate as level 1 - Replace all gates with NAND gates, leaving all interconnections between gates unchanged - Leave the inputs to levels 2,4,6, unchanged
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7.4
Design of Multi-Level NAND- and NOR-Gates Circuits
Example : Multi-Level Circuit Conversion to NAND Gates
F1 = a[b + c(d + e) + f g ] + hij + k
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7.5
Circuit Conversion Using Alternative Gate Symbols
Inverter
Alternative Gate Symbols
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7.5
Circuit Conversion Using Alternative Gate Symbols
NAND Gate Circuit Conversion
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7.5
Circuit Conversion Using Alternative Gate Symbols
Conversion to NOR Gates
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7.5
Circuit Conversion Using Alternative Gate Symbols
Conversion of AND-OR Circuits to NAND Gates
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7.6
Design of Two-Level,Multiple-Output Circuits
Example : Design a circuit with four inputs and three outputs
F1 ( A, B, C , D ) = m(11,12,13,14,15)
F2 ( A, B, C , D ) = m(3,7,11,12,13,15)
F3 ( A, B, C , D ) = m(3,7,12,13,14,15)
Karnaugh Maps for Equations
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7.6
Design of Two-Level,Multiple-Output Circuits
Realization of Equations
Multiple-Output Realization of Equations
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7.6
Design of Two-Level,Multiple-Output Circuits
Example : Design a multiple-output circuit with 4-inputs and 3-outputs
f1 = m(2,3,5,7,8,9,10,11,13,15) f 2 = m(2,3,5,6,7,10,11,14,15) f 3 = m(6,7,8,9,13,14,15)
Karnaugh Maps for Equations
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7.6
Design of Two-Level,Multiple-Output Circuits
Minimized equations
f1 = bd + bc + ab f 2 = c + abd abd 10gates, f 3 = bc + abc + or 25gate input acd
The minimal solution
f1 = abd + abd + abc + bc f 2 = c + abd f 3 = bc + abc + abd
8 gates 22 gate inputs
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7.6
Design of Two-Level,Multiple-Output Circuits
Determination of Essential Prime Implicants for Multiple-Output Realization
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7.7
Multiple-Output NAND and NOR Circuits
Multi-level Circuits Conversion to NOR Gates
F1 = [(a + b)c + d ] (e + f )
F2 = [(a + b)c + g ] (e + f )h
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