Contents 1. Introduction to 8085 and 8086 Microprocessors 2. 8085 Programming 3. Interfacing ICs .Description Sheet MICROPROCESSORS Chapter-1 : Introduction to 8085 and 8086 Microprocessors + Mictoprocessor definitions * Computer block diagram * Differences between microprocessor and microcontroller ‘+ Memory (Memory architecture) differences * Importance of Hexa-Decimal Numbers + Memory basic + Register unit: General purpose registers, Special purpose registers + Arthmetical Logical Unit ‘Timing and Control unt, Signals, ALU, RD, WR, |O/M, HOLD and HLDA * Interrupts Unit: Types, Triggering, Vector address, applications * Serial /0 control unit SID and SOD + PIN Layout (Optional) Chapter-2 : 8085 Programming * Softwares definitions * Programming cycle - Steps in writing According to length-1 byte, 2 byte, 3 byte ‘+ Memory representation of a program Definition: state, Machine cycle and instruction oycle. Example for an instruction. + Datatransfer/Copy instructions ‘+ Arithmetic and Logical instructions ‘* Branching instructions Machine contol instructions + Simple addresses * Loops and /O applications Chapter-3 : Interfacing ICs ‘+ Memories - Basics, Classification * Notation of memory, (Mx N) ‘+ Problems: = Memorymapping = Starting and Ending addresses = Using decoders ‘Interfacing IC's: 8251, 8253, 8255, 8257/37, 8279 * Interfaces: = Different buses (for ESE) SPI, IPC, CAN, USB ‘+ Applications of Microprocessors (for ESE)]Publleatians 4ossoo01do91W $808 TANI JO oumoouUoIy sng eieaysseuppy sng ssauppy cay ay Ny Nas3y GOH Aavae aS x vous i vai ak wor Hi 7 we per 62 | Electrical engineering + Microprocessors ronuog pue Buu ‘soy ss Ls feauog N39 % Gara sennimed] [pmnaseny | a = F GNo— Addns. | ASrael so8Kod Keuy sjsu re sdoisdig ) Bey Bey “duel (2 vexoidgny xf —_|_,.(@) seisi6eu Lonomsu & j oS hee | Fons moe + 4 f os de seta etna ah ) soyenuraoy @ ww madecaspblcaonsorg ‘© Copyright :MROE ERSSMADE EASY Warkivor | 63 Publiaatione AdsressiStats Aseress (Data bus AulSs-AySs ‘AD, ADs lemary edaress and cata bus interfacing Internal data bus 4-z¢ mopnamaz- oce 4-z¢ zo-4comxm Timing ane ‘contol crit t Cock and contro! Signals Architecture of INTEL 8086 Microprocessor © Copyright MABE ERSH ® vom madeeasypublications.orgDey rete Introduction to 8085 and 8086 Microprocessors Q.6 In microprocessor interface, the concept of Zel Multiple Cholce Questions detecting some error condition such as ‘no oe match found’ is called (@) Syntaxertor, (6) Samanticerror Q.1 -75Hinbinary would be (6) Logical@rota (2) Error trapping {@) 10001010) t0001011 Q.7 Ina microprocessor, the register which keep (© 10111000 (@) Nowe track of next insifuetion to be fetched is (@) Accumulator (0) Program Counter @.2 CPU contains (c) Stack Pointer (d) Instruction Register (@)_ SMPS (power supply) [GATE-1993} (©) Mother boarciPOB (@) DVDwnter PCB, SMPS Q.8 Which of the folowing s nota vectored interrupt? {¢) ALU, CU, registers, internal data bus fa) TRAP (©) INTR (6) RST75 (6) RSTS Q3 If address lines of a microprocessor afe [@ATE-2000] increased, then the number of pins (@) may ormay notbe increagd Q.9 Ina microprocessor, the service routine for a ) mustinstosee Certain interrupt starts trom a fixed location of (0) norelaton with ecgiags ing memory which cannot be externally set, but the nee interrupt can be delayed or rejected, Such an , interruptis Q.4 1. Thevalueoféign fagis modifiodin al ALU (a) nonemaskable andinon-vectored instructions (©) maskable and non-vectored 2. Signtlagis generallyonsidered foran ALU (6) non-maskable and vectored ‘poration with respect to MSB of result, (6) maskable and vectored Which of the above statements is/are correct? [eaTe-2009} (@) only 1 (b) only2 Q.10 The register equivalent to'PC' in 8086 is (©) neither tnor2 (d) both t and 2 (@) cs (©) 0s Q.5_ Serial datainto microprocessor 8085's received eal or through (@) SID pin and by SIM instruction (©) SID pin and by RIM instruction (6) SOD pin and by RIM instruction (6) None Q.11 Which one of the following flags makes the microprocessor to work in single step execution mode. f@) s (c) TRAP fo) {d) Direction © Copyright: MADE ERSY @ ww madecaspblcaonsorgPublloatlons Q.12 Fastest Memory is (@) Flash Memory (bo) PROM () SRAM (d) Register Memory Q.13 Overlapped Execution of Instruction is (@) Synchronizing (©) Interleaved Execution (6) Dynamic Execution (d) Pipelining Q.14 The clock frequency of a microprocess or is 4.MHz, a program requires 50 T-states which execute only once and other 30 Tstates repeat Stimes. The total execution time for the program will be Q.15 In burst mode of DMA, number of 0 devices accessing memory is Q.16 ‘SP register contains an address C579H, iftwo register pairs are pushed onto stack (wt. 8085), the data al top of stack would be at Q.17 The number of segments in 8086 is @ 1 (o) 4 (o) 16 (d) 20 Q.18 The technique of 6 bytes queue in 8086 (a) FIFO (b) LIFO, (c) both (a)and(b) (d) None Q.19 In a microprocessor the effective address is calculated by adding ‘on subtracting displacement value to (a) immediateaddress iru iolang 1w6iK009 @ hd ASV 3OVHO Jo ued oN “WWl9q MON ‘suo in J0 pe2npoides 9q Kew 1009 #1 WRT pa Uayra EBT WnDe ensu workpook | 65 (0) relative address (c) absolute address (d) base address Q.20 Discuss the importance of flags in 8085. Q.21 Explain the difference between maskable non-maskable interrupts. Q.22 Design a memory of 8 KB, using 2 KB memory chips and a decoder having memory map of 2000H-3F FFM: Q.23 Explain the significance of effective address in 8086. Try Yourself T1. Explain flag register in 8085 with suitable example. T2, Explain DMA (Direct memory access) operation in 20885, © Copyright | MADE ERSS @ vn madecaspubleatonsorgUrs 8085 Programming Multiple Choice Questions | Non ‘suonesiara AS¥3 CHO} anew clans wUkdeo Q.1.Tomask the higher nibble in accumulator, which of the following instruction is used (@) ORIFOH (b) ANIFOH (c) ANIOFH (d)_ None Q.2_ Inthe given program, the result in accumulator s MV MA ADI HT (@) positive value of 06H (b) 2s complement of FAH (0) negative value of 06H (d)_ 168 complement of FAH A,O6H oO Q.3._ In RP instruction, the control of program shift to (2) addresSaccessed ftom data at top of stack (2 bytes) based on parity lag address at top of stack based on odd parity only address at top of stack based on sign flag (0) (e) (9) address at top of stack based on sign flag =1 Q.4. When IN 59H is executed, the value placed on address bus in the last machine cycle is (a) 0059 (b) FF59H (c) S959H (d) None Te Se a es Q.5 An8086 assembly language program is given below. Assume that the carry flag is initially unset. The content ofthe aecumulator after the execution ofthe program is MI AO7H RL MOV B.A RLC RLC ADD B RRC fa) 8CH (c) 23H (©) 64H () 15H [GATE-2011] ‘Common Data for Questions (6 and 7): Consider an 8085 microprocessor system Q.6 The following program starts at location 0100H LXISP, OOF FH LXIH, 0107H MVIA, 20H SUBM The content of accumulator when the program counter reaches 0109H is (a) 20H (©) 02H (©) OOH (o FH [GATE-2005] Q.7 Initially content of accumulator are 00 H and content of memory location are 20 F Itin addition following code exists from 0109 onwards, ‘ORI 40H ADDM © Copyright | MADE ERSS @ ww madecaspblcaonsorgPubliaatione What will be the result in the accumulator after the last instruction is executed? (@) 40H (b) 20H () 60H (@) 42H [GATE-2005] Q.8 Forthe 8085 assembly language program given below, the content of the accumulator after the ‘execution of the program is [S000H WTA 45H 002 MOV 8 A '3003H STC (3004 H_ CMC \3005H RAR \3006H_XRA B (b) 4H (6) E7H_ (GATE-2010] (a) OOH (c) 67H Q.9 The following instructions have been executed by an 8085 uP ADDRESS (HEX) INSTRUCTION 6010 L0H, 8A73H 6013 MOV A, L. 6014 ADD H 6015 DAA 6016 MOV Heo e017 PCHL From which address will the nextinstrution be fetched? (@) 6019 (©) 6379 (©) 6979 (@) None ofthe above [GATE-1997} Q.10 Following is the segment of a 8085 assembly language program: UXISP, EFFFH CALL 3000H 3000 H: LXIH, SCF4H PUSH PSW SPHL POP PSW RET (On completion of RET execution, the conter of SP is (a) 3CFOH (c) EFFDH @ (b) 3CF8H HK [GATE-2008) jeu fang 1uBUKICD @ hd ASV 3OVHO Jo ued oN “joa MeN “sun in so pe2npoides 94 Aes 1009 #1 Tara SRT WnDe ensu workpook 67 Q.11 An 8085 microprocessor executes "STA 1234H! with starting adress location 1FFEH (STA copies the contents of the Accumulator to the 16-bit address location). While the instruction s fetched and executed, the sequence of values written at the address pins Aj, — Ay is (@) 1FH, 1FH, 20H, 124 (b) 1FH, FEH, 1FH, FFH, 12H (0) 1FH, 1FH, 12H, 12 (0) 1FH, 1FH, 12H, 204, 42H [GATE-2014] Q.12 The content of some of the memory location in an 8085 A based system are given below. intent 26FE 26FF | Ot 2700 2704 2702 The content of stack (SP), program counter (PC) and (H, L) are 2700 H, 2100 H and 0000 H respectively. When the following sequence of instruction are executed 2100H: DAD SP 2101 H: PCHL the content of (SP) and (PC) at the end of ‘execution willbe (a) PC = 2102 H, SP = 2700 H (b) PC = 2700 H, SP = 2700 H (c) PC = 2800 H, SP = 26FE H (a) PC = 2802 H, SP = 2702 H IGATE-2008] Q.13 The clock frequency of an 8085 microprocessor is S MHz. If the time required to execute an instruction is 1.4 4s, then the number of T- states needed for executing the instruction is @1 ©) 6 7 we [GATE-2017] © Copyright / MADE ERS @ vn madecaspubleatonsorg68 | Electrical Engineering + Microprocessors Q.14 The total number of memory accesses involved {inclusive of the op-code fetch) when an 8085 processor executes the instruction MVI M, 5OHis (a1 2 3 (a4 [GATE-1996] Q.16 The contents of Register (B) and Accumulator (A) of 8085 microprocessor are 49 H and 3A H respectively. The contents of A and the status of carry flag (CY) and sign flag (S) after executing SUB Binstruction are (@) A=FIH, CY=1,S=1 (b) A=0FH,CY=1,S=1 (0) A=FOH, CY=0,S=0 (9) A=1FH,CY=1,S=1 [GATE-2000] Q.16 In.an 8085 microprocessor, the contents of the accumulator and the carty flag are A7 (in hex) and 0, respectively. If the instruction RLC is. ‘executed, then the contents of the accumulator (inhex) and the carry flag, respectively, willbe (@) 4€ ando (b) 4€ and 1 (¢) 4Fando (@) 4F and 1 [GATE-2016] Q.17 The contents of the accumulator in an 8085 microprocessor is altered after the execution of the instruction (@) CMP C (b) CPI 3A’ (@) ANI 5c (@)ORA A (GATE-1994) Q.18 In an 8085 microprocessor, after the execution of XRA A instruction (a) the cany tag is set. (b) the accumulator contain FFH. (0) the zero flaghis set. (6) the accumulator contents are shifted left by one bit. [GATE-1995] Q.19 Which signal of 8085 microprocessor is used to insert wait states? (a) READY (@) HOLD (©) ALE (@ INTR Q.20 Which of the following instructions does not use the stack? yeu yaelang subukdog @ a men “eu je wed ows fale | pean paRtey eas Ca I oy Aue uy po: eur anowy Publleatians fa) CALL (o) XTHL, (e) IMP (a) RET Q.21 In an 8085 microprocessor, which one of the followings the correct sequence of the machine cycles for the execution of the OCR M instruction? (a) opcode fetch (0) opcode fetch, memory read, memory write (c) opcode fetch, memoty read (a) opcode fetch, memory write, memory write Q.22 Which instruction in an 8085 processor can set aflag? (a) MOV B,C (c) STA2000H {o) JNZ 2100 (@) ADD B Q.23 In 8085 processor has register contents SP = SFFBH, 8 = 34H, and C= 7FH before the ‘execution of instruction PUSH B. The value of SP and the content of the Stack Top after the execution of the instruction respectively are (a) SFFAH and 7-H (b) SFF6H and 34H (c) SFF6Hand7FH (d) SFF8H and 34H Q.24 In instruction LHLD 5080H and SHLD 5090H, the common operations include (a) Fetch, memory read, memory read (0) Fetch, memory write, memory write (0) Fetch, memory write, memory read (d) None Q.25 When RET instruction of 8085 microprocessor is executed, then the stack pointer is (a) incremented by one {b) incremented by two: (c) remains same (d) decremented by two Q.26 To mask RST 5.5, RST 6.5 and to send logict ‘on Serial Output Data (SOD) pin of an 8085 microprocessor, the data required in the accumulator (A) before execution of "SIM instruction should be equal to (a) ABH (b) ACH (o) CBH (@) BCH © Copyright | MADE ERSS @ ww madecaspblcaonsorgPubliaatione Q.27 If an instruction in 8085 requires 5 memory cycles having one write eycle among them, then the number oftimes AD signal required Q.28 In RST7instruction the op-code fetch operation is of __ Tstates Q.29 The addressing mode of RET instruction is. Q.30 Consider the following 8085 assembly language program, Lx 0020H Loop: DCXD MOV A, D ORAE JNZ LOOP Number of times the above loop will be executed is Q.31 A program has 4 instructions, whose lengths are 1B, 2B, 38, 1B. Itprogram starts at 4198+, then the 4th instruction address is Q.32 LDA 7540H, Data at 7501H is FFH and the data at next location is 55H, data til 7600H is alternative i.e., FH and 5H. The\content of accumulator after execution of instruction is _ Questions J Q.33 Draw he timing giagram of MOV, B, assuming the instruction is @3000H and [HL] = 5090H_ [B] = FFH. Q.34 Write a program to generate a delay of 200 ms using 8085, . @ Try Yourself J T1. Consider the following assembly language program iru lang 1W6ishd09 @ hd ASV 3OVHO Jo ued oN “WWl9a mon ‘suone> in s0 pe2npoides 94 hes 009 #1 Wa ARET pa uapraERT 12, 13. 14. 15, WnDe ensu workpook | 69 XRAA MVIA, 50 H MVIB, OF H. DCRA NZ LOOP INR B. JCLOOP Ho The program is executed in INTEL 8085, find the number of times INR B executed Loor (Ans: 1] Initially i the zero flag is RESET (2— 0). MVIA, O7H Lt: RLC JNZ ut HLT The'loop will execute for__ times. [Ans. Infinite] Consider the following 8085 microprocessor rogram MVIC, FFH MIB, FFH Li-peRc NZL DCRB NZL HIT How many times DCR C instruction executes? [ans: 65,279] Consider the following instructions executed in 8086 PUSH AX; AX has 0020H in it PUSH BX; BX has 1234H init POP AX; ADD AX, BX: POP CX Find the content of CX register after execution, [Ans: 20 H] The instruction RIM is related to (a) RESET accumulator (0) serialdata (c) maskable interrupts (6) both (b) and (c) Ans. (@)] © Copyright | MADE ERSS @ vn madecaspubleatonsorgUrs Interfacing ICs (3) Multiple Choice Questions Qa An output device is interfaced with 8-bit microprocessor 8085 A. The interfacing circuit is shown in figure. an external device is shown in the figure. The instruction for correct data transfer is ata aus (O,~ By) Non ‘suonesiara AS¥3 CHO} anew clans wUkdeo a $08 SLX BL Decoder * et, hoe aa 2p Lee ls. 3 8 St [Bag] % — @MVIAFBH —(B) INFBH Te © @ourren (6) LDAFaFaH vo [GATE-2014] acs The interfacing circuit makes Use of 3 Line to 8 Line decoder|having 3 enable lines E,, Ea, Es. The address of the device is (a) 50H (©) 5000H (0) ADH (a) AOooH [GATE-2014] az Ifall the HO addresses, in ]O mapped V/O, are used for input devices only, then the possible instructions are (@) IN OOH -IN7FH only (0) IN80H - IN FFH only (c) OUTOOH-OUTFFH (@) INOOH -INFFH F the 8085 microprocessor, the interfacing Circuit to input &-bit digital data (Df, - Df,) from Se Sa ae aa as a6 ‘Two 82594 priority interrupt control chips are used/connected in cascade, the maximum interrupts possible are fa) 2 tb) 16 (©) 8 {d) None of these Inmode-0 of 8253 (a) Square wave can be generated. (b) Interrupts generated after 50% of count. {c) An interrupt is generated when count = 0. (d) None of the above In Asynchronous mode of data transmission using 8251 (USART). &-bits of data and 1 start and 1 stop bits are used. If 100 such data bytes are transmitted, then total bits are (a) 1000 bits (©) 2000 bits (e) 1500 bits (0) None of these © Copyright | MADE ERSS @ ww madecaspblcaonsorgPubliaatione ~ Numerical Answer Type Questions Q.7 The range of the addresses of the RAM which is interfaced to a microprocessor as shown in figure is F400 -F7FFH, RAM Ayla 3008 ecocer T AB vet An 4u—[ > an The outputs of decoder are labelled as YY, You You Yo. Yo» Then the value of Xis__. 2) Q8 In a2KB ROM, GS is connected to Y, of a 3x 8 decode if A,, = 0, A,, = 1, then ending address of the memory chip is_. Q.9 The control word to be loaded into GWR of 8255, to get Port A> Input port Port B > Output port Port C > Input port In mode-9, Q.10 If starting address of a4 KB RAM 97AEH, the ending address is_ Q.11 Aninstruction CALL S060H is at 21FEH, the next consecutive instruction adress of main program will be @ Try Yourself ] Ti. Ifapage of memoryis assumed to be 256 bytes then in how many pages total memory of 8085 canbe treated? [Ans: 256] jeu fang 1uBUKICD @ hd ASV 3OVHO Jo ued oN “joa MeN “sun in s0 pa2npoids 9q hews 1009 #1 ara meaT 4 x 13, TA, WnDe ensu workpook 71 A1 Kbyte memory module has to be interfaced with an 8-bit microprocessor that has 16 address lines. The address lines A, to Ay of the processor are connected to the corresponding address lines of the memory module. The active low chip select OS of the memory module is connected to the y, output of a3 to8 decoder with active low outputs. S,, S,, and S, are the input lines to the decoder, with S, as the MSB. Thedecoderhas one active low EN, and one active high EN, enable lines as shown below. Thé aduiress range(s) that gets mapped onto this memory module is (are) Aig As Au YoY We We Ye Ye Ye He co {a) 3000,, to 33FF,, and £000,, to ESF, (bo) 1400,,t0 17FF., (c) 5300,, to 53FF;, and A300, to ASFF,, (d) §800,, to SBFF,, and D809,, to DBFF,, In WO mapped I/O mode of 8085, how many maximum input devices and maximum output devices can be connected ? What will be their addresses? An 8-bit microprocessor has 16-bitaddress bus Ag-Ayg: The processor has a 1 kB memory chip as shown, The address range for the chip is Ay o Ay x oe to a 2 [tae aC | Ra], aa 3 |® af 8 oa ae a (a) FOOF HtoF40E H (b) F100 HtoF4FF (c) FOOO Hto F3FFH (d) F700 Hto FAFF H © Copyright | MADE ERSS @ vn madecaspubleatonsorg