+ 2

William Stallings + Chapter 10

Computer Organization
and Architecture
Processor Structure and Function
10th Edition

+ Processor Organization 3 4

Processor Requirements:
 Fetch instruction
 The processor reads an instruction from memory (register, cache, main memory)

 Interpret instruction
 The instruction is decoded to determine what action is required

 Fetch data
 The execution of an instruction may require reading data from memory or an I/O
module

 Process data
 The execution of an instruction may require performing some arithmetic or logical
operation on data

 Write data
 The results of an execution may require writing data to memory or an I/O module

 In order to do these things the processor needs to store some data

temporarily and therefore needs a small internal memory
 5
+ 6

Register Organization
 Within the processor there is a set of registers that function as a
level of memory above main memory and cache in the
hierarchy

 The registers in the processor perform two roles:

User-Visible Registers Control and Status Registers

 Enable the machine or  Used by the control unit to

assembly language control the operation of the
programmer to minimize main processor and by privileged
memory references by operating system programs to
optimizing use of registers control the execution of
programs

7 8
User-Visible Registers Table 14.1
Condition Codes
Categories:
Referenced by means of • General purpose
the machine language • Can be assigned to a variety of functions by the
programmer
that the processor • Data
executes • May be used only to hold data and cannot be
employed in the calculation of an operand
address
• Address
• May be somewhat general purpose or may be
devoted to a particular addressing mode
• Examples: segment pointers, index registers,
stack pointer
• Condition codes
• Also referred to as flags
• Bits set by the processor hardware as the result
of operations
+ 9
+ Program Status Word (PSW) 10

Control and Status Registers

Four registers are essential to instruction execution:

 Program counter (PC) Register or set of registers that

 Contains the address of an instruction to be fetched contain status information
 Instruction register (IR)
 Contains the instruction most recently fetched

 Memory address register (MAR) Common fields or flags include:

 Contains the address of a location in memory • Sign
• Zero
 Memory buffer register (MBR) • Carry
 Contains a word of data to be written to memory or the word most • Equal
recently read • Overflow
• Interrupt Enable/Disable
• Supervisor

11 12

Includes the following

stages:
Instruction
Cycle

Fetch Execute Interrupt

If interrupts are enabled

Read the next and an interrupt has
Interpret the opcode
instruction from occurred, save the
and perform the
memory into the current process state
indicated operation
processor and service the
interrupt
13 14

15 16
17 18

Pipelining Strategy

To apply this concept

to instruction
execution we must
Similar to the use of recognize that an
an assembly line in a instruction has a
manufacturing plant number of stages

New inputs are

accepted at one end
before previously
accepted inputs
appear as outputs at
the other end

19
+ Additional Stages 20

 Fetch instruction (FI)

 Read the next expected  Fetch operands (FO)
instruction into a buffer  Fetch each operand from
memory
 Decode instruction (DI)  Operands in registers need
 Determine the opcode and not be fetched
the operand specifiers
 Execute instruction (EI)
 Calculate operands (CO)  Perform the indicated
 Calculate the effective operation and store the
address of each source result, if any, in the specified
operand destination operand location
 This may involve
displacement, register  Write operand (WO)
indirect, indirect, or other  Store the result in memory
forms of address calculation
21 22

23 24
25
Pipeline Hazards 26

Occur when the

pipeline, or some
portion of the There are three types
pipeline, must stall of hazards:
because conditions • Resource
do not permit • Data
continued execution • Control

Also referred to as a
pipeline bubble

27 28
+ Types of Data Hazard 29
+ 30

Control Hazard
 Read after write (RAW), or true dependency
 Also known as a branch hazard
 An instruction modifies a register or memory location
 Succeeding instruction reads data in memory or register Occurs when the pipeline makes the wrong decision on a

location
 Hazard occurs if the read takes place before write operation is branch prediction
complete
 Brings instructions into the pipeline that must subsequently
 Write after read (WAR), or antidependency be discarded
 An instruction reads a register or memory location
 Succeeding instruction writes to the location  Dealing with Branches:
 Hazard occurs if the write operation completes before the  Multiple streams
read operation takes place  Prefetch branch target
 Write after write (WAW), or output dependency  Loop buffer
 Two instructions both write to the same location  Branch prediction
 Hazard occurs if the write operations take place in the reverse  Delayed branch
order of the intended sequence

31 32
Multiple Streams Prefetch Branch Target
A simple pipeline suffers a penalty for a  When a conditional branch is recognized, the
branch instruction because it must choose target of the branch is prefetched, in addition
one of two instructions to fetch next and may
make the wrong choice to the instruction following the branch

 Target is then saved until the branch

instruction is executed
A brute-force approach is to replicate the
initial portions of the pipeline and allow the  If the branch is taken, the target has already
pipeline to fetch both instructions, making been prefetched
use of two streams
 IBM 360/91 uses this approach
+
Drawbacks:
• With multiple pipelines there are contention delays for
access to the registers and to memory
• Additional branch instructions may enter the pipeline
before the original branch decision is resolved
+ 33 34

Loop Buffer
 Small, very-high speed memory maintained by the
instruction fetch stage of the pipeline and containing the n
most recently fetched instructions, in sequence

 Benefits:
 Instructions fetched in sequence will be available without the
usual memory access time
 If a branch occurs to a target just a few locations ahead of the
address of the branch instruction, the target will already be in the
buffer
 This strategy is particularly well suited to dealing with loops

 Similar in principle to a cache dedicated to instructions

 Differences:
 The loop buffer only retains instructions in sequence
 Is much smaller in size and hence lower in cost

+ 35 36

Branch Prediction

 Various techniques can be used to predict whether a branch

will be taken:

1. Predict never taken  These approaches are static

2. Predict always taken  They do not depend on the
execution history up to the time of
3. Predict by opcode the conditional branch instruction

1. Taken/not taken switch

 These approaches are dynamic
2. Branch history table
 They depend on the execution history
 37 38

Intel 80486 Pipelining

39 40

Fetch
Objective is to fill the prefetch buffers with new data as soon as Operates independently of the other stages to keep the prefetch
the old data have been consumed by the instruction decoder buffers full

Decode stage 1
All opcode and addressing-mode 3 bytes of instruction are passed to the D1 D1 decoder can then direct the D2 stage to
information is decoded in the D1 stage stage from the prefetch buffers capture the rest of the instruction

Decode stage 2
Also controls the computation of the more complex addressing
Expands each opcode into control signals for the ALU
modes

Execute

Stage includes ALU operations, cache access, and register update

Write back
Updates registers and status flags modified during the preceding execute stage
 41 42

Table 14.2

x86
Processor
Registers

43 44
+ 45 46

Interrupt Processing
Interrupts and Exceptions
Table 14.3
 Interrupts
 Generated by a signal from hardware and it may occur at random x86
times during the execution of a program Exception
 Maskable and
 Nonmaskable Interrupt
Vector Table
 Exceptions
 Generated from software and is provoked by the execution of an
instruction
 Processor detected
 Programmed

 Interrupt vector table

 Every type of interrupt is assigned a number
 Number is used to index into the interrupt vector table Unshaded: exceptions
Shaded: interrupts

+ The ARM Processor 47 48

ARM is primarily a RISC system with the following

attributes:
 Moderate array of uniform registers

 A load/store model of data processing in which operations only perform

on operands in registers and not directly in memory

 A uniform fixed-length instruction of 32 bits for the standard set and 16

bits for the Thumb instruction set

 Separate arithmetic logic unit (ALU) and shifter units

 A small number of addressing modes with all load/store addresses

determined from registers and instruction fields

 Auto-increment and auto-decrement addressing modes are used to

improve the operation of program loops

 Conditional execution of instructions minimizes the need for conditional

branch instructions, thereby improving pipeline efficiency, because
pipeline flushing is reduced
Processor Modes 49
Exception Modes 50

Most application Have full access

programs execute in to system Entered when
ARM user mode
architecture resources and can specific
• While the processor is in
supports seven user mode the program change modes exceptions occur
execution
being executed is unable
to access protected
freely
modes system resources or to
change mode, other than
by causing an exception
to occur

Advantages to defining Exception modes: System mode:

Remaining six
so many different • Supervisor mode • Not entered by any
execution modes privileged modes exception and uses the
are referred to as •The OS can tailor the use of
• Abort mode same registers available
privileged modes system software to a variety • Undefined mode in User mode
of circumstances • Is used for running certain
• These modes are •Certain registers are • Fast interrupt mode privileged operating
used to run system dedicated for use for each of
the privileged modes, allows
• Interrupt mode system tasks
software swifter changes in context • May be interrupted by
any of the five exception
categories

51 52
 53
+ Summary
54

Processor Structure
and Function
Chapter 14
Table 14.4
 Processor organization  Instruction pipelining
Pipelining strategy
ARM

 Register organization
 Pipeline performance
User-visible registers
Interrupt 

 Control and status registers

 Pipeline hazards

Vector  Instruction cycle




Dealing with branches
Intel 80486 pipelining
 The indirect cycle
 The Arm processor
 Data flow
 Processor organization
 The x86 processor family  Processor modes
 Register organization  Register organization
 Interrupt processing  Interrupt processing