Lecture – Intro to ARM assembly language

I started out with machine code and assembly language.

– Charles Petzold
Microsoft MVP

© 2018 by George B. Adams III 1

What is chapter 6 MI format?
n Read chapter 6.1-6.4
n Learning objectives
¡ Explain the machine instruction representation
used in Chapter 6

© 2018 by George B. Adams III 2

ARM history
n Advanced RISC Machines, Inc. (ARM)
n Used by Apple in the first iPod
n 64-bit ARM is called ARMv8 and AArch64

© 2018 by George B. Adams III 3

Reference info
n ARMv8 is a load-store, Harvard architecture
n In User mode, assembly has access to
¡ 31 general-purpose 64-bit registers; X0 thru X30
¡ PC – program counter register
¡ SP, XZR – register storing either stack pointer or
2’s complement zero, depending on context
¡ Note: Convention is that X30 is the link register,
LR, and stores function call return address
¡ W0 thru W30, WZR refer to the least significant
32 bits of X0 thru X30, XZR; use when desired
© 2018 by George B. Adams III 4
ARM Instruction Format
n 32-bit fixed-length representation (format)
n 5-bit register pointers

© 2018 by George B. Adams III 5

AArch64 Instruction Formats
n ALU operation instruction format

31 30 29 28-24 23-22 21 20-16 15-10 9-5 4-0

Reg type, 0=W, 1=X

Set condition code,

Imm6 immediate
Shift operation

Rm register
0=no, 1=yes

Rn register

Rd register
Opcode

Opcode

© 2018 by George B. Adams III 6

More info about fields
n Shift operation – 2 bits to specify a possible
shift operation to perform on one operand
n Rm, Rn – operand register pointers
n Rd – destination (result) register pointer
n Imm6 – 6-bit field for immediate data
n Reg_Type bit – implies all registers must be
either X type (64-bit) or R type (low order 32
bits of eadh 64-bit X register); there is no
mixing of register types as operands in an
assembly instruction (no implicit casting)
© 2018 by George B. Adams III 7
Register name semantics
n 31 general purpose registers of 64 bits each,
named X0 through X30
¡ However, X30 is used to hold the return address
when calling a function, so use only with care
¡ XZR stores all 0 bits or storing the current stack
pointer value, depending on context
¡ May name just the lower 32 bits of a register by
replacing X (for extended, i.e., 64 bits) with W for
(word, i.e., 32 bits)
n When calling a function, place arguments in
order argv[0], argv[1], … in regs X0, X1, …, X7
© 2018 by George B. Adams III 8
Register name syntax
n Register Xn for n=0 to 31 is a 64-bit register
n Every Xn register can be named Wn to refer
to only the lower 32 bits of the 64 bits

n Example, if X5 contains the bit string

0x0123456789ABCDEF
then W5 contains the bit string
0x89ABCDEF
n A write to a W register sets the upper 32 bits
of the underlying X circuit to all 0 bits
© 2018 by George B. Adams III 9
Symbolic names in assembly lang instrs.
n Example
Instruction{S} Rd, Rn, Operand2
n {S} – if mnemonic has S appended then
comparison flags are Set when executed
n Rd – destination register
n Rn – register that an operation operates on;
may be either X or W
n Operand2 – may be a register source, a
register source then modified, or may be an
immediate value
© 2018 by George B. Adams III 10
ALU instruction examples
n Each line of code is an independent example; the snippet is
not intended as a coherent whole

Loop:
ADD W0, W1, W2, LSL #3 // W0 = W1 + (W2 << 3)
SUBS X0, X4, X3, ASR #2 // X0 = X4 - (X3 >> 2), set flags
BGE Loop // Loop if not negative
MOV X0, X1 // Copy X1 to X0
CMP W3, W4 // Set flags based on W3 - W4
ADD W0, W5, #27 // W0 = W5 + 27

© 2018 by George B. Adams III 11

Load with offset mode forms
Example instruction Description
LDR X0, [X1] Load from the address in X1
LDR X0, [X1, #8] Load from address X1 + 8
LDR X0, [X1, X2] Load from address X1 + X2
LDR X0, [X1, X2, LSL, #3] Load from address X1 + (X2 << 3)
LDR X0, [X1, W2, SXTW] Load from address X1 + sign extend(W2)
LDR X0, [X1, W2, SXTW, #3] Load from address X1 + (sign extend(W2) << 3)

© 2018 by George B. Adams III 12

Example use of offset modes for C code
n // A C example showing accesses that
// a compiler is likely to generate.

void example_dup(int32_t a[], int32_t length)

{
int32_t first = a[0]; // LDR W3, [X0]
for (int32_t i = 1; i < length; i++)
{
a[i] = first; // STR W3, [X0, W2, SXTW, #2]
}
}

© 2018 by George B. Adams III 13

Compare
n CMP Rn, Operand2
n Compares register Rn with Operand2 in that
order and sets 4 flags to record 16 different
comparison conditions
n Destination register is a dedicated 4-bit
device; no need to name it

© 2018 by George B. Adams III 14

Branch
n Branch conditions include
EQ - ==
NE - !=
LT - signed <
LE - signed <=
GT - signed >
GE - signed >=
n Syntax is B<cond> or B.<cond>
Example: BLT is branch if less than

© 2018 by George B. Adams III 15

Move
n MOV Rd, Operand2
n Examples
MOV X1, X0 // Copy contents of X0 into X1

© 2018 by George B. Adams III 16

Summary
n This is a brief introduction to ARMv8 assembly
language
n The language provides more basic operations
and many ways to express data structure
accessing and parallel operations

© 2018 by George B. Adams III 17