a Precision JFET-Input

Operational Amplifiers
OP15/OP17
FEATURES GENERAL DESCRIPTION
Significant Performance Advantages over LF155 and The ADI-JFET input series of devices offer clear advantages over
LF157 Devices industry-generic devices and are superior in both cost and perfor-
Low Input Offset Voltages: 500 ␮V Max mance to many dielectrically-isolated and hybrid op amps. All devices
Low Input Offset Voltage Drift: 2.0 ␮V/ⴗC offer offset voltages as low as 0.5 mV with TCVOS guaranteed to
Minimum Slew Rate Guaranteed on All Models 5 mV/∞C. A unique input bias cancellation circuit reduces the IB
Temperature-Compensated Input Bias Currents by a factor 10 over conventional designs. In addition ADI specifies
Bias Current Specified Warmed-Up Over Temperature IB and IOS with the devices warmed up and operating at 25∞C ambient.
Internal Compensation These devices were designed to provide real precision performance
Low Input Noise Current: 0.01 pA/÷ ÷ Hz along with high speed. Although they can be nulled, the design
High Common-Mode Rejection Ratio: 100 dB objective was to provide low offset-voltage without nulling. Systems
Models with MIL-STD 883 Processing Available generally become more cost effective as the number of trim circuits
OP15 is decreased. ADI achieves this performance by use of an improved
156 Speed with 155 Dissipation: 80 mW Typ bipolar compatible JFET process coupled with on chip, zener-zap
Wide Bandwidth: 6 MHz offset trimming.
High Slew Rate: 13 V/␮s The OP15 provides an excellent combinations of high speed and
Fast Settling to ±0.1%: 1,200 ns low input offset voltage. In addition, the OP15 offers the speed
OP17 of the 156A op amp with the power dissipation of a 155A. The
Highest Slew Rate: 60 V/␮s combination of a low input offset voltage of 500 mV, slew rate of
Fastest Settling to ±0.1%: 600 ns 13 V/ms, and settling time of 1,200 ns to 0.1% makes the OP15
Highest Gain Bandwidth Product (AVCL = 5 Min): 30 MHz an op amp of both precision and speed. The additional features
Guaranteed Input Bias Current @ 125ⴗC of low supply current coupled with an input bias current makes
the OP15 ideal for a wide range of applications.
The OP17 has a slew rate of 60 V/ms and is the best choice for
applications requiring high closed-loop gain with high speed. See
OP42 datasheet for unity gain applications and the OP215 datasheet
for a dual configuration of the OP15.

V+ *R7, R8 ARE ELECTRONICALLY

J5 ADJUSTED ON CHIP FOR
R8* R7* MINIMUM OFFSET VOLTAGE.
Q5 J8
NULL NULL
Q6 Q16

R3 Q7 Q9 J6
Q19

Q8 Q24
R1
J11
NONINVERTING Q17 Q22
INPUT J1 J2 R13
–INV R2 C2
INPUT
OUTPUT
Q1 Q2
Q10
Q3 Q4 J10

Q12 Q23
J9
Q11 R5 Q13 R6 Q14 Q20 Q25
R3 3.6k⍀ 3.6k⍀
J3 J4
C1
7.4pF Q16 Q15 Q21 R11
R4
V–

Figure 1. Simplified Schematic

REV. A
Information furnished by Analog Devices is believed to be accurate and
reliable. However, no responsibility is assumed by Analog Devices for its
use, nor for any infringements of patents or other rights of third parties that One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
may result from its use. No license is granted by implication or otherwise Tel: 781/329-4700 www.analog.com
under any patent or patent rights of Analog Devices. Fax: 781/326-8703 © Analog Devices, Inc., 2002
OP15/OP17–SPECIFICATIONS
ELECTRICAL CHARACTERISTICS (@ V = ⴞ15 V, T = 25ⴗC, unless otherwise noted)
S A

OP15A, OP15E OP15F OP15G

OP17A, OP17E OP17F OP17G
Parameter Symbol Conditions Min Typ Max Min Typ Max Min Typ Max Unit
Input Offset Voltage VOS RS = 50 W 0.2 0.5 0.4 1.0 0.5 3.0 mV
Input Offset Current IOS
OP15 TJ = 25∞C1 3 10 6 20 12 50 pA
Device Operating 5 22 10 40 20 100 pA
OP17 TJ = 25∞C1 3 10 6 20 12 50 pA
Device Operating 5 25 10 50 20 125 pA
Input Bias Current IB
OP15 TJ = 25∞C1 ± 15 ± 50 ± 30 ± 100 ± 60 ± 200 pA
Device Operating ± 18 ± 110 ± 40 ± 200 ± 80 ± 400 pA
OP17 TJ = 25∞C1 ± 15 ± 50 ± 30 ± 100 ± 60 ± 200 pA
Device Operating ± 20 ± 130 ± 40 ± 250 ± 80 ± 500 pA
Input Resistance RIN 1012 1012 1012 W
Large-Signal AVO RL ≥ 2 kW 100 240 75 220 50 200 V/mV
Voltage Gain VO = ± 10 V
Output Voltage VO RL = 10 kW ± 12 ± 13 ± 12 ± 13 ± 12 ± 13 V
Swing RL = 2 kW ± 11 ± 12.7 ± 11 ± 12.7 ± 11 ± 12.7 V
Supply Current ISY OP15 2.7 4.0 2.7 4.0 2.8 5.0 mA
OP17 4.6 7.0 4.6 7.0 4.8 8.0 mA
Slew Rate2 SR AVCL = 1, OP15 10 13 7.5 11 5 9 V/ms
AVCL = 5, OP17 45 60 35 50 25 40 V/ms
Gain Bandwidth3 GBW OP15 4.0 6.0 3.5 5.7 3.0 5.4 MHz
Product OP17 20 30 15 28 11 26 MHz
Closed-Loop CLBW AVCL = 1, OP15 14 13 12 MHz
Bandwidth AVCL = 5, OP17 11 10 9 MHz
Settling Time tS
OP15 To 0.01% 4.5 4.5 4.7 ms
To 0.05% 1.5 1.5 1.6 ms
To 0.10% 1.2 1.2 1.3 ms
OP17 To 0.01% 1.5 1.5 1.6 ms
To 0.05% 0.7 0.7 0.8 ms
To 0.10% 0.6 0.6 0.7 ms
Input Voltage Range IVR ± 10.5 ± 10.5 ± 10.3 V
Common-Mode CMRR VCM = ± 10.5 V 86 100 86 100 dB
Rejection Ratio VCM = ± 10.3 V 82 96 dB
Power Supply PSRR VS = ± 10 V to ± 18 V 10 51 10 51 mV/V
Rejection Ratio VS = ± 10 V to ± 18 V 10 80 mV/V
Input Noise en fO = 100 Hz 20 20 20 nV/÷Hz
Voltage Density fO = 1 kHz 15 15 15 nV/÷Hz
Input Noise in fO = 100 Hz 0.01 0.01 0.01 pA/÷Hz
Current Density fO = 1 kHz 0.01 0.01 0.01 pA/÷Hz

Input Capacitance CIN 3 3 3 pF

NOTES
1
Input bias current is specified for two different conditions. The T J = 25∞C specification is with the junction at ambient temperature; the device operating specification
is with the device operating in a warmed-up condition at 25∞C ambient. The warmed-up bias current value is correlated to the junction temperature value via the
curves of I B versus TJ and IB versus TA. ADI has a bias current compensation circuit which gives improved bias current over the standard JFET input op amps. I B and
IOS are measured at VCM = 0.
2
Settling time is defined here for a unity gain inverter connection using 2 k W resistors. It is the time required for the error voltage (the voltages at the inverting input pit
on the amplifier) to settle to within a specified percent of its final value from the time a 10 V step input is applied to the inverter. See settling time test circuit.
3
Sample tested.
4
Settling time is defined here for A V = –5 connection with RF = 2 kW. It is the time required for the error voltage (the voltage at the inverting input pin on the amplifier) to
settle to within 0.01% of its final value from the time a 2 V step input is applied to the inverter. See settling time test circuit.

–2– REV. A
 OP15/OP17
Electrical Characteristics (@ V = ±15 V, –55ⴗC £ T £ 125ⴗC, unless otherwise noted.)
S A

Parameter Symbol Conditions Min Typ Max Units

Input Offset Voltage VOS RS = 50 W 0.4 0.9 mV
1
Average Input Offset Voltage Drift
Without External Trim TCVOS 2 5 mV/∞C
With External Trim TCVOS RP = 100 W 2 mV/∞C
Input Offset Current2 IOS TJ = 125∞C 0.6 4.0 nA
OP17 TA = 125∞C, device operating 1.0 8.5 nA
Input Bias Current2 IB TJ = 125∞C ± 1.2 ± 5.0 nA
OP17 TA = 125∞C, device operating ± 2.0 ± 11 nA
Input Voltage Range IVR ± 10.4 V
Common-Mode Rejection Ratio CMRR VCM = ± 10.4 V 85 97 dB
Power Supply Rejection Ratio PSRR VS = ± 10 V to ± 18 V 15 57 mV/V
Large Signal Voltage Gain AVO RL ≥ 2 kW, VO = ± 10 V 35 120 V/mV
Output Voltage Swing VO RL ≥ 10 kW ± 12 ± 13 V
NOTES
1
Sample tested.
2
Input bias current is specified for two different conditions. The T J = 25∞C specification is with the junction at ambient temperature; the device operating specification
is with the device operating in a warmed-up condition at 25∞C ambient. The warmed-up bias current value is correlated to the junction temperature value via the
curves of I B versus TJ and IB versus TA. ADI has a bias current compensation circuit which gives improved bias current over the standard JFET input op amps. I B and
IOS are measured at VCM = 0.

(@ VS = ⴞ15 V, 0ⴗC £ TA £ 70ⴗC for E and F grades, –40ⴗC £ TA £ 85ⴗC for G grades
ELECTRICAL CHARACTERISTICS unless otherwise noted)
OP15E/OP17E OP15F/OP17F OP15G/OP17G
Parameter Symbol Conditions Min Typ Max Min Typ Max Min Typ Max Unit
Input Offset Voltage VOS RS = 50 W 0.3 0.75 0.55 1.5 0.7 3.8 mV
Average Input Offset
Voltage Drift1
Without External Trim TCVOS 2 5 3 10 4 30 mV/∞C
With External Trim TCVOSn RP = 100 W 2 3 4 mV/∞C
Input Offset Current2 IOS TJ = 70∞C 0.04 0.30 0.06 0.45 0.08 0.85 nA
OP15 TA = 70∞C, Device Operating 0.06 0.55 0.08 0.80 0.10 1.2 nA
TJ = 70∞C 0.04 0.30 0.06 0.45 0.08 0.85 nA
OP17 TA = 70∞C, Device Operating 0.07 0.70 0.10 1.1 0.15 1.7 nA
Input Bias Current2 IB TJ = 70∞C ± 0.10 ± 0.40 ± 0.12 ± 0.60 ± 0.14 ± 0.80 nA
OP15 TA = 70∞C, Device Operating ± 0.13 ± 0.75 ± 0.16 ± 1.1 ± 0.19 ± 1.5 nA
TJ = 70∞C ± 0.10 ± 0.40 ± 0.12 ± 0.60 ± 0.14 ± 0.80 nA
OP17 TA = 70∞C, Device Operating ± 0.15 ± 0.90 ± 0.20 ± 1.4 ± 0.25 ± 2.0 nA
Input Voltage Range IVR ± 10.4 ± 10.4 ± 10.25 V
Common-Mode CMRR VCM = ± 10.4 V 85 98 85 96 dB
Rejection Ratio VCM = ± 10.25 V 80 94 dB
Power Supply PSRR VS = ± 10 V to ± 18 V 13 57 13 57 mV/V
Rejection Ratio VS = ± 10 V to ± 15 V 20 100 mV/V
Large Signal AVO RL ≥ 2 kW 65 200 50 180 35 160 V/mV
Voltage Gain VO = ± 10 V
Output Voltage VO RL ≥ 10 kW ± 12 ± 13 ± 12 ± 13 ± 12 ± 13 V
Swing
NOTES
1
Sample tested.
2
Input bias current is specified for two different conditions. The T J = 25∞C specification is with the junction at ambient temperature; the device operating specification
is with the device operating in a warmed-up condition at 25∞C ambient. The warmed-up bias current value is correlated to the junction temperature value via the
curves of I B versus TJ and IB versus TA. ADI has a bias current compensation circuit which gives improved bias current over the standard JFET input op amps. I B and
IOS are measured at VCM = 0.

REV. A –3–
OP15/OP17–SPECIFICATIONS
ABSOLUTE MAXIMUM RATINGS 1 Package Type ␪JA* ␪JC Unit
Supply Voltage
All Devices Except C, G (Packaged) 8-Lead Hermetic DIP (Z) 148 16 ∞C/W
and GR Grades . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ± 22 V 8-Lead SO (S) 158 43 ∞C/W
C, G (Packaged) and GR Grades . . . . . . . . . . . . . . . . ± 18 V TO-99 (J) 150 18 ∞C/W
Operating Temperature
*␪JA is specified for worst-case mounting conditions, i.e., ␪JA is specified for device
A Grade . . . . . . . . . . . . . . . . . . . . . . . . . . –55∞C to +125∞C in socket for CERDIP and PDIP packages; ␪JA is specified for device soldered to
E, F Grades . . . . . . . . . . . . . . . . . . . . . . . . . . . 0∞C to 70∞C printed circuit board for SO packages.
G Grade . . . . . . . . . . . . . . . . . . . . . . . . . . . –40∞C to +85∞C
Maximum Junction Temperature . . . . . . . . . . . . . . . . . 150∞C
Differential Input Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . .
All Devices Except C, G Grades . . . . . . . . . . . . . . . . ± 40 V
C, G Grades . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ± 30 V +20V
Input Voltage2
All Devices Except C, G Grades . . . . . . . . . . . . . . . . ± 20 V 10k⍀

C, G Grades . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ± 16 V
Input Voltage 2 7
OP15E, OP15F . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ± 20 V 3
8

OP15G . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ± 16 V +3V
300⍀
4 10k⍀
OP17A, OP17E, OP17F . . . . . . . . . . . . . . . . . . . . . . ± 20 V
OP17G . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ± 16 V –20V

Output Short-Circuit Duration Indefinite Figure 2. Burn-In Circuit

Storage Temperature Range . . . . . . . . . . . . –65∞C to +150∞C
Lead Temperature Range (Soldering, 60 sec) . . . . . . . . 300∞C
NOTES
*Absolute Maximum Ratings apply to packaged parts, unless otherwise noted.

8-Lead CERDIP 8-Lead SOIC 8-Lead TO-99

(Z-Suffix) (S-Suffix) (J-Suffix)

BAL 1 8 NC BAL 1 8 NC

–IN 2 7 V+ –IN 2 7 V+

+IN 3 6 OUT +IN 3 6 OUT

V– 4 5 BAL V– 4 5 BAL

ORDERING GUIDE

TA = 25∞C Package Options Operating

VOS MAX Temperature
(mV) TO-99 CERDIP SOIC Range
0.5 OP17EJ OP15EZ COM
OP17EZ
1.0 OP15FJ* OP15FZ* COM
OP17FJ OP17FZ
3.0 OP15GJ* OP15GZ* OP15GS* XIND
OP17GZ

For military processed devices, please refer to the Standard Microcircuit Drawing
(SMD) available at www.dscc.dl.mil/programs/milspec/default.asp.

SMD Part Number ADI Equivalent

5962-8954201GA* OP15AJMDA
5962-8954201PA* OP15AZMDA
5962-8954301GA* OP16AJMDA
5962-8954301PA* OP16AZMDA
*Not recommended for new designs. Obsolete April 2002.

–4– REV. A
 Typical Performance Characteristics –OP15/OP17
30 100
VS = 15V WARMED-UP IN FREE AIR
27 VS = 15V
TA = 25ⴗC
PEAK-TO-PEAK OUTPUT SWING – V

80
24

INPUT BIAS CURRENT – pA

–55ⴗC
21
60
+25ⴗC
18 a. UNDERCANCELLED IB = +16pA @ V CM = 0
b. PERFECTLY CANCELLED IB = 0pA @ V CM = 0
15 40 c. UNDERCANCELLED IB = –16pA @ V CM = 0
+125ⴗC
12
20
9 a

b c
6
0
3

0 –20
100 1k 10k 100k –12 –10 –8 –6 –4 –2 0 2 4 6 8 10 12
OUTPUT LOAD RESISTANCE – ⍀ INPUT COMMON-MODE VOLTAGE – V

TPC 1. Maximum Output Swing vs. Load Performance TPC 4. Input Bias Current vs. Common-Mode Voltage

20 1M
RL = 2k⍀
COMMON-MODE INPUT VOLTAGE RANGE – V

TA = 25ⴗC
500k

OPEN-LOOP VOLTAGE GAIN – V/V

400k
–55ⴗC
15 300k
200k
25ⴗC

125ⴗC
10 100k

POSITIVE
5
FROM –55ⴗC TO –125ⴗC
CHANGE IN CMVR IS < 0.2V
NEGATIVE

0 10k
0 5 10 15 20 5 10 15 20
SUPPLY VOLTAGE – V SUPPLY VOLTAGE – V

TPC 2. Common-Mode Input Voltage Range vs. Supply TPC 5. Open-Loop Voltage Gain vs. Supply Voltage
Voltage

1k 40
TA = 25ⴗC RL = 2k⍀
VS = 15V TA = 25ⴗC
PEAK-TO-PEAK OUTPUT SWING – V

100Hz < f < 10kHz

100 10Hz < f < 10kHz FOR RS > 4M⍀
INPUT NOISE VOLTAGE – ␮V

a AMPLIFIER NOISE 30
b JOHNSON RESISTOR NOISE
c AMPLIFIER NOISE MEASURED
10 WITH SOURCE RESISTOR
c b
20

10
0.1

a
0.01 0
100k 1M 10M 100M 1G 10G 0 5 10 15 20
SOURCE RESISTANCE – ⍀ SUPPLY VOLTAGE – V

TPC 3. Voltage Noise vs. Source Resistance TPC 6. Output Voltage Swing vs. Supply Voltage

REV. A –5–
OP15/OP17
9 1n
VS = 15V
NULLED OFFSET VOLTAGE DRIFT – ␮V/ⴗC

TA = 25ⴗC
7 ISY = 4.0mA FOR MAX CURVES
2.5mA FOR TYP CURVES

INPUT BIAS CURRENT – A

5
155A MAX
VOS
3 OP15A MAX
100p
1
155A TYP
TYPICAL DRIFT BAND
–1

–3
OP15 TYP
–5 10p
10k 100k 1M
0 20 40 60 80 100 120 140
RP-TRIMMING POTENTIOMETER VALUE – ⍀ TIME AFTER POWER APPLIED – s

TPC 7. Nulled Offset Voltage Drift vs. Potentiometer Size TPC 10. OP15 Bias Current vs. Time in Free Air

6 1n
VS = 15V

4 156A/157A MAX

INPUT BIAS CURRENT – A

OFFSET VOLTAGE – mV

2
156A/157A TYP

0 100p OP17A MAX

VS = 15V
–2 TA = 25ⴗC
ISY = 6.7mA FOR MAX CURVES
5.0mA FOR TYP CURVES
–4
OP17A TYP

–6 10p
–50 –25 0 25 50 75 100 125 0 20 40 60 80 100 120 140
TEMPERATURE – ⴗC TIME AFTER POWER APPLIED – s

TPC 8. Offset Voltage Drift vs. Temperature of TPC 11. OP17 Bias Current vs. Time in Free Air
Representative Units

100n
100n
VS = 15V
UNITS ARE WARMED UP 155A MAX
INPUT BIAS CURRENT – A

155A MAX 10n

155A TYP
INPUT BIAS CURRENT – A

10n
155A TYP
OP15A MAXP OP15A MAX
1n
1n OP15A TYP
OP15 TYP

100p
100p

10p
10 30 50 70 90 110 130 150
10p AMBIENT TEMPERATURE – ⴗC
10 30 50 70 90 110 130 150
AMBIENT TEMPERATURE – ⴗC
TPC 12. OP15 Input Bias Current vs. Ambient Temperature
TPC 9. Input Bias Current vs. Ambient Temperature (Units Warmed Up in Free Air)
(Units Warmed Up in Free Air)

–6– REV. A
 OP15/OP17
100n 0

156A/157A MAX
0
INPUT BIAS CURRENT – A

10n 0
156A/157A TYP

VOLTAGE – 5V/DIV
OP17A MAX
0

1n 0

0
OP17A TYP
100p 0

10p 0
10 30 50 70 90 110 130 150 0 0 0 0 0 0 0 0 0 0 0
AMBIENT TEMPERATURE – ⴗC TIME – 500ns/DIV

TPC 13. OP17 Input Bias Current vs. Ambient Temperature TPC 16. OP15 Large Signal Transient Response
(Units Warmed Up in Free Air)

3.5 0

3.0 0
SUPPLY CURRENT – mA

VOLTAGE – 20mV/DIV
0

–55ⴗC
2.5 0
25ⴗC
125ⴗC 0

2.0 0

1.5 0
0 5 10 15 20 0 0 0 0 0 0 0 0 0 0 0
SUPPLY VOLTAGE – V TIME – 100ns/DIV

TPC 14. OP15 Supply Current vs. Supply Voltage TPC 17. OP15 Small Signal Transient Response

5.5 10
VS = 15V
TA = 25ⴗC 10mV 5mV 1mV
OUTPUT VOLTAGE SWING FROM 0V – V

AV = –1

5.0 5
SUPPLY CURRENT – mA

4.5 0
–55ⴗC
25ⴗC

4.0 –5
125ⴗC

10mV 5mV 1mV

3.5 –10
0 5 10 15 20 0 0.5 1.0 1.5 2.0 2.5
SUPPLY VOLTAGE – V SUPPLY VOLTAGE – V

TPC 15. OP17 Supply Current vs. Supply Voltage TPC 18 OP15 Settling Time

REV. A –7–
OP15/OP17
18 90 28
VS = 15V VS = 15V
16 PHASE MARGIN = 86ⴗ 100
TA = 25ⴗC TA = 25ⴗC
14 110 24

PEAK-TO-PEAK OUTPUT SWING – V

AV = 1
12 120

PHASE SHIFT – Degrees

10 130 20
VOLTAGE GAIN – dB

8 140
6 AV > 10 150 16
4 160
2 170 12
0 180
–2 190 8

–4 200
–6 AV = 1 4
–8
–10 0
1M 10M 100M 100k 1M 10M
FREQUENCY – MHz FREQUENCY – MHz

TPC 19. OP15 Closed-Loop Bandwidth and Phase vs. TPC 22. OP15 Maximum Output Swing vs. Frequency
Frequency

28 70
VS = 15V VS = 15V
24 60 AV = 1
BANDWIDTH VARIATION FROM
5V < VS < 20V IS < 5 %
20 SLEW RATE – V/␮sec 50
BANDWIDTH – MHz

NEGATIVE
16 CLOSED-LOOP 40
BANDWIDTH AV = 1

12 30
GAIN BANDWIDTH
PRODUCT
8 20
POSITIVE
4 10

0 0
–50 –25 0 25 50 75 100 125 –50 –25 0 25 50 75 100 125
TEMPERATURE – ⴗC AMBIENT TEMPERATURE – ⴗC

TPC 20. OP15 Bandwidth vs. Temperature TPC 23. OP15 Slew Rate vs. Temperature

120 100
VS = 15V VS = 15V
TA = 25ⴗC TA = 25ⴗC
COMMON-MODE REJECTION RATIO – dB

100
OPEN-LOOP VOLTAGE GAIN – dB

80

80

60
60

40
40

20

20
0

–20 0
1 10 100 1k 10k 100k 1M 10M 100M 1 10 100 1k 10k 100k 1M 10M 100M
FREQUENCY – Hz FREQUENCY – Hz

TPC 21. OP15 Open-Loop Gain vs. Frequency TPC 24. OP15 Common-Mode Rejection Ratio vs. Frequency

–8– REV. A
 OP15/OP17
120 0
TA = 25ⴗC
POWER SUPPLY REJECTION RATIO – dB

0
100

VOLTAGE – 5V/DIV
80
0
POSITIVE SUPPLY

60 0

NEGATIVE SUPPLY
0
40

0
20
0

0 0
10 100 1k 10k 100k 1M 10M 0 0 0 0 0 0 0 0 0 0 0
FREQUENCY – Hz TIME – 200ns/DIV

TPC 25. OP15 Power Supply Rejection Ratio vs. Frequency TPC 28. OP17 Large Signal Transient Response

100 0
VS = 15V
TA = 25ⴗC 0
AV = 100

0
OUTPUT IMPEDANCE – ⍀

VOLTAGE – 20mV/DIV
10
0

AV = 10 0
AV = 1
0
1

0 0
1k 10k 100k 1M 10M 0 0 0 0 0 0 0 0 0 0 0
FREQUENCY – Hz TIME – 100ns/DIV

TPC 26. OP15 Output Impedance vs. Frequency TPC 29. OP17 Small Signal Transient Response

140 10
VS = 15V VS = 15V
TA = 25ⴗC 10mV 5mV 1mV TA = 25ⴗC
OUTPUT VOLTAGE SWING FROM 0V – V

120
VOLTAGE NOISE DENSITY – nV/ Hz

AV = –5

5
100

80
0
60
l/f CORNER FREQUENCY
40
–5
10mV 5mV 1mV
20

0 –10
1k 10k 100k 1M 10M 0 0.5 1.0 1.5 2.0 2.5
FREQUENCY – Hz SUPPLY VOLTAGE – V

TPC 27. OP15 Voltage Noise Density vs. Frequency TPC 30. OP17 Settling Time

REV. A –9–
OP15/OP17
28 120
VS = 15V
TA = 25ⴗC
TA = 25ⴗC

POWER SUPPLY REJECTION RATIO – dB

24
PEAK-TO-PEAK OUTPUT SWING – V

AV = 5 100
POSITIVE
20 SUPPLY
80

16
60
12
NEGATIVE SUPPLY
40
8

20
4

0 0
100k 1M 10M 10 100 1k 10k 100k 1M 10M
FREQUENCY – MHz FREQUENCY – Hz

TPC 31. OP17 Maximum Output Swing vs. Frequency TPC 34. OP17 Power Supply Rejection Ratio vs. Frequency

110 100
NEGATIVE VS = 15V VS = 15V
100 AV = 5 TA = 25ⴗC

OUTPUT IMPEDANCE – ⍀
90
SLEW RATE – V/␮sec

10

80 POSITIVE AV = 100

AV = 10
70

1.0
60

50

40 0
–50 –25 0 25 50 75 100 125 1k 10k 100k 1M 10M
AMBIENT TEMPERATURE – ⴗC FREQUENCY – Hz

TPC 32. OP17 Slew Rate vs. Temperature TPC 35. OP17 Output Impedance vs. Frequency

100 140
VS = 15V
VS = 15V
TA = 25ⴗC
COMMON-MODE REJECTION RATIO – dB

TA = 25ⴗC
120
VOLTAGE NOISE DENSITY – nV/ Hz

80

100

60
80

60
40
l/f CORNER FREQUENCY
40
20
20

0 0
1 10 100 1k 10k 100k 1M 10M 100M 1k 10k 100k 1M 10M
FREQUENCY – Hz FREQUENCY – Hz

TPC 33. OP17 Common-Mode Rejection Ration vs. TPC 36. OP17 Voltage Noise vs. Frequency
Frequency

–10– REV. A
 OP15/OP17
TEST CIRCUITS 2k⍀
0.1%
+15V
V+

10V 400⍀
100k⍀
0V 0.1% 2 7
6
2
7 5 OP17 2N4416
1 1k⍀ 3
6 0.1%
4 100pF
3 –15V 3k⍀ VOUT
4
SUMMING
5k⍀ AV = –1
NODE
NOTE: V OS CAN BE TRIMMED WITH POTENTIOMETERS 0.1%
RANGING FROM 10k⍀ TO 1M⍀. FOR MOST UNITS
TCVOS WILL BE MINIMIZED WHEN VOS IS ADJUSTED SCOPE
2N4416 +15V
WITH A 100k⍀ POTENTIOMETER

Figure 3. Input Offset Voltage Nulling 2k⍀

2k⍀
0.1% Figure 6. OP17 Settling Time Test Circuit
+15V

10V 2k⍀ APPLICATION INFORMATION

0V 0.1% 2 7 Dynamic Operating Considerations
OP15
6
2N4416
As with most amplifiers, care should be taken with lead dress,
5k⍀
0.1%
3 component placement and supply decoupling in order to ensure
4 100pF stability. For example, resistors from the output to an input should
–15V 3k⍀ VOUT
be placed with the body close to the input to minimize “pick-up”
SUMMING
NODE 5k⍀ AV = –1 and maximize the frequency of the feedback pole by minimizing
0.1% the capacitance for the input to ground.
SCOPE
2N4416 +15V A feedback pole is created when the feedback around any amplifier
is resistive. The parallel resistance and capacitance from the input
2k⍀ of the device (usually the inverting input) to ac ground set the
frequency of this pole. In many instances the frequency of this
Figure 4. OP15 Settling Time Test Circuit pole is much greater than the expected, 3 dB frequency of the
close-loop gain, and consequently there is negligible effect on
stability margin. However, if the feedback pole is less than approxi-
mately six times the expected 3 dB frequency, a lead capacitor
should be placed from the output to the negative input of the op
amp. The value of the added capacitor should be such that the
RC time-constant of this capacitor and the resistance it parallels
is greater than, or equal to, the original feedback pole time is constant.

R1 R2
10k⍀ 5k⍀

DIGITAL INPUTS C2
30pF
+10V MSB LSB
+15V
RREF 5 6 7 8 9 10 11 12
5k⍀
B1 B2 B3 B4 B5 B6 B7 B8 7
14 4 2
VREF+ IO 6
DAC08E OP15F
VREF– IO
15 2 3 VO = 0V TO 10V
V+ V– CC VLC 4

3 13 16 1
C1
0.1␮F

+15V –15V –15V

Figure 5. Current-to-Voltage Amplifier Output

REV. A –11–
OP15/OP17
OUTLINE DIMENSIONS
Dimensions shown in millimeters and (inches).

8-Lead Ceramic Dip – Glass Hermetic Seal [CERDIP] 8-Lead Standard Small Outline Package [SOIC]
(Q-8) Narrow Body
(R-8)
0.13 (0.0051) 1.40 (0.0551)

C02789–0–9/02(A)
MIN MAX
5.00 (0.1968)
8 5 4.80 (0.1890)

7.87 (0.3089)
8 5
PIN 1 5.59 (0.2201) 4.00 (0.1574) 6.20 (0.2440)
1 4 3.80 (0.1497) 5.80 (0.2284)
1 4

2.54 (0.1000) BSC

8.13 (0.3201) PIN 1
10.29 (0.4051) MAX
7.37 (0.2902) 1.27 (0.0500) 0.50 (0.0196)
1.52 (0.0600) 1.75 (0.0688) ⴛ 45ⴗ
BSC 0.25 (0.0099)
5.08 (0.2000) 0.38 (0.0150) 0.25 (0.0098) 1.35 (0.0532)
MAX
0.10 (0.0040)
5.08 (0.2000) 3.81 (0.1500) 0.51 (0.0201) 8ⴗ
MIN
3.18 (0.1252) COPLANARITY 0.33 (0.0130) 0.25 (0.0098) 0ⴗ 1.27 (0.0500)
0.10 SEATING 0.41 (0.0160)
0.58 (0.0228) SEATING 0.38 (0.0150) PLANE 0.19 (0.0075)
1.78 (0.0701) PLANE 15
0.36 (0.0142) 0 0.20 (0.0079)
0.76 (0.0299) CONTROLLING DIMENSIONS ARE IN MILLIMETERS; INCH DIMENSIONS
(IN PARENTHESES) ARE ROUNDED-OFF MILLIMETER EQUIVALENTS FOR
CONTROLLING DIMENSIONS ARE IN MILLIMETERS; INCH DIMENSIONS REFERENCE ONLY AND ARE NOT APPROPRIATE FOR USE IN DESIGN
(IN PARENTHESES) ARE ROUNDED-OFF MILLIMETER EQUIVALENTS FOR
REFERENCE ONLY AND ARE NOT APPROPRIATE FOR USE IN DESIGN COMPLIANT TO JEDEC STANDARDS MS-012AA

8-Lead Metal Can [TO-99]

(H-08)

REFERENCE PLANE
12.70 (0.5000)
MIN
4.70 (0.1850)
4.19 (0.1650) 6.35 (0.2500) MIN
2.54 (0.1000) BSC
1.27 (0.0500) MAX 4.06 (0.1600)
3.56 (0.1400)
5
9.40 (0.3700)
8.51 (0.3350)
8.51 (0.3350)
7.75 (0.3050)

4 6 1.14 (0.0450)
5.08
0.69 (0.0270)
(0.2000) 3 7
BSC
2 8

2.54 1
0.48 (0.0190)
(0.1000)
0.41 (0.0160) BSC
1.02 (0.0400) MAX 0.86 (0.0340)
0.53 (0.0210) 0.71 (0.0280)
1.02 (0.0400) 0.41 (0.0160)
0.25 (0.0100) 45 BSC
BASE & SEATING PLANE

CONTROLLING DIMENSIONS ARE IN MILLIMETERS; INCH DIMENSIONS

(IN PARENTHESES) ARE ROUNDED-OFF MILLIMETER EQUIVALENTS FOR
REFERENCE ONLY AND ARE NOT APPROPRIATE FOR USE IN DESIGN
COMPLIANT TO JEDEC STANDARDS MO-002AK

Revision History
Location Page

9/02—Data Sheet changed from REV. 0 to REV. A. PRINTED IN U.S.A.

Deleted OP16 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .Universal

Edits to FEATURES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
Edits to GENERAL DESCRIPTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
Edits to SPECIFICATIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2
Edits to ORDERING GUIDE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2
Edits to ABSOLUTE MAXIMUM RATINGS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2
Edits to DICE CHARACTERISTICS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
Edits to WAFER TEST LIMITS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
Deleted 12 TPCs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11-12
Updated OUTLINE DIMENSIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12

–12– REV. A