HARDWARE INTERN JD – NVIDIA
Do you have a passion for computing using new age technologies?
Do you want to work on leading-edge problems alongside some of the best & brightest in the
world?
Do you like working in a dynamic working environment that involves creative problem solving
and thinking on your feet?
We, at NVIDIA, want to nd and bring the brightest young technologists of our generation to
do their life’s best work at NVIDIA.
We are hiring interns for a duration of 1-year for positions in our HW teams and a brief about
the teams and their requirements is given below.
CPU VERIFICATION TEAM
As a design and veri cation/validation engineer in the ARM CPU team, you will be working on
the next generation of 64bit ARM CPUs and SOCs. As part of this assignment, you will get a
chance to learn about computer architecture at a very granular level, System Verilog, Design
Veri cation, SOC Veri cation, Veri cation methodologies and C/C++ programming. You also will
get an opportunity to get familiar with industry standard tools in veri cation and validation.
During the course of the internship, you will contribute to building test benches, developing
architectural simulators, modifying random instruction generators, and creating stimulus for
veri cation and validation of di erent units of the CPU and SOC.
Areas you will be working on:
• Computer Architecture
• Digital Design and Programming in C/C++/Perl
• ARM, CPU Design and Veri cation/ Validation
ASIC-PD (Timing Closure / VLSI)
VLSI team works in the areas of RTL Design, Veri cation, Design for Test, CAD tools, Synthesis,
Timing, Place & Route, Circuit Design, Silicon Bring-up and Characterization. Responsible for
state-of-the-art methodologies, tools, ows and project execution on all Nvidia GPU, CPU,
Auto, and Switch chips. As an intern you will be working on one or more such areas.
Skills you will use/develop:
RTL Design, VCS, SV, UVM, Formal
Verilog, C/C++, Python, TCL, Perl
Logic Scan Test, Memory Test, High-speed IO Test, In-System Test
Synthesis, Timing Closure (Primetime)
Physical Design, Innovus, ICC2, Physical extraction, Place and Route, Floorplan
SRAM, Analog, Digital circuit design, Hspice, EMIR, Silicon Correlation (ATPG, data
visualization & analysis)
Layout (Cadence Virtuoso)
Silicon characterization for ageing, DPPM, Signal Integrity, Power Integrity, and familiarity
with PC/SOC sub-system Architecture.