Chapter 1: 8086 Microprocessor

Outlines:
– µ-processors-Evolution and Introduction
– Signal Description of 8086
– 8086 Architecture
– Functional Diagram of 8086
– Register Organization
– Memory Segmentation
– Minimum and Maximum Mode signals

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 Prerequisites: Microprocessor Architecture
 Course Objectives:
1. To learn the Peripheral architecture and
programming 0f Microprocessor.
2. To learn peripherals and their interfacing with 8086
Microprocessor.
3. To study the DOS Internals.
4. To Study NDP and Design of Microprocessor based
System.
 Course Outcomes:
1.Ability to handle, interface and program using legacy
peripherals
2.Ability to understand I/O Hub functions

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Books
 Adv microprocessors and peripherals - Tata Mcgraw
Hill – Ray
 Microprocessors and interfacing – McGraw – Douglas
Hall
 Assembly language programming – Pearson – Peter
Abel

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Bits and bytes
 1 Bit = Binary Digit
 8 Bits = 1 Byte
 1024 Bytes = 1 Kilobyte
 1024 Kilobytes = 1 Megabyte
 1024 Megabytes = 1 Gigabyte
 1024 Gigabytes = 1 Terabyte
 1024 Terabytes = 1 Petabyte
 1024 Petabytes = 1 Exabyte
 1024 Exabytes = 1 Zettabyte
 1024 Zettabytes = 1 Yottabyte
 1024 Yottabytes = 1 Brontobyte
 1024 Brontobytes = 1 Geopbyte

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 INTRODUCTION

• The microprocessor is an electronic chip that functions as the

central processing unit of a computer.

• Microprocessor based systems with limited resources are called

microcomputers.

• Today microprocessor found in almost all consumer electronic

devices such as computer printers, washing machines,
microwave ovens and in advanced applications such as satellites,
radars and flights.

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What is a microprocessor?
 An integrated circuit that performs the functions of a
CPU.
 So, a chip on machine…
 Which microprocessors do you know?
 8085,8086,80285,80386,486,pentium…..
 Which is latest?
 Intel core i3, i5, i7
 What type of processor?
 16 or 32 or 64?

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32 or 64 bit?
 What determines that my machine is 32 or 64?
 Amount of data that can be handled
 The RAM support for 32 bit is 4 GB where as for 64 bit it
is 16EB.
 64 bit of course leads to faster operations.

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What is 8086?
• It is a 16 bit µp.

• 8086 has a 20 bit address bus can access up to 220

memory locations ( 1 MB) .

• It can support upto 64K I/O ports.

• It provides 14, 16-bit registers.

• It has multiplexed address and data bus AD0- AD15

and A16 – A19.

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 Evolution of Microprocessor
• It is a program-controlled device, which fetches the
instructions from memory, decodes and executes the
instructions.

• Most Micro Processor are single- chip devices.

• It is a backbone of computer system. which is called CPU

• Its speed depends on the on DATA BUS WIDTH.

• A common way of categorizing microprocessors is by the no.

of bits that their ALU can Work with at a time.

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 Cont..
• The address bus is unidirectional because the address information is
always given by the Micro Processor to address a memory location
of an input / output devices.

• The data bus is Bi-directional because the same bus is used for
transfer of data between Micro Processor and memory or input /
output devices in both the direction.

• Most Microprocessor does not support floating-point operations.

• Microprocessor contain ROM chip because it contain instructions to

execute data.

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1st / 2nd / 3rd / 4th generation processor
• The processor made of PMOS technology is called 1st generation
processor, and it is made up of 4 bits
• The processor made of NMOS technology is called 2nd generation
processor, and it is made up of 8 bits
• The processor made of CMOS technology is called 3rd generation
processor, and it is made up of 16 bits
• The processor made of HCMOS technology is called 4th generation
processor, and it is made up of 32 bits (HCMOS : High-density n- type
Complementary Metal Oxide Silicon field effect transistor)

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8086 Architecture

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 Cont..
• Clock: The clock is a symmetrical square wave
signal that drives the CPU Instructions:
• An instruction is an elementary operation that
the processor can accomplish. Instructions are
stored in the main memory, waiting to be
processed by the processor. An instruction has
two fields:
• Operation code represents the action that the
processor must execute.
• Operand code defines the parameters of the action.
The operand code depends on the operation. It can be
data or a memory address.
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Overview or Features of 8086

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Architecture - 8086

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 Architecture of 8086
 8086 has two blocks BIU and EU.
 The BIU performs all bus operations such as
instruction fetching, reading and writing operands for
memory and calculating the addresses of the memory
operands.
 The instruction bytes are transferred to the instruction
queue.
 EU executes instructions from the instruction system
byte queue.

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 Cont..
 BIU and EU operate asynchronously to give the 8086
an overlapping instruction fetch and execution
mechanism which is called as Pipelining.
 This results in efficient use of the system bus and
system performance.
 BIU contains Instruction queue, Segment registers,
Instruction pointer, Address adder.
 EU contains Control circuit, Instruction decoder, ALU,
Pointer and Index register, Flag register

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 Cont..
 Bus Interface Unit:
 It provides a full 16 bit bidirectional data bus and 20
bit address bus.
 The bus interface unit is responsible for performing all
external bus operations.
 Specifically it has the following functions:
 Instruction fetch, Instruction queuing, Operand fetch
and storage, Address relocation and Bus control.
 The BIU uses a mechanism known as an instruction
stream queue to implement a pipeline architecture.

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 Cont..
 EXECUTION UNIT :
 The Execution unit is responsible for decoding and
executing all instructions.
 The EU extracts instructions from the top of the queue in
the BIU, decodes them, generates operands if necessary,
passes them to the BIU and requests it to perform the read
or write bys cycles to memory or I/O and perform the
operation specified by the instruction on the operands.
 During the execution of the instruction, the EU tests the
status and control flags and updates them based on the
results of executing the instruction.

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Pin diagram - 8086

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8086 pin description cont..

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Important Pin descriptions
 AD0-Ad15: Multiplexed memory/IO address and data bus.
 ALE: High the lower order bits to be latched, then these
can be used for the data.
 READY: Acknowledgement from addressed memory or IO
that it will complete the operation.
 INTR: Level triggered input, helps in determining whether
the processors should enter into interrupt ack operation. A
subroutine is vectored through an interrupt vector table.
 INTA: interrupt ack from the Microprocessor
 RESET: Causes processor to terminate its present activity.
Signal must be high fro at least 4 clock cycles. Restarts the
execution.

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Common signals for 8086

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The Programming Model
8086
 General Purpose Registers
 Segment Registers
 Flag Register
 Pointer and index Registers
SP

BP
AX AH AL CS

SI
BX BH BL DS

CX DI
CH CL ES

DX DH DL SS Flag IP

General Purpose Segment Registers Flag Register Pointer and Index Registers

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Registers Organisation
 16-Bit General Purpose Registers
– can access all 16-bits at once
– can access just high (H) byte, or low (L) byte

 only the General Purpose

registers allow access as 8-
bit High/Low sub-
registers

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 Cont..
 Register Set
16-Bit Segment Addressing Registers
CS Code Segment
DS Data Segment
SS Stack Segment
ES Extra Segment

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 Cont..
16-Bit Offset Addressing Registers
SP Stack Pointer
BP Base Pointer
SI Source Index
DI Destination Index

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 Cont..
16-Bit Control/Status Registers
- IP Instruction Pointer (Program Counter
for execution control)
- FLAGS 16-bit register

• It is not a 16-bit value but it is a

collection of 9 bit-flags (six are unused)

• Flag is set when it is equal to 1

• Flag is clear when it is equal to 0

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General purpose Registers
 AX
 Accumulator Register

 Preferred register to use in arithmetic, logic and data

transfer instructions because it generates the shortest

Machine Language Code

 Must be used in multiplication and division operations

 Must also be used in I/O operations

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 Cont..

 BX
 Base Register

 Also serves as an address register

 Used in array operations

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 Cont..

 CX
 Count register

 Used as a loop counter

 Used in shift and rotate operations

 DX

 Data register

 Used in multiplication and division

 Also used in I/O operations

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Pointer & Index Registers
 Contain the offset addresses of memory locations

 Can also be used in arithmetic and other operations

 SP: Stack pointer

 Used with SS to access the stack segment

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Pointer & Index Registers (continued)

 BP: Base Pointer

 Primarily used to access data on the stack

 Can be used to access data in other segments

 SI: Source Index register
 is required for some string operations

 When string operations are performed, the SI register

points to memory locations in the data segment which

is addressed by the DS register. Thus, SI is associated
with the DS in string operations. 33
Pointer & Index Registers (continued)
 DI: Destination Index register
 is also required for some string operations.

 When string operations are performed, the DI register

points to memory locations in the data segment which

is addressed by the ES register. Thus, DI is associated
with the ES in string operations.

 The SI and the DI registers may also be used to access

data stored in arrays
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Segment Registers
 Are Address registers

 Store the memory addresses of instructions and data

 Memory Organization

 Each byte in memory has a 20 bit address starting with 0

to 220-1 of addressable memory

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Segment Registers (continued)
 Addresses are expressed as 5 hex digits from 00000 -

FFFFF

 Problem: But 20 bit addresses are TOO BIG to fit in 16

bit registers!

 Solution: Memory Segment

 Block of 64K (65,536) consecutive memory bytes

 A segment number is a 16 bit number

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Segment Registers (continued)
 Segment numbers range from 0000 to FFFF

 Within a segment, a particular memory location is

specified with an offset

 An offset also ranges from 0000 to FFFF

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Segment Registers (continued)
 If the segment address is for example, 2915, then the
addresses in this segment start at 2915:0000 and go up
to 2915:FFFF, which is the highest address in this
particular segment.

 This range expressed in terms of absolute or physical

addresses is from 29150 through 3914F.
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Segment Registers (continued)

Memory Model for 20-bit Address Space 39

Memory Segmentation

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Memory Segmentation

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Memory Address Generation
Offset Value (16 bits)

Segment Register (16 bits) 0000

Adder

Physical Address (20 Bits)

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Memory Address Generation
 to calculate physical memory address

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 Flag Register

Carry flag
Overflow

Direction Parity flag

Interrupt enable Auxiliary flag

Trap Zero

Sign
6 are status flags
3 are control flag

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Pinout Diagram

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Minimum mode operation

Ground Power Supply

5V  10%

Reset

Registers, seg regs, flags

CS: FFFFH, IP: 0000H
Clock If high for minimum 4 clks
Duty cycle: 33%

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Minimum mode operation ( Conti..)

Address/Data Bus:

Contains address bits

A15-A0 when ALE is 1 &
data bits D15 – D0
Address Latch Enable:
when ALE is 0.
When high, multiplexed
address/data bus contains
address information.

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 Minimum mode operation ( Conti..)

INTERRUPT

Non-maskable interrupt

Interrupt acknowledge
Interrupt request

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Minimum mode operation ( Conti..)

Memory Access

Hold

Hold acknowledge

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Minimum mode operation ( Conti..)
S6: Logic 0.

S5: Indicates Address/Status Bus

condition of IF flag
bits. Address bits A19 – A16 &
Status bits S6 – S3
S4-S3: Indicate
which segment is
accessed during
current bus cycle:

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Minimum mode operation ( Conti..)

BHE#, A0: Bus High Enable/S7

0, 0: Whole word Enables most significant

(16-bits) data bits D15 – D8 during
read or write operation.
0,1: High byte S7: Always 1.
to/from odd address

1,0: Low byte

to/from even address

1,1: No selection

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Minimum mode operation ( Conti..)
Min/Max mode

Minimum Mode: +5V

Maximum Mode: 0V

Min mode pins

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Minimum mode operation ( Conti..)

When 1, transmit mode,

when 0 receive mode from
memory or IO

Indicates the availability

of valid data over address
and data lines. Active
from t2 to t4

Determined by wait
instruction, when
goes low, continue
else idle state 53
Minimum mode operation ( Conti..)
Read Signal

Write Signal

Memory or I/0

Data Bus Enable

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Maximum mode operation

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Maximum mode operation ( Conti..)

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 Maximum mode operation ( Conti..)
S2 S1 S0
000: INTA
001: read I/O port
010: write I/O port
011: halt
100: code access
101: read memory Status Signal
110: write memory Inputs to 8288 to generate
111: none -passive eliminated signals due to
max mode.

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Maximum mode operation ( Conti..)

DMA
Request/Grant

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 Maximum mode operation ( Conti..)

Lock Output
Used to lock peripherals
off the system
Activated by using the
Lock Output
LOCK: prefix on any
instruction

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 Maximum mode operation ( Conti..)

QS1 QS0
00: Queue is idle
01: First byte of opcode
Queue Status
10: Queue is empty
Used by numeric
11: Subsequent byte of coprocessor (8087)
opcode

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8288 Bus Controller – Bus Command and Control
• Signals: 8086 does not directly provide all the signals that are
required to control the memory, I/O and interrupt interfaces.

• Specially the WR, M/IO, DT/R, DEN, ALE and INTA, signals are
no longer produced by the 8086. Instead it outputs three status
signals S0, S1, S2 prior to the initiation of each bus cycle. This 3-
bit bus status code identifies which type of bus cycle is to follow.

• S2 S1 S0 are input to the external bus controller device, the bus

controller generates the appropriately timed command and
control signals.

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Min-Max modes
Min mode Max mode
1. MN/ MX high MN/MX low

2. Generates INTA(bar), ALE, Generates QS1, QS0, S0(bar) ,S1(bar) ,

DEN(bar), DT/R(bar), M/IO(bar), S2(bar),LOCK(bar),RQ(bar)/GT1,RQ(b
HLDA,HOLD and WR(bar) control ar)/GT0 control signals.
signals.
3. There is only one processor in the clearly there are multiple processors in
system the system
4. No interfacing or master/slave interfacing, master/slave and
signals is required multiplexing and several such control
signals are required
5. Direct RD WR signals can be used. A bus controller is required to produce
No bus controller required. A simple control signals. This bus controller
demultiplexer would do the job. of produces MEMRDC, MEMWRC,
producing the control signals. This IORDC, IOWRC, ALE, DEN, DT/R
demultiplexer produces MEMRD, control signals
MEMWR, IORD, IOWR control signals

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 Thank You

END OF CHAPTER ONE

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