WELCOME

ITC is the world’s premier conference dedicated to electronics test. This year’s ITC continues with its
mission to play a unique role as an information sharing forum, where the wide range of its offerings
allows ITC participants to learn, network and conduct business. This year’s program includes a top-
notch technical program, vibrant exhibitors, information-packed tutorials, interactive technical panels,
two focused workshops, as well as the all-important networking that these events can provide. The
technical program has been designed to optimize personal interactions on all levels. This year’s program
will include papers from a pool of impressive submissions and solicited papers. Of these submissions, a
large number will focus on AI, automotive, memory, and hardware security. In complement to the paper
presentations, there will be special sessions on hardware security certification, chiplet integration, silicon
lifecycle management, computing in memory, as well as design and test of high-power compound
devices and quantum electronics.

We are continuing and expanding on the inclusion of the Industrial Practice papers sessions as ITC has
a very strong focus on industry practice as well as industry and academia advances. The three keynotes
will encompass the past, present and future of our industry. In addition, there will be a visionary talk
on AI accelerators.

ITC 2022 features a vibrant exhibition showcasing relevant companies. The exhibition will serve as a
convenient one-stop-shop for all the elements of test technology.

In the past 53 years, ITC has helped globalize our industry and wants to continue to do so in the future.
This year’s return to a live event will enable us to embrace all the features of the conference we have
missed such as personal interaction.
ADMISSION TO ITC AND TEST WEEK ACTIVITIES
A personal registration badge is required for admission to all Test Week™ Activities.
LOCATION OF EVENTS
ITC Test Week 2022 events will take place at the Disneyland Hotel, Anaheim, CA. Check the Technical
Session listings for session locations.

PANEL SESSIONS
ITC encourages the free exchange of ideas in panel sessions. Opinions in these sessions are often in a
formative stage and do not represent completed work or the official position of the speaker or of his or
her company. Panel sessions are "off the record"―what is said in them is not for quotation or
attribution. Tape recorders and cameras are not permitted.
PHOTOGRAPHY AND RECORDINGS
Attendance at, or participation in, this conference constitutes consent to the use and distribution by IEEE
of the attendee’s image or voice for informational, publicity, promotional and/or reporting purposes in
print or electronic communications media.
Video recording by participants and other attendees during any portion of the conference is not allowed
without special prior written permission of IEEE.
Photographs of copyrighted PowerPoint or other slides are for personal use only and are not to be
reproduced or distributed. Do not photograph any such images that are labeled as confidential and/or
proprietary.

REGISTRATION FOR ALL EVENTS

ITC registration counter at the Disneyland Hotel
Sunday: 7:30 am – 3:00 p.m. Monday: 7:30 a.m. – 5:00 p.m.
Tuesday: 8:00 a.m. – 6:00 p.m. Wednesday: 8:00 a.m. – 4:00 p.m.
Thursday: 8:00 a.m. – 3:00 p.m. Friday: 7:30 a.m. – 12:00 p.m.
Registration is closed 12:00 – 1:00 p.m. Tuesday – Thursday, 11:00 a.m.
– 1:00 p.m. Sunday, Monday
HIGHLIGHTS TABLE OF CONTENTS

TTTC TUTORIALS Awards – Paper and TTTC, ITC

TTTC presents 12 half-day tutorials on Sunday Committees
and Monday. Disney Convention Center Map
MONDAY PANEL Tuesday Corporate Forum
An Industry-wide Dialog on Chiplets and Wednesday Corporate Forum
Heterogeneous Integration Exhibitor Booth Index
KEYNOTE TALKS
Exhibitor Profiles
Keynotes on Tuesday, Wednesday and Exhibitor Ads: Start Here
Thursday. Exhibit Hours………….………. see below
Exhibits Passport
VISIONARY TALKS Exhibit Hall Map
One Visionary Talk Wednesday.
Fringe Meetings
TECHNICAL SESSIONS General Information ….……previous page
22 technical paper sessions Tuesday – Thursday Highlights ……….……………….this page
SPECIAL SESSIONS Tuesday Keynote
10 special sessions Tuesday – Thursday Wednesday Keynote and Visionary Talk
Thursday Keynote
ITC WELCOME RECEPTION Panels: 1, 2, 3, 4
All ITC registered full-conference attendees and Plenary Session/Keynote
exhibitors are invited to attend on Tuesday from
6:00 p.m. to 8:00 p.m.
Post-Panel Reception
Posters
POSTER SESSIONS Proceedings Distribution
View 36 posters in the exhibit hall. Registration Hours
CORPORATE FORUM Technical Papers: Tuesday, Wednesday,
The latest technical innovations from our Thursday,
exhibitors and corporate supporters. Test Week At-a-Glance
Tutorials
WORLD-CLASS EXHIBITS Workshops
See the latest technology on the exhibit floor. Welcome Reception
EXHIBITS PASSPORT PROGRAM
Visit company booths to be eligible for prizes.

COMPLIMENTARY EXHIBIT HALL

LUNCHES DAILY EXHIBIT HOURS
Tuesday, Wednesday and Thursday for full-
conference and one-day conference registrants. Tuesday 10:30 a.m. – 5:30 p.m.
WORKSHOPS Wednesday 9:30 a.m. – 4:30 p.m.
TTTC presents two two-day workshops on Thursday 9:30 a.m. – 1:00 p.m.
Thursday and Friday.
Complimentary lunch
FRINGE TECHNICAL MEETINGS Tuesday, Wednesday and Thursday
TTTC committees and standards working groups. in the exhibit hall for full- and one-day
ITC conference registrants.

Free exhibits entry every day

(Registration required - lunch not
included)
 ITC 2022 Supporters and Sponsors

Corporate Supporters

Diamond

Platinum

Gold

Silver

Sponsors

Philadelphia Section
 TUTORIALS Sunday, September 25 8:30 a.m. – 4:30 p.m.
Monday, September 26 8:30 a.m. – 4:30 p.m.

The Tutorials and Education Group of the IEEE Computer Society Test Technology Technical Council
(TTTC) organizes a comprehensive set of Test Technology Educational Program (TTEP) tutorials.
TTEP offers fundamental education and expert knowledge in state-of-the-art test technology topics and
also the opportunity to earn official certification from IEEE TTTC under the TTEP program.
The following 12 half-day tutorials qualify for credit towards IEEE TTTC certification.

Tutorials are a half-day in length. One-Day tutorial registration fee is for two tutorials—a morning
tutorial and afternoon tutorial, both on the same day, e.g., Tutorial 1 and Tutorial 4 on Sunday. You may
register for up to four tutorials (two consecutive on Sunday and two consecutive on Monday).
All-Access Pass tutorial registration provides in-and-out access to all twelve tutorials over both days.
For more information, inquire at the registration counter.
Room assignments are subject to change. Please see the digital monitors for the latest information.

Sunday 8:30 a.m. – 12:00 p.m. Monday 8:30 a.m. – 12:00 p.m.
TUTORIAL 1 Magic Kingdom Ballroom 1 TUTORIAL 7 Magic Kingdom Ballroom 1
Dependability and Testability of AI Silicon Lifecycle Management for
Hardware Emerging SOCs
F. Su, H. Stratigopoulos, Y. Makris Y. Zorian, F. Massoudi
TUTORIAL 8 Magic Kingdom Ballroom 3
TUTORIAL 2 Magic Kingdom Ballroom 3 Testing and Monitoring of Die-2-Die
Early System Reliability Analysis for Interconnects in 2.5D/3D IC
Cross-layer Soft Errors S.-Y. Huang
A. Bosio, S. Di Carlo, A. Salvino
TUTORIAL 9 Grand Ballroom North B
TUTORIAL 3 Magic Kingdom Ballroom 4 Domain-Specific Machine Learning in
Device-Aware Test for Emerging Semiconductor Test
Memories L.-C. Wang
S. Hamdioui

Sunday 1:00 p.m. – 4:30 p.m. Monday 1:00 p.m. – 4:30 p.m.
TUTORIAL 4 Magic Kingdom Ballroom 1 TUTORIAL 10 Magic Kingdom Ballroom 1
Computation in Memory: Technologies, Automotive Safety, Reliability and Test
Design, Test and Reliability Solutions
M. Tahoori R. Mariani, Y. Zorian

TUTORIAL 5 Magic Kingdom Ballroom 3 TUTORIAL 11 Magic Kingdom Ballroom 3

Mixed-Signal DFT and BIST: Trends, SoC Security Verification
Principles and Solutions M. Tahoori, F. Farahmandi
S. Sunter
TUTORIAL 12 Grand Ballroom North B
TUTORIAL 6 Grand Ballroom North B Advances in Defect-Oriented Testing
Scan Test Escapes, New Fault Models, A. Singh, A. Glowatz
and the Effectiveness of Functional
System Level Tests
A. Singh

Tutorial attendees receive study material, breaks and lunches on the days attended. Tutorial registration,
coffee and pastry are available at 7:30 a.m. on Sunday and Monday. Lunch is served from 12:00 p.m.
to 1:00 p.m.

Table of Contents
 PANEL Monday, September 26 4:30 p.m. – 6:00 p.m.

PANEL 1 Magic Kingdom Ballroom 1 & 4

An Industry-wide Dialog on Chiplets and Heterogeneous Integration

Moderator: Phil Nigh
Three short presentations will be followed by a dialog with the audience. The goal: to gather feedback
on the HR roadmap projections and about current and future test standards. .
Panelists: Jeff Rearick (AMD) on chiplet trends and drivers
Yervant Zorian, Synopsys on UCIe
Ken Butler (Advantest) on HIR

Post-panel reception follows 6:00 p.m. – 7:30 p.m.

Following this panel on Monday afternoon, stick around for a reception to carry on the
lively discussion. Meet us at the Adventure Lawn for some networking over libations and
hors d’oeuvres.

Tomorrow (Tuesday)
Continental breakfast: 8:00 a.m.
Plenary: 9:00 a.m.
Exhibits open: 10:30 a.m. – 5:30 p.m.
Corporate forum: 11:30 a.m.
Exhibit hall lunch: 12:00 p.m.
Technical sessions: 2:00 p.m.
ITC Welcome Reception: 6:00 p.m. – 8:00 p.m.

ITC 2022 PROCEEDINGS DISTRIBUTION

4:30 p.m. – 6:00 p.m.

ITC Proceedings Are Delivered Electronically

All ITC full-conference and one-day attendees, including students, will receive access to
the 2022 ITC online proceedings free of charge.
.

Preregistered Full-Conference Attendees

All preregistered full-conference attendees should have received an email containing a
proceedings download link a few days before the conference. The ITC 2022 technical
presentations will be available at the Underline site for ITC. Information on how to
access them will be provided to all registrants before the conference.

Onsite Full-Conference and One-Day Attendees

Full-conference and one-day attendees registering onsite will receive the links
at the time of registration.

.
 SUNDAY, SEPTEMBER 25 – HALF-DAY TUTORIALS
8:30 a.m. – Tutorial 1 Tutorial 2 Tutorial 3
12:00 p.m. Dependability and Early System Reliability Device-Aware Test for
Testability of AI Hardware Analysis for Cross-layer Emerging Memories
Soft Errors

1:00 p.m. – Tutorial 4 Tutorial 5 Tutorial 6

4:30 p.m. Computation in memory: Mixed-Signal DFT and Scan Test Escapes, New
Technologies, Design, Test BIST: Trends, Principles Fault Models, and the
and Reliability and Solutions Effectiveness of
Functional System Level
Tests

MONDAY, SEPTEMBER 26 – HALF-DAY TUTORIALS

8:30 a.m. – Tutorial 7 Tutorial 8 Tutorial 9
12:00 p.m. Silicon Lifecycle Testing and Monitoring of Domain-Specific
Management for Emerging Die-2-Die interconnects in Machine Learning in
SOCs 2.5D/3D IC Semiconductor Test

1:00 p.m. – Tutorial 10 Tutorial 11 Tutorial 12

4:30 p.m. Automotive Safety, SoC Security Verification Advances in Defect-
Reliability and Test Oriented Testing
Solutions

4:30 p.m. – Panel 1 - An Industry-wide Dialog on Chiplets and Heterogeneous

6:00 p.m. Integration
 TUESDAY, SEPTEMBER 27 – TECHNICAL SESSIONS
9:00
a.m. – Plenary – Opening Session Keynote: Make Computing Count: Some Grand
10:30 Opportunities for Testing, Parthasarathy Ranganathan, Google
a.m.

10:30 , President, Macronix International Corp., Chairman and CEO, Ardentec Corp.
a.m. – Exhibits
5:30 p.m.

11:00
a.m. –
Diamond Supporter Presentation
12:00
p.m.

12:00
p.m. – Lunch and Corporate Forum
2:00 p.m.

Session E1
Session D1 Special
Session B1 Session
Session A1 TTTC
2:00 p.m. Innovation and Session C1 Dedicated
New Frontiers McCluskey
– 3:30 Machine Diagnosis and to the Memory of
in Fault PhD
p.m. Learning I Debug T. W.
Modeling Competition
Williams,
W. Maly and
D. Pradhan

3:30
p.m. –
Coffee Break
4:00
p.m.

4:00 Session A2 Session B2 Session C2 Session D2 Session E2

p.m. – Panel 2 Innovation New Test of HW Special
5:30 Are Last with Machine Frontiers in Accelerators I Session:
p.m. Century’s Learning II Test Content Experiences
Test Optimization in Silicon
Techniques Lifecycle
Suitable for Management
21st Century
Silent
Errors?

6:00 ITC Welcome Reception – Adventure Lawn

p.m. -
8:00
p.m.
 WEDNESDAY, SEPTEMBER 28 – TECHNICAL SESSIONS
Plenary Session
9:00 Keynote: The Future of High-Performance Computing Beyond Moore’s Law,
a.m. – John Shalf, Lawrence Berkeley National Labs
10:30
a.m. Visionary Talk: Ultra Low-Power AI Accelerators for AIoT, Tim Cheng, The
Hong Kong University of Science and Technology

9:30 a.m.
– 4:30 Exhibits
p.m.

10:30
a.m. –
Coffee Break and Corporate Forum
11:00
a.m.

Session C3 Session D3 Session E3

11:00 Session B3 Industrial
Session A3 Memory Special
a.m.– Latest on Practices I
Hardware Test/Diagno Session on
12:30 Wafer Map
Security I sis Compute-In-
p.m. Analytics
Memory

12:30
p.m. – Lunch, Posters and Corporate Forum
2:30 p.m.

Session B4
Session A4
2:30 p.m. Test of HW Session C4 Session D4 Session E4
Hardware
– 4:00 Accelerators Memory Automotive I Industrial
Security II
p.m II Test/Repair Practices II

4:00
p.m. –
Coffee Break
4:30
p.m.

4:30 Session A5 Session B5 Session C5 Session D5 Session E5

p.m. – Special Analog Panel 3: Automotive: Analog Test,
6:00 Session on Testing Performing Special Diagnosis,
p.m. HW Security RAS in Session on Test Cost,
Certification Today’s High-Power All-In-One
Mission Electronics
Critical
Systems

Table of Contents
 THURSDAY, SEPTEMBER 29 – TECHNICAL SESSIONS
9:00 Plenary Session
a.m. – Keynote: What Did We Learn in 120 Years of DFT and Test? Grady Giles, Mike
10:00 Bienek, & Tim Wood, AMD
a.m.

9:30 a.m.
– 1:00 Exhibits
p.m.

10:00
a.m. –
Coffee Break
10:30
a.m.

Session A6 Session B6 Session C6 Session D6 Session E6

Special Scan-Based Special Automotive II Industrial
10:30 Session on Learning and Session: Practices III
a.m.– Test of Diagnosis Road to
12:00 Quantum Chiplets:
p.m. Circuits UCIe

12:00
p.m. – Lunch
1:30 p.m.

Session E7
Session C7 Special
Special Session:
Session: Session D7 Industrial
Session A7
Session B7 Design-for- Panel 4: Practices from
1:30 p.m. Test
Low Power Verification Automotive ITC India
– 3:00 Generation
and Test (DfV): A New Safety &
p.m.
Direction in Security
Design Interoperability
Qualification

THURSDAY, SEPTEMBER 29 – WORKSHOPS

4:00 p.m. ART 2022: IEEE Automotive Reliability 2nd IEEE Intl Workshop on Silicon
– 6:30 and Test & Safety Workshop 2022 Lifecycle Management (SLM)
p.m. Plenary1: Opening, Keynote Plenary1: Opening, Keynote

FRIDAY, SEPTEMBER 30 – WORKSHOPS

8:00 a.m. ART 2022: IEEE Automotive 2nd IEEE Intl Workshop on Silicon
– 4:00 Reliability and Test & Safety Lifecycle Management (SLM)
p.m. Workshop 2022
 PLENARY 1 Tuesday, September 27 9:00 a.m. – 10:30
a.m.
Disney Grand Ballroom
Opening Remarks
Teresa McLaurin, ITC 2022 General Chair

Keynote Address 1
Make Computing Count: Some Grand Opportunities for Testing
Parthasarathy Ranganathan
VP/technical Fellow, Google

This talk will discuss the trends shaping the future computing landscape, with a specific focus on the
role of testing -- for correctness, agility, and performance -- and some grand challenges, and
opportunities, for the field.

About the speaker: Partha Ranganathan is currently a VP, technical Fellow at Google where he is
the area technical lead for hardware and datacenters, designing systems at scale.

ITC Paper Awards TTTC Awards

Theresa McLaurin, ITC 2021 Program Yervant Zorian
Chair
TTTC Life Time Contribution Medal
ITC Ned Kornfield Best Paper Award
Exploiting Application Tolerance for ITC/TTTC G. Gordon Student Service Award
Functional Safety
TTTC Bob Madge Innovation Award
P. V. Pillai, R. Parekhji, Texas Instruments,
India; B. Amrutur, Indian Institute of
Science

Honorable Mentions ITC 2022 Technical Program

Introduction
A Fast and Low Cost Embedded Test
Solution for CMOS Image Sensors Kuen-Jong Lee, ITC 2022 Program Chair
J. Lefevre,P. Debaud, STM
Microelectronics; P. Girard, A. Virazel,
LIRMM Imaging Division, DFT University Closing Remarks
of Montpellier
T. McLaurin, ITC 2022 General Chair
Improving Volume Diagnosis and Debug
with Test Failure Clustering and
Reorganization
M-T Wu, C-S Kuo, J. C-M Li, National
Taiwan University; C. Nigh, G. Bhargava,
Qualcomm

Table of Contents
 CORPORATE FORUM Tuesday, September 27 11:00 a.m. – 2:00 p.m.

Exhibit Hall

The corporate forum allows you to stay on top of the latest commercial products in the semiconductor test
industry and helps you understand how the innovations behind the products can add value to your workIn
this interactive forum, ITC exhibitors and supporters will make presentations describing their company, its
products and product roadmaps.. Typical presentations include case studies, best practices and
testimonials.

11:00 a.m.–12:00 p.m.

Disney Grand Ballroom Center
1:45 p.m. Galaxy
Siemens
Diamond Supporter Event
Open Architecture and Democratized Data
1. DFT to In-Life monitoring for Systems: The Logical Evolution of Test
dependable electronic systems. A. Data Analytics,
Gupta, Siemens D. King, Galaxy
2. Reducing Design Effort, Test Time
And Power With SSN in AWS Custom
Silicon, D. Trock, Amazon
3. Advancements in DFT automation for
2.5D / 3D IC era, V. Neerkundar,
Siemens
4. Structural Deterministic Test in Silicon
Lifecycle, J. Rajski, Siemens

12:00 p.m.–2:00 p.m.

Exhibit Hall

12:00 p.m. Synopsys

Test and Analytics: Enabling Silicon

Lifecycle Management,
R. Ruiz, Synopsys

12:30 p.m. Advantest

Enabling Leading-Edge Technologies in an

Exascale Era,
K. Schaub, Advantest

1:30 p.m. Chroma

Facing the Challenges in Automated

Handling of Advanced IC Packaging,
J. Hauck, Chroma
 TECHNICAL SESSIONS Tuesday, September 27 2:00 p.m. – 3:30 p.m.

SESSION A1 Magic Kingdom Ballroom 1 SESSION B1 Magic Kingdom Ballroom 2

New Frontiers in Fault Modeling
S. Adham (Chair) Innovation with Machine Learning I
A1.1 PEPR: Pseudo-Exhaustive Physical K. Butler (Chair)
Region Testing B1.1 DeepTPI: Test Point Insertion with
W. Li, D. Duvalsaint, R. Blanton*, Carnegie Deep Reinforcement Learning
Mellon University; C. Nigh, Qualcomm Z. Shi*, M. Li, S. Khan, Q. Xu, The Chinese
Technologies, Inc.; S. Mitra, Stanford University of Hong Kong; L. Wang, Huawei
University Technologies Co., Ltd.; N. Wang, Y. Huang,
A1.2 Error Model- A New Way of Doing Hisilicon
Fault Simulation B1.2 Efficient and Robust Resistive Open
N. Saxena*, A. Lotfi, NVIDIA Defect Detection Based on
A1.3 Using Custom Fault Modelling to Unsupervised Deep Learning
Y. Liao*, Z. Najafi-Haghi, H-J. Wunderlich, B.
Improve Understanding of Silicon Yang, University of Stuttgart
Failures B1.3 RCANet: Root Cause Analysis via
S. Kundu*, The University of Texas at Dallas; Latent Variable Interaction Modeling for
G. Bhargava, L. Endrinal, L. Ranganathan, Yield Improvement
Qualcomm Technologies Inc X. Zhang*, E. Young, The Chinese University
of Hong Kong; S. Hu, Z. Chen, S. Zhu, J. Hao,
Huawei Noahs Ark Lab; P. Li, C. Chen, Y.
Huang, HiSilicon

* Presenter
 TECHNICAL SESSIONS Tuesday, September 27 2:00 p.m. – 3:30 p.m.

SESSION C1 Magic Kingdom Ballroom 3 SESSION E1 Grand Ballroom South AB

Diagnosis and Debug Special Session Dedicated To The
S-Y Huang (Chair) Memory Of Tom W. Williams,
C1.1 Scaling Physically Aware Logic Diagnosis Wojciech Maly and Dhiraj Pradhan
to Complex High Volume 7nm Server Y. Zorian (Chair)
Processors E1.1 Wojciech Maly Memorial
B. Nandakumar*, S. Chillarige, M. A. Meixner, IBM; P. Nigh, Broadcom
Maheshwari, Cadence Design Systems; R. E1.2 Tom W Williams Memorial
Redburn, J. Zimmerman, N. L'Esperance, E. R. Mercer; S. Mitra, Stanford
Dziarcak, IBM E1.3 Dhiraj K Pradhan Memorial
C1.2 Diagnosing Double Faulty Chains A. Singh, Auburn U; S. Gupta, USC
through Failing Bit Separation
C-S. Kuo, J-M. Li, B-H. Hsieh*, National
Taiwan University; C. Nigh, M. Chern, G.
Bhargava, Qualcomm Technologies Inc
C1.3 Transient Fault Pruning for Effective
Candidate Reduction in Functional .
Debugging
D-A. Yang, National Tsing Hua University,
Department of Electrical Engineering; J-J.
Liou*, National Tsing Hua University,
Department of Electrical Engineering; H. .
Chen, MediaTek Inc., Computing and AI
Technology Group

SESSION D1 Magic Kingdom Ballroom 4

TTTC PhD Thesis Competition - Final

Round
M. Portolan (Chair)
D1.1 Next Generation Design For
Testability, Debug and Reliability Using
Formal Techniques
S. Huhn*, University of Bremen; R. Drechsler,
University of Bremen, Germany
D1.2 Testing of Analog Circuits using
Statistical and Machine Learning
Techniques
S. Srimani*, H. Rahaman, Indian Institute of
Engineering Science and Technology
D1.3 AI-Driven Assurance of Hardware IP
against Reverse Engineering Attacks
P. Charaborty*, S. Bhunia, University of
Florida

Table of Contents
 TECHNICAL SESSIONS Tuesday, September 27 4:00 p.m. – 5:30 p.m.

SESSION A2 Magic Kingdom Ballroom 1 C2.3 Low Capture Power At-Speed Test
Panel: Are Last Century’s Test Techniques with Local Hot Spot Analysis to
Suitable for 21st Century Silent Errors? Reduce Over-Test
S. Chakravarty, Intel; S. Mitra, Stanford A. Srivastava*, J. Abraham, Qualcomm Inc
(Organizers)
J. Rearick (Moderator) SESSION D2 Magic Kingdom Ballroom 4
Test of HW Accelerators I
Panelists: K. Chakravadhanula (Chair)
R. Govindaraju, Google D2.1 A Multi-level Approach to Evaluate
H. Dixit, Meta the Impact of GPU Permanent Faults
P. Bose, IBM on CNN's Reliability
J. Rodriguez Condia*, J. Guerrero
S. Chakravarty, Intel
Balaguera, M. Sonza Reorda, Politecnico di
S. Mitra, Stanford Torino; F. Fernandes dos Santos, Institut
National de Recherche en Sciences et
Technologies du Numérique (INRIA); P.
SESSION B2 Magic Kingdom Ballroom 2 Rech, University of Trento
Innovation with Machine Learning II D2.2 Accelerating RRAM Testing with
H.-P. Wen (Chair) Low-cost Computation-in-Memory
B2.1 Neural Fault Analysis for SAT-based based DFT
ATPG A. Singh*, M. Fieback, R. Bishnoi, F.
J. Huang, Noah's Ark Lab, Huawei; H-L. Bradaić, A. Gebregiorgis, S. Hamdioui, TU
Zhen*, Noah's Ark Lab, Huawei; N. Wang, Delft; R. Joshi, IBM
Hisilicon, Huawei; H. Mao, Noah's Ark Lab, D2.3 Compact Functional Test Generation
Huawei; M. Yuan, Noah's Ark Lab, Huawei; for Memristive Deep Learning
Y. Huang, Hisilicon, Huawei Implementations Using Approximate
B2.2 Improving Test Quality of Memory Gradient Ranking
Chips by a Decision Tree-Based S. Ahmed, Karlsruhe Institute Of Technology;
Screening Method M. Tahoori*, Karlsruhe Institute of
Y-C. Cheng*, M-D. Shieh, NCKU; P-Y. Tan, Technology (KIT), Faculty of Informatik
C-W. Wu, NTHU; C-H. Chien-Hui Chuang,
G. Liao, TSMC
B2.3 Fault Resilience Techniques for SESSION E2 Grand Ballroom South AB
Flash Memory of DNN Accelerators Special Session: Experiences in Silicon
S-K. Lu*, Y-S. Wu, National Taiwan Lifecycle Management
University of Science and Technology; J-H. Y. Zorian (Organizer)
Hong, National University of Kaohsiung; K. Swapnil Bahl (Chair)
Miyase, Kyushu Institute of Technology E2.1 In-Field System Debug and Silicon
Life Cycle Management of Compute
Systems
SESSION C2 Magic Kingdom Ballroom 2 S. Menon, R. Kuehnis, R. Kandula, Intel
New Frontiers in Test Content E2.2 Sensor Aware Production Testing
Optimization F. Massoudi, A. Patel, K. Darbinian, Y.
P. Song (Chair) Zorian, Synopsys
C2.1 Automatic Structural Test Generation E2.3 Addressing System-Level Challenges
for Analog Circuits using Neural Twins for Power-On Self-Test
J. Talukdar, A. Chaudhuri*, K. Chakrabarty, R. Kumar Tiwari, S. Tandon, M. Singla, S.
Duke University; M. Bhattacharya, Synopsys Patil, Qualcomm
C2.2 DEFCON: Defect Acceleration
through Content Optimization
S. Natarajan*, A. Sathaye, C. Oak, N.
Chaplot, S. Banerjee, Intel Corporation
ITC Welcome Reception Tuesday, September 27 6:00 p.m. – 8:00 p.m.

Adventure Lawn

Join the party on Tuesday, September 27, from 6:30-8:30 PM. Reconnect with friends and colleagues for
the first time in three years. Food and beverage for all registered attendees and exhibitors. The past two
years we had to party virtually, now we can party for real.

Tomorrow (Wednesday)
Continental breakfast: 8:00 a.m.
Keynote and Visionary Talks: 9:00 a.m.
Technical sessions: 11:00 a.m.
Exhibits open: 9:30 a.m. – 4:30 p.m.
.
Lunch, Poster Session and Corporate Forum: 12:30 a.m.
Technical sessions: 2:30 p.m.
PLENARY 2 Wednesday, September 28 9:00 P.M.– 10:30
p.m.
Keynote Address2 Disney Grand Ballroom Center

The Future of High-Performance Computing Beyond Moore’s Law

John Shalf
Lawrence Berkeley National Labs
J. Rearick (Chair)

There are a number of developments that will change how we will compute in 10 years: the
foreseeable end of Moore’s law will lead to the exploration of new architectures and the
introduction of new technologies in HPC; the rapid progress in machine learning in the last
decade has led to a refocus of HPC towards large scale data analysis and machine learning;
the feasibility of quantum computing has led to the introduction of new paradigms for
scientific computing; meanwhile 30 billion IOT devices will push advances in energy
efficient computing and bring an avalanche of data.

About the speaker: John Shalf is Department Head for Computer Science at Lawrence
Berkeley National Laboratory, and recently was deputy director of Hardware Technology for
the DOE Exascale Computing Project.

Visionary Talk
Ultra Low-Power AI Accelerators for AIoT – Compute-in-memory, Co-Design, and
Heterogeneous Integration
Tim Cheng
The Hong Kong University of Science and Technology
K-J Lee, (Chair)

We will give an overview of the objectives and some recent progress in designing ultra-low-
power AI accelerators for supporting a wide range of AIoT devices with powerful embedded
intelligence and test.

About the speaker: Tim Cheng is currently Vice-President for Research and Development
at Hong Kong University of Science and Technology (HKUST) and Chair Professor jointly
in the Departments of ECE and CSE., music analysis/retrieval, image classification,
medical/healthcare data analytics, and FinTech.
TECHNICAL SESSIONS Wednesday, September 28 11:00 a.m. – 12:30 p.m.

SESSION A3 Magic Kingdom Ballroom 1 SESSION C3 Magic Kingdom Ballroom 3

Hardware Security I Memory Test/Diagnosis
J. Dworak (Chair) S-K Lu (Chair)
A3.1 RTL-FSMx: Fast and Accurate Finite C3.1 Fault Diagnosis for Resistive
State Machine Extraction at the RTL for Random- Access Memory and
Security Applications Monolithic Inter-tier Vias in Monolithic
R. Kibria*, M. Rahman, F. Farahmandi, M. 3D Integration
Tehranipoor, University of Florida S-C. Hung*, A. Chaudhuri, K. Chakrabarty,
A3.2 TAMED: Transitional Approaches for Duke University; S. Banerjee, Intel
LFI Resilient State Machine Encoding Corporation
M. Choudhury*, M. Gao, S. Tajik, D. Forte, C3.2 Fault Modeling and Testing of
University of Florida Memristor-Based Spiking Neural
A3.3 Reliability Study of 14 nm Scan Networks
Chains and Its Application to Hardware K-W. Hou*, H-H. Cheng, C. Tung, National
Security Tsing Hua University; C-W. Wu, NTHU; J-M.
F. Stellari, P. Song*, IBM Lu, Industrial Technology Research
Institute
C3.3 Fault-coverage Maximizing March
SESSION B3 Magic Kingdom Ballroom 2 Tests for Memory Testing
R. Feng, Y. Lin, Y. Lou, L. Gao, V. Gera,
Latest on Wafer Map Analytics B. Li, V. Chowdary Nekkanti, A. Rajendra
J. Li (Chair) Pharande, K. Sheth, M. Thommondru, G.
B3.1 Language Driven Analytics for Ye, University of Southern California; S.
Failure Pattern Feedforward and Gupta*, Purdue University
Feedback C3.4 Enhanced Data Pattern to Detect
M. Yang, Y. Zeng*, L-C. Wang, University of Defects in Flash Memory Address
California Santa Barbara Decoder
B3.2 Wafer Map Defect Classification J. Soh*, C. He, NXP Semiconductors
Based on the Fusion of Pattern and
Pixel Information SESSION D3 Magic Kingdom Ballroom 4
Y. Liao*, P. Genssler, H. Amrouch, B. Yang, Special Session on In-Memory Computing
University of Stuttgart; R. Latty, Advantest Design and Test Challenges
Europe GmbH S. Adham, TSMC; S. Hamdioui, Delft,
B3.3 WXAI: Wafer Defect Pattern University (Organizers)
Classification with Explainable Rule A. Adham (Chair)
Based Decision Tree Methodology D3.1 In-Memory Computing: History,
K-C. Cheng*, A-A. Huang, C-S. Lee, L-Y. Overview, Current and Future
Chen, P-Y. Liao, N-Y. Tsai, NXP Directions
Semiconductors Taiwan Ltd.; K-M. Li, N. Shanhbag*, Univ. of Illinois
National Sun Yat-Sen University; S-J. Wang, D3.2 Testing Computation-in-Memory
National Chung Hsing University Architectures Based on Memristive
B3.4 Yield-Enhanced Probing Cleaning Devices
with AI-Driven Image and Signal S. Hamdioui*, Delft, University
Integrity Pattern Recognition for Wafer D3.3 Fully Digital Compute In Memory
Test Design and Test challenges
N. Sinhabahu*, S, J. Wang, NXP S. Adham*, TSMC
Semiconductors Taiwan Ltd.; K-M. Li,
National Sun Yat-Sen University; J-D. Li, S-J.
Wang, National Chung Hsing University

* Presenter
 TECHNICAL SESSIONS Wednesday, September 28 11:00 a.m. – 12:30 p.m.

SESSION E3 Grand Ballroom South AB Disaggregated Microprocessor

Industrial Practices I Products
P. Nigh (Chair) E. Garita-Rodriguez*, R. Rimolo-Donadio, R.
Zamora-Salazar, Intel
E3.1 Application of Sampling in Industrial E3.3 New R&R Methodology in
Analog Defect Simulation Semiconductor Manufacturing
M. Bhattacharya, B. Solignac, M. Durr*, Electrical Testing
Synopsys A. Pagani, F. Brembilla*,
E3.2 Challenges for High Volume Testing STMicroelectronics
of Embedded IO Interfaces in

Posters Wednesday, September 28 12:30 p.m. – 2:30 p.m.

Exhibit Hall
PO.1 Neural Machine Translation for PO.9 Chiplet Level Test Parallelization
Test Language for 3D Stacking Products
S Go, SungKyunKwan University, A. Margulis, T. Payakapan, J. Yuan, N.l
Samsung Electronics Patel, A. Loh, AMD
PO.2 Compositive Framework for Wafer PO.10 Pre-Analysis for ATPG Pattern
Pattern Recognition with Failures
Confidence Relabeling Technique D. Appello, D. Petrali, V. Tancorre,
L-Y Chen, Y-A Huang, C-S Lee, C-C STMicroelectronics; G. Chan, R.
Cheng, Y-Y Liao, L Chou J. Elwell, Dokken, Roguevation
PNXP Semiconductors; S-M Li, PO.11 Accelerating Design Cycle with
National Sun Yat-Sen University; S-J DFT and Test Coverage Analysis
Wang, National Chung Hsing at RTL
University M. Arneson, Micron Technology; R.
PO.4 Teradyne’s PortBridge Software Singhal, S. Nanduru, Synopsys
Expedites Silicon Bring-Up, PO.12 Prediction of Total Jitter using
Debug, Production Readiness and Machine Learning for LVDS Output
Foundry Feedback Characterization
R. Fanning,Teradyne; S. Molavi, P. L. Lee, Intel
Broadcom
PO.13 Ehanced Jitter Reduction for
PO.5 Bridging Repairability Gaps in Multi-GHz ATE
Shared Bus Architecture with D. Keezer, Eastern Institute for
Shared Physical Memory Advanced Study; D. Minier, Boreas
Implementation Technologies
W. Pradeep, N. Karkare; Google
PO.14 Deploying Real-Time Machine
PO.6 Design-for-Diagnosis for Multiple Learning Applications with Deep
Defects per Chain Data at Test
E. Gizdarski, Y. Kanzawa, Synopsys M. Hutner, A. Burlak, A. Mittall,
proteanTecs
PO.7 Roadblocks and Strategy to the PO.15 HBM3 Test/Debug Solution
Reuse of Test Solutions for Supporting PHY-Mastered Interface
Analog and Mixed-Signal Blocks of HBMPHY
H. Son, Y. Lim, D. Han, Samsung
P. Bauwens, R. Vanhooren, A. Coyette, Foundry
W. Dobbelaere, onsemi; G. Gielen, N.
Xama, J. Gomez, KU Leuve PO.16 Enabling a Low Cost and High
Quality Scan Test Methodology in
PO.8 Leveraging Existing High Speed 16nm FinFet Automotive Products
Functional Serial Interfaces for S. Traynor, J. T. Ng, R. Chen., NXP
Testing & Monitoring Silicon Semiconductor
Throughout the Entire Lifecycle
R. Allen, A. Patel, Synopsys; K. Hilliges,
Advantest; B. Tully, A. Pandey, Amazon
 Posters (Continued) Wednesday, September 28 12:30 p.m. – 2:30 p.m.
PO.28 ATE Integration of High
PO.17 Ultra-Fast and Secure 5G Digital
Pre-Distortion with ACS Edge Performance, High Data Rate 3rd
D. Belkin, O. Olansky, Intel; Y. Chen, K. Party Instruments
T. Lyons, Teradyne
Butler, K. Schaub, Advantest
PO.18 IR-Drop Improvement with Packet- PO.29 A Novel DFT [Design for Test]
Based Scan Clock Gating Technique to Reduce
J. Reynick, Siemens EDA; S. Alampally., Power Consumption
Broadcom A. Gangwar, F. Shukla, Synopsys; S.
PO.19 Investigation of Jitter Spur Impact Murthy, P. Policke, Qualcomm
on Eye Width Margin
O. Choong, W. C. Liew, Intel PO.31 Test Manufacturing Breakthroughs
To Maximize Total Sellable Yield in
PO.20 Improving Engineering Efficiency 5G Network ASIC.
& Time to Market Through Multi- S. E. Wong, Intel
Variable Characterization
D. King, Galaxy Semiconductor PO.32 A Breakthrough Manufacturing
PO.21 Re-targeting Block-Level Patterns Solution - Array Erratic Fluctuation
Using Top-Level On-Chip Clock Predictive through Machine
Controller (OCC) --- An Industrial Learning Methods
Case Study N. H. Chun, T. Aik, Intel
Z. Zhong, S. Biswas, A. Wangoo, M.
Bhattarai; Marvell Semiconductor Inc; PO.33 Advanced Core Wrapping for
A. Gangwar, Synopsys Power, Early Test Coverage and
Automation
PO.22 Identical HW and SW for A. Gangwar, F. Shukla, K. Bachu,
producton test and lab validation Synopsys
of modules PO.34 Speedup Logic Diagnosis with
F. Haas, A. Matiz, ams-OSRAM Static Layout Data
PO.23 Cell-Aware Test integration R. Guo, Synopsys
towards achieving 0 DPPB on
automotive designs PO.35 Design for test (DFT)
N. K, S. Ramesh, R. Kaistha, J. K. Loh, Considerations when Designing
G. S Clark, C. Ling, NXP Tile-based/abutted Physical Blocks
Semiconductors V. Neerkundar, Siemens
PO.24 A Novel Shift-left Method in
PO.36 Improving System Level Screening
Reducing Networking ASIC
Efficiency Through Negative Voltage
Customer Field DPM
Margining
K. A. Chuah, T. H. H. Tan, C. C. Tan,
L.D. Rojas, J. Rodriguez, D. Wilhelmi, D.
Intel
Lerner, Intel
PO.25 Lcpll DTR: Recovering Yield Loss
with Fusing and Graphics Driver PO.37 Built-In Self-Test architecture
N. Wang-Lee, J. Abbas, K. L. Ng, H. enabling diagnosis for massive
Zhao, Y. Park, Intel Embedded Memory banks in large
SoCs
PO.26 An Application of Spatially G. Insinga, P. Bernardi, G. Paganini,
Resolved Netlists to Graphical A. Guerriero, Politecnico di Torino; W.
Error Detection Mischo, R. Ullmann, M. Coppetta, G.
N. Taylor, J. Delozier, T. McDonley, K. Carnevale, Infineon Technologies
Liszewski, B. Hayden, A. Kimura, Battelle
Memorial Institute

PO.27 Low Cost, At-Speed Validation of

I3C Target Design
P. Bansal, P. Bal, A. Kumari,
STMicroelectronics
 CORPORATE FORUM Wednesday, September 28 10:30 a.m. – 2:30
p.m.

10:30 a.m.–11:00 a.m. 1:30 p.m.–3:00 p.m.

Exhibit Hall Exhibit Hall

10:30 a.m. UNITES Systems 1:30 p.m. Chroma

Testing SiC and GaN discrete High Multisite Testing for Hi Fidelity True
semiconductors, Wireless Stereo (TWS) Devices,
O. Betak, UNITES Systems E. Lin, Chroma

1:45 p.m. DR Yield

10:40 a.m. Xallent, Inc YieldWatchDog Solution for AI Test Data

Analytics,
Thin Films Testing Up to 300X Faster, K. Tropper, DR Yield
Kwame Amponsah, Xallent

2:00 p.m. Caliber Interconnect

10:50 a.m. yieldHUB Solutions

Revolutionize your yield management, C. S. Value Proposition - Caliber Interconnect

Moore, yieldHub Solutions,
M. Berry, Caliber

2:15 p.m. Roos Instruments, Inc.

Roos Cassini: Continuous Coverage to

110GHz,
M. Roos, Roos
TECHNICAL SESSIONS Wednesday, September 28 2:30 p.m. – 4:00 p.m.

.
SESSION A4 Magic Kingdom Ballroom 1 B4.3 The Impact of On-chip Training to
Hardware Security II Adversarial Attacks in Memristive
P. Song (Chair) Crossbar Arrays
A4.1 Modeling Challenge Covariances B. Paudel*, S. Tragoudas, Southern Illinois
and Design Dependency for Efficient University, Carbondale
Attacks on Strong PUFs B4.4 RIBoNN: Designing Robust In-
H. Wang*, W. Liu, H. Jin, Y. Chen, W. Cai, Memory Binary Neural Network
Huazhong University of Science and Accelerators
Technology S. Kundu*, K. Basu, The University of Texas
A4.2 ADWIL: A Zero-Overhead Analog at Dallas; A. Malhotra, S. Gupta, Purdue
Device Watermarking Using Inherent University; A. Raha, Intel Corporation
IP Features
U. Das*, M. Muttaki, M. Tehranipoor, F.
Farahmandi, University of Florida SESSION C4 Magic Kingdom Ballroom 3
A4.3 Circuit-to-Circuit Attacks in SoCs Memory Test/Repair
via Trojan-Infected IEEE 1687 Test J. Yun (Chair)
Infrastructure C4.1 Configurable BISR Chain For Fast
M. Portolan*, Univ Grenoble Alpes, CNRS; Repair Data Loading
A. Pavlidis, H. Stratigopoulos, Sorbonne W. Zou*, B. Nadeau-Dostie, Siemens EDA
Université LIP6; G. Di Natale, CNRS; E. C4.2 Efficient Built-In Self-Repair
Faehn, ST Microelectronics Techniques with Fine-Grained
A4.4 Hardware Root of Trust for SSN- Redundancy Mechanisms for NAND
based DFT Ecosystems Flash Memories
J. Tyszer, B. Wlodarczak, Poznan University S-K. Lu*, S-C. Tseng, National Taiwan
of Technology; J. Rajski*, M. Trawka, University of Science and Technology; K.
Siemens Digital Industries Software Miyase, Kyushu Institute of Technology
C4.3 Analyzing the Electromigration
Challenges of Computation in
Resistive Memories
SESSION B4 Magic Kingdom Ballroom 2
M. Mayahinia, Karlsruhe Institute of
Test of HW Accelerators II
Technology (KIT); M. Tahoori*, Karlsruhe
S. Gupta (Chair)
Institute of Technology (KIT), Faculty of
B4.1 Functional In-Field Self-Test for Deep
Informatik; M. Perumkunnil, K. Croes, F.
Learning Accelerators in Automotive
Catthoor, IMEC
Applications
C4.4 DFT-Enhanced Test Scheme for
T. Uezono, Hitachi; Y. He*, Y. Li, University
Spin-Transfer-Torque (STT) MRAMs
of Chicago
Z-W. Pan*, J-F. Li, National Central
B4.2 Defect-Directed Stress Testing Based
University
on Inline Inspection Results
C. He*, P. Grosch, O. Anilturk, J. Witowski,
C. Ford, R. Kalyan, NXP Semiconductors; J.
Robinson, D. Price, J. Rathert, B. Saville,
KLA Corporation
 TECHNICAL SESSIONS Wednesday, September 28 2:30 p.m. – 4:00 p.m.

SESSION D4 Magic Kingdom Ballroom 4 E4.2 4.5Gsps MIPI D-PHY Receiver

Automotive I Circuit for Automatic Test Equipment
P. Wohl (Chair) S. Lee*, C. Park, M. Kang, J. Won, H. Ryu,
D4.1 An innovative Strategy to Quickly J. Choi, B. Yim, Samsung Electronics
Grade Functional Test Programs E4.3 Optimization of Tests for Managing
P. Bernardi*, A. Francesco, S. Quer, L. Silicon Defects in Data Centers
Cardone, A. Calabrese, D. Piumatti, A. D. Lerner*, B. Inkley, S. Sahasrabudhe, E.
Niccoletti, Politecnico di Torino; D. Hansen, A. Van De Ven, Intel Corporation
Appello, V. Tancorre, R. Ugioli, E4.4 Improving Structural Coverage of
STMicroelectronics Functional Tests with Checkpoint
D4.2 A Practical Online Error Detection Signature Computation
Method for Functional Safety Using B. Niewenhuis*, D. Varadarajan, Texas
Three-Site Implications Instruments
K. Ioki*, ROHM Co., Ltd.; Y. Kai, K. E4.5 Zero Trust Approach to IC
Miyase, S. Kajihara, Kyushu Institute of Manufacturing and Testing
Technology B. Buras*, Advantest; C. Xanthopoulos, J.
D4.3 PPA Optimization of Testpoints in Kim, K. Butler, Advantest America Inc
Automotive Designs E4.6 Virtual Prototyping: Closing the
B. Foutz*, S. Singhal, P. Rai, K. Digital Gap between Product
Chakravadhanula, V. Chickermane, B. Requirements and Post-Si
Nandakumar, S. Chillarige, C. Papameletis, Verification & Validation
S. Ravichandran, Cadence Design Systems T. Nirmaier*, M. Harrant, M. Huppmann,
G. Pelz, Infineon Technologies
SESSION E4 Grand Ballroom South AB
Industrial Practices II
C-W Wu (Chair)
E4.1 Accurate Failure Rate Prediction
Based on Gaussian Process Using
WAT Data
M. Eiki*, M. Kajiyama, T. Nakamura, Sony
Semiconductor Manufacturing; M. Shintani,
Kyoto Institute of Technology; M. Inoue,
Nara Institute of Science and Technology * Presenter

Table of Contents
 TECHNICAL SESSIONS Wednesday, September 28 4:30 p.m. – 6:0 p.m.

SESSION A5 Magic Kingdom Ballroom 1 D. Gizopoulos, Univ of Athens

Special Session on HW Security C. Liu, Alibaba
Certification
T-Y Chan (Chair)
A5.1 Latest Cybersecurity Regulations,
Certifications and Labeling Trends SESSION D5 Magic Kingdom Ballroom 4
R. Menda-Shabat*, Winbond Automotive: Special Session on High-
A5.2 GlobalPlatform: 20 years of Power Electronics
Security Evaluation on Secure S.-Y. Huang, National Tsing Hua
Components, University (Organizer, Chair)
G. Bernabeu*, GlobalPlatform D5.1 The Importance and Demand
A5.3 Hardware Security in IoT Platforms Market of SiC Substrate Defect
and Certification Testing,
T.-Y. Chan*, Winbond W-C Chang*, Industrial Technology
Research Institute
SESSION B5 Magic Kingdom Ballroom 2 D5.2 Validation of SPICE Models for
Analog Testing Commercial SiC MOSFETs
H. M. von Staudt (Chair) H-Y Teng*, Industrial Technology
B5.1 ML-Assisted Bug Emulation Research Institute
Experiments for Post-Silicon Multi- D5.3 Practice Design Experiences on a
Debug of AMS Circuits Multi-Voltage-Level Motor Driver
J-Y. Lei*, A. Chatterjee, Georgia System using a Power Inverter
Institute of Technology C-C Chiu*, Industrial Technology
B5.2 A Path Selection Flow for Research Institute
Functional Path Ring Oscillators
using Physical Design Data
T. Kilian*, Infineon Technologies AG /
Technical University of Munich; M. SESSION E5 Grand Ballroom South AB
Hanel, U. Schlichtmann, Technical Analog Test, Diagnosis, Test Cost, All-
University of Munich; D. Tille, Infineon In-One
Technologies AG; M. Huch, Infineon A. Singh (Chair)
Technology AG E5.1 Efficient Low Cost Alternative
B5.3 IEEE P1687.1: Extending the Testing of Analog Crossbar Arrays
Network Boundaries for Test for Deep Neural Networks
M. Laisne, H. von Staudt, Dialog K. Ma*, A. Saha, C. Amarnath,A.
Semiconductor - a Renesas Company; Chatterjee, Georgia Institute of
A. Crouch, Amida Technology Technology
Solutions, Inc.; M. Portolan, Univ E5.2 Low-Cost High Accuracy Stimulus
Grenoble Alpes, CNRS; M. Keim*, Generator for On-chip Spectral
Siemens Digital Industries Software; B. Testing
Van Treuren, VT Enterprises K. Bhatheja*, S. Chaganti, D. Chen,
Consulting Services; J. Rearick, Iowa State University; X. Jin, C. Dao, J.
Advanced Micro Devices; S. Zuo, Ren, A. Kumar, D. Correa, M.
Tailored Management Lehrmann, T. Rodriguez, E. Kingham,
J. Knight. A. Dobbin, S. Herrin, D.
Garrity, NXP Semiconductors
E5.3 Optimal Order Polynomial
SESSION C5 Magic Kingdom Ballroom 3 Transformation for Calibrating
PANEL 3 Systematic Errors in Multisite
Performing RAS in Today’s Mission Testing
Critical Systems P. Farayola, I. Bruce, D. Chen, Iowa
Y. Zorian (Organizer) State University; S. Chaganti*, A.
P. Benardi (Moderator) Sheikh, S. Ravi, Texas Instruments
Panelists: E5.4 Transforming an n-Detection Test Set
R. Kinger, Google into a Test Set for a Variety of Fault
N. Saxena, Nvidia Models
H. Dixit, Meta I. Pomeranz*, Purdue University
Y. Zorian, Synopsys
E5.5 Improvements in the Automated IC E5.6 GreyConE: Greybox Fuzzing +
Socket Pin Defect Detection Concolic Execution Guided Test
V. Thangamariappan*, N. Agrawal, C. Generation for High Level Designs
C Xanthopoulos, J. Kim, I. Leventhal, M. Debnath, S. Sur-Kolay*, Indian
K. Butler, Advantest America; J. Xiao, Statistical Institute; A Chowdhury, New
Essai York University; D. Saha, University of
Calcutta

Tomorrow (Thursday)
Continental breakfast: 8:00 a.m.
Keynote Talk: 9:00 a.m.
Technical sessions: 10:30 a.m.
Exhibits open: 10:00 a.m. – 1:00 p.m.
Lunch: 12:00 p.m.
Technical sessions: 1:30 p.m.
Workshops: 3:30 p.m.

Fill in your Exhibit Hall Passport for Prizes

PLENARY 3 Thursday, September 29 9:00 a.m.– 10:00
a.m.

Keynote Address 3 Disney Grand Ballroom Center

What Did We Learn in 120 years of DFT and Test?

Grady Giles, Mike Bienek, & Tim Wood

AMD
Y. Zorian (Chair)
This interview-style discussion will feature three industry veterans whose careers have
followed (and propelled) the growth in our field. We plan to reflect on how our industry has
evolved, how this conference has reflected and driven that evolution, what lessons were
learned, and what we can expect (and make happen) next. Along the way, we’ll share some
anecdotes, tell some stories, brag about some accomplishments, and humbly give some advice
on things we found out the hard way (so that you don’t have to).
.

About the speakers: Grady Giles, Mike Bienek, and Tim Wood are all members of the DFX team at
AMD, with a combined 120+ years of experience in the industry.

Also in this session – announcement of the winner of the TTTC PhD Thesis Competition

TECHNICAL SESSIONS Thursday, September 29 10:30 a.m. – 12:00 p.m.

SESSION A6 Magic Kingdom Ballroom 1

Special Session on Test of Quantum B6.3 A Comprehensive Learning-Based
Circuits Flow for Cell-Aware Model Generation
J. Li, (Chair) P. d'Hondt*, LIRMM / STMicroelectronics;
A6.1 Qubit fluctuations in quantum A. Ladhar, STMicroelectronics; P. Girard,
systems A. Virazel, LIRMM
M. Carroll*, IBM B6.4 Runtime Fault Diagnostics for GPU
A6.2 Introduction to Quantum Circuit Tensor Cores
Testing (from Test Engineer’s S. Hukerikar*, N. Saxena, NVIDIA
Perspective)
J. Li*, National Taiwan University SESSION C6 Magic Kingdom Ballroom 3
Special Session: Road to Chiplets: UCIe
Y. Zorian (Chair)
SESSION B6 Magic Kingdom Ballroom 2 Presenters: D. D. Sharma, Intel, Y. Zorian,
Scan-Based Learning and Diagnosis Synopsys. K-D Hillinges, M. Braun,
W-T Cheng (Chair) Advantest
B6.1 Scan-Based Test Chip Design with
XOR-based C-testable Functional
Blocks * Presenter
Y-F. Chen, Dept. EE, National Cheng
Kung University; D-Y. Kang*, Dept. EE,
National Cheng Kung University; K-J. Lee,
Dept. EE, National Cheng Kung University
B6.2 Industry Evaluation of Reversible
Scan Chain Diagnosis
S. Urban, J. Janicki, M. Sharma, W-T.
Cheng, Siemens EDA; M. Parley, K.
Chung, S. Nicholson, S. Mittal*, Qualcomm
SESSION D6 Magic Kingdom Ballroom 4 SESSION E6 Grand Ballroom South AB
Automotive II Industrial Practices III
C. He (Chair) K. Peng (Chair)
D6.1 Unsupervised Learning-based Early E6.1 Probeless DfT Concept for Testing
Anomaly Detection in AMS 20k I/Os of an Automotive Micro-LED
Circuits of Automotive SoCs Headlamp Driver IC
A. Arunachalam*, A. Kizhakkayil, H. von Staudt*, Dialog Semiconductor - a
University of Texas at Dallas; S. Renesas Company; L. Elnawawy, Dialog
Kundu, K. Basu, The University of Semiconductor, A Renesas Company; S.
Texas at Dallas; A. Raha, S. Wang, Dialog Semiconductor, A Renesas
Banerjee, F. Su, Intel Corporation; X. Company; L. Ping, Dialog Semiconductor,
Jin, NXP Semiconductors A Renesas Company; J. Choi, Samsung
Electronics
D6.2 Just-Enough Stress Test for Infant- E6.2 Reusing IEEE 1687-Compatible
Mortality Screening Using Speed Instruments and Sub-Networks over a
Binning System Bus
C-L. Tsai, S-Y. Huang*, National Tsing F. Ghani Zadegan, Z. Zhang, K.
Hua University Petersén, Ericsson; E. Larsson*, Lund
D6.3 Existence of Single-Event Double- University
Node Upsets (SEDU) in Radiation- E6.3 Multi-die Parallel Test Fabric for
Hardened Latches for Sub-65 nm Scalability and Pattern Reusability
CMOS Technologies A. Sinha*, Y. Cho, J. Easter, M. V. Leiva
M-H. Hsiao, P-T. Wang*, C-W. Liang, Rojas, Intel
H-P. Wen, National Yang Ming Chiao
Tung University

TECHNICAL SESSIONS Thursday, September 29 1:30 p.m. – 3:00 p.m.

SESSION A7 Magic Kingdom Ballroom 1
Test Generation
S-K Lu (Chair)
A7.1 Compression-Aware ATPG B7.2 Multiple Guard Bands for Low Power
X. Wang*, University of Chinese Consumption
Academy of Sciences, Academy of W-C. Lin*, C-H. Hsieh, J-M. Li, C. Chen,
mathematics and Systems Science; Z. National Taiwan University; E-W. Fang,
Wang, HiSilicon Technologies Co., Ltd.; MediaTek Inc.; S-Y. Hsueh, MediaTek inc.
N. Wang, Hisilicon, Huawei; W. Zhang, B7.3 Comprehensive Power-Aware ATPG
HiSilicon Technologies Co., Ltd.; Y. Methodology for Complex Low-power
Huang, Hisilicon, Huawei Designs
A7.2 DIST: Deterministic In-System Test L. Manchukonda*, E. Tsai, K. Abdel-
with X-masking Hafez,M. Dsouza, K. Natarajan, Synopsys;
J. Tyszer, B. Wlodarczak, Poznan S. Lai, W. Hsueh, MediaTek
University of Technology; G. Mrugalski, J.
Rajski*, Siemens Digital Industries
Software
A7.3 Test Generation for an Iterative .
Design Flow with RTL Changes
J. Joe*, I. Pomeranz, Purdue University;
N. Mukherjee, J. Rajski, Siemens Digital
Industries Software
Session Break
SESSION B7 Magic Kingdom Ballroom 2
Low-Power and Test Thursday session refreshment break in the
H.-P. Wen (Chair) exhibit hall.
10:00 a.m.– 10:30 a.m.
B7.1 Understand VDDmin Failures for
Improved Testing of Timing
Marginalities
A. Singh*, TU Delft
SESSION C7 Magic Kingdom Ballroom 3
Special Session: Design-for-Verification
(DfV): A New Direction in Design
Qualification
Y. Zorian (Organizer)
A. Majumdar (Moderator)
Presenter: D. Akselrod, AMD
Panelists:
S. Millican, Auburn University
S. Sunter, Siemens
A. Sharma, Synopsys
S. Huhn, University of Bremen

SESSION D7 Magic Kingdom Ballroom 4

Panel 4: Automotive Safety & Security
Interoperability
Organizer: Nir Maor, QualComm
Moderator: Yervant Zorian, Synopsys
Panelists:
• Sohrab Aftabjahani, Intel
• Luca Di Mauro, Arm
• Joytika Athavale, Nvidia
• Nir Maor, Qualcomm
• Jason M Fung, Intel
• P. V. Pillai, Texas Instruments
• Thiyagu Loganathan, Infineon

SESSION E7 Grand Ballroom South AB

Industrial Practices from ITC India
P. Wohl (Chair)
E7.1 TSV BIST Repair: Design-For-Test
Challenges and Emerging Solution
for 3D Stacked IC’s
S. Akkapolu, Vaishnavi G, S. R.
Malige, AMD

E7.2 Selective Multiple Capture Test

(SMART) XLBIST
P. Wohl*, J. Waicukauski, V. Kumar K S,
A. Bhat, R. Karmakar, Synopsys

E7.3 Transfer-Matrix Abstractions to

Analyze the Effect of Manufacturing
Variations in Silicon Photonic
Circuits
P. Agnihotri*, P. Kalla, S. Blair, The
University of Utah
 WORKSHOPS Thursday, September 29 4:00 p.m. – 6:30 p.m.
Friday, September 30 8:30 a.m. – 4:00 p.m.

ART2022: IEEE Automotive Reliability, Test & Safety Workshop 2022

Magic Kingdom Ballroom 1

The ARTS workshop focuses exclusively on test, reliability and Safety of automotive and mission-critical
electronics, including design, manufacturing, burn-in, system-level integration and in-field test, diagnosis
and repair solutions, as well as architectures and methods for reliable and safe operations under different
environmental conditions. With increasing system complexity, security, stringent runtime requirements for
functional safety, and cost constraints of a mass market, the reliable operation of electronics in safety-
critical domains is still a major challenge. This edition of the ARTS Workshop offers a forum to present
and discuss these challenges and emerging solutions among researchers and practitioners alike.

Program Highlights:

• After the opening session of Thursday, Sundarrajan Subramanian , Qualcomm Vice President, will give
the first Keynote speech on "Journey from Mobile to Automobile: Leverage Learn Lead” .
• Friday will start start with Vasanth Waran , Synopsys Senior Director, who will give the second Keynote
speech on "Evolution and Trends driving the Automotive Architecture and Ecosystems of the future” .
• Four technical sessions will focus on:

o Advanced BIST design

o NVM oriented reliability
o In-field testing
o Simulation and fault simulation techniques.
• Technical sessions will be interleaved with a special session with a speech on "The Accellera Functional
Safety Standard: enabling automation, interoperability and traceability” given by Alessandra Nardi ,
Accellera FS WG Chair.

.
General Chair: Yervant Zorian,
Program Chair: Paolo Bernardi
ART Web Page: http://art.tttc-events.org/
Second IEEE International Workshop on Silicon Lifecycle Management (SLM)
Magic Kingdom Ballroom 4
With increasing system complexity, security, stringent runtime requirements for functional safety, and
cost constraints of a mass market, the reliable and secure operation of electronics in safety- critical,
enterprise servers and cloud computing domains is still a major challenge. While traditionally design
time and test time solutions were supposed to guarantee the in-field dependability and security of
electronic systems, due to complex interaction of runtime effects from running workload and
environment, there is a great need for a holistic approach for silicon lifecycle management, spanning
from design time to in-field monitoring and adaptation. Therefore, the solutions for lifecycle
management should include various sensors and monitors embedded in different levels of the design
stack, access mechanisms and standards for such on-chip and in- system sensor network, as well as data
analytics on the edge and in the cloud. The SLM Workshop offers a forum to present and discuss these
challenges and emerging solutions among researchers and practitioners alike.

SLM include three keynote addresses and five technical sessions.

See the SLM Web Page for the complete SLM Program.

General Chair: Yervant Zorian, [email protected]

Program Chair: Mehdi Tahoori
SLM Web Page: https://people.rennes.inria.fr/Marcello.Traiola/SLM22/index.html

Workshop Registration for Both Workshops

All workshop participation requires registration. Workshop registration includes the opening address,
technical sessions, digest of papers, workshop reception, break refreshments, continental breakfast and
lunch.
You may register onsite at regular rates at the ITC registration counter Admission for onsite registrants is
subject to availability.

Workshop Reception
All registered workshop participants are invited to a reception to be held 7:00 p.m. – 9:00 p.m. on Thursday,
September 29 at the Adventure Lawn.

Workshop Schedule
The workshops will all adhere to the same schedule:

Thursday, September 29
Registration 7:30 a.m. – 5:00 p.m.
Opening Address 4:00 p.m. – 5:00 p.m.
Technical Sessions 5:00 p.m. – 6:30 p.m.
Reception 7:00 p.m. – 9:00 p.m.

Friday, September 30
Technical Sessions 8:00 a.m. – 4:00 p.m.
Note: Workshop schedule is subject to change
 FRINGE TECHNICAL MEETINGS See registration desk for schedule.

Castle C
ITC STEERING COMMITTEE

Teresa. McLaurin, ARM, General Chair

Jennifer Dworak, Southern Methodist University, Past General Chair

ARRANGEMENTS
Jill Sibert, Raspberry Communications, Chair

EXHIBITS
Chen-huan Chiang, Intel, Chair
FINANCE
Kenneth Mandl, Chair

MARKETING
Ron Press, Siemens, Chair
Scott Davidson, Vice Chair

PLANNING
Gordon Roberts, McGill University, Chair
William Lowd, BZ International, Vice Chair

PROGRAM
Kuen-Jong Lee, National Cheng Kung University, Chair
Jeff Rearick, AMD, Vice Chair

TTTC WORKSHOPS AND TUTORIALS LIAISON

Yervant Zorian, Synopsys

MEMBERS
Shawn Blanton, Carnegie Mellon University
Anne Gattiker, IBM
Marc Hutner
Peter Maxwell
Li-C Wang, University of California, Santa Barbara

IEEE PHILADELPHIA SECTION REPRESENTATIVE

Peter Silverberg

TTTC REPRESENTATIVE
Peilin Song, IBM

Table of Contents
 ITC PROGRAM COMMITTEE

J-F Li, National Central University

S, Adham, TSMC X. Li, Chinese Academy of Science
S. A. Aftabjahani, Intel Y. Li, University of Chicago
E. Amyeen, Intel J-J. Liou, National Tsing Hua University
L. Anghel, INP-TIMA Laboratory S.-K. Lu, National Taiwan University
D. Armstrong, Advantest Y. Makris, University of Texas at Dallas
R. Arnold, Infineon Technologies EJ. Marinissen, IMEC
B. Becker, University of Freiburg P. Maxwell
G. Bhargava, Qualcomm T. McLaurin, ARM
S. Blanton, CMU S. Natarajan, Intel
K. Butler, Advantest P. Nigh, Broadcom
J. Carulli, GLOBALFOUNDRIES P. Pant, Inteal
K. Chakrabarty, Duke University R. Parekhji, Texas Instruments India
K. Chakravadhanula, Cadence Design Systems K. Peng, ARM
A. Chatterjee, Georgia Institute of Technology M. Portolan, TIMA
H. Chen, MidiaTek J. Rajski, Siemens
V. Chickermane, Cadence Design Systems S. Ravi, Texas Instruments
G. Colon-Bonet, Intel G. Roberts, McGill University
W. Dobbelaere, ON Semiconductor O. Sinanoglu, New York University Abu Dhabi
J. Dworak, Southern Methodist University P. Song, IBM
F. Farahmandi, University of Florida F. Su, Intel
F. Frederixk, ARM M. Tahoori, Karlsruhe Institute of Technology
M. Fujita, University of Tokyo S. Teehan, IBM
A. Gattiker, IBM M. Tehranipoor, University of Florida
P. Girard, LIRMM J. Tyszer, Poznan University of Technology
S. Goel, TSMC H. von Staudt, Dialog Semiconductor
S. Goh, Qualcomm H. Walker, Texas A&M University
U. Guin, Auburn University Li-C. Wang, U. of California, Santa Barbara
S. Gupta, University of Southern California S.-J. Wang, National Chung Hsing University
S. Gupta, NVIDIA H.-P. Wen, National Chiao Tung University
M. Hashimoto, Kyoto University X. Wen, Kyushu Institute of Thechnology
C. He, NXP L. Winemberg, Intel
T.-Y. Hsieh, National Sun Yat-sen University P. Wohl, Synopsys
J-L. Huang, National Taiwan University C-W. Wu, National Tsing-Hua University
S-Y. Huang, National Tsing-Hua University H-J. Wunderlich, University of Stuttgart
T-C. Huang, National Changhua University F. Zhang, Southern Methodist University
M. Inoue, Nara Inst. of Science and Tech. Y. Zorian, Synopsys
M. Ishida, Advantest
Y. Iskander, Microsoft
H. Jiao, Peking University
Y. Jin, The University of Florida
R. Kapur, Synopsys
N. Karimi, University of Maryland
R. Karri, Polytechnic Institute of NYU
H. Kobayashi, Gunma University
J. Lee, National Taiwan University
ITC AWARDS

Program Committee Awards

Steering Committee Awards
Outstanding Contribution Awards in
Meritorious Service Award
recognition of service to the IEEE
For major contributions and leadership of IEEE
International Test Conference Program
International Test Conference while serving as
Committee
General Chair for 2021
Jennifer Dworak

25 Years of Service Outstanding Contribution Award

For major contributions and leadership to IEEE
Shawn Blanton International Test Conference while serving as
Program Chair for 2021
15 Years of Service Teresa McLaurin

Jeff Rearick Outstanding Contribution Awards

Outstanding Contribution Awards in
recognition of service to the IEEE
Li-C Wang International Test Conference Steering
Committee
10 Years of Service

David Armstrong Yiorgos Makris 35 Years of Service

John Caroli Ozgur Sinanoglu Amy Gold

Masahiro Fujita 25 Years of Service

Bill Lowd
5 Years of Service

Jill Sibert
Robert Aitken Rubin Parekhji
20 Years of Service
Abhijit Chatterjee Srivaths Ravi
Scott Davidson
Vivek Srikanth
Chickermane Venkataraman Gordon Roberts

Jennifer Dworak Xiaoqing Wen 15 Years of Service

Patrick Girard LeRoy Winemberg Ron Press

Rohit Kapur Peter Wohl 5 Years of Service

Kuen-Jong Lee Yervant Zorian Jennifer Dworak

Sammy Makar Li-C Wang

EXHIBITORS

Advantest class full turnkey solutions to

3061 Zanker Road 150+ global customers for the past two
San Jose, CA 95134 decades.
Phone: 408-456-3600 Our 600+ engineers are steeped in
http://www.advantest.com/ technology innovation and have a
Booth 223 unique combination of expertise to provide
A world-class technology company, a maximum value proposition
Advantest is the leading producer of to our customers. We have been providing
automatic test equipment (ATE) for the cost-effective solutions across products on
semiconductor industry and a premier multiple verticals including IC test
manufacturer of measuring instruments engineering (ATE &
used in the design and production of Bench), IC packaging Design, Design,
electronic instruments and systems. Its SI/PI simulation and manufacturing
leading-edge systems and products are of high-speed / high-density PCBs
integrated into the most advanced (including ATE probe / final / system
semiconductor production lines in the level test boards), and embedded
world. The company also focuses on R&D system/power electronics solutions. Our
for emerging markets that benefit from test engineering services include new
advancements in nanotech and terahertz product introduction, test
technologies and has introduced multi- platform conversions, sustaining product
vision metrology scanning electron maintenance such as test time
microscopes essential to photomask optimization and yield improvement, multi-
manufacturing, as well as groundbreaking site solutions, characterization, and
3D imaging and analysis tools. Founded in program releases.
Tokyo in 1954, Advantest established its
first subsidiary in 1982 in the USA and
now has subsidiaries worldwide. More Chroma ATE, Inc.
information is available
7 Chrysler
at www.advantest.com.
Irvine, CA 92618
Phone: 949-421-0355 x128
Advanced Test Equipment Corp
Fax: 949-421-0353
10401 Roselle Street http://www.chromaus.com
San Diego, CA 92121
Booth 315
Phone: 800-404-ATEC (2832)
Chroma ATE Inc. is a world-leading
https://www.atecorp.com/ designer and manufacturer of complete
Booth 309 turn-key , IC thermal management and
automated IC Handling solutions.
Specializing in integrated and fully
Caliber Interconnect Solutions automated turn-key electronic test and
MES solutions for the semiconductor, front
https://caliberinterconnect.com/servicedet
and back-end test spaces. Chroma is
ails/IC_Test_Engineering driven to provide unique, tailored solutions,
Booth 325 and technical support to help our US-based
customers excel in today's high demanding
As a leading Semiconductor Test service environment.
provider, Caliber
Interconnects has been providing best-in-
 EXHIBITORS

integral heatsink for medium power and

optional heatsinking to over 100 watts. Up to
500k insertions. Adapters for prototype,
D|R|Yield package conversion, and more. Quick-Turn
volume adapters are our specialty
Opernring 4 8010
Graz Austria
Phone: +43 316 225 7140 Micro Control Company
https://dryield.com/ 7956 Main Street NE
Minneapolis, MN 55432
Booth 123 Phone: 1-800-328-9923
http://www.microcontrol.com
DR YIELD is the premier global provider of
Booth 222
YieldWatchDog and the innovative leader in
Micro Control Company is the test with burn-
Big Data analytics.
in expert. Devices that successfully complete
Our software, YieldWatchDog is the smart
a burn-in cycle in a Micro Control burn-in with
solution for semiconductor data visualization
test system stimulation are proving
and automated process control. More
significantly more reliable for long-term use.
specifically, YieldWatchDog is the powerful
Electronic stimulation is applied during the
yield management software for the
burn-in cycle Stressing the devices during
integration, advanced analysis and
burn-in causes devices that are going to fail,
enhanced visualization of all chip
to fail early. By monitoring the devices as
manufacturing and test data. It is capable of
they are detected and eliminated from the lot.
recognizing patterns and automatically
notifies you if any irregularities occur. Using
patented data aggregation technology and Roos Instruments,Inc.
advanced algorithms, YieldWatchDog
quickly integrates even large amounts of data 2285 Martin Avenue, C
into one large-scale, highly compressed Santa Clara, CA 95050
database.
Phone: (408) 748-8589
YieldWatchDog’s user-friendly and intuitive
interface gives you deep insight into your http://www.roos.com
data.
Booth 210
YieldWatchDog is a customizable, fully
scalable, turnkey solution that saves on Roos Instruments is the premier supplier of
engineering time and IT infrastructure costs. highly automated test solutions for wireless
Visit our website for more information: devices. Our system's performance and
https://dryield.com/ technical expertise are the tools our
customers rely on to meet the challenges of
Ironwood Electronics next generation products.

1335 Eagandale Court

Eagan, MN 55121
Phone: 952-229-8200
Fax: 952-229-8201
http://ironwoodelectronics.com

Booth 111

Includes 75 GHz bandwidth sockets for BGA

and QFN, only slightly larger than IC with
Fill in Your Exhibit Hall Passport for Prizes

All registered attendees will receive a passport in their conference bag. Get your passport
stamped Tuesday and Wednesday while visiting exhibitor booths and at least one Corporate
Forum session. Drop your completed passport into the collection box located in the exhibit
hall, and be eligible for the drawing at 4:00 p.m. on Wednesday in the exhibit hall. You need
not be present at the time of drawing to win.

Please see the full instructions included with your passport for details.

Table of Contents
 EXHIBITORS

Siemens TESEC
8005 SW Boeckman Road 1225 W. 190th Street, Suite 325
Wilsonville, OR 97070 Gardena, CA 90248
https://eda.sw.siemens.com/en- Phone: 1-480-829-6879
US/ic/tessent/ http://www.tesecinc.com/
Booth 115
Booth 323
Siemens is the technology and market
leading provider of design-for-test Tesec is a world leader in power
solutions. With the industry’s only semiconductor test and automation. We
comprehensive hierarchical DFT offering, provide high-volume production and
our solutions enable our customers to engineering test solutions for a variety of
achieve the lowest cost of test, highest applications including High-Power & High-
test quality, fastest yield ramps and meet Reliability devices, MEMS, and
the most rigorous functional safety WLCSP/Strip-Test. The leading provider of
requirements demanded by the yield improvement.
automotive market’s ISO 26262 standard.

Synopsys
690 E Middlefield Road
Mountain View, CA 94043
Phone: 650-584-5000
Fax: 650-584-4249
http://www.synopsys.com

Booth 306

The Synopsys TestMAX™ family offers

unparalleled test quality and efficiency, with tight
integration across the Synopsys Fusion Design
Platform to enable faster turnaround time while
uniquely meeting both design and test goals
concurrently.

TDK-Lambda

405 Essex Road

Neptune, NJ 07753
Phone: +1 732 922 9300
Fax: +1 732 922 1441
https://www.us.lambda.tdk.com/

Booth 227
EXHIBITORS

Test Technology Technical Council

Test Spectrum Phone: 540-937-8280
http://tab.computer.org/tttc
http://testspectrum.com/home/
Booth 309
Booth 226
TTTC's goals are to contribute to our
Test Spectrum is a recognized leader in members' professional development and
semiconductor test solutions. We provide advancement, to help them solve
software products that are essential tools for engineering problems in electronic test, and
every test engineer and world class to help advance the state-of-the art.
engineering services in test software and test
hardware development. We are ITAR
Certified.
Our customers include fabless UNITES Systems
semiconductor companies, integrated device
Phone: 503-555-1212
manufacturers (IDMs), automated test
equipment companies (ATE), test and https://unites-systems.com//
assembly houses, and IP companies from all Booth 324
across the globe.
Founded in 1999 in Austin, Texas, Test UNITES Systems a.s. is on the market since
Spectrum is an independent corporation with 1991. Our main focus is on development
one goal in mind – to provide cutting edge
and production of dedicated test and
technical solutions to the semiconductor test
community. Our team is considered to have measurement systems, mainly ATE
the best and brightest test development solutions for discrete semiconductors (such
talent serving the semiconductor industry
as MOSFETs, IGBTs, Diodes, BJTs and
today.
Power modules) with hundreds of
installations worldwide. Recently with

TSE emphasis on SiC and GaN semiconductors.

Apart from this, UNITES also develops and
http://www.tse21.com/
produce platforms for functional and in-
Booth 329
circuit testing of assembled PCB testing
(PCBA).

TSSI

920 SW Sixth Avenue

Portland, OR 97204
Phone: +1 503-764-2308 Table of Contents
https://www.tessi.com/

Booth 317

Founded in 1979, TSSI is a worldwide leader in

design-to-test conversion and validation software
solutions. Our all-in-one graphical user interface
allows all tools available at your fingertips, and
data to be visualized throughout the vector
translation process. Vector translation should not
be a blind-conversion where extra steps are
needed to even know whether the output patterns
are correct. Also come to see how TSSI
VirtualTester reduces silicon bring-up time from
months to hours, and how 100% test patterns
worked the first time. If visiting our physical
booth in-person at Disneyland Hotel, come by to
get a chance to win an Apple product!
 EXHIBITORS

yieldHUB
Versatile Power
https://www.yieldhub.com/
743 Camden Ave. Booth 307
Campbell, CA 95008 With today’s added pressures of time to
market, along with the high cost of
Phone: 408-341-4604
manufacturing, and material shortages, it’s
Fax: 408-341-4601 never been a better time for semiconductor
https://versatilepower.com companies and fabless startups to invest in
a yield management platform. yieldHUB was
Booth 322 designed to offer modern automated
Versatile Power has a long history of solutions for all yield management
designing robust power supplies for military, challenges.
industrial, commercial, laboratory and
medical applications. Founded in 2002, Smart engineering is at the core of our
Versatile Power offers a line of standard platform, which was built so engineers can
power supplies as well as custom-design easily access and analyze data with
power solutions. All of our products are unrivaled speed and accuracy. As volume
designed and manufactured in the US. grows, yieldHUB users can analyze and
stack hundreds and even thousands of
wafers at the same time using our cloud
Xallent Inc. product on a web browser. Your engineers
will be able to monitor production from any
https://xallent.com/
device no matter where they are.
Booth 326
The yieldHUB platform offers exclusive and
unique features to its customers, combined
with intuitive design, innovative
communication tools, and help from our
team of highly experienced experts. We’ve
helped improve the yield for manufacturers
of 60 billion chips in the past year.

You could be just a few clicks away from

having all your yield management problems
solved by our team today.
Visit www.yieldhub.com to get started.
 EXHIBITOR BOOTH LOCATIONS

Advantest..............................................223 TDK-Lambda ……………………………..227

Advanced Test Equipment Corp...........309 TESEC....................................................323
Caliber Interconnect ……………………325 Test Spectrum …………………………...226
Chroma ATE, Inc. ……………….……...315 TSE ……………………………………….329
D|R|Yield …………………………………123 TSSI ……………………………………….317
Ironwood Electronics…………….……...111 TTTC ………………………………….…..209
Micro Control Company.........................222 UNITES Systems ……………………… 324
Roos Instruments, Inc. ………….………210 Versatile Power......................................322
Siemens………………..……….……......115 Xallent Inc…………………………………326
Synopsys, Inc. ………............................306 YieldHUB................................................307

Table of Contents
Exhibits Floor Plan