FM25S01A

3.3V 1G-BIT SPI NAND FLASH

MEMORY

Datasheet

Apr. 2019

Datasheet
FM25S01A 3.3V 1G-BIT SPI NAND FLASH MEMORY Ver.1.0 1
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Datasheet
FM25S01A 3.3V 1G-BIT SPI NAND FLASH MEMORY Ver.1.0 2
1. Description
The FM25S01A is a 1G-bit (128M-byte) SPI (Serial Peripheral Interface) NAND Flash memory,
with advanced write protection mechanisms. The FM25S01A supports the standard Serial
Peripheral Interface (SPI), Dual/Quad I/O option.

2. Features
 1G-bit NAND Flash Memory  Program/Erase/Read Speed
– Single-level cell (SLC) technology – PAGE PROGRAM time : 400µs typical
– Page size : 2112bytes(2048 + 64bytes) – BLOCK ERASE time : 4ms typical
– Block size : 64 pages(128K + 4K bytes) – PAGE READ time :
– Device size: 1Gb(1024 blocks) 100µs maximum (with ECC)
 Serial Interface 25µs maximum (without ECC)
– Standard SPI: CLK, CS#, DI, DO, WP#  Advanced Features for NAND
– Dual SPI: CLK, CS#, DQ0, DQ1, WP# – 1bit Internal ECC option, per 512 bytes
– Quad SPI: CLK, CS#, DQ0, DQ1, DQ2, – Software and Hardware Write-Protect
DQ3 – 32B Unique ID and 2KB parameter
 High Performance page
– 104MHz for fast read – 25 OTP pages
– Quad I/O data transfer up to 416Mbits/s – INTERNAL DATA MOVE by page
– Promised golden block0
 Supply Voltage
 Package
– FM25S01A:2.7V~3.6V
– WSON8 8x6mm (TDFN8 8x6mm)
 Low Power, Wide Temperature Range
– All Packages are RoHS Compliant and
– 20mA active current Halogen-free
– -40~85°C operating range  Minimum 100,000 Program/Erase Cycles
 Data Retention: 10 years

Datasheet
FM25S01A 3.3V 1G-BIT SPI NAND FLASH MEMORY Ver.1.0 3
3. Packaging Type and Pin Configurations
FM25S01A is offered in a WSON8 8x6mm (TDFN8 8x6mm) as shown in Figure1. Package
diagram and dimension are illustrated at the end of this datasheet.

Figure 1 Pad Assignments, WSON8 8x6mm (TDFN8 8x6mm)

Top View
CS# 1 8 VCC
DO(DQ1) 2 7 HOLD#(DQ3)
WP#(DQ2) 3 6 CLK
VSS 4 5 DI(DQ0)

3.1. Pin Description

Table 1 Pin Description
PIN NO. PIN NAME I/O FUNCTION
1 CS# I Chip Select Input
2 DO (DQ1) I/O Data Output (Data Input Output 1)(1)
3 WP# (DQ2) I/O Write Protect Input (Data Input Output 2)(2)
4 VSS Ground
5 DI (DQ0) I/O Data Input (Data Input Output 0)(1)
6 CLK I Serial Clock Input
7 HOLD# (DQ3) I/O Hold Input (Data Input Output 3)(2)
8 VCC Power Supply
Note:
1 DQ0 and DQ1 are used for Dual SPI instructions.
2 DQ0 – DQ3 are used for Quad SPI instructions.

Datasheet
FM25S01A 3.3V 1G-BIT SPI NAND FLASH MEMORY Ver.1.0 4
4. Block Diagram
Figure 2 SPI NAND Flash Memory Block Diagram

DI/ DO/ WP#/ HOLD#/

CLK CS# DQ0 DQ1 DQ2 DQ3

Serial Interface Logic

VCC

Status Cache
VSS NAND
Register Memory
Flash
memory
core
ECC codec

Datasheet
FM25S01A 3.3V 1G-BIT SPI NAND FLASH MEMORY Ver.1.0 5
5. Memory Mapping
Figure 3 Memory Map

Blocks 0 1 2 1023
RA<15:6>

Pages
0 1 63
RA<5:0>

Bytes 0 1 2 2111
CA<11:0>

Note:
1. CA: Column Address. The 12-bit column address is capable of addressing from 0 to 4095 bytes; however,only bytes
0 through 2111 are valid. Bytes 2112 through 4095 of each page are “out of bounds, ” do not exists in the
device, and cannot be addressed.
2. RA: Row Address. RA<5:0> selects a page inside a block, and RA<15:6> selects a block.

Datasheet
FM25S01A 3.3V 1G-BIT SPI NAND FLASH MEMORY Ver.1.0 6
6. Array Organization
Table 2 Array Organization
Each device has Each block has Each page has Unit
128M + 4M 128K + 4K 2K + 64 bytes
1024 x 64 64 - Pages
1024 - - Blocks

Figure 4 Array Organization

DQ3-DQ0
Cache Register 2048 64

1 page = (2K + 64 bytes)

1 block = 64 pages
= (128K + 4K) bytes
1024 Blocks 1 device = 1024 blocks
Per device 1 block
= 1Gb

Datasheet
FM25S01A 3.3V 1G-BIT SPI NAND FLASH MEMORY Ver.1.0 7
7. Device Operations
7.1. Single Data Rate (SDR)
7.1.1. Standard SPI
The FM25S01A is accessed through an SPI compatible bus consisting of four signals: Serial
Clock (CLK), Chip Select (CS#), Serial Data Input (DI) and Serial Data Output (DO). Standard
SPI instructions use the DI input pin to serially write instructions, addresses or data to the device
on the rising edge of CLK. The DO output pin is used to read data or status from the device on
the falling edge of CLK.

SPI bus operation Mode 0 (0,0) and 3 (1,1) are supported. The primary difference between
Mode 0 and Mode 3 concerns the normal state of the CLK signal when the SPI bus master is in
standby and data is not being transferred to the Serial Flash. For Mode 0, the CLK signal is
normally low on the falling and rising edges of CS#. For Mode 3, the CLK signal is normally high
on the falling and rising edges of CS#.

Figure 5 SPI SDR Modes Supported

CS#
MODE3 MODE3
CLK MODE0 MODE0

DI Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 DONT CARE
MSB
HIGH IMPEDANCE
DO Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0
MSB

7.1.2. Dual SPI

The FM25S01A supports Dual SPI operation when using the x2 and dual IO instructions. These
instructions allow data to be transferred to or from the device at two times the rate of ordinary
Serial Flash devices. When using Dual SPI instructions, the DI and DO pins become
bidirectional I/O pins: DQ0 and DQ1.

7.1.3. Quad SPI

The FM25S01A supports Quad SPI operation when using the x4 and Quad IO instructions. These
instructions allow data to be transferred to or from the device four times the rate of ordinary Serial
Flash. When using Quad SPI instructions the DI and DO pins become bidirectional DQ0 and DQ1
and the WP # and HOLD# pins become DQ2 and DQ3 respectively.

7.2. CS#
The SPI Chip Select (CS#) pin enables and disables device operation. When CS# is high, the
device is deselected and the Serial Data Output (DO, or DQ0, DQ1, DQ2, DQ3) pins are at high
impedance. When deselected, the devices power consumption will be at standby levels unless
an internal page read, erase, program or reset is in progress. When CS# is brought low, the
device will be selected, power consumption will increase to active levels and instructions can be

Datasheet
FM25S01A 3.3V 1G-BIT SPI NAND FLASH MEMORY Ver.1.0 8
 written to and data read from the device. After power-up, CS# must transition from high to low
before a new instruction will be accepted.

7.3. CLK
This input signal provides the synchronization reference for the SPI interface. Instructions,
addresses, or data input are latched on the rising edge of the CLK signal. Data output changes
after the falling edge of CLK.

7.4. Serial Input (DI) / DQ0

This input signal is used to transfer data serially into the device. It receives instructions,
addresses, and data to be programmed. Values are latched on the rising edge of serial CLK
clock signal.

DI becomes DQ0 - an input and output during Dual and Quad commands for receiving data to be
programmed (values latched on rising edge of serial CLK clock signal) as well as shifting out
data (on the falling edge of CLK).

7.5. Serial Output (DO) / DQ1

This output signal is used to transfer data serially out of the device. Data is shifted out on the
falling edge of the serial CLK clock signal.

DO becomes DQ1 - an input and output during Dual and Quad commands for receiving data to
be programmed (values latched on rising edge of serial CLK clock signal) as well as shifting out
data (on the falling edge of CLK).

7.6. Write Protect (WP#) / DQ2

WP# is driven LOW to prevent writing the Feature Registers. The WPE bit in Protection Register
controls the function of WP#, and the other bits in Register can protect a specific portion of array.
When WPE=1, the device is in the Hardware-protection mode that WP# functions as a dedicated
active low input pin for the Write Protect of the device. If WPE=1 and WP# goes LOW, the
device will become READ-only. When WPE=0, the device is in the Software-protection mode
that only Protection Register can be protected. WP# functions as a data I/O pin.

The WP# function is replaced by DQ2 for input and output during Quad mode for receiving data
to be programmed (values are latched on rising edge of the CLK signal) as well as shifting out
data (on the falling edge of CLK).

7.7. Hold (HOLD#) / DQ3

For Standard SPI and Dual SPI operations, the HOLD# signal allows the FM25S01A operation
to be paused while it is actively selected (when CS# is low). The HOLD# function may be useful
in cases where the SPI data and clock signals are shared with other devices. For example,
consider if the page buffer was only partially written when a priority interrupt requires use of the
SPI bus. In this case the HOLD# function can save the state of the instruction and the data in the
buffer so programming can resume where it left off once the bus is available again.

To initiate a HOLD# condition, the device must be selected with CS# low. A HOLD# condition
will activate on the falling edge of the HOLD# signal if the CLK signal is already low. If the CLK is
not already low the HOLD# condition will activate after the next falling edge of CLK. The HOLD#
condition will terminate on the rising edge of the HOLD# signal if the CLK signal is already low. If
the CLK is not already low the HOLD# condition will terminate after the next falling edge of CLK.
During a HOLD# condition, the Serial Output (DO) is high impedance, and Serial Input (DI) and
Serial Clock (CLK) are ignored. The Chip Select (CS#) signal should be kept active (low) for the
full duration of the HOLD# operation to avoid resetting the internal logic state of the device.

Datasheet
FM25S01A 3.3V 1G-BIT SPI NAND FLASH MEMORY Ver.1.0 9
 The HOLD# function is not available during the Quad mode. The Hold function is replaced by
DQ3 for input and output during Quad mode for receiving addresses, and data to be
programmed (values are latched on rising edge of the CLK signal) as well as shifting out data
(on the falling edge of CLK).

Figure 6 Hold Condition Waveform

Active Hold Active Hold Active

Datasheet
FM25S01A 3.3V 1G-BIT SPI NAND FLASH MEMORY Ver.1.0 10
8. Status Register
Four Status Registers are provided for FM25S01A: Protection Register (SR-1), Configuration
Register (SR-2), Status Register (SR-3) and Drive Register (SR-4). Each register is accessed by
GET FEATURE and SET FEATURE commands combined with 1-Byte Register Address
respectively.

8.1. Protection Register/Status Register-1(Volatile Writable)

Figure 7 Protection Register (Address A0h)

S7 S6 S5 S4 S3 S2 S1 S0

After Power On 0 1 1 1 1 1 0 0

SRP0 BP3 BP2 BP1 BP0 TB WPE SRP1

Status Register Protect-0

(Volatile Writable)

Block Protect Bits

(Volatile Writable)
Top/Bottom Protect Bit
(Volatile Writable)
WP# Protect Bit
(Volatile Writable)
Status Register Protect-1
(Volatile Writable)

8.1.1. Block Protection Bits (BP3, BP2, BP1, BP0, TB)

The Block Protect bits (BP3, BP2, BP1, BP0, TB) are volatile read/write bits in the status register-
1 that provide Write Protection control and status. Block Protect bits can be set using the SET
FEATURE Instruction. All, none or a portion of the memory array can be protected from Program
and Erase instructions (See Status Register Memory Protection table). The default values for the
Block Protection bits (BP3, BP2, BP1, BP0, TB) are 1 after power up to protect the entire array.

8.1.2. Block Register Write Protection Bit (SRP1, SRP0, WPE)

The block lock feature provides the ability to protect the entire device, or ranges of blocks, from
the PROGRAM and ERASE operations. After power-up, the device is in the “locked” state, i.e.,
feature bit BP0, BP1, BP2, BP3, and TB are set to 1. To unlock all the blocks, or a range of
blocks, the SET FEATURE command must be issued to alter the state of protection feature bit.

Datasheet
FM25S01A 3.3V 1G-BIT SPI NAND FLASH MEMORY Ver.1.0 11
 Table 3 Protection Bits of Protection Register
Software Protection (Controller, X4 Program/Read is enable)
SRP1 SRP0 WPE WP# Description
0 0 0 X No WP# functionality, and WP# pin will always function as DQ2
SR1 cannot be changed, and WP# pin will function as DQ2 for
0 1 0 0
X4 operation
0 1 0 1 SR1 can be changed, and WP# pin will always function as DQ2
Power Lock Down SR1, and WP# pin will always function as
1 0 0 X
DQ2
Set PR_L=1 is allowed, and SR1 is locked until next Power
1 1 0 X
cycle, and WP# pin will always function as DQ2
Hardware Protection (System Circuit/PCB layout, X4 Program/Read is disable)
SRP1 SRP0 WPE WP# Description
0 X 1 VCC SR1 can be changed
1 0 1 VCC Power Lock Down(1) SR1
Set PR_L=1 is allowed, and SR1 is locked until next Power
1 1 1 VCC
cycle
All Write operation are blocked, and entire device(Register,
X X 1 GND
Array, and OTP area) is Read-only

NOTE:
1. When SRP1=1 and SRP0=0, a cycle of power-down to power-up will change the state to
SRP1=0 and SRP0=0.
2. Once BP[3:0], TB, and WPE bits are set correctly, SRP0 and SRP1 should both be set to “1”
as well to allow PR_L bit being set to “1” to lock the protection in the SR1 (Protection
Register) until next Power cycle.

8.2. Configuration Register/Status Register-2

Figure 8 Configuration Register (Address B0h)

S7 S6 S5 S4 S3 S2 S1 S0

After Power On 0 0 0 1 R R R R

OTP_ OTP_ ECC_

PR_L R R R R
PRT EN E

OTP Data Pages Lock

(OTP Lock)
Enter OTP Mode
(Volatile Writable)
Status Register-1 Lock
(Volatile Writable)
Enable ECC
(Volatile Writable)

Reserved

Datasheet
FM25S01A 3.3V 1G-BIT SPI NAND FLASH MEMORY Ver.1.0 12
8.2.1. One Time Program Lock Bit (OTP_PRT) —OTP Lockable
In addition to the main memory array, FM25S01A also provides an OTP area for the system to
store critical data that cannot be changed once it’s locked. The OTP area consists of 30 pages of
2,112-Byte each. The default data in the OTP area are FFh. Only Program command can be
issued to the OTP area to change the data from “1” to “0”, and data is not reversible (“0” to “1”)
by the Erase command. Once the correct data is programmed in and verified, the system
developer can set OTP_PRT bit to 1, so that the entire OTP area will be locked to prevent further
alteration to the data.

8.2.2. Enter OTP Access Mode Bit (OTP_EN) — Volatile Writable

The OTP_EN bit must be set to 1 in order to use the standard Program/Read commands to
access the OTP area as well as to read the Unique ID/ Parameter Page information. The default
value after power up is 0.

8.2.3. Protection Register Lock Bit (PR_L) — Volatile Writable

When SRP1=1 and SRP0=1, The PR_L bit can be set to 1 to lock Protection Register lock. After
that, Protection register (SR1) is locked until next Power cycle.

8.2.4. ECC Enable Bit (ECC_E) — Volatile Writable

FM25S01A has a built-in ECC algorithm that can be used to preserve the data integrity. Internal
ECC calculation is done during page programming, and the result is stored in the extra area for
each page. During the data read operation, ECC engine will verify the data values according to
the previously stored ECC information and to make necessary corrections if needed. The
verification and correction status is indicated by the ECC Status Bits. ECC function is enabled by
default when power on (ECC_E=1), and it will not be reset to 0 by the Device Reset command.

8.3. Status Register-3

Figure 9 Status Register-3 (Address C0h)

S7 S6 S5 S4 S3 S2 S1 S0

After Power On R R 0/1 0/1 0 0 0 0

P_FA E_FA
R R ECCS1 ECCS0 WEL OIP
IL IL

Reserved

ECC Status Bit[1:0]

(Status Only)
Program Failure
(Status Only)

Erase Failure
(Status Only)

Write Enable Latch

(Status Only)
Operation in Process
(Status Only)

Datasheet
FM25S01A 3.3V 1G-BIT SPI NAND FLASH MEMORY Ver.1.0 13
8.3.1. Cumulative ECC Status (ECCS1, ECCS0) —Status Only
ECC function is used in NAND flash memory to correct limited memory errors during read
operations. The ECC Status Bits (ECCS1, ECCS0) should be checked after the completion of a
Read operation to verify the data integrity. The ECC Status bits values are don’t care if ECC_E=0.
These bits will be cleared to 0 after a RESET command.
After power-on, ECC status is set to reflect the contents of block 0, page 0.

Table 4 ECC Status Bits

ECC Status
Description
ECCS1 ECCS0
0 0 No errors
0 1 1-bit error detected and corrected
1 0 2-bit or more than 2-bit errors detected and not corrected
1 1 Reserved

8.3.2. Program/Erase Failure (P_FAIL, E_FAIL) —Status Only

The Program/Erase Failure Bits are used to indicate whether the internally-controlled
Program/Erase operation was executed successfully or not. These bits will also be set
respectively when the Program or Erase command is issued to a locked or protected memory or
OTP area. Both bits will be cleared at the beginning of the Program Execute or Block Erase
instructions as well as the device RESET instruction.

8.3.3. Write Enable Latch (WEL) —Status Only

Write Enable Latch (WEL) is a read only bit in the status register that is set to 1 after executing a
Write Enable Instruction. The WEL status bit is cleared to 0 when the device is write disabled. A
write disable state occurs upon power-up or after any of the following instructions: Write Disable,
Program Execute, Block Erase, Program Execute for OTP pages, and OTP locking.

8.3.4. Operation In Progress (OIP) —Status Only

OIP is a read only bit in the status register that is set to a 1 state when the device is powering up
or executing a Page Data Read, Program Execute, Block Erase, Program Execute for OTP area,
OTP Locking and RESET instruction. During this time the device will ignore further instructions
except for the GET FEATURE, RESET and Read ID instructions. When the program, erase or
page read instruction has completed, the OIP bit will be cleared to a 0 state indicating the device
is ready for further instructions.

Datasheet
FM25S01A 3.3V 1G-BIT SPI NAND FLASH MEMORY Ver.1.0 14
8.4. Output Drive Register
Figure 10 Output Drive Register (Address D0h)

S7 S6 S5 S4 S3 S2 S1 S0

After Power On R 0 1 R R R R R

R DRS1 DRS0 R R R R R

Reserved
Output Drive Strength
(Volatile Writable)

Reserved

8.4.1. Output Drive Strength (DRS1, DRS0)— Volatile Writable

Output Drive Strength bit can be used to adjust output PAD strength.

Table 5 Drive Strength Bits

DRS1 DRS0 Driver Strength
0 0 100%
0 1 75%
1 0 50%
1 1 25%

Datasheet
FM25S01A 3.3V 1G-BIT SPI NAND FLASH MEMORY Ver.1.0 15
9. Command Definition
9.1. Command Set Tables
Table 6 Standard SPI Command Set
INSTRUCTION NAME BYTE 1 BYTE 2 BYTE 3 BYTE 4 BYTE 5 BYTE N
WRITE ENABLE 06h
WRITE DISABLE 04h
GET FEATURE 0Fh A7-A0 (D7-D0)
SET FEATURE 1Fh A7-A0 D7-D0
PAGE READ 13h A23-A16 A15-A8 A7-A0
READ FROM CACHE 03h/0Bh A15-A8(2) A7-A0 dummy (D7-D0)
READ ID 9Fh dummy (MID) (7) (DID) (7)
PROGRAM LOAD 02h A15-A8(6) A7-A0 D7-D0 Next byte Byte N
PROGRAM LOAD RANDOM (6)
84h A15-A8 A7-A0 D7-D0 Next byte Byte N
DATA
PROGRAM EXECUTE 10h A23-A16 A15-A8 A7-A0
BLOCK ERASE D8h A23-A16 A15-A8 A7-A0
RESET FFh

Table 7 Dual SPI Command Set

INSTRUCTION NAME BYTE 1 BYTE 2 BYTE 3 BYTE 4 BYTE 5 BYTE N
(2)
READ FROM CACHE x 2 3Bh A15-A8 A7-A0 dummy (D7-D0)x2
READ FROM CACHE DUAL IO BBh A15-A0(3) dummy(4) (D7-D0)x2

Table 8 Quad SPI Command Set

INSTRUCTION NAME BYTE 1 BYTE 2 BYTE 3 BYTE 4 BYTE 5 BYTE N
(2)
READ FROM CACHE x4 6Bh A15-A8 A7-A0 dummy (D7-D0)x4
READ FROM CACHE QUAD (D7-
EBh A15-A0(5)
IO D0)x4
PROGRAM LOAD x4 32h A15-A8(6) A7-A0 (D7-D0)x4 Next byte Byte N
PROGRAM LOAD RANDOM
34h A15-A8(6) A7-A0 (D7-D0)x4 Next byte Byte N
DATA x4
Notes:
1. Data bytes are shifted with Most Significant Bit first. Byte fields with data in parenthesis “( )” indicate data
output from the device on either 1, 2 or 4 DQ pins.
2. The x8 clock = dummy<3:0>, A11-A8
3. The x8 clock = dummy<3:0>, A11-A0
4. The x8 clock = dummy<7:0>, D7-D0
5. The x8 clock = dummy<3:0>, A11-A0, dummy<15:0>
6. The x8 clock = dummy<3:0>, A11-A8
7. MID is Manufacture ID(A1h for FMSH), DID is Device ID(E4h for current device)

Datasheet
FM25S01A 3.3V 1G-BIT SPI NAND FLASH MEMORY Ver.1.0 16
9.2. WRITE operation
9.2.1. WRITE ENABLE (WREN) (06h)
The WRITE ENABLE (WREN) command sets the WEL bit in the status register to 1. The WEL
bit must be set prior to following operations that changes the contents of the memory array:
 PAGE PROGRAM
 OTP PROGRAM
 OTP LOCK
 BLOCK ERASE

Figure 11 WRITE ENABLE (06h) Timing

CS#

Mode 3 0 1 2 3 4 5 6 7 Mode 3
CLK Mode 0 Mode 0

Instruction (06h)

DI

High Impedance
DO

9.2.2. WRITE DISABLE (WRDI) (04h)

The WRITE DISABLE (WRDI) command resets the WEL bit in the status register to 0. The WEL
bit is automatically reset after Power-up and upon completion of the following operations:
 PAGE PROGRAM
 OTP PROGRAM
 OTP LOCK
 BLOCK ERASE

Figure 12 WRITE DISABLE (04h) Timing

CS#

Mode 3 0 1 2 3 4 5 6 7 Mode 3

CLK Mode 0 Mode 0

Instruction (04h)

DI

High Impedance
DO

Datasheet
FM25S01A 3.3V 1G-BIT SPI NAND FLASH MEMORY Ver.1.0 17
9.3. Feature Operation
9.3.1. GET FEATURE (0Fh) and SET FEATURE (1Fh)
The GET FEATURE (0Fh) and SET FEATURE (1Fh) commands are used to alter the device
behavior from the default power-on behavior. These commands use a 1-byte feature address to
determine which feature is to be read or modified. Features such as OTP and block protection
can be enabled or disabled by setting specific bits in feature address A0h and B0h (shown the
following table). The status register is mostly read, except WEL, which is writable bit with the
WREN (06h) command.

When a feature is set, it remains active until the device is power cycled or the feature is written to.
Unless otherwise specified in the Status Register section, once the device is set, it remains set,
even if a RESET (FFh) command is issued.

Table 9 Features Setting

Data Bits
Register Address
7 6 5 4 3 2 1 0
SR-1 A0h SRP0 BP3 BP2 BP1 BP0 TB WPE SRP1
SR-2 B0h OTP_PRT OTP_EN PR_L ECC_E Reserved Reserved Reserved Reserved
SR-3 C0h Reserved Reserved ECCS1 ECCS0 P_FAIL E_FAIL WEL OIP
SR-4 D0h Reserved DRS1 DRS1 Reserved Reserved Reserved Reserved Reserved

Figure 13 GET FEATURE (0Fh) Timing

CS#

Mode3 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23
CLK Mode0

Command 1 byte Address

DI 0Fh 7 6 5 4 3 2 1 0
Data Out
HIGH IMPEDANCE
DO 7 6 5 4 3 2 1 0

Figure 14 SET FEATURE (1Fh) Timing

CS#

Mode3 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23
CLK Mode0

Command 1 byte Address Data byte

DI 1Fh 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0

HIGH IMPEDANCE
DO

Datasheet
FM25S01A 3.3V 1G-BIT SPI NAND FLASH MEMORY Ver.1.0 18
9.4. READ Operation
9.4.1. PAGE READ
The PAGE READ (13h) command transfers the data from the NAND Flash array to the cache
register. The command sequence is follows:
 13h (PAGE READ TO CACHE)
 0Fh (GET FEATURE command to read the status)
 READ FROM CACHE Operation
– 0Bh or 03h (READ FROM CACHE)
– 3Bh (READ FROM CACHE x2)
– 6Bh (READ FROM CACHE x4)
– BBh (READ FROM CACHE DUAL IO)
– EBh (READ FROM CACHE QUAD IO)

The PAGE READ command requires a 24-bit address consisting of 8 dummy bits followed by a
16-bit block/page address. After the block/page addresses are registered, the device starts the
transfer from the main array to the cache register, and is busy for tRD time. During this time, the
GET FEATURE (0Fh) command can be issued to monitor the status of the operation (refer to the
Status Register section). Following a status of successful completion, the READ FROM CACHE
(03h/0Bh/3Bh/6Bh/BBh/EBh) command must be issued in order to read the data out of the cache.

The READ FROM CACHE command requires 4 dummy bits, followed by 12-bit column address
for the starting byte address. The starting byte address must be in 0 to 2111.

Datasheet
FM25S01A 3.3V 1G-BIT SPI NAND FLASH MEMORY Ver.1.0 19
9.4.2. PAGE READ TO CACHE (13h)
Figure 15 Page Read to Cache (13h) Timing
CS#

Mode3 0 1 2 3 4 5 6 7 8 9 10 26 27 28
CLK Mode0

Command 24-bit Address

DI 13h 23 22 21 5 4 3

HIGH IMPEDANCE
DO
tCS 1

CS#

28 29 30 31 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
CLK
Get Features Command 1-byte address (C0h)

DI 3 2 1 0 0Fh 7 6 5 4 3 2 1 0

HIGH IMPEDANCE
DO
1 2

CS#
13 14 15 16 17 18 19 20 21 22 23
CLK

DI 2 1 0
Status register data out Status register data out

DO 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0

Datasheet
FM25S01A 3.3V 1G-BIT SPI NAND FLASH MEMORY Ver.1.0 20
9.4.3. READ FROM CACHE (03h/0Bh)
Figure 16 READ FROM CACHE (03h / 0Bh) Timing

CS#

Mode3 0 1 2 3 4 5 6 7 8 9 10 21 22 23
CLK Mode0
4 dummy bits A<11:0>
Command
DI 03h or 0Bh 15 14 13 12 11 10 2 1 0

HIGH IMPEDANCE
DO

CS#

24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46
CLK
Dummy

DI 7 6 5 4 3 2 1 0
Data Out 1 Data Out 2
HIGH IMPEDANCE
DO 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1

9.4.4. READ FROM CACHE x2 (3Bh)

Figure 17 READ FROM CACHE x2 (3Bh) Timing

CS#

Mode3 0 1 2 3 4 5 6 7 8 9 10 21 22 23
CLK Mode0
4 dummy bits A<11:0>
Command
DI/DQ0 3Bh 15 14 13 12 11 10 2 1 0

HIGH IMPEDANCE
DO/DQ1

CS#

24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46
CLK
Dummy Data Out 1 Data Out 2 Data Out 3

DI/DQ0 7 6 5 4 3 2 1 0 6 4 2 0 6 4 2 0 6 4 2 0 6 4 2

HIGH IMPEDANCE
DO/DQ1 7 5 3 1 7 5 3 1 7 5 3 1 7 5 3

Datasheet
FM25S01A 3.3V 1G-BIT SPI NAND FLASH MEMORY Ver.1.0 21
9.4.5. READ FROM CACHE x4 (6Bh)
Figure 18 READ FROM CACHE x4 (6Bh) Timing

CS#

Mode3 0 1 2 3 4 5 6 7 8 9 10 21 22 23
CLK Mode0
4 dummy bits A<11:0>
Command
DI/DQ0 6Bh 15 14 13 12 11 10 2 1 0

HIGH IMPEDANCE HIGH IMPEDANCE

DO/DQ1

HIGH IMPEDANCE HIGH IMPEDANCE

WP#/DQ2

HIGH HIGH IMPEDANCE

HOLD#/DQ3

CS#

24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46
CLK
Dummy
Byte1 Byte2 Byte3 Byte4 Byte5
DI/DQ0 7 6 5 4 3 2 1 0 4 0 4 0 4 0 4 0 4 0 4 0 4 0 4

HIGH IMPEDANCE
DO/DQ1 5 1 5 1 5 1 5 1 5 1 5 1 5 1 5

HIGH IMPEDANCE
WP#/DQ2 6 2 6 2 6 2 6 2 6 2 6 2 6 2 6

HIGH IMPEDANCE
HOLD#/DQ3 7 3 7 3 7 3 7 3 7 3 7 3 7 3 7

Datasheet
FM25S01A 3.3V 1G-BIT SPI NAND FLASH MEMORY Ver.1.0 22
9.4.6. READ FROM CACHE DUAL IO (BBh)
The READ FROM CACHE DUAL IO command is similar to the READ FROM CACHE x2
command except that dummy bits, 12-bit column address and dummy bits are input through two
pins DQ0, DQ1.

Figure 19 READ FROM CACHE DUAL IO (BBh) Timing

CS#

Mode3 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23
CLK Mode0

Command
DI/DQ0 BBh 6 4 2 0 6 4 2 0 6 4 2 0 6 4 2 0

HIGH IMPEDANCE
DO/DQ1 7 5 3 1 7 5 3 1 7 5 3 1 7 5 3 1
4 dummy bits, A7-0 dummy Byte 1
A11-8

CS#

24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43
CLK

DI/DQ0 6 4 2 0 6 4 2 0 6 4 2 0 6 4 2 0 6 4 2 0

DO/DQ1 7 5 3 1 7 5 3 1 7 5 3 1 7 5 3 1 7 5 3 1
Byte2 Byte3 Byte4 Byte5

9.4.7. READ FROM CACHE QUAD IO (EBh)

The READ FROM CACHE QUAD IO command is similar to the READ FROM CACHE x4
command except that dummy bits, 12-bit column address and dummy bits are input through four
pins DQ0, DQ1, DQ2 and DQ3.

Figure 20 READ FROM CACHE QUAD IO (EBh) Timing

CS#

Mode3 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22
CLK Mode0

Command
DI/DQ0 EBh 4 0 4 0 4 0 4 0 4 0 4 0 4 0 4

HIGH IMPEDANCE
DO/DQ1 5 1 5 1 5 1 5 1 5 1 5 1 5 1 5

HIGH IMPEDANCE
WP#/DQ2 6 2 6 2 6 2 6 2 6 2 6 2 6 2 6

HIGH
HOLD#/DQ3 7 3 7 3 7 3 7 3 7 3 7 3 7 3 7
dummy3-0,A11-8 A7-0 dummy dummy Byte1 Byte2 Byte3 Byte4

Datasheet
FM25S01A 3.3V 1G-BIT SPI NAND FLASH MEMORY Ver.1.0 23
9.4.8. READ ID (9Fh)
The READ ID command is used to read the 2 bytes of identifier code programmed into the NAND
Flash device. The READ ID command reads a 2-byte that includes the Manufacturer ID and the
device configuration.
Figure 21 READ ID (9Fh) Timing
CS#

Mode 3 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
CLK Mode 0

Command Dummy byte

DI
9Fh 7 6 5 4 3 2 1 0
(DQ0)

D0 High Impedance
(DQ1)

CS#
15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Mode 3

CLK Mode 0

DI
(DQ0)
Manufacture ID Device ID
D0
7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0
(DQ1)

9.5. PROGRAM Operation

The PAGE PROGRAM operation sequence programs 1 byte to 2112 bytes of data within a page.
The page program sequence is as follows:
 02H (PROGRAM LOAD)/32H (PROGRAM LOAD x4)
 06H (WRITE ENABLE)
 10H (PROGRAM EXECUTE)
 0FH (GET FEATURE command to read the status)

The 1st step is to issue a PROGRAM LOAD (02H/32H) command. PROGRAM LOAD consists of
an 8-bit Op code, followed by 4 dummy bits and a 12-bit column address, then the data bytes to
be programmed. The data bytes are loaded into a cache register which is 2112 bytes long. If
more than 2112 bytes are loaded, then those additional bytes are ignored by the cache register.
The command sequence ends when CS# goes from LOW to HIGH. Figure 22 shows the
PROGRAM LOAD operation.

The 2nd step, prior to performing the PROGRAM EXECUTE operation, is to issue a WRITE
ENABLE (06H) command. As with any command that changes the memory contents, the WRITE
ENABLE must be executed in order to set the WEL bit. If this command is not issued, then the
rest of the program sequence is ignored.

The 3rd step is to issue a PROGRAM EXECUTE (10h) command to initiate the transfer of data
from the cache register to the main array. PROGRAM EXECUTE consists of an 8-bit Op code,
followed by a 24-bit address (8 dummy bits and an 16-bit page/block address). After the
page/block address is registered, the memory device starts the transfer from the cache register to

Datasheet
FM25S01A 3.3V 1G-BIT SPI NAND FLASH MEMORY Ver.1.0 24
 the main array, and is busy for tPROG time. This operation is shown in Figure 24.

During this busy time, the status register can be polled to monitor the status of the operation
(refer to the Status Register section). When the operation completes successfully, the next series
of data can be loaded with the PROGRAM LOAD command.

Note: The number of consecutive partial page programming operations (NOP) within the same
page must not exceed 4. In addition, pages must be sequentially programmed within a block.

9.5.1. PROGRAM LOAD (02h)

Figure 22 PROGRAM LOAD (02h) Timing

CS#

Mode 3 0 1 2 3 4 5 6 7 8 9 10 11 12 13 21 22 23 24 25 26 27 28 29 30 31
CLK Mode 0
Command 4 dummy bits 12-bit column address Data Byte 1

DI 02h 15 14 13 12 11 10 2 1 0 7 6 5 4 3 2 1 0

 
=MSB

CS#

39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 Mode 3

CLK Mode 0
Data Byte 2 Data Byte 3 Data Byte 2112

DI 0 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0
  

9.5.2. PROGRAM LOAD x4 (32h)

The PROGRAM LOAD x4 command (32H) is similar to the PROGRAM LOAD command (02H)
but with the capability to input the data bytes by four pins: DQ0, DQ1, DQ2, and DQ3. The
command sequence is shown below. The WPE bit of feature (A0[1]) must be reset to “0” to
enable the PROGRAM LOAD x4 command.

Figure 23 PROGRAM LOAD x4 (32h) Timing

CS#

Mode 3 0 1 2 3 4 5 6 7 8 9 10 11 12 13 21 22 23 24 25 26 27
CLK Mode 0
Command 4 dummy bits 12-bit column address Byte Byte Byte
1 2 2112
DI
32h 15 14 13 12 11 10 2 1 0 4 0 4 0 4 0
(DQ0)

DO HIGH IMPEDANCE
5 1 5 1 5 1
(DQ1)
HIGH
WP#
6 2 6 2 6 2
(DQ2)
HIGH
HOLD#
7 3 7 3 7 3
(DQ3)

Datasheet
FM25S01A 3.3V 1G-BIT SPI NAND FLASH MEMORY Ver.1.0 25
9.5.3. PROGRAM EXECUTE (PE) (10h)
Figure 24 PROGRAM EXECUTE (10h) Timing
CS#

Mode 3 0 1 2 3 4 5 6 7 8 9 29 30 31 Mode 3
CLK Mode 0 Mode 0

Command 24-Bit Address

DI 10h 23 22 2 1 0

High Impedance
DO
tCS

CS#

28 29 30 31 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
CLK

Get Features Command 1-byte address (C0h)

DI
3 2 1 0 0Fh 7 6 5 4 3 2 1 0

DO
HIGH IMPEDANCE

CS#
13 14 15 16 17 18 19 20 21 22 23
CLK

DI 2 1 0
Status register data out Status register data out

DO 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0

9.5.4. Random Data Program

The command sequence is as follows:
 84h (PROGRAM LOAD RANDOM DATA x1) / 34h (x4)
 06H (WRITE ENABLE)
 10H (PROGRAM EXECUTE)
 0FH (GET FEATURE command to read the status)

The random data program operation sequence programs or replaces data in a page with existing
data. PROGRAM LOAD RANDOM DATA command requires 16-bit address with 4 dummy bits
and a 12-bit column address. New data is loaded in the column address provided. If the random
data is not sequential, then another PROGRAM LOAD RANDOM DATA command must be
issued with a new column address. After the data is loaded, PROGRAM EXECUTE command
can be issued to start the programming operation.

Datasheet
FM25S01A 3.3V 1G-BIT SPI NAND FLASH MEMORY Ver.1.0 26
9.5.5. PROGRAM LOAD RANDOM DATA (84h)
Figure 25 PROGRAM LOAD RANDOM DATA (84h) Timing
CS#

Mode 3 0 1 2 3 4 5 6 7 8 9 10 11 12 13 21 22 23 24 25 26 27 28 29 30 31
CLK Mode 0
Command 4 dummy bits 12-bit column address Data Byte 1

DI 84h 15 14 13 12 11 10 2 1 0 7 6 5 4 3 2 1 0

CS#

39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 Mode 3

CLK Mode 0
Data Byte 2 Data Byte 3 Data Byte 2112

DI 0 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0

9.5.6. PROGRAM LOAD RANDOM DATA x4 (34h)

Figure 26 PROGRAM LOAD RANDOM DATA x4 (34h) Timing
CS#

Mode 3 0 1 2 3 4 5 6 7 8 9 10 11 12 13 21 22 23 24 25 26 27
CLK Mode 0
Command 4 dummy bits 12-bit column address Byte Byte Byte
1 2 2112
DI
34h 15 14 13 12 11 10 2 1 0 4 0 4 0 4 0
(DQ0)

DO HIGH IMPEDANCE
5 1 5 1 5 1
(DQ1)
HIGH
WP#
6 2 6 2 6 2
(DQ2)
HIGH
HOLD#
7 3 7 3 7 3
(DQ3)

9.5.7. PROGRAM LOAD RANDOM DATA Quad IO (72h)

Figure 27 PROGRAM LOAD RANDOM DATA Quad IO (72h) Timing
CS#

Mode 3 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19

CLK Mode 0
4 dummy bits
Command Byte
12-bit column Byte1 Byte2 Byte3 Byte4
2112
address
DI
72h 12 8 4 0 4 0 4 0 4 0 4 0 4 0
(DQ0)

DO HIGH IMPEDANCE
13 9 5 1 5 1 5 1 5 1 5 1 5 1
(DQ1)
HIGH
WP#
14 10 6 2 6 2 6 2 6 2 6 2 6 2
(DQ2)
HIGH
HOLD#
15 11 7 3 7 3 7 3 7 3 7 3 7 3
(DQ3)

Datasheet
FM25S01A 3.3V 1G-BIT SPI NAND FLASH MEMORY Ver.1.0 27
9.5.8. INTERNAL DATE MOVE
The INTERNAL DATA MOVE command sequence programs or replaces data in a page with
existing data. The INTERNAL DATA MOVE command sequence is as follows:
 13H (PAGE READ TO CACHE)
 84H/34H (PROGRAM LOAD RANDOM DATA : Optional)
 06H (WRITE ENABLE)
 10H (PROGRAM EXECUTE)
 0FH (GET FEATURE command to read the status)

Prior to performing an INTERNAL DATA MOVE operation, the target page content must be read
out into the cache register by issuing a PAGE READ (13H) command. The PROGRAM LOAD
RANDOM DATA (84H/34H) command can be issued, if user wants to update bytes of data in the
page. This command consists of an 8-bit Op code, followed by 4 dummy bits and a 12-bit column
address. New data is loaded in the 12-bit column address. If the RANDOM DATA is not
sequential, another PROGRAM LOAD RANDOM DATA (84H/34H) command must be issued
with the new column address. After the data is loaded, the WRITE ENABLE command must be
issued, then a PROGRAM EXECUTE (10H) command can be issued to start the programming
operation.

9.6. ERASE Operation

9.6.1. BLOCK ERASE (D8h)
The BLOCK ERASE (D8h) command is used to erase at the block level. The blocks are
organized as 64 pages per block, 2112 bytes per page (2048 + 64 bytes). Each block is 132
Kbytes. The BLOCK ERASE command (D8h) operates on one block at a time. The command
sequence for the BLOCK ERASE operation is as follows:
 06h (WRITE ENBALE command)
 D8h (BLOCK ERASE command)
 0Fh (GET FEATURE command to read the status register)

Prior to performing the BLOCK ERASE operation, a WRITE ENABLE (06h) command must be
issued. As with any command that changes the memory contents, the WRITE ENABLE command
must be executed in order to set the WEL bit. If the WRITE ENABLE command is not issued,
then the rest of the erase sequence is ignored. A WRITE ENABLE command must be followed by
a BLOCK ERASE (D8h) command. This command requires a 24-bit address consisting of 8
dummy bits followed by a 16-bit row address. After the row address is registered, the control logic
automatically controls timing and erase-verify operations. The device is busy for tERS time during
the BLOCK ERASE operation. The GET FEATURE (0Fh) command can be used to monitor the
status of the operation (refer to the Status Register section).

Datasheet
FM25S01A 3.3V 1G-BIT SPI NAND FLASH MEMORY Ver.1.0 28
 Figure 28 BLOCK ERASE (D8h) Timing

CS#

Mode 3 0 1 2 3 4 5 6 7 8 9 29 30 31 Mode 3
CLK Mode 0 Mode 0

Command 24-Bit Address

DI D8h 23 22 2 1 0

High Impedance
DO
tCS

CS#

28 29 30 31 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
CLK

Get Features Command 1-byte address (C0h)

DI
3 2 1 0 0Fh 7 6 5 4 3 2 1 0

DO
HIGH IMPEDANCE

CS#
13 14 15 16 17 18 19 20 21 22 23
CLK

DI 2 1 0
Status register data out Status register data out

DO 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0

Datasheet
FM25S01A 3.3V 1G-BIT SPI NAND FLASH MEMORY Ver.1.0 29
9.7. RESET Operation
9.7.1. RESET (FFh)
The RESET (FFh) command after POWER ON sequence stops all operations. For example, in
case of a program or erase or read operation, the reset command can make the device enter the
standby state after tRST.
Figure 29 RESET (FFh) Timing

tCS

CS#

Mode 3 0 1 2 3 4 5 6 7
CLK Mode 0

Reset Command tRST

DI FFh

9.8. Write Protection

The write protection will be determined by the combination of TB, BP[3:0] bits in the Block Lock
Register (A0h).
Table 10 Block Lock Register Block Protect Bits
TB BP3 BP2 BP1 BP0 Protected Row Address Protected Rows
X 0 0 0 0 None None; all unlocked
0 0 0 0 1 0FF80h~0FFFFh Upper 1/512 locked (BLK1022 & 1023)
0 0 0 1 0 0FF00h~0FFFFh Upper 1/256 locked
0 0 0 1 1 0FE00h~0FFFFh Upper 1/128 locked
0 0 1 0 0 0FC00h~0FFFFh Upper 1/64 locked
0 0 1 0 1 0F800h~0FFFFh Upper 1/32 locked
0 0 1 1 0 0F000h~0FFFFh Upper 1/16 locked
0 0 1 1 1 0E000h~0FFFFh Upper 1/8 locked
0 1 0 0 0 0C000h~0FFFFh Upper 1/4 locked
0 1 0 0 1 08000h~0FFFFh Upper 1/2 locked
1 0 0 0 1 00000h~0007Fh Lower 1/512 locked (BLK0 & 1)
1 0 0 1 0 00000h~000FFh Lower 1/256 locked
1 0 0 1 1 00000h~001FFh Lower 1/128 locked
1 0 1 0 0 00000h~003FFh Lower 1/64 locked
1 0 1 0 1 00000h~007FFh Lower 1/32 locked
1 0 1 1 0 00000h~00FFFh Lower 1/16 locked
1 0 1 1 1 00000h~01FFFh Lower 1/8 locked
1 1 0 0 0 00000h~03FFFh Lower 1/4 locked
1 1 0 0 1 00000h~07FFFh Lower 1/2 locked
X 1 0 1 X All All locked
X 1 1 X X All All locked
NOTE:
1. X = don’t care
2. Any Erase or Program command for the protected area will be ignored.
Datasheet
FM25S01A 3.3V 1G-BIT SPI NAND FLASH MEMORY Ver.1.0 30
10. Unique ID/Parameter/OTP Pages
In addition to the main memory array, the FM25S01A is also equipped with one Unique ID Page,
one Parameter Page, and twenty-five OTP Pages.
Page Address Page Name Descriptions Data Length
00h Unique ID Page Factory programmed, Read Only 32-ByteX16
01h Parameter Page Factory programmed, Read Only 256-ByteX3
02h OTP Page[0] Program Only, OTP lockable 2,112-Byte
… OTP Page[1:23] Program Only, OTP lockable 2,112-Byte
1Ah OTP Page[24] Program Only, OTP lockable 2,112-Byte
To access these additional data pages, the OTP-EN bit in the Status Register-2 must be set to “1”
first. Then, Read operations can be performed on the Unique ID and Parameter Pages, Read and
Program operations can be performed on the OTP pages if it’s not already locked. To return to
the main memory array operation, OTP_EN bit needs to be set to 0.

The device offers a protected, One-Time Programmable NAND Flash memory area. Twenty-five
full pages (2112 bytes per page) are available on the device, and the entire range is guaranteed
to be good. Customers can use the OTP area any way they want, like programming serial
numbers, or other data, for permanent storage. When delivered from factory, feature bit
OTP_PRT is 0.

To access the OTP feature, the user must issue the SET FEATURE command, followed by
feature address B0h. When the OTP is ready for access, pages 02h–1Ah can be programmed in
sequential order. Every page can program only ONCE. The PROGRAM LOAD (02H/32H) and
PROGRAM EXECUTE (10H) commands can be used to program the pages. Also, the PAGE
READ (13H) command and READ FROM CACHE (03h/0Bh/3Bh/6Bh/BBh/EBh) commands can
be used to read the OTP area. The data bits used in feature address B0h to enable OTP access
are shown in the table below.

OTP Access
To access OTP, perform the following command sequence:
 Issue the SET FEATURE command (1Fh) to set OTP_EN
 Issue the SET FEATURE command (1Fh) to reset BP3~BP0 to all 0 before PAGE PROGRAM.
 Issue the PAGE PROGRAM (if OTP_EN=1) or PAGE READ command. Every page can
program only ONCE.

It is important to note that after bits 6 and 7 of the Configuration register are set by the user, the
OTP area becomes read-only and no further programming is supported. For OTP states, see the
following table.

OTP Protect
 Issue the SET FEATURE command (1FH) to set OTP_EN and OTP_PRT
 Issue the SET FEATURE command (1Fh) to reset BP3~BP0 to all 0.
 06H (WRITE ENABLE)
 Issue the PROGRAM EXECUTE (10H) command
 After power-on, OTP_PRT is 0(OTP_PRT is volatile bit). But OTP area is still protected by
internal flag.

Datasheet
FM25S01A 3.3V 1G-BIT SPI NAND FLASH MEMORY Ver.1.0 31
 Table 11 OTP States
OTP_PRT OTP_EN State
0 0 Normal Operation
0 1 Access OTP region
1 0 Not applicable
1 1 Lock the OTP area

Datasheet
FM25S01A 3.3V 1G-BIT SPI NAND FLASH MEMORY Ver.1.0 32
10.1. Parameter Page Data Definitions
The Parameter Page contains 3 identical copies of the 256-Byte Parameter Data. The table
below lists all the key data byte locations. All other unspecified byte locations have 00h data as
default.
Table 12 Parameter Page Definition
Byte
Descriptions Values
Number
0~3 Parameter Page signature 4Fh, 4Eh, 46h, 49h
4~5 Revision number 00h
6~7 Feature supported 00h
8~9 Optional command supported 06h,00h
10~31 Reserved All 00h
46h,55h,44h,41h,4eh,4dh,49h,43
32~43 Device manufacture
h,52h,4fh, 20h, 20h
46h,4dh,32h,35h,53h,30h,31h,
44~63 Device model 41h, 20h,20h, 20h, 20h, 20h, 20h,
20h, 20h, 20h, 20h, 20h,20h
64 Manufacture ID A1h
65~66 Date code 00h,00h
67~79 Reserved All 00h
80~83 Number of data bytes per page 00h, 08h, 00h, 00h
84~85 Number of spare bytes per page 40h, 00h
86~91 Reserved All 00h
92~95 Number of pages per block 40h, 00h, 00h, 00h
96~99 Number of blocks per block unit 00h, 04h, 00h, 00h
100 Number of logic units 01h
101 Number of address bytes 00h
102 Number of bits per cell 01h
103~104 Bad blocks maximum per unit 14h, 00h
105~106 Block endurance 01h,05h
107 Guaranteed valid blocks at beginning of target 01h
108~109 Block endurance for guaranteed valid blocks 00h,00h
110 Number of programs per page 04h
111 Reserved All 00h
112 Number of ECC bits 00h
113 Number of plane address bits 00h
114 Multi-plane operation attribute 00h
115~127 Reserved All 00h
128 I/O pin capacitance, maximum 08h
129~132 Reserved All 00h
133~134 Maximum page program time (μs) 84h,03h
135~136 Maximum block erase time (μs) 10h,27h
137~138 Maximum page read time (μs) 64h,00h
139~163 Reserved All 00h
164~165 Vendor specified revision number 00h,00h
166~253 Vendor specific All 00h
254~255 Integrity CRC Set at test
256~511 Value of bytes 0~255
512~767 Value of bytes 0~255
768+ Reserved

Datasheet
FM25S01A 3.3V 1G-BIT SPI NAND FLASH MEMORY Ver.1.0 33
11. Error Management
This NAND Flash device is specified to have the minimum number of valid blocks (NVB) of the
total available blocks per die shown in the table below. This means the devices may have blocks
that are invalid when shipped from the factory. An invalid block is one that contains at least one
page that has more bad bits than can be corrected by the minimum required ECC. Additional bad
blocks may develop with use. However, the total number of available blocks will not fall below
NVB during the endurance life of the product.

Although NAND Flash memory devices may contain bad blocks, they can be used reliably in
systems that provide bad-block management and error-correction algorithms. This ensures data
integrity.

Internal circuitry isolates each block from other blocks, so the presence of a bad block does not
affect the operation of the rest of the NAND Flash array.

NAND Flash devices are shipped from the factory erased. The factory identifies invalid blocks
before shipping by attempting to program the bad-block mark into every location in the first and
second page of each invalid block. It may not be possible to program every location in an invalid
block with the bad-block mark. However, the first spare area location (800h) in each bad block is
guaranteed to contain the bad-block mark. This method is compliant with ONFI factory defect
mapping requirements. See the following table for the bad-block mark.

System software should initially check the first spare area location (800h) for non-FFh data on the
page 0 and page 1 of each block prior to performing any program or erase operations on the
NAND Flash device. A bad-block table can then be created, enabling system software to map
around these areas. Factory testing is performed under worst-case conditions. Because invalid
blocks may be marginal, it may not be possible to recover the bad-block marking if the block is
erased.

Table 13 Error Management Details

Description Requirement
Minimum number of valid blocks (NVB) 1004
Total available blocks per die 1024
First spare area location Column 2048 of page 0 and page 1
Bad-block mark Non FFh

Datasheet
FM25S01A 3.3V 1G-BIT SPI NAND FLASH MEMORY Ver.1.0 34
12. ECC Protection
The device offers data corruption protection by offering optional internal ECC. READs and
PROGRAMs with internal ECC can be enabled or disabled by setting feature bit ECC_E. ECC is
enabled after device power up, so the default READ and PROGRAM commands operate with
internal ECC in the active state.

To enable/disable ECC, perform the following command sequence:

 Issue the SET FEATURE command (1FH).
 Set the feature bit ECC_E as you want:
1. To enable ECC, Set ECC_E to 1.
2. To disable ECC, Clear ECC_E to 0.

During a PROGRAM operation, the device calculates an ECC code on the 2k page in the cache
register, before the page is written to the NAND Flash array.

During a READ operation, the page data is read from the array to the cache register, where the
ECC code is calculated and compared with the ECC code value read from the array. If error bits
are detected, the error is corrected in the cache register. Only corrected data is output on the I/O
bus. The ECC status bit indicates whether or not the error correction was successful. The ECC
Protection table below shows the ECC protection scheme used throughout a page.

The device will automatically read first page of first block to cache after power on, then host can
directly read data from cache for easy boot. Also the data is promise correctly by internal ECC.

With internal ECC, the user must accommodate the following:

 Spare area definitions provided in the ECC Protection table below.
 ECC can protect according main and spare areas. WRITEs to the ECC area are ignored.

Table 14 ECC Protection and Spare Area

Min Byte Max Byte ECC Number
Area Description
Address Address Protected Of Bytes
000H 1FFH Yes 512 Main 0 User data 0
200H 3FFH Yes 512 Main 1 User data 1
400H 5FFH Yes 512 Main 2 User data 2
600H 7FFH Yes 512 Main 3 User data 3
800H 80FH Yes 16 Spare 0 User meta data 0
810H 81FH Yes 16 Spare 1 User meta data 1
820H 82FH Yes 16 Spare 2 User meta data 2
830H 83FH Yes 16 Spare 3 User meta data 3
NOTE:
1. Spare 800h byte is for bad block marker
2. Spare area 800H to 83FH is all available for user. ECC parity codes are programmed in
additional space and not user accessible.

Datasheet
FM25S01A 3.3V 1G-BIT SPI NAND FLASH MEMORY Ver.1.0 35
13. Electrical Characteristics
13.1. Absolute Maximum Ratings
Table 15 Absolute Maximum Ratings
Operating Temperature -40°C to +85°C
Storage Temperature -65°C to +150°C
Voltage on I/O Pin with Respect to Ground -0.5V to 4.0V
VCC -0.5V to 4.0V
Note: Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the
device. This is a stress rating only and functional operation of the device at these or any other conditions beyond
those indicated in the operational sections of this specification are not implied. Exposure to absolute maximum
rating conditions for extended periods may affect device reliability.

13.2. Pin Capacitance

Table 16 Pin Capacitance
Applicable over recommended operating range from: TA = 25°C
Symbol Test Condition Max Units Conditions
CIN(1) Input Capacitance 8 pF VIN = 0V
COUT(1) Output Capacitance 8 pF VOUT = 0V
Note: 1. characterized and is not 100% tested.

13.3. Power-up Timing

Figure 30 Power-On Timing

VCC
VCC (max)
Program,Erase and Write Instructions are lgnored
CS# Must Track VCC

VCC (min)
tVSL tRES

Power on sequence Device is Fully

Reset
State
Accessible

VRST

Datasheet
FM25S01A 3.3V 1G-BIT SPI NAND FLASH MEMORY Ver.1.0 36
 Table 17 Power-On Timing and Write Inhibit Threshold
SPEC
PARAMETER SYMBOL UNIT
MIN MAX
VCC (min) to CS# Low tVSL 1 ms
Power on sequence tRES 1 ms
Write Inhibit Voltage VWI 2.5 V
Chip Reset Voltage VRST 2.3 V

13.4. DC Electrical Characteristics

Table 18 DC Characteristics
Applicable over recommended operating range from: TA = -40°C to 85°C, VCC = 2.7V to 3.6V (unless
otherwise noted).
SPEC
SYMBOL PARAMETER CONDITIONS UNIT
MIN TYP MAX
VCC Power supply 2.7 3.6 V
ILI Input Leakage Current ±10 µA
ILO Output Leakage Current ±10 µA
VCC= VCCmax, CS# =
ISB1 Standby Current VCC, 10 50 µA
VIN = VSS or VCC
FCLK=104MHz,
ICC1 CS#=VIL, Iout=0mA， 16 20 mA
Operating Current Page Read
ICC2 Program 16 20 mA
ICC3 Erase 16 20 mA
VIL(1) Input Low Voltage -0.3 0.2VCC V
VIH(1) Input High Voltage 0.7VCC VCC+0.3 V
VOL Output Low Voltage IOL = 1mA 0.15Vcc V
VOH Output High Voltage IOH = -20 µA 0.7VCC V
Notes:
1. VIL min and VIH max are reference only and are not tested.

Datasheet
FM25S01A 3.3V 1G-BIT SPI NAND FLASH MEMORY Ver.1.0 37
13.5. AC Measurement Conditions
Table 19 AC Measurement Conditions
SPEC
SYMBOL PARAMETER UNIT
MIN MAX
CL Load Capacitance 15 pF
TR, TF Input Rise and Fall Times 5 ns
VIN Input Pulse Voltages 0.2 VCC to 0.8 VCC V
IN Input Timing Reference Voltages 0.3 VCC to 0.7 VCC V
OUT Output Timing Reference Voltages 0.5VCC V

Figure 31 AC Measurement I/O Waveform

Input Levels Input Timing Reference Level Output Timing Reference Level
0.8 Vcc
0.7 Vcc AC
Measurement 0.5 Vcc
0.3 Vcc Level
0.2 Vcc

13.6. AC Electrical Characteristics

Table 20 AC Characteristics
Applicable over recommended operating range from: TA = -40°C to 85°C, VCC = 2.7V to 3.6V, (unless
otherwise noted).
SPEC
SYMBOL PARAMETER UNIT
MIN TYP MAX
FC Serial Clock Frequency for all other instructions 104 MHz
FR Serial Clock Frequency for BB,EB command 40 MHz
tCH1(1) Serial Clock High Time 4.5 ns
tCL1(1) Serial Clock Low Time 4.5 ns
tCLCH(2) Serial Clock Rise Time (Slew Rate) 0.1 V/ns
tCHCL(2) Serial Clock Fall Time (Slew Rate) 0.1 V/ns
tSLCH CS# Active Setup Time 4.5 ns
tCHSH CS# Active Hold Time 4.5 ns
tSHCH CS# Not Active Setup Time 4.5 ns
tCHSL CS# Not Active Hold Time 4.5 ns
tSHSL/tCS CS# High Time 80 ns
tSHQZ(2) Output Disable Time 20 ns
tCLQX Output Hold Time 1.5 ns
tDVCH Data In Setup Time 2 ns
tCHDX Data In Hold Time 3 ns
tHLCH HOLD# Low Setup Time ( relative to CLK ) 4.5 ns
tHHCH HOLD# High Setup Time ( relative to CLK ) 4.5 ns
tCHHH HOLD# Low Hold Time ( relative to CLK ) 4.5 ns
tCHHL HOLD# High Hold Time ( relative to CLK ) 4.5 ns
tHLQZ(2) HOLD# Low to High-Z Output 7 ns
Datasheet
FM25S01A 3.3V 1G-BIT SPI NAND FLASH MEMORY Ver.1.0 38
 SPEC
SYMBOL PARAMETER UNIT
MIN TYP MAX
tHHQX(2) HOLD# High to Low-Z Output 7 ns
tCLQV Output Valid from CLK 8 ns
tWHSL WP# Setup Time before CS# Low 20 ns
tSHWL WP# Hold Time after CS# High 100 ns
5/5/10
tRST Resetting time during Idle/Read/Program/Erase µs
/500
Notes:
1. TCH1+TCL1 >= 1 / FC ;
2. Characterized and not 100% tested.

Table 21 Performance Timing

SPEC
SYMBOL PARAMETER UNIT
MIN TYP MAX
Page Read From Array (with ECC) 100
tRD µs
Page Read From Array (without ECC) 25
tPROG Page Program 400 900 µs
tPOTP OTP Page Program 800 2000 µs
tERS Block Erase 4 10 ms

Figure 32 Serial Output Timing

CS#
tCH
CLK
tCLQV tCLQV tCL tSHQZ
tCLQX tCLQX
I/O
LSB OUT

Figure 33 Serial Input Timing

tSHSL
CS#
tCHSL tCHSH tSHCH
tSLCH
CLK
tDVCH
tCHDX tCLCH tCHCL
I/O
INPUT MSB IN LSB IN

I/O (High Impedance)

OUTPUT

Datasheet
FM25S01A 3.3V 1G-BIT SPI NAND FLASH MEMORY Ver.1.0 39
 Figure 34 Hold Timing
CS#

tHLCH
tCHHL tHHCH

CLK
tCHHH
tHLQZ
tHHQX
I/O
OUTPUT

I/O
INPUT

HOLD#

Figure 35 WP Timing

CS#
tWHSL tSHWL

WP#

Datasheet
FM25S01A 3.3V 1G-BIT SPI NAND FLASH MEMORY Ver.1.0 40
14. Ordering Information
FM 25S 01A -XXX -C -H
Company Prefix
FM = Fudan Microelectronics Group Co.,ltd

Product Family
25S = 3.3V SPI NAND Flash

Product Density
01A = 1G-bit (Page Size 2112-Byte)

Package Type
DND = WSON8 8x6mm (TDFN8 8x6mm)

Product Carrier

A = Tray

HSF ID Code
G = RoHS Compliant, Halogen-free, Antimony-free

Datasheet
FM25S01A 3.3V 1G-BIT SPI NAND FLASH MEMORY Ver.1.0 41
15. Part Marking Scheme
WSON8 8x6mm (TDFN8 8x6mm)

FM25S01A
YYWWALH

FM25S01A
Product Density

YYWWALH
HSF ID Code
G = RoHS Compliant, Halogen-free, Antimony-free
Package Lot Number (just with 0~9, A~Z)
Assembly’s Code
Work week during which the product was molded (eg..week 12)
The last two digits of the year in which the product was sealed/molded

Datasheet
FM25S01A 3.3V 1G-BIT SPI NAND FLASH MEMORY Ver.1.0 42
16. Packaging Information
WSON8 8x6mm (TDFN8 8x6mm)

Symbol MIN MAX

e 1.270 BSC
D 7.900 8.100
E 5.900 6.100
L 0.450 0.550
A 0.700 0.800
A1 0.000 0.050
C 0.180 0.250
b 0.350 0.450
D2 3.300 3.500
E2 4.200 4.400

Note:
1. Dimensions are in Millimeters.

Datasheet
FM25S01A 3.3V 1G-BIT SPI NAND FLASH MEMORY Ver.1.0 43
17. Revision History
Publication Paragraph or
Version Pages Revise Description
date Illustration
preliminary Aug. 2018 45 Initial Document Release
1. Updated the Part Marking Scheme.
1.0 Apr. 2019 45
2. Corrected the typo

Datasheet
FM25S01A 3.3V 1G-BIT SPI NAND FLASH MEMORY Ver.1.0 44
Sales and Service
Shanghai Fudan Microelectronics Group Co., Ltd.
Address: Bldg No. 4, 127 Guotai Rd,
Shanghai City China.
Postcode: 200433
Tel: (86-021) 6565 5050
Fax: (86-021) 6565 9115
Shanghai Fudan Microelectronics (HK) Co., Ltd.
Address: Unit 506, 5/F., East Ocean Centre, 98 Granville Road, Tsimshatsui
East, Kowloon, Hong Kong
Tel: (852) 2116 3288 2116 3338
Fax: (852) 2116 0882
Beijing Office
Address: Room 423, Bldg B, Gehua Building,
1 QingLong Hutong, Dongzhimen Alley north Street,
Dongcheng District, Beijing City, China.
Postcode: 100007
Tel: (86-010) 8418 6608
Fax: (86-010) 8418 6211
Shenzhen Office
Address: Room.1301, Century Bldg, No. 4002, Shengtingyuan Hotel, Huaqiang Rd
(North),
Shenzhen City, China.
Postcode: 518028
Tel: (86-0755) 8335 0911 8335 1011 8335 2011 8335 0611
Fax: (86-0755) 8335 9011
Shanghai Fudan Microelectronics (HK) Ltd Taiwan Representative
Office
Address: Unit 1225, 12F., No 252, Sec.1 Neihu Rd., Neihu Dist., Taipei City
114, Taiwan
Tel : (886-2) 7721 1889 (886-2) 7721 1890
Fax: (886-2) 7722 3888

Shanghai Fudan Microelectronics (HK) Ltd Singapore Branch Office

Address: 47 Kallang Pudding Road, #08-06
The Crescent @ Kallang, Singapore 349318
Tel: +65 64430860
Fax: +65 64431215
Email: [email protected]

Fudan Microelectronics (USA) Inc.

Address: 97 E Brokaw Road, Suite 320,San Jose,CA 95112
Tel: (+1)408-335-6936
Contact name: Xinyue Huang
Email: [email protected]

Web Site: http://www.fmsh.com/

Datasheet
FM25S01A 3.3V 1G-BIT SPI NAND FLASH MEMORY Ver.1.0 45