Analog Circuits

Day-8
Frequency Response of Common Source Amplifier:
• Let us consider a typical common source amplifier as shown in the above
figure
From above figure, it shows the high frequency equivalent circuit for
the given amplifier circuit. It shows that at high frequencies coupling
and bypass capacitors act as short circuits and do not affect the
amplifier high frequency response. The equivalent circuit shows
internal capacitances which affect the high frequency response.

Using Miller theorem, this high frequency equivalent circuit can be

further simplified as follows:
• The internal capacitance Cgd can be splitted into
Cin(miller) and Cout(miller) as shown in the following figure.
Where,
From simplified high frequency equivalent circuit, it has two
RC networks which affect the high frequency response of the
amplifier. These are,

· Input RC network
· Output RC network
• Input RC network:
From above figure,
• This network is further reduced as follows since Rs<<
RG
The critical frequency for the reduced input RC network is,
Output RC network:
 The critical frequency for the above circuit is,

It is not necessary that these frequencies should be equal.

The network which has lower critical frequency than other
network is called dominant network.
The phase shift in high frequency is
Problem:
Determine the high frequency response of the amplifier circuit
shown in the following figure.
Solution:
Before calculating critical frequencies it is necessary to calculate mid
frequency gain of the given amplifier circuit. This is required to calculate
Cin(miller) and Cout(miller).
Av = -gmRD

Here RD should
be replaced by
RD || RL
Cgs = Ciss – Crss = 4pF

Now analyze the input and output network for critical frequency,
• The above analysis shows that the output network produces the dominant
higher critical frequency. High frequency response of the given amplifier
is shown in the following figure
 4.4 FET as amplifier
• Field Effect Transistor (FET) amplifiers provide an excellent voltage gain and
high input impedance. Because of high input impedance and other
characteristics of JFETs they are preferred over BJTs for certain types of
applications.
• There are 3 basic FET circuit configurations:
• i)Common Source ii)Common Drain iii)Common Gain
• Similar to BJT CE,CC and CB circuits, only difference is in BJT large output
collector current is controlled by small input base current whereas FET
controls output current by means of small input voltage. In both the cases
output current is controlled variable.
• FET amplifier circuits use voltage controlled nature of the JFET. In Pinch off
region, ID depends only on VGS.
Common Source(CS) Amplifier
• Voltage Gain
• Source resistance (RS) is used to set the Q-Point but is bypassed by CS
for mid-frequency operation. From the small signal equivalent circuit
,the output voltage
• VO = -RDµVgs(RD + rd)
• Where Vgs = Vi , the input voltage, Hence, the voltage gain,
• AV = VO / Vi = -RDµ(RD + rd)
Input Impedance
• From Fig. (b) Input Impedance is Zi = RG
• For voltage divider bias as in CE Amplifiers of BJT
• RG = R1 ║ R2
Output Impedance
• Output impedance is the impedance measured at the output terminals with the
input voltage VI = 0 From the Fig. 5.1(b) when the input voltage Vi = 0,
• Vgs = 0 and hence
• µ Vgs = 0
•
The equivalent circuit for calculating output impedance is given in Fig. 5.2.
Output impedance Zo = rd ║ RD
• Normally rd will be far greater than RD . Hence Zo ≈ RD
 Common Drain Amplifier
A simple common drain amplifier is shown in Fig. 5.2(a) and associated small signal equivalent
circuit using the voltage source model of FET is shown in Fig. 5.2(b).Since voltage Vgd is more easily
A simple common drain amplifier is shown in Fig. (a) and associated small signal
determined circuit
equivalent than Vgs,using
the voltage source insource
the voltage the output circuit
model ofisFET
expressed in terms
is shown in of Vgs (b).Since
Fig. and
voltage Vgd is more easily determined than Vgs, the voltage source in the output
Thevenin’s theorem.
circuit is expressed in terms of Vgs and Thevenin’s theorem.
Voltage Gain
• The output voltage,
• VO = RSµVgd / (µ + 1) RS + rd Where Vgd = Vi the input voltage.
Hence, the voltage gain,
• Av = VO / Vi = RSµ / [(µ + 1) RS + rd]
Input Impedance
• From Fig. (b), Input Impedance Zi = RG
• Output Impedance
• From Fig. (b), Output impedance measured at the output terminals
with input voltage Vi = 0 can be calculated from the following
equivalent circuit.
• As Vi = 0: Vgd = 0: µvgd / (µ + 1) = 0 Output Impedance
•
ZO = rd / (µ + 1) ║RS
• When µ » 1
• ZO = ( rd / µ) ║RS = (1/gm) ║RS
JFET AS A VVR OR VDR

• Let us consider the drain characteristics of FET as shown in the fig.

• In this characteristics we can see that in the region before pinch off
voltage, drain characteristics are linear, i.e. FET operation is linear. In this
region the FET is useful as a voltage controlled resistor, i.e. the drain to
source resistance is controlled by the bias voltage VGS.( In this region
only FET behaves like an ordinary resistor This resistances can be varied
by VGS ) .The operation of FET in the region is useful in most linear
applications of FET.In such an application the FET is also referred to as a
voltage variable resistor (VVR) or voltage dependent resistor (VDR).
Previous Year GATE Questions with Solutions
• Problem 3:

The ‘Pinch – off’ voltage of a JFET is 5.0 volts. Its ‘cut – off’ voltage is
(a) (5.0)1/2 V

(b)2.5 V

(c) 5.0 V

(d)(5.0)3/2 V
Solution:

Given,
Pinch – off voltage (VP) = 5 V
We know
|𝑽𝑮𝑺 (𝒐𝒇𝒇)| = |𝑽𝑷|
So cut – off voltage = 5 V
Option (c)
58. The parameters of a FET are gm = 3 mA/V, rd = 30k. RL = 3k as a source follower load. The output
impedance is given by

1. 333 Ω 2. 3 kΩ 3. 2.7 Ω 4. 300Ω

1
The output impedance of Source follower load is given as 𝑅𝑜 = || r || RL
gm d

1 1 1
= gm + +
𝑅𝑜 rd RL

1 1 1 90+1+10 101
=3+ + = =
𝑅𝑜 30 3 30 30

30k
∴ 𝑅𝑜 =
101

= 297 Ω

≈ 300 Ω
62. A common-source FET amplifier has a load resistance RL = 500 kΩ. rd = 100 kΩ & µ = 24,
where µ = gmrD . The voltage gain is

1. -25 2. 25
3. 20 4. -20

µRL
Av =
( RL + rd)

24 ×500 ×103 24 ×500 ×103

= =
500 ×103+100 ×103 600 ×103

24 ×5
=
6

∴ Av = 20
63. A JFET (with tuned load in the drain circuit) is operated as a tuned amplifier. Given for the FET 𝐠 𝐦
= 3×10-3 , 𝐫𝐝 = 60 kΩ , 𝐂𝐝𝐬 = 10 pF and for the drain circuit L = 10 mH in parallel with R = 80 kΩ , C
= 90 pF , 𝐑 𝐃 = 30 kΩ.

The magnitude of voltage gain of the amplifier at resonance is _____.

The voltage gain of the circuit of resonance frequency

|AV | = g m ( rd || R D || R )

=3×10−3 ( 60k || 30k || 80k )

⇒ |AV | = 48
66. A FET is a better chopper than a BJT because it has

1. Lower off-set voltage 2. Higher series ON resistance

3. Lower input current 4. Higher input impedance

To turn on BJT a minimum of 0.7V is required but in FET there is no such type of Offset Voltage.
So FET acts like a better chopper than a BJT.
Answer: 1
17. The input voltage to the gate of the FET amplifier is 5V. The output voltage of the circuit is ____ Volt.

Applying KVL to the input circuit,

The voltage drop across the 1K resistor is = 5 - 2 - VT = 2 V
Thus, ID = 2 mA.
Vout = 10 - 2k × 2 mA = 6 V.
6. The enhancement type MOSFET in the circuit below operates according to the square law. μnCox =
100 μA/V2, the threshold voltage (VT) is 500 mV. Ignore channel length modulation. The output
voltage Vout is

1. 100 mV 2. 500 mV
3. 600 mV 4. 2 V
Given that, μnCox = 100 μA/V2

Threshold voltage (VT) = 500 mV = 0.5 V

VGS = Vout

VDS(sat) = VGS - Vth = Vout – 0.5 = VDS – 0.5

⇒ VDS = VDS(sat) + 0.5 ⇒ VDS > VDS(sat)

So, the transistor is operating in saturation region.
We know that,
𝜔
ID=0.5 μxCox ( )(VGS − VT)2
𝐿

⇒5×10−6 = 0.5×100×10−6×10×(VGS −0.5)2

1
⇒(VGS −0.5)2 =
100

1
⇒ VGS −0.5 = = 0.1
10

⇒ VGS = 0.6 = 600 mV = Vout

55. Find the magnitude of voltage gain of the circuit.

𝒈𝒎 𝑹𝑫 𝒈𝒎 𝑹𝑷
1. 𝟏+ 𝒈𝟏 2. 𝟏+ 𝒈𝟏
𝒎𝟐 𝑹𝑷 𝒎𝟐 𝑹𝑫

𝒈𝒎 𝑹𝑷 𝒈𝒎𝟏 𝑹𝑫 𝒈𝒎𝟐 𝑹𝑷
3. 𝟏+ 𝒈𝟐 4.
𝒎𝟏 𝑹𝑫 𝟏+ 𝒈𝒎𝟐 𝑹𝑷

Sol: Apply ac analysis then the given figure becomes,

Small signal equivalent model for the above figure is
Apply KVL at above transistor we get, Vout = −gm2 Vgs RD = − gm2 RD (0 − VS ) ------------(1)
Now apply KCL at below transistor we get,

VS 1
gm2 (0 − VS ) = gm1 Vin + ⇒ VS (gm2 + ) + gm1 Vin = 0 -------------(2)
Rp Rp
from (1) and (2 ) get

−g Vin
Vout = (gm2 RD ) × m1
gm2 + 1
Rp

V
∴ 𝐴V = | out| = 1
𝑔𝑚 𝑅𝐷 𝑔𝑚2 𝑅𝑃
Vin 1+ 𝑔𝑚2 𝑅𝑃

Answer: 4
Problem 2:
• Consider long channel N MOS transistor with source and body
connected together.
Assume that the electron mobility is dependent of VGS and VDS.
Given,
Solution:
Problem 4:
Solution:
Problem 5:
Solution:
Problem 6:
Solution:
Problem 8:
Solution:
Problem 10:
Solution:
Problem 11:
Solution:
Problem 12:
Solution:
Problem 13:
Solution:
Problem 15:
Solution:
Problem 16:
Solution:
Problem 17:
Solution:
Problem 18:
Solution:
Problem 19:
Solution:
End of Presentation