Microprocessor and Microcontroller in
Industrial Systems
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D32T001M20
8051 Microcontroller
Microprocessor Based System
CPU
External RAM, ROM, I/O
(No internal RAM, ROM, I/O ports in the CPU)
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Microcontroller
A smaller computer on a CHIP
On-chip RAM, ROM, I/O Ports, Timer, Serial Controller…
Example: Motorola’s 6811, Intel’s 8051, Atmel 32
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Microprocessor vs. Microcontroller
Microprocessor Microcontroller
CPU is stand-alone, RAM, ROM, CPU, RAM, ROM, I/O and timer are
I/O, timer are separate all on a single chip
Designer can decide on the Fixed amount of on-chip ROM,
amount of ROM, RAM and I/O RAM, I/O ports
ports.
Not Expansive
Expansive
Single-purpose
Versatility
Special Purpose.
General-purpose
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C based Embedded Systems
Special purpose computer system usually completely inside the device it
controls
Has specific requirements and performs pre-defined tasks
Cost reduction compared to general purpose processor
Different design criteria
◦ Performance
◦ Reliability
◦ Availability
◦ Safety
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Embedded Systems Examples
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Examples
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Harvard Architecture
In Harvard Architecture the data and instructions are stored
in separate memory units each with their own bus.
Advantages:
Speeding up the data transfer rate,
Permits the designer to implement different bus widths and
word sizes for program and data memory space.
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8051 CPU Operation
1. Features
2. Pin Diagram
3. Block Diagram
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8051 Microcontroller
Intel introduced 8051, referred as MCS- 51, in 1981.
The 8051 is an 8-bit processor
◦ The CPU can work on only 8 bits of data at a time
The 8051 became widely popular after allowing other
manufactures to make and market any flavor of the 8051.
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Features of 8051
8 bit Processor
4KB Internal ROM
128 Bytes Internal RAM
Four 8 BIT I/O PORTS (32 I/O LINES)
Two 16 Bit Timers/Counters
On Chip Full Duplex UART for Serial Communication
5 Vector Interrupts ( 2 External, 3 Internal - Timer0,Timer1,Serial)
On Chip Clock Oscillator
16 bit Address bus
64k External Code Memory
64k External Data Memory
16-bit program counter to access external Code Memory and
16 bit Data Pointer to access external Data Memory
128 user defined flags
32 General Purpose Registers each of 8 bits
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8051 Family
The 8051 is a subset of the 8052
The 8031 is a ROM-less 8051
◦ Add external ROM to it
◦ You lose two ports, and leave only 2 ports for I/O operations
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Pin Diagram
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Block Diagram of 8051
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Separate read instructions for external data and code memory.
Internal code
External data memory
Memory
RAM
ROM or EPROM
64k
4k or up
0xFF
SFR(direct access)
128 bytes External code memory
ROM or EPROMext
64k
0x80
0x7F
General purpose RAM
(variable data) 80 bytes
0x30
0x2F
Bit addressible RAM 16 bytes
16x8 bits
0x20
0x1F Register bank 0(R0-R7)
Register bank 1(R0-R7) 4x8=
32 bytes
Register bank 2(R0-R7)
0x00 Register bank 3(R0-R7)
Internal data memory
RAM
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Pin Description of the 8051
8051 family members (e.g., 8751, 89C51, 89C52, DS89C4x0)
◦ Have 40 pins dedicated for various functions such as I/O, RD, WR, address,
data, and interrupts.
◦ Come in different packages, such as
◦ DIP(dual in-line package),
◦ QFP(quad flat package), and
◦ LLC(leadless chip carrier)
Some companies provide a 20-pin version of the 8051 with a reduced
number of I/O ports for less demanding applications
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XTAL1 and XTAL2
The 8051 has an on-chip oscillator but requires an external crystal to
run it
◦ A quartz crystal oscillator is connected to inputs XTAL1 (pin19) and XTAL2
(pin18)
◦ The quartz crystal oscillator also needs two capacitors of 30 pF value
◦ The original 8051 operates at 12 MHZ
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XTAL1 and XTAL2 …..
If you use a frequency source other than a crystal oscillator, such as a
TTL oscillator:
◦ It will be connected to XTAL1
◦ XTAL2 is left unconnected
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RST
RESET pin is an input and is active high (normally low)
Upon applying a high pulse to this pin, the microcontroller will reset and
terminate all activities
This is often referred to as a power-on reset
Activating a power-on reset will cause all values in the registers to be
lost
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EA’
EA’, “external access’’, is an input pin and must be connected to Vcc or
GND
The 8051 family members all come with on-chip ROM to store programs
and also have an external code and data memory.
Normally EA pin is connected to Vcc (Internal Access)
EA pin must be connected to GND to indicate that the code or data is
stored externally.
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PSEN’ and ALE
PSEN, “program store enable’’, is an output pin
This pin is connected to the OE pin of the external memory.
For External Code Memory, PSEN’ = 0
For External Data Memory, PSEN’ = 1
ALE pin is used for demultiplexing the address and data.
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I/O Port Pins
The four 8-bit I/O ports P0, P1, P2 and P3 each
uses 8 pins.
All the ports upon RESET are configured as
output, ready to be used as input ports by the
external device.
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Port 0
Port 0 is also designated as AD0-AD7.
When connecting an 8051 to an external memory, port
0 provides both address and data.
The 8051 multiplexes address and data through port 0
to save pins.
ALE indicates if P0 has address or data.
◦ When ALE=0, it provides data D0-D7
◦ When ALE=1, it has address A0-A7
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Port 1 and Port 2
In 8051-based systems with no external memory
connection:
◦ Both P1 and P2 are used as simple I/O.
In 8051-based systems with external memory
connections:
◦ Port 2 must be used along with P0 to provide the 16-bit
address for the external memory.
◦ P0 provides the lower 8 bits via A0 – A7.
◦ P2 is used for the upper 8 bits of the 16-bit address,
designated as A8 – A15, and it cannot be used for I/O.
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Port 3
Port 3 can be used as input or output.
Port 3 has the additional function of providing
some extremely important signals
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PIN TYPE NAME AND FUNCTION
Vss
Vcc
Pin Description
I
I
Summary
Ground: 0 V reference.
Power Supply: This is the power supply voltage for normal,
idle, and power-down operation.
P0.0 - P0.7 I/O Port 0: Port 0 is an open-drain, bi-directional I/O port. Port
0 is also the multiplexed low-order address and data bus
during accesses to external program and data memory.
P1.0 - P1.7 I/O Port 1: Port I is an 8-bit bi-directional I/O port.
P2.0 - P2.7 I/O Port 2: Port 2 is an 8-bit bidirectional I/O. Port 2 emits the
high order address byte during fetches from external
program memory and during accesses to external data
memory that use 16 bit addresses.
P3.0 - P3.7 I/O Port 3: Port 3 is an 8 bit bidirectional I/O port. Port 3 also
serves special features as explained.
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PIN TYPE NAME AND FUNCTION
RST I Reset: A high on this pin for two machine cycles while the
ALE
Pin O
Description Summary
oscillator is running, resets the device.
Address Latch Enable: Output pulse for latching the low byte
of the address during an access to external memory.
PSEN* O Program Store Enable: The read strobe to external program
memory. When executing code from the external program
memory, PSEN* is activated twice each machine cycle,
except that two PSEN* activations are skipped during
each access to external data memory.
EA*/VPP I External Access Enable/Programming Supply Voltage: EA*
must be externally held low to enable the device to fetch
code from external program memory locations. If EA* Is
held high, the device executes from internal program
memory. This pin also receives the programming supply
voltage Vpp during Flash programming. (applies for 89c5x
MCU's)
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General Block Diagram of 8051
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Detailed Block Diagram
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SURESH.P.NAIR , HOD - ECE , RCET
Thank You…
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