Control System Analysis/ Closed Loop Analysis of PLL

Phase locked loops can also be analyzed as control systems by applying the
Laplace transform.

The loop response can be written as:

Where

 θo is the output phase in radians

 θi is the input phase in radians

 Kp is the phase detector gain in volts per radian

 Kv is the VCO gain in radians per volt-second

 F(s) is the loop filter transfer function (dimensionless)

The loop characteristics can be controlled by inserting different types of loop

filters. The simplest filter is a one-pole RC circuit. The loop transfer function in
this case is:

The loop response becomes:

This is the form of a classic harmonic oscillator. The denominator can be related to
that of a second order system:

Where

ζ is the damping factor

ωn is the natural frequency of the loop.

For the one-pole RC filter,

The loop natural frequency is a measure of the response time of the loop, and the
damping factor is a measure of the overshoot and ringing. Ideally, the natural
frequency should be high and the damping factor should be near 0.707 (critical
damping). With a single pole filter, it is not possible to control the loop frequency
and damping factor independently. For the case of critical damping,

A slightly more effective filter, the lag-lead filter includes one pole and one zero.
This can be realized with two resistors and one capacitor. The transfer function for
this filter is
This filter has two time constants

τ1 = C(R1 + R2) τ2

=CR2

Substituting above yields the following natural frequency and damping factor

The loop filter components can be calculated independently for a given natural
frequency and damping factor

Real world loop filter design can be much more complex eg using higher order
filters to reduce various types or source of phase noise.

Applications of PLL:

The PLL principle has been used in applications such as

 FM stereo decoders

 motor speed control

 tracking filters

 FM modulation and demodulation

 FSK modulation

 Frequency multiplier
 Frequency synthesis etc.,

Example PLL ICs:560 series (560, 561, 562, 564, 565 & 567)

Operation of Basic Phase Locked Loop

The PLL consists of i) Phase detector ii) LPF iii) VCO. The phase detector or
comparator compares the input frequency fIN with feedback frequency fOUT.

 The output of the phase detector is proportional to the phase difference

between fIN & fOUT. The output of the phase detector is a dc voltage & therefore
is often referred to as the error voltage.

 The output of the phase detector is then applied to the LPF, which removes the
high frequency noise and produces a dc level. This dc level in turn, is input to the
VCO.

 The output frequency of VCO is directly proportional to the dc level. The

VCO frequency is compared with input frequency and adjusted until it is equal to
the input frequencies.

 PLL goes through 3 states, i) free running ii) Capture iii) Phase lock.

Before the input is applied, the PLL is in free running state. Once the input
frequency is applied the VCO frequency starts to change and PLL is said to be in
the capture mode. The VCO frequency continuous to change until it equals the
input frequency and the PLL is in phase lock mode. When Phase locked, the loop
tracks any change in the input frequency through its repetitive action.

If an input signal vs of frequency fs is applied to the PLL, the phase detector

compares the phase and frequency of the incoming signal to that of the output vo
of the VCO. If the two signals differ in frequency of the incoming signal to that of
the output vo of the VCO.

The phase detector is basically a multiplier and produces the sum (f s + fo) and
difference (fs - fo) components at its output.

The high frequency component (fs + fo) is removed by the low pass filter and the
difference frequency component is amplified then applied as control voltage vc to
VCO.

The signal vc shifts the VCO frequency in a direction to reduce the frequency
difference between fs and fo. Once this action starts, we say that the signal is in the
capture range. The VCO continues to change frequency till its output frequency is
exactly the same as the input signal frequency. The circuit is then said to be locked.
Once locked, the output frequency fo of VCO is identical to fs except for a finite
phase difference φ. This phase difference φ generates a corrective control voltage
vc to shift the VCO frequency from f0 to fs and thereby maintain the lock. Once
locked, PLL tracks the frequency changes of the input signal. Thus, a PLL goes
through three stages (i) free running, (ii) capture and (iii) locked or tracking.

Capture range: the range of frequencies over which the PLL can acquire lock
with an input signal is called the capture range. This parameter is also expressed as
percentage of fo.

Pull-in time: the total time taken by the PLL to establish lock is called pull-in
time. This depends on the initial phase and frequency difference between the two
signals as well as on the overall loop gain and loop filter characteristics.
 Phase Detector

Digital EX-OR EDGE TRIGGER MONOLITHIC

Phase
Detectors

DEVICE EX-OR Gate RS Flip Flop Digital Phase detector

OUTPUT Non-Linear with slope Linear with slope Lock acquired between 0
180o 360o frequency to quadrature lock

Phase detector compares the input frequency and VCO frequency and generates
DC voltage i.e., proportional to the phase difference between the two frequencies.
Depending on whether the analog/digital phase detector is used, the PLL is called
either an analog/digital type respectively. Even though most monolithic PLL
integrated circuits use analog phase detectors.

Ex for Analog: Double-balanced mixer

Ex for Digital: Ex-OR, Edge trigger, monolithic Phase detector.

Ex-OR Phase Detector:

This uses an exclusive OR gate. The output of the Ex-OR gate is high only when
fIN or fOUT is high.

The DC output voltage of the Ex-OR phase detector is a function of the phase
difference between its two outputs. The maximum dc output voltage occurs when
the phase difference is Π radians or

180 degrees. The slope of the curve between 0 or Π radians is the conversion gain
kp of the phase detector for eg; if the Ex-OR gate uses a supply voltage V cc = 5V,
the conversion gain Kp is
Advantages of Edge Triggered Phase Detector over Ex-OR are

i) The dc output voltage is linear over 2Π radians or 360 degrees, but in Ex-OR it
is Π radians or 180 degrees.

ii) Better Capture, tracking & locking characteristics.

Edge triggered type of phase detector using RS Flip – Flop. It is formed from a pair
of cross coupled NOR gates.

RS FF is triggered, i.e., the output of the detector changes its logic state on the
positive edge of the inputs fIN & fOUT

Monolithic Phase detector:

• It consists of 2 digital phase detector, a charge pump and an amplifier.

• Phase detector 1 is used in applications that require zero frequency and phase
difference at lock.

• Phase detector 2, if quadrature lock is desired, when detector 1 is used in the

main loop, detector can also be used to indicate whether the main loop is in lock or
out of lock.

Low – Pass filter

The function of the LPF is to remove the high frequency components in the output
of the phase detector and to remove the high frequency noise. LPF controls the
characteristics of the phase locked loop. i.e., capture range, lock ranges, bandwidth

 Lock range(Tracking range):

The lock range is defined as the range of frequencies over which the PLL system
follows the changes in the input frequency fIN.

 Capture range:

Capture range is the frequency range in which the PLL acquires phase lock.
Capture range is always smaller than the lock range.

 Filter Bandwidth:

Filter Bandwidth is reduced, its response time increases. However reduced

Bandwidth reduces the capture range of the PLL. Reduced Bandwidth helps to
keep the loop in lock through momentary losses of signal and also minimizes
noise.

Voltage Controlled Oscillator (VCO):

The third section of PLL is the VCO; it generates an output frequency that is
directly proportional to its input voltage. The maximum output frequency of
NE/SE 566 is 500 Khz.

Feedback path and optional divider:

Most PLLs also include a divider between the oscillator and the feedback input to
the phase detector to produce a frequency synthesizer. A programmable divider is
particularly useful in radio Transmitter applications, since a large number of
transmit frequencies can be produced from a single stable, accurate, but expensive,
quartz crystal–controlled reference oscillator.

Some PLLs also include a divider between the reference clock and the reference
input to the phase detector. If this divider divides by M, it allows the VCO to
multiply the reference frequency by N / M. It might seem simpler to just feed the
PLL a lower frequency, but in some cases the reference frequency may be
constrained by other issues, and then the reference divider is useful.
Frequency multiplication in a sense can also be attained by locking the PLL to the
'N'th harmonic of the signal.

The equations governing a phase-locked loop with an analog multiplier as the

phase detector may be derived as follows. Let the input to the phase detector
be xc(t) and the output of the voltage- controlled oscillator (VCO) is xr(t) with
frequency ωr(t), then the output of the phase detector xm(t) is given by

xm(t) = xc(t) + xr(t)

the VCO frequency may be written as a function of the VCO input y(t) as

ω (t) = ω + g y(t)
r f v

where gv is the sensitivity of the VCO and is expressed in Hz / V.

Hence the VCO output takes the form

The loop filter receives this signal as input and produces an

output xf(t) = Ffilter(xm(t))

where Filter is the operator representing the loop filter transformation.

When the loop is closed, the output from the loop filter becomes the input to the
VCO thus

y(t) = xf(t) = Ffilter(xm(t))

We can deduce how the PLL reacts to a sinusoidal input signal:

xc(t) = Acsin(ωct).

The output of the phase detector then is:

ωm(t) = Acsin(ωct) Arcos(ωft +φ(t))

This can be rewritten into sum and difference components using trigonometric
identities:
As an approximation to the behaviour of the loop filter we may consider only the
difference frequency being passed with no phase change, which enables us to
derive a small-signal model of the phase-locked loop. If we can make ω f≈ ωc then
the sin (.)can be approximated by its argument resulting in: y(t)=x f(t)=-
AcAfφ(t)/ωdt. The phase-locked loop is said to be locked if this is the case.

Voltage Controlled Oscillator:

Referring to the circuit in the above figure, the capacitor c1 is linearly charged or
discharged by a constant current source/sink. The amount of current can be
controlled by changing the voltage vc applied at the modulating input (pin 5) or by
changing the timing resistor R1 external to the IC chip. The voltage at pin 6 is held
at the same voltage as pin 5.

Thus, if the modulating voltage at pin 5 is increased, the voltage at pin 6 also
increases, resulting in less voltage across R 1 and thereby decreasing the charging
current.

The voltage across the capacitor C 1 is applied to the inverting input terminal of
Schmitt trigger via buffer amplifier. The output voltage swing of the Schmitt
trigger is designed to Vcc and 1.5 Vcc. If R a = Rb in the positive feedback loop, the
voltage at the non-inverting input terminal of Schmitt trigger swings from 0.5 Vcc
to 0.25 Vcc.

When the voltage on the capacitor c1 exceeds 0.5 Vcc during charging, the output
of the Schmitt trigger goes LOW (0.5 Vcc). The capacitor now discharges and
when it is at 0.25 Vcc, the output of Schmitt trigger goes HIGH (Vcc). Since the
source and sink currents are equal, capacitor charges and discharges for the same
amount of time. This gives a triangular voltage waveform across c1 which is also
available at pin 4.

The square wave output of the Schmitt trigger is inverted by buffer amplifier at pin
3. The output waveforms are shown near the pins 4 and 3.

The output frequency of the VCO can be given as follows:

where V+ is Vcc.

The output frequency of the VCO can be changed either by (i) R 1, (ii) c1 or (iii) the
voltage vc at the modulating input terminal pin 5. The voltage vc can be varied by
connecting a R1R2 circuit as shown in the figure below. The components R1and c1
are first selected so that VCO output frequency lies in the centre of the operating
frequency range.

Now the modulating input voltage is usually varied from 0.75 Vcc to Vcc which
can produce a frequency variation of about 10 to 1.

The signetics NE/SE 560 series is monolithic phase locked loops. The SE/NE 560,
561, 562, 564, 565 & 567 differ mainly in operating frequency range, poser supply
requirements & frequency & bandwidth adjustment ranges.

Monolithic Phase Locked Loops (PLL IC 565):

Pin Configuration of PLL IC 565

Basic Block Diagram Representation of IC 565

The important electrical characteristics of the 565 PLL are,

 Operating frequency range: 0.001Hz to 500 Khz.

 Operating voltage range: ±6 to ±12v

 Input level required for tracking: 10mv rms min to 3 Vpp max

 Input impedance: 10 K ohms typically.

 Output sink current: 1mA

 Output source current: 10 Ma

The center frequency of the PLL is determined by the free running frequency of
the VCO, which is given by

fOUT = 1.2/ 4R1C1

where R1&C1 are an external resistor & a capacitor connected to pins 8 & 9.

 The VCO free-running frequency fOUT is adjusted externally with R1 & C1

to be at the center of the input frequency range.

 C1 can be any value; R1 must have a value between 2 k ohms and 20 K ohms.

 Capacitor C2 connected between 7 & +V.

 The filter capacitor C2 should be large enough to eliminate variations in the

demodulated output voltage in order to stabilize the VCO frequency.

The lock range fL & capture range fc of PLL is given by,

∆fL= ±7.8 fout/ V Hz

Where fOUT = free running frequency of VCO (Hz)

V = (+Vcc)-(-Vcc) volts

∆fC= ±[ ∆fL/(2Π)(3.6)(103)C2 ]½

Monolithic PLL IC 565 applications:

The output from a PLL system can be obtained either as the voltage signal vc(t)
corresponding to the error voltage in the feedback loop, or as a frequency signal at
VCO output terminal. The voltage output is used in frequency discriminator
applications whereas the frequency output is used in signal conditioning, frequency
synthesis or clock recovery applications.

The circuit diagram of LM565 PLL

When PLL is locked to an input frequency, the error voltage vc(t) is proportional to
(fs-fo). If the input frequency is varied as in the case of FM signal vc will also vary
in order to maintain the lock. Thus the voltage output serves as a frequency
discriminator which converts the input frequency changes to voltage changes.

In the case of frequency output, if the input signal is comprised of many frequency
components corrupted with noise and other disturbances, the PLL can be made to
lock, selectively on one particular frequency component at the input. The output of
VCO would then regenerate that particular frequency (because of LPF which gives
output for beat frequency) and attenuate heavily other frequencies. VCO output
thus can be used for regenerating or reconditioning a desired frequency signal
(which is weak and buried in noise) out of many undesirable frequency signals.

Some of the typical applications of PLL are discussed below.

Frequency Multiplier:

Frequency divider is inserted between the VCO & phase comparator. Since the
output of the divider is locked to the fIN, VCO is actually running at a multiple of
the input frequency.

The desired amount of multiplication can be obtained by selecting a proper divide-

by-N network, where N is an integer.
Frequency Shift Keying (FSK) demodulator:

In computer peripheral & radio (wireless) communication the binary data or code
is transmitted by means of a carrier frequency that is shifted between two preset
frequencies. Since a carrier frequency is shifted between two preset frequencies,
the data transmission is said to use a FSK. The frequency corresponding to logic 1
& logic 0 states are commonly called the mark & space frequency.

For example, When transmitting teletype writer information using a modulator-

demodulator (modem) a 1070-1270 (mark-space) pair represents the originate
signal, while a 2025-2225 Hz (mark-space) pair represents the answer signal.
FSK Generator:

 The FSK generator is formed by using a 555 as an astable multivibrator,

whose frequency is controlled by the state of transistor Q1.

 In other words, the output frequency of the FSK generator depends on the
logic state of the digital data input.

 150 Hz is one the standards frequencies at which the data are commonly
transmitted.

 When the input is logic 1, the transistor Q1 is off. Under the condition, 555
timer works in its normal mode as an astable multivibrator i.e., capacitor C charges
through RA & RB to 2/3 Vcc & discharges through RB to 1/3 Vcc. Thus capacitor C
charges & discharges between 2/3 Vcc & 1/3 Vcc as long as the input is logic 1.

 The frequency of the output waveform is given

 When the input is logic 0, (Q1 is ON saturated) which in turn connects the
resistance Rc across RA. This action reduces the charging time of capacitor
C1 increases the output frequency, which is given by,

 By proper selection of resistance Rc, this frequency is adjusted to equal the

space frequency of 1270 Hz. The difference between the FSK signals of 1070 Hz
& 1270 Hz is 200 Hz, this difference is called “frequency shift”.

 The output 150 Hz can be made by connecting a voltage comparator between

the output of the ladder filter and pin 6 of PLL.

 The VCO frequency is adjusted with R1 so that at fIN = 1070 Hz.

FSK Demodulator:

 The output of 555 FSK generators is applied to the 565 FSK demodulator.

 Capacitive coupling is used at the input to remove dc line.

 At the input of 565, the loop locks to the input frequency & tracks it between
the 2 frequencies.

 R1 & C1 determine the free running frequency of the VCO, 3 stages RC

ladder filter is used to remove the carrier component from the output.

Applications:

In digital data communication and computer peripheral, binary data is transmitted

by means of a carrier frequency which is shifted between two preset frequencies.
This type of data transmission is called frequency shift keying (FSK) technique.
The binary data can be retrieved using FSK demodulator. The figure below shows
FSK demodulator using PLL for tele-typewriter signals of 1070 Hz and 1270 Hz.
As the signal appears at the input, the loop locks to the input frequency and tracks
it between the two frequencies with a corresponding dc shift at the output. A three
stage filter removes the carrier component and the output signal is made logic
compatible by a voltage comparator.

AM Demodulation:

A PLL may be used to demodulate AM signals as shown in the figure below. The
PLL is locked to the carrier frequency of the incoming AM signal. The output of
VCO which has the same frequency as the carrier, but unmodulated is fed to the
multiplier. Since VCO output is always 90 0 before being fed to the multiplier. This
makes both the signals applied to the multiplier and the difference signals, the
demodulated output is obtained after filtering high frequency components by the
LPF. Since the PLL responds only to the carrier frequencies which are very close
to the VCO output, a PLL AM detector exhibits high degree of selectivity and
noise immunity which is not possible with conventional peak detector type AM
modulators.
FM Demodulation:

If PLL is locked to a FM signal, the VCO tracks the instantaneous frequency of the
input signal. The filtered error voltage which controls the VCO and maintains lock
with the input signal is the demodulated FM output.

The VCO transfer characteristics determine the linearity of the demodulated

output. Since, VCO used in IC PLL is highly linear, it is possible to realize highly
linear FM demodulators.

Frequency multiplication/division:

The block diagram shown below shows a frequency multiplier/divider using PLL.
A divide by N network is inserter between the VCO output and the phase
comparator input. In the locked state, the VCO output frequency fo is given by f o =
Nfs. The multiplication factor can be obtained by selecting a proper scaling factor
N of the counter.

Frequency multiplication can also be obtained by using PLL in its harmonic

locking mode. If the input signal is rich in harmonics e.g. square wave, pulse train
etc., then the VCO can be directly locked to the n-th harmonic of the input signal
without connecting any frequency divider in between. However, as the amplitude
of the higher order harmonics becomes less, effective locking may not take place
for high values of n. Typically n is kept less than 10.
The circuit of the figure above can also be used for frequency division. Since the
VCO

output (a square wave) is rich in harmonics, it is possible to lock the m-th

harmonic of the VCO output with the input signal fs. The output fo of VCO is now
given by fo=fs/m

PLL Frequency Synthesis:

In digital wireless communication systems (GSM, CDMA etc), PLL's are used to
provide the Local Oscillator (LO) for up-conversion during transmission, and
down-conversion during reception. In most cellular handsets this function has been
largely integrated into a single integrated circuit to reduce the cost and size of the
handset.

However due to the high performance required of base station terminals, the
transmission and reception circuits are built with discrete components to achieve
the levels of performance required. GSM LO modules are typically built with a
Frequency Synthesizer integrated circuit, and discrete resonator VCO's.

Principle of PLL synthesizers

A phase locked loop does for frequency what the Automatic Gain Control does for
voltage. It compares the frequencies of two signals and produces an error signal
which is proportional to the difference between the input frequencies.

The error signal is then low pass filtered and used to drive a voltage-controlled
oscillator (VCO) which creates an output frequency. The output frequency is fed
through a frequency divider back to the input of the system, producing a negative
feedback loop.

If the output frequency drifts, the error signal will increase, driving the frequency
in the opposite direction so as to reduce the error. Thus the output is locked to the
frequency at the other input. This input is called the reference and is derived from a
crystal oscillator, which is very stable in frequency.

The block diagram below shows the basic elements and arrangement of a PLL
based frequency synthesizer.

The key to the ability of a frequency synthesizer to generate multiple frequencies is

the divider placed between the output and the feedback input. This is usually in the
form of a digital counter, with the output signal acting as a clock signal.

The counter is preset to some initial count value, and counts down at each cycle of
the clock signal. When it reaches zero, the counter output changes state and the
count value is reloaded.
This circuit is straightforward to implement using flip-flops, and because it is
digital in nature, is very easy to interface to other digital components or a
microprocessor. This allows the frequency output by the synthesizer to be easily
controlled by a digital system.

Example:

Suppose the reference signal is 100 kHz, and the divider can be preset to any value
between 1 and 100. The error signal produced by the comparator will only be zero
when the output of the divider is also 100 kHz. For this to be the case, the VCO
must run at a frequency which is 100 kHz x the divider count value.

Thus it will produce an output of 100 kHz for a count of 1, 200 kHz for a count of
2, 1 MHz for a count of 10 and so on. Note that only whole multiples of the
reference frequency can be obtained with the simplest integer N dividers.
Fractional N dividers are readily available

Practical considerations:

In practice this type of frequency synthesizer cannot operate over a very wide
range of frequencies, because the comparator will have a limited bandwidth and
may suffer from aliasing problems. This would lead to false locking situations, or
an inability to lock at all. In addition, it is hard to make a high frequency VCO that
operates over a very wide range.

This is due to several factors, but the primary restriction is the limited capacitance
range of varactor diodes. However, in most systems where a synthesizer is used,
we are not after a huge range, but rather a finite number over some defined range,
such as a number of radio channels in a specific band.

Many radio applications require frequencies that are higher than can be directly
input to the digital counter. To overcome this, the entire counter could be
constructed using high-speed logic such as ECL, or more commonly, using a fast
initial division stage called a prescaler which reduces the frequency to a
manageable level.
Since the prescaler is part of the overall division ratio, a fixed prescaler can cause
problems designing a system with narrow channel spacing’s - typically
encountered in radio applications. This can be overcome using a dual-modulus
prescaler.

Further practical aspects concern the amount of time the system can switch from
channel to channel, time to lock when first switched on, and how much noise there
is in the output. All of these are a function of the loop filter of the system, which is
a low-pass filter placed between the output of the frequency comparator and the
input of the VCO.

Usually the output of a frequency comparator is in the form of short error pulses,
but the input of the VCO must be a smooth noise- free DC voltage. (Any noise on
this signal naturally causes frequency modulation of the VCO.).

Heavy filtering will make the VCO slow to respond to changes, causing drift and
slow response time, but light filtering will produce noise and other problems with
harmonics. Thus the design of the filter is critical to the performance of the system
and in fact the main area that a designer will concentrate on when building a
synthesizer system.

Analog To Digital Conversion

The natural state of audio and video signals is analog. When digital technology
was not yet around, they are recorded or played back in analog devices like vinyl
discs and cassette tapes. The storage capacity of these devices is limited and doing
multiple runs of re-recording and editing produced poor signal quality.
Developments in digital technology like the CD, DVD, Blu-ray, flash devices and
other memory devices addressed these problems.

For these devices to be used, the analog signals are first converted to digital signals
using analog to digital conversion (ADC). For the recorded audio and video signals
to be heard and viewed again, the reverse process of digital to analog conversion
(DAC) is used.

ADC and DAC are also used in interfacing digital circuits to analog systems.
Typical applications are control and monitoring of temperature, water level,
pressure and other real-world data.
An ADC inputs an analog signal such as voltage or current and outputs a digital
signal in the form of a binary number. A DAC, on the other hand, inputs the binary
number and outputs the corresponding analog voltage or current signal.

Sampling rate

The analog signal is continuous in time and it is necessary to convert this to a flow
of digital values. It is therefore required to define the rate at which new digital
values are sampled from the analog signal. The rate of new values is called
the sampling rate or sampling frequency of the converter.

A continuously varying band limited signal can be sampled (that is, the signal
values at intervals of time T, the sampling time, are measured and stored) and then
the original signal can be exactly reproduced from the discrete-time values by an
interpolation formula. The accuracy is limited by quantization error. However, this
faithful reproduction is only possible if the sampling rate is higher than twice the
highest frequency of the signal. This is essentially what is embodied in the
Shannon-Nyquist sampling theorem.

Since a practical ADC cannot make an instantaneous conversion, the input value
must necessarily be held constant during the time that the converter performs a
conversion (called the conversion time). An input circuit called a sample and hold
performs this task—in most cases by using a capacitor to store the analog voltage
at the input, and using an electronic switch or gate to disconnect the capacitor from
the input. Many ADC integrated circuits include the sample and hold subsystem
internally.
Accuracy

An ADC has several sources of errors. Quantization error and (assuming the ADC
is intended to be linear) non-linearity is intrinsic to any analog-to-digital
conversion. There is also a so-called aperture error which is due to a clock jitter
and is revealed when digitizing a time-variant signal (not a constant value).

These errors are measured in a unit called the LSB, which is an abbreviation for
least significant bit. In the above example of an eight-bit ADC, an error of one
LSB is 1/256 of the full signal range, or about 0.4%.

Quantization error

Quantization error is due to the finite resolution of the ADC, and is an unavoidable
imperfection in all types of ADC. The magnitude of the quantization error at the
sampling instant is between zero and half of one LSB.

In the general case, the original signal is much larger than one LSB. When this
happens, the quantization error is not correlated with the signal, and has a uniform
distribution.

Its RMS value is the standard deviation of this distribution, given by 1/√12 LSB ≈
0.289LSB. In the eight-bit ADC example, this represents 0.113% of the full signal
range.

At lower levels the quantizing error becomes dependent of the input signal,
resulting in distortion. This distortion is created after the anti-aliasing filter, and if
these distortions are above 1/2 the sample rate they will alias back into the audio
band. In order to make the Quantizing error independent of the input signal, noise
with amplitude of 1 quantization step is added to the signal. This slightly reduces
signal to noise ratio, but completely eliminates the distortion. It is known as dither.

Non-linearity
All ADCs suffer from non-linearity errors caused by their physical imperfections,
resulting in their output to deviate from a linear function (or some other function,
in the case of a deliberately non-linear ADC) of their input. These errors can
sometimes be mitigated by calibration, or prevented by testing.

Important parameters for linearity are integral non-linearity (INL) and differential
non- linearity (DNL). These non-linear ties reduce the dynamic range of the signals
that can be digitized by the ADC, also reducing the effective resolution of the
ADC.

D To A Converter- Specifications

D/A converters are available with wide range of specifications specified by

manufacturer. Some of the important specifications are Resolution, Accuracy,
linearity, monotonicity, conversion time, settling time and stability.

Resolution:

Resolution is defined as the number of different analog output voltage levels that
can be provided by a DAC. Or alternatively resolution is defined as the ratio of a
change in output voltage resulting for a change of 1 LSB at the digital input.
Simply, resolution is the value of LSB.

Resolution (Volts) = VoFS / (2n - 1) = 1 LSB

increment Where ‘n’ is the number of input bits

‘VoFS’ is the full scale output voltage.

Example:

Resolution for an 8 – bit DAC for example is said to have

: 8 – bit resolution

: A resolution of 0.392 of full-Scale (1/255)

: A resolution of 1 part in 255.

Thus resolution can be defined in many different ways.

The following table shows the resolution for 6 to 16 bit DACs

Accuracy:

Absolute accuracy is the maximum deviation between the actual converter output
and the ideal converter output. The ideal converter is the one which does not suffer
from any problem. Whereas, the actual converter output deviates due to the drift in
component values, mismatches, aging, noise and other sources of errors.

The relative accuracy is the maximum deviation after the gain and offset errors
have been removed. Accuracy is also given in terms of LSB increments or
percentage of full-scale voltage. Normally, the data sheet of a D/A converter
specifies the relative accuracy rather than absolute accuracy.

Linearity:

Linearity error is the maximum deviation in step size from the ideal step size.
Some D/A converters are having a linearity error as low as 0.001% of full scale.
The linearity of a D/A converter is defined as the precision or exactness with
which the digital input is converted into analog output. An ideal D/A converter
produces equal increments or step sizes at output for every change in equal
increments of binary input.

Monotonicity:

A Digital to Analog converter is said to be monotonic if the analog output

increases for an increase in the digital input. A monotonic characteristic is essential
in control applications. Otherwise it would lead to oscillations. If a DAC has to be
monotonic, the error should be less than ± (1/2) LSB at each output level. Hence
all the D/A converters are designed such that the linearity error satisfies the above
condition.

When a D/A Converter doesn’t satisfy the condition described above, then, the
output voltage may decrease for an increase in the binary input.

Conversion Time:

It is the time taken for the D/A converter to produce the analog output for the given
binary input signal. It depends on the response time of switches and the output of
the Amplifier. D/A converters speed can be defined by this parameter. It is also
called as setting time.

Settling time:

It is one of the important dynamic parameter. It represents the time it takes for the
output to settle within a specified band ± (1/2) LSB of its final value following a
code change at the input (Usually a full-scale change). It depends on the switching
time of the logic circuitry due to internal parasitic capacitances and inductances. A
typical settling time ranges from 100 ns to 10 µs depending on the word length and
type of circuit used.
Stability:

The ability of a DAC to produce a stable output all the time is called as Stability.
The performance of a converter changes with drift in temperature, aging and power
supply variations. So all the parameters such as offset, gain, linearity error &
monotonicity may change from the values specified in the datasheet. Temperature
sensitivity defines the stability of a D/A converter.

Digital To Analog Conversion

A DAC converts an abstract finite-precision number (usually a fixed-point binary

number) into a concrete physical quantity (e.g., a voltage or a pressure). In
particular, DACs are often used to convert finite-precision time series data to a
continually-varying physical signal.

A typical DAC converts the abstract numbers into a concrete sequence of impulses
that are then processed by a reconstruction filter using some form of interpolation
to fill in data between the impulses.

Other DAC methods (e.g., methods based on Delta-sigma modulation) produce a

pulse-density modulated signal that can then be filtered in a similar way to produce
a smoothly-varying signal.By the Nyquist–Shannon sampling theorem, sampled
data can be reconstructed perfectly provided that its bandwidth meets certain
requirements (e.g., a baseband signal with bandwidth less than the Nyquist
frequency). However, even with an ideal reconstruction filter, digital sampling
introduces quantization that makes perfect reconstruction practically impossible.
Increasing the digital resolution (i.e., increasing the number of bits used in each
sample) or introducing sampling dither can reduce this error.

DACs are at the beginning of the analog signal chain, which makes them very
important to system performance. The most important characteristics of these
devices are:

Specifications:
Resolution: This is the number of possible output levels the DAC is designed to
reproduce. This is usually stated as the number of bits it uses, which is the base
two logarithm of the number of levels. For instance a 1 bit DAC is designed to
reproduce 2 (21) levels while an 8 bit DAC is designed for 256 (2 8) levels.
Resolution is related to the

Effective number of bits (ENOB) which is a measurement of the actual resolution

attained by the DAC.

Maximum sampling frequency: This is a measurement of the maximum speed

at which the DACs circuitry can operate and still produce the correct output. As
stated in the Nyquist–Shannon sampling theorem, a signal must be sampled at over
twice the frequency of the desired signal. For instance, to reproduce signals in all
the audible spectrum, which includes frequencies of up to 20 kHz, it is necessary to
use DACs that operate at over 40 kHz. The CD standard samples audio at kHz,
thus DACs of this frequency are often used. A common frequency in cheap
computer sound cards is 48 kHz—many work at only this frequency, offering the
use of other sample rates only through (often poor) internal resampling.

Monotonicity: This refers to the ability of a DAC's analog output to move only in
the direction that the digital input moves (i.e., if the input increases, the output
doesn't dip before asserting the correct output.) This characteristic is very
important for DACs used as a low frequency signal source or as a digitally
programmable trim element.

THD+N: This is a measurement of the distortion and noise introduced to the signal
by the DAC. It is expressed as a percentage of the total power of unwanted
harmonic distortion and noise that accompany the desired signal. This is a very
important DAC characteristic for dynamic and small signal DAC applications.
Dynamic range: This is a measurement of the difference between the largest and
smallest signals the DAC can reproduce expressed in decibels. This is usually
related to DAC resolution and noise floor.

Other measurements, such as phase distortion and sampling period instability, can
also be very important for some applications.

Binary-Weighted Resistor DAC

The binary-weighted-resistor DAC employs the characteristics of the inverting

summer Op Amp circuit. In this type of DAC, the output voltage is the inverted
sum of all the input voltages. If the input resistor values are set to multiples of two:
1R, 2R and 4R, the output voltage would be equal to the sum of V1, V2/2 and V3/4.
V1 corresponds to the most significant bit (MSB) while V 3 corresponds to the least
significant bit (LSB).

The circuit for a 4-bit DAC using binary weighted resistor network is shown
below:
The binary inputs, ai (where i = 1, 2, 3 and 4) have values of either 0 or 1. The
value, 0, represents an open switch while 1 represents a closed switch.

The operational amplifier is used as a summing amplifier, which gives a weighted

sum of the binary input based on the voltage, Vref.

For a 4-bit DAC, the relationship between Vout and the binary input is as follows:

The negative sign associated with the analog output is due to the connection to a
summing amplifier, which is a polarity-inverting amplifier. When a signal is
applied to the latter type of amplifier, the polarity of the signal is reversed (i.e. a +
input becomes -, or vice versa).

For a n-bit DAC, the relationship between Vout and the binary input is as follows:
The LSB, which is also the incremental step, has a value of - 0.625 V while the
MSB or the full scale has a value of - 9.375 V.

Practical Limitations:

o The most significant problem is the large difference in resistor values required
between the LSB and MSB, especially in the case of high resolution DACs (i.e.
those that has large number of bits). For example, in the case of a 12-bit DAC, if
the MSB is 1 k Ω, then the LSB is a staggering 2 MΩ.

o The maintenance of accurate resistances over a large range of values is

problematic. With the current IC fabrication technology, it is difficult to
manufacture resistors over a wide resistance range that maintains an accurate ratio
especially with variations in temperature.

R-2R Ladder DAC

An enhancement of the binary-weighted resistor DAC is the R-2R ladder network.

This type of DAC utilizes Thevenin’s theorem in arriving at the desired output
voltages.

A disadvantage of the former DAC design was its requirement of several different
precise input resistor values: one unique value per binary input bit.

The R-2R network consists of resistors with only two values - R and 2xR. If each
input is supplied either 0 volts or reference voltage, the output voltage will be an
analog equivalent of the binary value of the three bits. VS 2 corresponds to the most
significant bit (MSB) while VS0 corresponds to the least significant bit (LSB).
Vout = - (VMSB + Vn + VLSB) = - (VRef + VRef/2 + VRef/ 4)

Inverted or Current Mode DAC

Current mode DACs operates based on the ladder currents. The ladder is formed
by resistance R in the series path and resistance 2R in the shunt path. Thus the
current is divided into i1 , i2, i3 …………in. in each arm. The currents are either
diverted to the ground bus (io) or to the Virtual-ground bus ( io ).

The currents are given as

i1 = VREF/2R = (VREF/R) 2-1, i2 = (VREF)/2)/2R = (VREF/R) 2-2 ………in = (VREF/R) 2-n.

And the relationship between the currents are given as

i2 = i1/2

i3 = i1/4

i4 = i1/8

in = i1/2n-1

Using the bits to identify the status of the switches, and letting V0 = -Rf io gives

V0 = - (Rf/R) VREF (b12-1 + b22-2+ ……….. + bn2-n)

The two currents io and io are complementary to each other and the potential
of io bus must be sufficiently close to that of the io bus. Otherwise, linearity errors
will occur. The final op-amp is usedas current to voltage converter.
Advantages

1. The major advantage of current mode D/A converter is that the voltage change
across each switch is minimal. So the charge injection is virtually eliminated and
the switch driver design is made simpler.

2. In Current mode or inverted ladder type DACs, the stray capacitance do not
affect the Speed of response of the circuit due to constant ladder node voltages. So
improved speed performance.

Voltage Mode DAC

This is the alternative mode of DAC and is called so because the 2R resistance in
the shunt path is switched between two voltages named as V L and VH. The output of
this DAC is obtained from the leftmost ladder node. As the input is sequenced
through all the possible binary state starting from All 0s (0…..0) to all 1s (1…..1).
The voltage of this node changes in steps of 2-n (VH - VL) from the minimum voltage
of Vo = VL to the maximum of Vo = VH - 2-n (VH - VL).
The diagram also shows a non-inverting amplifier from which the final output is
taken. Due to this buffering with a non- inverting amplifier, a scaling factor
defined by K = 1 + (R2/R1) results.

Advantages

1. The major advantage of this technique is that it allows us to interpolate

between any two voltages, neither of which need not be a zero.

2. More accurate selection and design of resistors R and 2R are possible and
simple construction.

3. The binary word length can be easily increased by adding the required number
or R-2R sections.

Switches For DAC

The Switches which connects the digital binary input to the nodes of a D/A
converter is an electronic switch. Although switches can be made of using diodes,
bipolar junction Transistors, Field Effect transistors or MOSFETs, there are four
main configurations used as switches for DACs. They are

i) Switches using overdriven Emitter Followers.

ii) Switches using MOS Transistor- Totem pole MOSFET Switch and CMOS
Inverter Switch.

iii) CMOS switch for Multiplying type DACs.

iv) CMOS Transmission gate switches.

These configurations are used to ensure the high speed switching operations for
different types of DACs.

Switches using overdriven Emitter Followers:

The bipolar transistors have a negligible resistance when they are operated in
saturation. The bipolar transistor operating in saturation region indicates a
minimum resistance and thus represents ON condition. When they are operating in
cut-off region indicates a maximum resistance and thus represents OFF condition.

The circuit shown here is the arrangement of two transistors connected as emitter
followers. A silicon transistor operating in saturation will have an offset voltage of
0.2V dropped across them. To have a zero offset voltage condition, the transistors
must be overdriven because the saturation factor becomes negative. The two
transistors Q1 (NPN) and Q2 (PNP) acts as a double pole switch. The bases of the
transistors are driven by +5.75V and -5.75V.

Case 1:

When VB1 = VB2 = +5.75V, Q1 is in saturation and Q2 is OFF. And VE ≈ 5V

with VBE1 = VBE2 = 0.75V

Case 2:
When VB1 = VB2 = -5.75V, Q2 is in saturation and Q1 is OFF. And VE ≈ - 5V
with VBE1 = VBE2 = 0.75V

Thus the terminal B of the resistor Re is connected to either -5V or +5V depending
on the input bit.

Switches using MOS transistor:

i) Totem pole MOSFET Switch:

As shown in the figure, the totem pole MOSFET Switch is connected in series with
resistors of R-2R network. The MOSFET driver is connected to the inverting
terminal of the summing op-amp.

The complementary outputs Q and Q drive the gates of the MOSFET M1

and M2 respectively. The SR flip flop holds one bit of digital information of the
binary word under conversion. Assuming the negative logic (-5V for logic 1 and
+5V for logic 0) the operation is given as two cases.

Case 1:

When the bit line is 1 with S=1 and R=0 makes Q=1 and Q =0. This makes the
transistor M1 ON, thereby connecting the resistor R to reference voltage -VR. The
transistor M2 remains in OFF condition.

Case 2:

When the bit line is 0 with S=0 and R=1 makes Q=0 and Q =1. This makes the
transistor M2 ON, thereby connecting the resistor R toGround. The transistor M1
remains inOFF condition.

ii) CMOS Inverter Switch:

The figure of CMOS inverter is shown here. It consists of a CMOS inverter

connected with an op-amp acting as a buffer. The buffer drives the resistor R with
very low output impedance.

Assuming positive logic (+5V for logic 1 and 0V for logic 0), the operation can be
explained in two cases.

Case1:
When the complement of the bit line Q is low, M1 becomes ON connecting VR to
the non- inverting input of the op-amp. This drives the resistor R HIGH.

Case2:

When the complement of the bit line Q is high, M2 becomes ON connecting

Ground to the non- inverting input of the op-amp. This pulls the resistor R LOW
(to ground).

CMOS switch for Multiplying type DACs:

The circuit diagram of CMOS Switch is shown here. The heart of the switching
element is formed by transistors M 1 and M2. The remaining transistors accept TTL
or CMOS compatible logic inputs and provides the anti-phase gate drives for the
transistors M1 and M2. The operation for the two cases is as follows.

Case 1:

When the logic input is 1, M 1 is ON and M2 is OFF. Thus current IK is diverted to

Io bus.

Case 2:

When the logic input is 0, M 2 is ON and M1 is OFF. Thus current IK is diverted to

Io bus.

CMOS Transmission gate switches:

The disadvantage of using individual NMOS and PMOS transistors are threshold
voltage drop (NMOS transistor passing only minimum voltage of V R- VTH and
PMOS transistor passing minimum voltage of VTH). This is eliminated by using
transmission gates which uses a parallel connection of both NMOS and PMOS.
The arrangement shown here can pass voltages from VR to 0V acting as a ideal
switch. The following cases explain the operation.
Case 1:

When the bit-line bk is HIGH, both transistors Mn and Mp are ON, offering low
resistance over the entire range of bit voltages.

Case 2:

When the bit-line bk is LOW, both the transistors are OFF, and the signal
transmission is inhibited (Withdrawn).

Thus the NMOS offers low resistance in the lower portion of the signal and PMOS
offers low resistance in the upper portion of the signal. As a combination, they
offer a low parallel resistance throughout the operating range of voltage. Wide
varieties of these kinds of switches were available. Example: CD4066 and
CD4051.

High Speed Sample and Hold Circuits

Introduction:

Sample-and-hold (S/H) is an important analog building block with many

applications, including analog-to-digital converters (ADCs) and switched-capacitor
filters. The function of the S/H circuit is to sample an analog input signal and hold
this value over a certain length of time for subsequent processing.

Taking advantages of the excellent properties of MOS capacitors and switches,

traditional switched capacitor techniques can be used to realize different S/H
circuits [1]. The simplest S/H circuit in MOS technology is shown in Figure 1,
where Vin is the input signal, M1 is an MOS transistor operating as the sampling
switch, Ch is the hold capacitor, ck is the clock signal, and Vout is the resulting
sample-and-hold output signal.

As depicted by Figure 4. , in the simplest sense, a S/H circuit can be achieved

using only one MOS transistor and one capacitor. The operation of this circuit is
very straightforward.
Figure 4, in the simplest sense, a S/H circuit can be achieved using only one MOS
transistor and one capacitor. The operation of this circuit is very straightforward.
Whenever ck is high, the MOS switch is on, which in turn allows Vout to track Vin.
On the other hand, when ck is low, the MOS switch is off. During this
time, Ch will keep Vout equal to the value of Vin at the instance when ck goes low.

Unfortunately, in reality, the performance of this S/H circuit is not as ideal as

described above. The two major types of errors occur. They are charge injection
and clock feed through, that are associated with this S/H implementation. Three
new S/H techniques, all of which try to minimize the errors caused by charge
injection and/or clock feed through.

Alternative CMOS Sample-and-Hold Circuits

Three alternative CMOS S/H circuits that are developed with the intention to
minimize charge injection and/or clock feed through are

Series Sampling:

The S/H circuit of Figure 4. is classified as parallel sampling because the hold
capacitor is in parallel with the signal. In parallel sampling, the input and the
output are dc-coupled. On the other hand, the S/H circuit shown in Figure 2 is
referred to as series sampling because the hold capacitor is in series with the signal.
When the circuit is in sample mode, both switches S2 and S3 are on, while S1 is off.
Then,S2 is turned off first, which means Vout is equal to VCC (or VDD for most circuits)
and the voltage drop across Ch will be VCC – Vin. Subsequently, S3 is turned off
and S1 is turned on simultaneously. By grounding node X, Vout is now equal to VCC –
Vin, and the drop from VCC to VCC – Vin is equal to the instantaneous value of the
input.

As a result, this is actually an inverted S/H circuit, which requires inversion of the
signal at a later stage. Since the hold capacitor is in series with the signal, series
sampling can isolate the common- mode levels of the input and the output.

This is one advantage of series sampling over parallel sampling. In addition, unlike
parallel sampling, which suffers from signal-dependent charge injection, series
sampling does not exhibit such behavior because S2 is turned off before S3. Thus,
the fact that the gate-to-source voltage, VGS, of S2 is constant means that charge
injection coming from S2 is also constant (as opposed to being signal-dependent),
which means this error can be easily eliminated through differential operation.

Limitations:

On the other hand, series sampling suffers from the nonlinearity of the parasitic
capacitance at node Y. This parasitic capacitance introduces distortion to the
sample-and hold value, thus mandating that Ch be much larger than the parasitic
capacitance. On top of this disadvantage, the settling time of the S/H circuit during
hold mode is longer for series sampling than for parallel sampling. The reason for
this is because the value of Vout in series sampling is being reset to VCC (or VDD)
for every sample, but this is not the case for parallel sampling.
Switched Op-Amp Based Sample-and-Hold Circuit:

This S/H technique takes advantage of the fact that when a MOS transistor is in the
saturation region, the channel is pinched off and disconnected from the drain.
Therefore, if the hold capacitor is connected to the drain of the MOS transistor,
charge injection will only go to the source junction, leaving the drain unaffected.
Based on this concept, a switched op- amp (SOP) based S/H circuit, as shown in
Figure 4.9

During sample mode, the SOP behaves just like a regular op-amp, in which the
value of the output follows the value of the input. During hold mode, the MOS
transistors at the output node of the SOP are turned off while they are still
operating in saturation, thus preventing any channel charge from flowing into the
output of the SOP. In addition, the SOP is shut off and its output is held at high
impedance, allowing the charge on Ch to be preserved throughout the hold mode.
On the other hand, the output buffer of this S/H circuit is always operational during
sample and hold mode and is always providing the voltage on Ch to the output of
the S/H circuit.

S/H circuits that operate in closed loop configuration can achieve high resolution,
but their requirements for high gain circuit block, such as an op-amp, limits the
speed of the circuits. As a result, better and faster S/H circuits must be developed.
The above figure shows a sample and holds circuit with MOSFET as Switch acting
as a sampling device and also consists of a holding capacitor Cs to store the sample
values until the next sample comes in. This is a high speed circuit as it is apparent
that CMOS switch has a very negligible propagation delay.

Three S/H circuits to reduce error:

o series sampling,

o SOP based S/H circuit,

o bottom plate S/H circuit with bootstrapped switch

A to D Converter- Specifications

Like DAC, ADCs are also having many important specifications. Some of them
are Resolution, Quantization error, Conversion time, Analog error, Linearity error,
DNL error, INL error & Input voltage range.

Resolution:
The resolution refers to the finest minimum change in the signal which is accepted
for conversion, and it is decided with respect to number of bits. It is given as 1/2 n,
where ‘n’ is the number of bits in the digital output word. As it is clear, that the
resolution can be improved by increasing the number of bits or the number of bits
representing the given analog input voltage.

Resolution can also be defined as the ratio of change in the value of input voltage
Vi, needed to change the digital output by 1 LSB. It is given as

Resolution = ViFS / (2n – 1)

Where ‘ViFS’ is the full-scale input voltage.

‘n’ is the number of output bits.

Quantization error:

If the binary output bit combination is such that for all the values of input voltage
Vi between any two voltage levels, there is a unavoidable uncertainty about the
exact value of Vi when the output is a particular binary combination. This
uncertainty is termed as quantization error. Its value is ± (1/2) LSB. And it is given
as,

QE = ViFS / 2(2n – 1)

Where ‘ViFS’ is the full-scale input voltage

‘n’ is the number of output bits.

Maximum the number of bits selected, finer the resolution and smaller the
quantization error.

Conversion Time:

It is defined as the total time required for an A/D converter to convert an analog
signal to digital output. It depends on the conversion technique and propagation
delay of the circuit components.
Analog error:

An error occurring due to the variations in DC switching point of the comparator,

resistors, reference voltage source, ripples and noises introduced by the circuit
components is termed as Analog error.

Linearity Error:

It is defined as the measure of variation in voltage step size. It indicates the

difference between the transitions for a minimum step of input voltage change.
This is normally specified as fraction of LSB.

Differential Non-Linearity(DNL) Error:

The analog input levels that trigger any two successive output codes should differ
by 1 LSB. Any deviation from this 1 LSB value is called as DNL error.

Integral Non-Linearity (INL) Error:

The deviation of characteristics of an ADC due to missing codes causes INL error.
The maximum deviation of the code from its ideal value after nulling the offset and
gain errors is called as Integral Non-Linearity Error.

Input Voltage Range:

It is the range of voltage that an A/D converter can accept as its input without
causing any overflow in its digital output.
Analog Switches

There were two types of analog switches. Series and Shunt switch. The Switch
operation is shown for both the cases VGS=0 VGS= VGs (off)

Direct-conversion ADC/Flash type ADC:

This process is extremely fast with a sampling rate of up to 1 GHz. The resolution
is however, limited because of the large number of comparators and reference
voltages required. The input signal is fed simultaneously to all comparators. A
priority encoder then generates a digital output that corresponds with the highest
activated comparator.

Successive-approximation ADCs

Successive-approximation ADC is a conversion technique based on a successive-

approximation register (SAR). This is also called bit-weighing conversion that
employs a comparator to weigh the applied input voltage against the output of an
N-bit digital-to-analog converter (DAC).

The final result is obtained as a sum of N weighting steps, in which each step is a
single-bit conversion using the DAC output as a reference. SAR converters sample
at rates up to 1Mbps, requires a low supply current, and the cheapest in terms of
production cost.
A successive-approximation ADC uses a comparator to reject ranges of voltages,
eventually settling on a final voltage range. Successive approximation works by
constantly comparing the input voltage to the output of an internal digital to analog
converter (DAC, fed by the current value of the approximation) until the best
approximation is achieved.

At each step in this process, a binary value of the approximation is stored in a

successive approximation register (SAR). The SAR uses a reference voltage
(which is the largest signal the ADC is to convert) for comparisons.

For example if the input voltage is 60 V and the reference voltage is 100 V, in the
1st clock cycle, 60 V is compared to 50 V (the reference, divided by two. This is
the voltage at the output of the internal DAC when the input is a '1' followed by
zeros), and the voltage from the comparator is positive (or '1') (because 60 V is
greater than 50 V). At this point the first binary digit (MSB) is set to a '1'. In the
2nd clock cycle the input voltage is compared to 75 V (being halfway between 100
and 50 V: This is the output of the internal DAC when its input is '11' followed by
zeros) because 60 V is less than 75 V, the comparator output is now negative (or
'0'). The second binary digit is therefore set to a '0'. In the 3rd clock cycle, the input
voltage is compared with 62.5 V (halfway between 50 V and 75 V: This is the
output of the internal DAC when its input is '101' followed by zeros). The output of
the comparator is negative or '0' (because 60 V is less than 62.5 V) so the third
binary digit is set to a 0. The fourth clock cycle similarly results in the fourth digit
being a '1' (60 V is greater than 56.25 V, the DAC output for '1001' followed by
zeros). The result of this would be in the binary form 1001. This is also called bit-
weighting conversion, and is similar to a binary.

The analogue value is rounded to the nearest binary value below, meaning this
converter type is mid-rise (see above). Because the approximations are successive
(not simultaneous), the conversion takes one clock-cycle for each bit of resolution
desired.

The clock frequency must be equal to the sampling frequency multiplied by the
number of bits of resolution desired. For example, to sample audio at 44.1 kHz
with 32 bit resolution, a clock frequency of over 1.4 MHz would be required.

ADCs of this type have good resolutions and quite wide ranges. They are more
complex than some other designs.
Dual slope ADC (Integrating ADCs)

In an integrating ADC, a current, proportional to the input voltage, charges a

capacitor for a fixed time interval T charge. At the end of this interval, the device
resets its counter and applies an opposite-polarity negative reference voltage to the
integrator input. Because of this, the capacitor is discharged by a constant current
until the integrator output voltage zero again.

The T discharge interval is proportional to the input voltage level and the resultant
final count provides the digital output, corresponding to the input signal. This type
of ADCs is extremely slow devices with low input bandwidths. Their advantage,
however, is their ability to reject high-frequency noise and AC line noise such as
50Hz or 60Hz. This makes them useful in noisy industrial environments and
typical application is in multi-meters.

An integrating ADC (also dual-slope or multi-slope ADC) applies the unknown

input voltage to the input of an integrator and allows the voltage to ramp for a
fixed time period (the run-up period). Then a known reference voltage of opposite
polarity is applied to the integrator and is allowed to ramp until the integrator
output returns to zero (the run-down period). The input voltage is computed as a
function of the reference voltage, the constant run-up time period, and the
measured run-down time period.
The run-down time measurement is usually made in units of the converter's clock,
so longer integration times allow for higher resolutions. Likewise, the speed of the
converter can be improved by sacrificing resolution.

Use: Converters of this type (or variations on the concept) are used in most
digital voltmeters for their linearity and flexibility.

A/D Using Voltage To Time Conversion:

The Block diagram shows the basic voltage to time conversion type of A to D
converter. Here the cycles of variable frequency source are counted for a fixed
period. It is possible to make an A/D converter by counting the cycles of a fixed-
frequency source for a variable period. For this, the analog voltage required to be
converted to a proportional time period.

As shown in the diagram a negative reference voltage -VR is applied to an

integrator, whose output is connected to the inverting input of the comparator. The
output of the comparator is at 1 as long as the output of the integrator Vo is less
than Va.

At t = T, Vc goes low and switch S remains open. When VEN goes high, the
switch S is closed, thereby discharging the capacitor. Also the NAND gate is
disabled. The waveforms are shown here.
Sigma-delta ADCs/ Over sampling Converters:

It consists of 2 main parts - modulator and digital filter. The modulator includes an
integrator and a comparator with a feedback loop that contains a 1-bit DAC. The
modulator oversamples the input signal, converting it to a serial bit stream with a
frequency much higher than the required sampling rate. This is then transformed
by the output filter to a sequence of parallel digital words at the sampling rate. The
characteristics of sigma-delta converters are high resolution, high accuracy,
Low noise and low cost.

Typical applications are for speech and audio.

A Sigma-Delta ADC (also known as a Delta-Sigma ADC) oversamples the

desired signal by a large factor and filters the desired signal band. Generally a
smaller number of bits than required are converted using a Flash ADC after the
Filter. The resulting signal, along with the error generated by the discrete levels of
the Flash, is fed back and subtracted from the input to the filter. This negative
feedback has the effect of noise shaping the error due to the Flash so that it does
not appear in the desired signal frequencies.

A digital filter (decimation filter) follows the ADC which reduces the sampling
rate, filters off unwanted noise signal and increases the resolution of the output.
(sigma-delta modulation, also called delta-sigma modulation)

The canonical form of a feedback system is shown in Figure 5 . 1, and Equation 1

describes the performance of any feedback system (an amplifier with passive
feedback Components constitute a feedback system).
Oscillation results from an unstable state; i.e., the feedback system can’t find a
stable state because its transfer function can’t be satisfied. Equation 1 becomes
unstable when (1+Aβ) = 0 because A/0 is an undefined state. Thus, the key to
designing an oscillator is to insure that Aβ = –1 (called the Barkhausen criterion),
or using complex math the equivalent expression is Aβ = 1 –180°. The 180° phase
shift criterion applies to negative feedback systems, and 0° phase shift applies to
positive feedback systems.

The output voltage of a feedback system heads for infinite voltage when Aβ = –1.
When the output voltage approaches either power rail, the active devices in the
amplifiers change gain, causing the value of A to change so the value of Aβ ≠1;
thus, the charge to infinite voltage slows down and eventually halts. At this point
one of three things can occur.

First, nonlinearity in saturation or cutoff can cause the system to become stable and
lock

up.

Second, the initial charge can cause the system to saturate (or cut off) and stay that
way for a long time before it becomes linear and heads for the opposite power rail.

Third, the system stays linear and reverses direction, heading for the opposite
power rail. Alternative two produces highly distorted oscillations (usually quasi
square waves), and the resulting oscillators are called relaxation oscillators.
Alternative three produces sine wave oscillators.
Phase Shift in Oscillators:

The 180° phase shift in the equation Aβ = 1 –180° is introduced by active and
passive components. The phase shift contributed by active components is
minimized because it varies with temperature, has a wide initial tolerance, and is
device dependent.

Amplifiers are selected such that they contribute little or no phase shift at the
oscillation frequency. A single pole RL or RC circuit contributes up to 90° phase
shift per pole, and because 180° is required for oscillation, at least two poles must
be used in oscillator design.

An LC circuit has two poles; thus, it contributes up to 180° phase shift per pole
pair, but LC and LR oscillators are not considered here because low frequency
inductors are expensive, heavy, bulky, and non-ideal. LC oscillators are designed
in high frequency applications beyond the frequency range of voltage feedback op
amps, where the inductor size, weight, and cost are less significant.

Multiple RC sections are used in low-frequency oscillator design in lieu of

inductors. Phase shift determines the oscillation frequency because the circuit
oscillates at the frequency that accumulates –180° phase shift. The rate of change
of phase with frequency, dS/dt, determines frequencystability.

When buffered RC sections (an op amp buffer provides high input and low output
impedance) are cascaded, the phase shift multiplies by the number of sections, n
(see Figure 2).

Although two cascaded RC sections provide 180° phase shift, dS/dt at the
oscillator frequency is low, thus oscillators made with two cascaded RC sections
have poor frequency stability. Three equal cascaded RC filter sections have a
higher dS/dt, and the resulting oscillator has improved frequency stability.

Adding a fourth RC section produces an oscillator with an excellent dS/dt, thus this
is the most stable oscillator configuration. Four sections are the maximum number
used
because op amps come in quad packages, and the four-section oscillator yields four
sine waves that are 45° phase shifted relative to each other, so this oscillator can be
used to obtain sine/cosine or quadrature sine waves.

Applications

Crystal or ceramic resonators make the most stable oscillators because resonators
have an extremely high dS/dt resulting from their non-linear properties.

Resonators are used for high- frequency oscillators, but low-frequency oscillators
do not use resonators because of size, weight, and cost restrictions.

Op amps are not used with crystal or ceramic resonator oscillators because op
amps have low bandwidth. It is more cost-effective to build a high- frequency
crystal oscillator and count down the output to obtain a low frequency than it is to
use a low-frequency resonator.

Gain in Oscillators:

The oscillator gain must equal one (Aβ = 1–180°) at the oscillation frequency. The
circuit becomes stable when the gain exceeds one and oscillations cease. When the
gain exceeds one with a phase shift of –180°, the active device non-linearity
reduces the gain to one.

The non-linearity happens when the amplifier swings close to either power rail
because cutoff or saturation reduces the active device (transistor) gain. The
paradox is that worst-case design practice requires nominal gains exceeding one
for manufacturability, but excess gain causes more distortion of the output sine
wave.

When the gain is too low, oscillations cease under worst-case conditions, and when
the gain is too high, the output wave form looks more like a square wave than a
sine wave.

Distortion is a direct result of excess gain overdriving the amplifier; thus, gain
must be carefully controlled in low distortion oscillators.

Phase-shift oscillators have distortion, but they achieve low-distortion output

voltages because cascaded RC sections act as distortion filters. Also, buffered
phase-shift oscillators have low distortion because the gain is controlled and
distributed among the buffers.

Sine Wave Generators (Oscillators)

Sine wave oscillator circuits use phase shifting techniques that usually employ

 Two RC tuning networks, and

 Complex amplitude limiting circuitry

RC Phase Shift Oscillator

RC phase shift oscillator using op-amp in inverting amplifier introduces the phase
shift of 180º between input and output. The feedback network consists of 3 RC
sections each producing 60º phase shift. Such a RC phase shift oscillator using op-
amp is shown in the figure.

The output of amplifier is given to feedback network. The output of feedback

network drives the amplifier. The total phase shift around a loop is 1800 of
amplifier and 180 due to 3 RC sections, thus 360 º. This satisfies the required
condition for positive feedback and circuit works as an oscillator.
The loop phase shift is –180° when the phase shift of each section is –60°, and this
occurs when ω = 2πf = 1.732/RC because the tangent 60° = 1.73. The magnitude of
β at this point is (1/2)3, so the gain, A, must be equal to 8 for the system gain to be
equal to 1.

Wien Bridge Oscillator:

Figure 5. 3 give the Wien-bridge circuit configuration. The loop is broken at the
positive input, and the return signal is calculated in Equation 2 below.

When ω = 2πf = 1/RC, the feedback is in phase (this is positive feedback), and the
gain is 1/3, so oscillation requires an amplifier with a gain of 3. When RF = 2RG,
the amplifier gain is 3 and oscillation occurs at f = 1/2πRC. The circuit oscillated at
1.65 kHz rather than 1.59 kHz with the component values shown in Figure 3, but
the distortion is noticeable.
Figure 4 shows a Wien-bridge circuit with non-linear feedback. The lamp
resistance, RL, is nominally selected as half the feedback resistance, RF, at the
lamp current established by RF and RL. The non-linear relationship between the
lamp current and resistance keeps output voltage changes small.

If a voltage source is applied directly to the input of an ideal amplifier with

feedback, the input current will be:

Where vin is the input voltage, vout is the output voltage, and Zf is the feedback
impedance. If the voltage gain of the amplifier is defined as:
If Av is greater than 1, the input admittance is a negative resistance in parallel with
an inductance.

The inductance is:

If a capacitor with the same value of C is placed in parallel with the input, the
circuit has a natural resonance at:

Substituting and solving for inductance yields:

If Av is chosen to be 3: Lin = R2C

Substituting this value yields:

Similarly, the input resistance at the frequency above is:

For Av = 3: Rin = − R

If a resistor is placed in parallel with the amplifier input, it will cancel some of the
negative resistance. If the net resistance is negative, amplitude will grow until
clipping occurs.

Similarly, if the net resistance is positive, oscillation amplitude will decay. If a

resistance is added in parallel with exactly the value of R, the net resistance will be
infinite and the circuit can sustain stable oscillation at any amplitude allowed by
the amplifier.

Increasing the gain makes the net resistance more negative, which increases
amplitude. If gain is reduced to exactly 3 when suitable amplitude is reached,
stable, low distortion oscillations will result.

Amplitude stabilization circuits typically increase gain until suitable output

amplitude is reached. As long as R, C, and the amplifier are linear, distortion will
be minimal.

Multivibrators

Astable Multivibrator

The two states of circuit are only stable for a limited time and the circuit switches
between them with the output alternating between positive and negative saturation
values.
Analysis of this circuit starts with the assumption that at time t=0 the output has
just switched to state 1, and the transition would have occurred.

An op-amp Astable multivibrator is also called as free running oscillator. The basic
principle of generation of square wave is to force an op-amp to operate in the
saturation region (±Vsat).

A fraction β =R2/(R1+R2) of the output is feedback to the positive input terminal

of op-amp. The charge in the capacitor increases & decreases upto a threshold
value called ±βVsat. The charge in the capacitor triggers the op-amp to stay either
at +Vsat or –Vsat.

Asymmetrical square wave can also be generated with the help of Zener diodes.
Astable multi vibrator do not require a external trigger pulse for its operation &
output toggles from one state to another and does not contain a stable state.

Astable multi vibrator is mainly used in timing applications & waveforms

generators.

Design

1. The expression of fo is obtained from the charging period t1 & t2 of capacitor

as T=2RCln (R1+2R2)/R1

2. To simplify the above expression, the value of R1 & R2 should be taken as R2

= 1.16R Such that fo simplifies to fo =1/2RC.
3. Assume the value of R1 and find R2.

4. Assume the value of C & Determine R from fo =1/2R C

5. Calculate the threshold point from βVSATl = R1lVTl/ R1-R2 l/βVSATl w h e r

e β is the feedback ratio.

Monostable Multivibrator using Op-amp:

circuit diagram:
A multivibrator which has only one stable and the other is quasi stable state is
called as Monostable multivibrator or one-short multivibrator. This circuit is useful
for generating signal output pulse of adjustable time duration in response to a
triggering signal. The width of the output pulse depends only on the external
components connected to the op-amp. Usually a negative trigger pulse is given to
make the output switch to other state. But, it then return to its stable state after a
time interval determining by circuit components. The pulse width T can be given
as T = 0.69RC. For Monostable operation the triggering pulse width Tp should be
less then T, the pulse width of Monostable multivibrator. This circuit is also called
as time delay circuit or gating circuit.

Design:

1. Calculating β from expression

2. The value of R and C from the pulse width time expression.

3. Triggering pulse width Tp must be much smaller than T. Tp < T.

Triangular Wave Generator Circuit:

This signal generator gives two waveforms: a triangle-wave and a square- wave.
The central component of this circuit is the integrator capacitor CI. Basically we
are interested in performing two functions on CI: charge it, discharge it - repeat
indefinitely. The output waveforms are shown here and it is apparent that a square
wave generator followed by an integrator acts as a triangular wave generator.

The triangle peaks and period may not accurately meet +/-10V swing at 100 us.
The main reason is that current source and thresholds are derived from Zener
diodes - not exactly the most accurate reference.

Linear Ramp Generator

A triangle wave implies that the circuit generates a linear voltage ramp. One way
to achieve this goal is by charging discharging CI with a constant current. The Op
Amp Integrator provides for this.

Ramp Up

Connect RI to VN and With V- held at the virtual ground (0V), a constant current
flows from V- to VN.

Iin = VN / RI.

CI integrates Iin creating a positive linear ramp at Vo. The ramp is linear because
Vo changes proportionally to the time elapsed ΔT.

ΔVo = - VN / (CI ∙ RI) ∙ ΔT

Ramp Down Connect RI to VP and constant current flows from VP to V-,

Iin = - VP / RI.

Now Vo ramps down linearly ΔVo = - VP / (CI ∙ RI) ∙ ΔT

Ramp Up:ΔVo/ΔT= -VN/(CIRI)

Ramp Down:ΔVo /ΔT = - VP / ( CI∙RI )

These equations show the parameters available to control the ramp up / down
speeds. Asymmetrical voltage swings are got by including a reference voltage
VREF to the comparator's negative input.

Vth+ =VREF∙(R1+R2)/R2-VN∙R1/R2

Vth- = VREF ∙ (R1+R2)/R2 -VP ∙ R1 / R2

Upper and Lower Bounds

When do we switch from charging to discharging CI? Basically, there is a need to

pick two levels - an upper and a lower threshold - to define the bounds of the
triangle wave. The circuit ramps up or down, reversing at the upper and lower
thresholds.

 With one leg of RI at VN, the output ramps up until the Upper Threshold
(Vth+ ) is reached. Then RI is switched from VN to VP.

 With one leg of RI at VP, the output ramps down until the Lower Threshold
(Vth- ) is reached. Then RI is switched from VP to VN.

Comparator:

An Op Amp Comparator with two thresholds. Produce circuit changes in output

state from VN to VP (or vice-versa) depending on the upper Vth+ and lower Vth-
thresholds.

Vth+=-VN∙R1/R2

Vth- = -VP ∙ R1 / R2

Comparator Working:

o When Vin > Vth+, the output switches to VP, the POSITIVE output state.

o When Vin < Vth-, the output switches to VN, the NEGATIVE output state.
Zener diodes D1 and D2 set the positive and negative output levels:

VP=VfD1+VZD2 VN = VfD2 + VZD1.

These output levels do double duty - they set the comparator thresholds, and set the
voltage levels for the next stage - the integrator.

Saw-Tooth Wave Generator

The saw tooth wave oscillator which used the operational amplifier. The
composition of this circuit is the same as the triangular wave oscillator basically
and is using two operational amplifiers.

At the circuit diagram above, IC(1/2) is the Schmitt circuit and IC(2/2) is the
Integration circuit. The difference with the triangular wave oscillator is to be
changing the time of the charging and the discharging of the capacitor. When the
output of IC (1/2) is positive voltage, it charges rapidly by the small resistance
(R1) value.

(When the integration output voltage falls) When the output of IC(1/2) is negative
voltage, it is made to charge gradually at the big resistance(R2) value. The output
waveform of the integration circuit becomes a form like the tooth of the saw. Such
voltage is used for the control of the electron beam (the scanning line) of the
television,

When picturing a picture at the cathode-ray tube, an electron beam is moved

comparative slow. (When the electron beam moves from the left to the right on the
screen). When turning back, it is rapidly moved.(When moving from the right to
the left).

Like the triangular wave oscillator, the line voltage needs both of the positive
power supply and the negative power supply. Also, to work in the oscillation, the
condition of R3>R4 is necessary. However, when making the value of R4 small
compared with R3, the output voltage becomes small. The near value is good for
R3 and R4

The oscillation frequency can be calculated by the following formula.

With the circuit diagram,the oscillation frequency is as follows.

f = (1/2C (R1+R2))*(R3/R4)

= (1/(2x0.1x10-6x(5.6x103+100x103))x(120x103/100x103)

= (1/(21.12x10-3))x1.2

= 56.8 Hz

Function Generator IC 8038:

It consists of two current sources, two comparators, two buffers, one FF and a sine
wave converter.
Pin description:

 Pin 1 & Pin 12: Sine wave adjusts:

The distortion in the sine wave output can be reduced by adjusting the 100KΩ pots
connected between pin12 & pin11 and between pin 1 & 6.

 Pin 2 Sine Wave Output:

Sine wave output is available at this pin. The amplitude of this sine wave is 0.22
Vcc. Where ± 5V ≤ Vcc ≤ ± 15 V.

 Pin 3 Triangular Wave output:

Triangular wave is available at this pin. The amplitude of the triangular wave is
0.33Vcc.

Where ± 5V ≤ Vcc ≤ ± 15 V.

 Pin 4 & Pin 5 Duty cycle / Frequency adjust:

The symmetry of all the output wave forms & 50% duty cycle for the square wave
output is adjusted by the external resistors connected from Vcc to pin 4. These
external resistors & capacitors at pin 10 will decide the frequency of the output
wave forms.

 Pin 6 + Vcc:

Positive supply voltage the value of which is between 10 & 30V is applied to this
pin.

 Pin 7 : FM Bias:

This pin along with pin no8 is used to TEST the IC 8038.

 Pin9 : Square Wave Output:

A square wave output is available at this pin. It is an open collector output so that
this pin

can be connected through the load to different power supply voltages. This
arrangement is very useful in making the square wave output.

 Pin 10 : Timing Capacitors:

The external capacitor C connected to this pin will decide the output frequency
along with the resistors connected to pin 4 & 5.

 Pin 11 : -VEE or Ground:

If a single polarity supply is to be used then this pin is connected to supply ground
& if (±) supply voltages are to be used then (-) supply is connected to this pin.

 Pin 13 & Pin 14: NC (No Connection)

Important features of IC 8038:

1. All the outputs are simultaneously available.

2. Frequency range : 0.001Hz to 500kHz

3. Low distortion in the output wave forms.

4. Low frequency drifts due to change in temperature.

5. Easy to use.

Parameters:

(i) Frequency of the output wave form:

The output frequency dependent on the values of resistors R1 & R2 along with the
external capacitor C connected at pin 10.

If RA= RB = R & if RC is adjusted for 50% duty cycle then f0= 0.3/RC; RA = R1,
RB =

R3, RC= R2.

(ii) Duty cycle / Frequency Adjust : (Pin 4 & 5):

Duty cycle as well as the frequency of the output wave form can be adjusted by
external resistors at pin 4 & 5.
The values of resistors RA & RB connected between Vcc pin 4 & 5 respectively
along

with the capacitor connected at pin 10 decide the frequency of the wave form. The
values of RA & RB should be in the range of 1kΩ to 1MΩ.

(iii)FM Bias:

• The FM Bias input (pin7) corresponds to the junction of resistors R1 & R2.

• The voltage Vin is the voltage between Vcc & pin8 and it decides the output
frequency.

• The output frequency is proportional to Vin as given by the following

expression.

For RA = RB (50% duty cycle).

f0= 5 Vin/CRAVcc ; where C is the timing capacitor.

 With pin 7 & 8 connected to each other the output frequency is given by f0=
0.3/RC where R = RA = RB for 50% duty cycle.

 This is because M Sweep input (pin 8):

• Vin=R1Vcc/R1+R2

• This input should be connected to pin 7, if we want a constant output

frequency.

• But if the output frequency is supposed to vary, then a variable dc voltage

should be applied to this pin.

• The voltage between Vcc & pin 8 is called Vin and it decides the output
frequency as,

f0=1.5 Vin/CRAVCC

A potentiometer can be connected to this pin to obtain the required variable voltage
required to change the output frequency.

The 555 Timer IC

The 555 is a monolithic timing circuit that can produce accurate & highly stable
time delays or oscillation. The timer basically operates in one of two modes: either

(i) Monostable (one - shot) multivibrator or

(ii) Astable (free running) multivibrator

The important features of the 555 timer are these:

(i) It operates on +5v to +18 v supply voltages

(ii) It has an adjustable duty cycle

(iii) Timing is from microseconds to hours

(iv) It has a current o/p

Pin description:
Pin 1: Ground:

All voltages are measured with respect to this terminal.

Pin 2: Trigger:

The o/p of the timer depends on the amplitude of the external trigger pulse applied
to this pin.

Pin 3: Output:

There are 2 ways a load can be connected to the o/p terminal either between pin3
& ground or between pin 3 & supply voltage

(Between Pin 3 & Ground ON load) (BetweenPin 3 & + Vcc OFF load)

(i) When the input is low:

The load current flows through the load connected between Pin 3 & +Vcc in to the
output terminal & is called the sink current.

(ii) When the output is high:

The current through the load connected between Pin 3 & +Vcc (i.e. ON load) is
zero. However the output terminal supplies current to the normally OFF load. This
current is called the source current.

Pin 4: Reset:

The 555 timer can be reset (disabled) by applying a negative pulse to this pin.
When the reset function is not in use, the reset terminal should be connected to
+Vcc to avoid any false triggering.

Pin 5: Control voltage:

An external voltage applied to this terminal changes the threshold as well as trigger
voltage. In other words by connecting a potentiometer between this pin & GND,
the pulse width of the output waveform can be varied. When not used, the control
pin should be bypassed to ground with 0.01 capacitor to prevent any noise
problems.

Pin 6: Threshold:
This is the non inverting input terminal of upper comparator which monitors the
voltage across the external capacitor.

Pin 7: Discharge:

This pin is connected internally to the collector of transistor Q1.

When the output is high Q1 is OFF.

When the output is low Q is (saturated) ON.

Pin 8: +Vcc:

The supply voltage of +5V to +18V is applied to this pin with respect to ground.
From the above figure, three 5k internal resistors act as voltage divider providing
bias voltage of 2/3 Vcc to the upper comparator & 1/3 Vcc to the lower
comparator. It is possible to vary time electronically by applying a modulation
voltage to the control voltage input terminal (5).

(i) In the Stable state:

The output of the control FF is high. This means that the output is low because of
power amplifier which is basically an inverter. Q = 1; Output = 0

(ii) At the Negative going trigger pulse:

The trigger passes through (Vcc/3) the output of the lower comparator goes high &
sets the FF. Q = 1; Q = 0

(iii) At the Positive going trigger pulse:

It passes through 2/3Vcc, the output of the upper comparator goes high and resets
the FF. Q = 0; Q = 1

The reset input (pin 4) provides a mechanism to reset the FF in a manner which
overrides the effect of any instruction coming to FF from lower comparator.

Monostable Operation:
Initially when the output is low, i.e. the circuit is in a stable state, transistor Q1 is
ON & capacitor C is shorted to ground. The output remains low. During negative
going trigger pulse, transistor Q1 is OFF, which releases the short circuit across the
external capacitor C & drives the output high. Now the capacitor C starts charging
toward Vcc through RA. When the voltage across the capacitor equals 2/3 Vcc,
upper comparator switches from low to high. i.e. Q = 0, the transistor Q1 = OFF ;
the output is high.
Since C is unclamped, voltage across it rises exponentially through R towards Vcc
with a time constant RC (fig b) as shown in below. After the time period, the upper
comparator resets the FF, i.e. Q = 1, Q1 = ON; the output is low.[i.e discharging
the capacitor C to ground potential (fig c)]. The voltage across the capacitor as in
fig (b) is given by

Vc = Vcc (1-e-t/RC)……. (1)

Therefore At t = T, Vc = 2/3 Vcc

2/3 Vcc = Vcc(1-e-T/RC)

or

T = RC ln (1/3)

Or

T = 1.1RC seconds ……………. (2)

If the reset is applied Q2 = OFF, Q1 = ON, timing capacitor C immediately

discharged. The output now will be as in figure (d & e). If the reset is released
output will still remain low until a negative going trigger pulse is again applied at
pin 2.

Applications of Monostable Mode of Operation:

(a) Frequency Divider:

The 555 timer as a monostable mode. It can be used as a frequency divider by

adjusting the length of the timing cycle tp with respect to the time period T of the
trigger input. To use the monostable multivibrator as a divide by 2 circuit, the
timing interval tp must be a larger than the time period of the trigger input. [Divide
by 2, tp > T of the trigger]
By the same concept, to use the monostable multivibrator as a divide by 3 circuit,
tp must be slightly larger than twice the period of the input trigger signal & so on, [
divide by 3 tp > 2T oftrigger]

(b) Pulse width modulation:

Pulse width of a carrier wave changes in accordance with the value of a incoming
(modulating signal) is known as PWM. It is basically monostable multivibrator.

A modulating signal is fed in to the control voltage (pin 5). Internally, the control
voltage is adjusted to 2/3 Vcc externally applied modulating signal changes the
control voltage level of upper comparator. As a result, the required to change the
capacitor up to threshold voltage level changes, giving PWM output.

(c) Pulse Stretcher:

This application makes use of the fact that the output pulse width (timing interval)
of the monostable multivibrator is of longer duration than the negative pulse width
of the input trigger. As such, the output pulse width of the monostable
multivibrator can be viewed as a stretched version of the narrow input pulse, hence
the name “Pulse stretcher”.

Often, narrow –pulse width signals are not suitable for driving an LED display,
mainly because of their very narrow pulse widths. In other words, the LED may be
flashing but not be visible to the eye because its on time is infinitesimally small
compared to its off time. The 55 pulse stretcher can be used to remedy this
problem. The LED will be ON during the timing interval tp = 1.1RAC which can
be varied by changing the value of RA & C.

The 555 timer as an Astable Multivibrator:

An Astable multivibrator, often called a free running multivibrator, is a rectangular

wave generating circuit. Unlike the monostable multivibrator, this circuit does not
require an external trigger to change the state of the output, hence the name free
running. However, the time during which the output is either high or low is
determined by 2 resistors and capacitors, which are externally connected to the 55
timer.
The above figures show the 555 timer connected as an astable multivibrator and its
model graph
Initially, when the output is high :

Capacitor C starts charging toward Vcc through RA & RB. However, as soon as
voltage across the capacitor equals 2/3 Vcc. Upper comparator triggers the FF &
output switches low.

When the output becomes Low:

Capacitor C starts discharging through RB and transistor Q1, when the voltage
across C equals 1/3 Vcc, lower comparator output triggers the FF & the output
goes high. Then cycle repeats. The capacitor is periodically charged & discharged
between 2/3 Vcc & 1/3 Vcc respectively. The time during which the capacitor
charges from 1/3 Vcc to 2/3 Vcc equal to the time the output is high & is given by

tc = (RA+RB)C ln 2……………(1) Where [ln 2 = 0.69]

= 0.69 (RA+RB) C

Where RA & RB are in ohms. And C is in farads.

Similarly, the time during which the capacitors discharges from 2/3 Vcc to 1/3 Vcc
is equal to the time, the output is low and is given by,

tc = RB C ln 2

td = 0.69 RB C …………………..(2)

where RB is in ohms and C is in farads.

Thus the total period of the output waveform is

T = tc + td = 0.69 (RA+2RB) C …………….(3)

This, in turn, gives the frequency of oscillation as,f 0 = 1/T = 1.45/(RA+2RB)C

………(4)

Equation 4 indicates that the frequency f 0 is independent of the supply voltage

Vcc. Often the term duty cycle is used in conjunction with the astable
multivibrator. The duty cycle is the ratio of the time tc during which the output is
high to the total time period T. It is generally expressed as a percentage.

% duty cycle = (tc / T )* 100

% DC = [(RA+RB)/ /(RA+2RB)] * 100

Astable Multivibrator Applications:

(a) Square wave oscillator:

Without reducing RA = 0 ohm, the astable multivibrator can be used to produce

square wave output. Simply by connecting diode D across Resistor RB. The
capacitor C charges through RA & diode D to approximately 2/3Vcc & discharges
through RB & Q1 until the capacitor voltage equals approximately 1/3Vcc, then
the cycle repeats.

To obtain a square wave output, RA must be a combination of a fixed resistor &

potentiometer so that the potentiometer can be adjusted for the exact square wave.
(b) Free – running Ramp generator:

 The astable multivibrator can be used as a free – running ramp generator when
resistor

 RA & RB is replaced by a current mirror.

 The current mirror starts charging capacitor C toward Vcc at a constant rate.

 When voltage across C equals to 2/3 Vcc, upper comparator turns transistor
Q1 ON and C rapidly discharges through transistor Q1.

 When voltage across C equals to 1/3 Vcc, lower comparator switches

transistor OFF & then capacitor C starts charging up again.

 Thus the charge – discharge cycle keeps repeating.

 The discharging time of the capacitor is relatively negligible compared to its

charging time.

 The time period of the ramp waveform is equal to the charging time & is
approximately is given by,
T = VccC/3IC

IC = (Vcc - VBE)/R = constant current

Therefore the free – running frequency of ramp generator is

f0 = 3IC/ Vcc C

Linear Regulators

 All electronic circuits need a dc power supply for their operation. To obtain
this dc voltage from 230 V ac mains supply, we need to use rectifier.

 Therefore the filters are used to obtain a “steady” dc voltage from the
pulsating one.

 The filtered dc voltage is then applied to a regulator which will try to keep the
dc output voltage constant in the event of voltage fluctuations or load variation.

The combination of rectifier & filter can produce a dc voltage. But the problem
with this type of dc power supply is that its output voltage will not remain constant
in the event of fluctuations in an AC input or changes in the load current(IL).

 The output of unregulated power supply is connected at the input of voltage

regulator circuit.

 The voltage regulator is a specially designed circuit to keep the output voltage
constant. It does not remain exactly constant. It changes slightly due to changes in
certain parameters.

Factors affecting the output voltage:

i) IL (Load Current)

ii) VIN (Input Voltage)

iii) T (Temperature)
IC Voltage Regulators:

They are basically series regulators.

Important features of IC Regulators:

1. Programmable output

2. Facility to boost the voltage/current

3. Internally provided short circuit current limiting

4. Thermal shutdown

5. Floating operation to facilitate higher voltage output

Classifications of IC voltage regulators:

IC Voltage Regulator

a. Fixed Volt Reg. Positive/negative

b. Adjustable O/P Volt Reg

c. Switching Reg
 Fixed & Adjustable output Voltage Regulators are known as Linear Regulator.

 A series pass transistor is used and it operates always in its active region.

Switching Regulator:

1. Series Pass Transistor acts as a switch.

2. The amount of power dissipation in it decreases considerably.

3. Power saving result is higher efficiency compared to that of linear.

Adjustable Voltage Regulator:

Advantages of Adjustable Voltage Regulator over fixed voltage regulator are,

1. Adjustable output voltage from 1.2v to 57 v

2. Output current 0.10 to 1.5 A

3. Better load & line regulation

4. Improved overload protection

5. Improved reliability under the 100% thermal overloading

Adjustable Positive Voltage Regulator (LM317):

 LM317 series adjustable 3 terminal positive voltage regulator, the three
terminals are Vin, Vout & adjustment (ADJ).

 LM317 requires only 2 external resistors to set the output voltage.

 LM317 produces a voltage of 1.25v between its output & adjustment

terminals. This voltage is called as Vref.

 Vref (Reference Voltage) is a constant, hence current I1 flows through R1 will

also be constant. Because resistor R1 sets current I1. It is called “current set” or
“program resistor”.

 Resistor R2 is called as “Output set” resistors, hence current through this

resistor is the sum of I1 & Iadj

 LM317 is designed in such as that Iadj is very small & constant with changes
in line voltage & load current.

 The output voltage Vo is, Vo=R1I1+(I1+Iadj)R2------------- (1)

Where I1= Vref/R1

Vo = (Vref/R1) R1 + Vref/R1 + Iadj /R2

= Vref + (Vref/R1) R2 + Iadj R2

Vo = Vref [1 + R2/R1] + Iadj R2------------- (2)

R1 = Current (I1) set resistor

R2 = output (Vo) set resistor.

Vref = 1.25v which is a constant voltage between output and ADJ terminals.

 Current Iadj is very small. Therefore the second term in (2) can be neglected.

 Thus the final expression for the output voltage is given by

Vo= 1.25v[1 + R2/R1] -------------- (3)

Eqn (3) indicates that we can vary the output voltage by varying the resistance R 2.
The value of R1 is normally kept constant at 240 ohms for all practical applications.

Practical Regulator using LM317:

 If LM317 is far away from the input power supply, then 0.1μf disc type or 1μf
tantalum capacitor should be used at the input of LM317.

 The output capacitor Co is optional. Co should be in the range of 1 to 1000μf.

 The adjustment terminal is bypassed with a capacitor C2 this will improve the
ripple rejection ratio as high as 80 dB is obtainable at any output level.

 When the filter capacitor is used, it is necessary to use the protective diodes.
 These diodes do not allow the capacitor C2 to discharge through the low
current point of the regulator.

 These diodes are required only for high output voltages (above 25v) & for
higher values of output capacitance 25μf and above.

IC 723 – General Purpose Regulator

Disadvantages of fixed voltage regulator:

1. Do not have the shot circuit

2. Output voltage is not adjustable

These limitations can be overcomes in IC723.

Features of IC723:

1. Unregulated dc supply voltage at the input between 9.5V & 40V

2. Adjustable regulated output voltage between 2 to 3V.

3. Maximum load current of 150 mA (ILmax = 150mA).

4. With the additional transistor used, ILmax upto 10A is obtainable.

5. Positive or Negative supply operation

6. Internal Power dissipation of 800mW.

7. Built in short circuit protection.

8. Very low temperature drift.

9. High ripple rejection.

The simplified functional block diagram can be divided in to 4 blocks.

1. Reference Generating block:

The temperature compensated Zener diode, constant current source & voltage
reference amplifier together from the reference generating block. The Zener diode
is used to generate a fixed reference voltage internally. Constant current source
will make the Zener diode to operate at affixed point & it is applied to the Non –
inverting terminal of error amplifier. The Unregulated input voltage ±Vcc is
applied to the voltage reference amplifier as well as error amplifier.

2. Error Amplifier:
Error amplifier is a high gain differential amplifier with 2 input (inverting & Non-
inverting). The Non-inverting terminal is connected to the internally generated
reference voltage. The Inverting terminal is connected to the full regulated output
voltage.

3. Series Pass Transistor:

Q1 is the internal series pass transistor which is driven by the error amplifier. This
transistor actually acts as a variable resistor & regulates the output voltage. The
collector of transistor Q1 is connected to the Un-regulated power supply. The
maximum collector voltage of Q1 is limited to 36Volts. The maximum current
which can be supplied by Q1 is 150mA.

4. Circuitry to limit the current:

The internal transistor Q2 is used for current sensing & limiting. Q2 is normally
OFF transistor. It turns ON when the IL exceeds a predetermined limit.

Low voltage, Low current is capable of supplying load voltage which is equal to or
between 2 to 7Volts.

Vload = 2 to 7V and Iload= 50mA

IC723 as a LOW voltage LOW current:

 R1 & R2 from a potential divider between Vref & Gnd.

 The Voltage across R2 is connected to the Non – inverting terminal of the
regulator IC Vnon-inv = R2/(R1+R2) Vref

 Gain of the internal error amplifier is large

Vnon-inv = Vin

 Therefore the Vo is connected to the Inverting terminal through R 3 & RSC must
also be equal to Vnon-inv

Vo = Vnon-inv =R2/(R1+R2) Vref

R1 & R2 can be in the range of 1 KΩ to 10KΩ & value of R3 is given by

R3 = R1ll R2 =R1R2/(R1+R2)

Rsc (current sensing resistor) is connected between Cs & CL. The voltage drop
across Rsc is proportional to the IL.

 This resistor supplies the output voltage in the range of 2 to 7 volts, but the
load current can be higher than 150mA.

 The current sourcing capacity is increased by including a transistor Q in the

circuit.

 The output voltage , Vo =R2/(R1+R2) Vref

IC723 as a HIGH voltage LOW Current:

 This circuit is capable of supplying a regulated output voltage between the

ranges of 7 to 37 volts with a maximum load current of 150 mA.

 The Non – inverting terminal is now connected to Vref through resistance R3.

 The value of R1 & R2 is adjusted in order to get a voltage of Vref at the

inverting terminal at the desired output.

Vin = Vref =R2 /(R1+R2)V0

Vo = [1+R1/R2] Vin
 Rsc is connected between CL & Cs terminals as before & it provides the
short Circuit current limiting Rsc =0.6/Ilimit

 The value of resistors R3 is given by ,

R3= R1ll R2 =R1R2/(R1+R2)

IC723 as a HIGH voltage HIGH Current:

 An external transistor Q is added in the circuit for high voltage low current
regulator to improve its current sourcing capacity.

 For this circuit the output voltage varies between 7 & 37V.

 Transistor Q increase the current sourcing capacity thus IL (MAX) is greater

than 150mA.

 The output voltage Vo is given by ,

V0= Vo = [1+R1/R2] Vin

Rsc =0.6/Ilimit

Switching Regulators

Introduction

The switching regulator offers the advantages

 higher power conversion efficiency

 Increased design flexibility (multiple output voltages of different polarities can

be generated from a single input voltage).

 a lot less heat and

 Smaller size.

The primary filter capacitor is placed on the input to the regulator to help filter out
the 60 cycle ripple. If the output voltage is 12 volts and the input voltage is 24
volts then we must drop 12 volts across the regulator. At output currents of 10
amps this translates into 120 watts (12 volts times 10 amps) of heat energy that the
regulator must dissipate into heat.

The switching regulator is much more efficient than the linear regulator achieving
efficiencies as high as 80% to 95% in some circuits. The obvious result is smaller
heat sinks, less heat and smaller overall size of the power supply.
The switching regulator is really nothing more than just a simple switch. This
switch goes on and off at a fixed rate usually between 50 Khz to 100Khz as set by
the circuit.

Operation:

Diode D1 has to be a Schottky or other very fast switching diode. Inductor L1must
be a type of core that does not saturate under high currents. Capacitor C1 is
normally a low ESR (Equivalent Series Resistance) type.

To understand the action of D1 and L1, let’s look at what happens when S1 is
closed as indicated below:

L1, which tends to oppose the rising current, begins to generate an electromagnetic
field in its core. Diode D1 is reversed biased and is essentially an open circuit at
this point.

When S1 opens, the electromagnetic field that was built up in L1 is now

discharging and generating a current in the reverse polarity. As a result, D1 is now
conducting and will continue until the field in L1 is diminished. This action is
similar to the charging and discharging of capacitor C1. The use of this
inductor/diode combination gives us even more efficiency and augments the
filtering of C1.

Because the switching system operates in the 50 to 100 kHz region and has an
almost square waveform, it is rich in harmonics way up into the HF and even the
VHF/UHF region Four most commonly used switching converter types:

Buck: used the reduce a DC voltage to a lower DC voltage.

Boost: provides an output voltage that is higher than the input.

Buck-Boost (invert): an output voltage is generated opposite in polarity to the

input.

Fly back: an output voltage that is less than or greater than the input can be
generated, as well as multiple outputs.

Converters:

Push-Pull: A two-transistor converter that is especially efficient at low input

voltages.

Half-Bridge: A two-transistor converter used in many off-line applications. Full-

Bridge: A four-transistor converter (usually used in off-line designs) that can
generate the highest output power of all the types listed.

Switching Regulator:

An example of general purpose regulator is Motorola’s MC1723. It can be used in

many different ways, for example, as a fixed positive or negative output voltage
regulator, variable regulator or switching regulator because of its flexibility.

To minimize the power dissipation during switching, the external transistor used
must be a switching power transistor.

To improve the efficiency of a regulator, the series pass transistor is used as a

switch rather than as a variable resistor as in the linear mode.

 A regulator constructed to operate in this manner is called a series switching

regulator. In such regulators the series pass transistor is switched between cut off
& saturation at a high frequency which produces a pulse width modulated (PWM)
square wave output.

 This output is filtered through a low pass LC filter to produce an average dc

output voltage.

 Thus the output voltage is proportional to the pulse width and frequency.
 The efficiency of a series switching regulator is independent of the input &
output differential & can approach 95%

A basic switching regulator consists of 4 major components,

1. Voltage source Vin

2. Switch S1

3. Pulse generator Vpulse

4. Filter F1

1. Voltage Source Vin:

It may be any dc supply – a battery or an unregulated or a regulated voltage. The

voltage source must satisfy the following requirements.

 It must supply the required output power & the losses associated with the
switching regulator.

 It must be large enough to supply sufficient dynamic range for line & load
regulations.

 It must be sufficiently high to meet the minimum requirement of the regulator

system to be designed.

 It may be required to store energy for a specified amount of time during power
failures.
2. Switch S1:

It is typically a transistor or thyristor connected as a power switch & is operated in

the saturated mode. The pulse generator output alternately turns the switch ON &
OFF

3. Pulse generator Vpulse:

It provides an asymmetrical square wave varying in either frequency or pulse

width called frequency modulation or pulse width modulation respectively. The
most effective frequency range for the pulse generator for optimum efficiency 20
KHz. This frequency is inaudible to the human ear & also well within the
switching speeds of most inexpensive transistors & diodes.

 The duty cycle of the pulse wave form determines the relationship between the
input & output voltages. The duty cycle is the ratio of the on time ton, to the period
T of the pulse waveform.

Duty cycle = ton/(ton+toff) = ton/T =ton.f

Where

ton = On-time of the pulse waveform toff=off-time of the pulse wave form

T = time period = ton + toff

=1/frequency or T = 1/f

 Typical operating frequencies of switching regulator range from 10 to 50 kHz.

 Lower operating frequency improve efficiency & reduce electrical noise, but
require large filter components (inductors & capacitors).
3. Filter F1:

It converts the pulse waveform from the output of the switch into a dc voltage.
Since this switching mechanism allows a conversion similar to transformers, the
switching regulator is often referred to as a dc transformer.

The output voltage Vo of the switching regulator is a function of duty cycle & the
input voltage Vin.

Vo is expressed as follows,

Vo= ton Vin/T

 This equation indicates that, if time period T is constant, Vo is directly

proportional to the ON-time, ton for a given value of Vin. This method of changing
the output voltage by varying ton is referred to as a pulse width modulation.

 Similarly, if ton is held constant, the output voltage Vo is inversely

proportional to the period T or directly proportional to the frequency of the pulse
waveform. This method of varying the output voltage is referred to as frequency
modulation (FM).

 Switching regulator can operate in any of 3 modes

i) Step – Down

ii) Step – Up

iii) Polarity inverting

Monolithic Switching Regulator [µa78s40]:

The µA78S40 consists of a temperature compensated voltage reference, duty cycle

controllable oscillator with an active current limit circuit, a high gain comparator, a
high- current, high voltage output switch, a power switching diode & an
uncommitted op-amp. Important features of the µA78S40 switching regulators are:

 Step up, down & Inverting operation

 Operation from 2.5 to 40V input

 80dB line & load regulations

 Output adjustable from 1.3 to 40V

 Peak current to 1.5A without external resistors

 Variable frequency, variable duty cycle device

The internal switching frequency is set by the timing capacitor CT, connected
between pin12 & ground pin 11. The initial duty cycle is 6:1. The switching
frequency & duty cycle can be modified by the current limit circuitry, IPK sense,
pin14, 7 the comparator, pin9 & 10.

Comparator:

The comparator modifies the OFF time of the output switch transistor Q1 & Q2. In
the step – up & step down modes, the non-inverting input(pin9) of the comparator
is connected to the voltage reference of 1.3V (pin8) & the inverting input (pin10) is
connected to the output terminal via the voltage divider network.
 In the Inverting mode the non – inverting input is connected to both the
voltage reference & the output terminal through 2 resistors & the inverting
terminal is connected to ground.

 When the output voltage is correct, the comparator output is in high state &
has no effect on the circuit operation.

 However, if the output is too high & the voltage at the inverting terminal is
higher than that at the non-inverting terminal, then the comparator output goes low.

 In the LOW state the comparator inhibits the turn on of the output switching
transistors. This means that, as long as the comparator output is low, the system is
in off time.

 As the output current rises or the output voltage falls, the off time of the
system decreases.
 Consequently, as the output current nears its maximum IoMAX, the off time
approaches its minimum value.

In all 3 modes (Step down, step up, Inverting), the current limit circuit is
completed by connecting a sense resistor Rsc, between IPK sense & Vcc.

 The current limit circuit is activated when a 330mV potential appears across
Rsc.

 Rsc is selected such that 330mV appears across it when the desired peak
current IPK, flows through it.

 When the peak current is reached, the current limit circuit is turned on.

The forward voltage drop, VD, across the internal power diode is used to
determine the value of inductor L off time & efficiency of the switching regulator.

Another important quantity used in the design of a switching regulator is the

saturation voltage Vs:

In the step down mode an “output saturation volt” is 1.1V typical, 1.3VMAX.

In the step up mode an “Output saturation volt” is 0.45V typical, 0.7 maximum.

The desired peak current value is reached; the current limiting circuit turns ON &
immediately terminates the ON time & starts OFF time.

 As we increase IL (load current), Vout will decrease, to compensate for this,

the ON time of the output is increased automatically.

If the IL decreased then Vout increased, to compensate for this, the OFF time of
the output is increased automatically.

(i) Step – Down Switching Regulator:

 CT is the timing capacitor which decides the switching frequency.  Rsc is the
current sensing resistance. Its value is given by
 The Non-inverting terminal of the internal op-amp (pin9) is connected to the
1.3V reference (pin8).

 Resistances R1 & R2 from a potential divider, across the output voltage Vo.
Their value should be such that the potential at the inverting input of the op-amp
should be equal to 1.3V ref when Vo is at its desired level.

The output capacitance Co is used for reducing the ripple contents in the output
voltage. It acts as a filter along with the inductor L.

 The inductor L is a part of filter connected on the output side, to reduce the
ripple percentage.

 The 0.1μF capacitor connected between pin8 & ground bypasses any noise
voltage coupled to the reference (pin8).
(ii) Step – Up Switching Regulator:

 Inductor is connected between the collectors of Q1 & Q2.

 When Q1 is ON, the output is shorted & the collector current of Q1 flows
through L.

 The diode D1 is reverse biased & Co supplies the load current.

 The inductor stores the energy. When the Q1 is turned OFF, there is a self
induced emf that appears across the inductor with polarities.

 The output voltage is given by,

Vo = Vin + VL

 Hence it will be always higher than Vin & step up operation is achieved.
(iii) Inverting Switching Regulator:

Inverting switching regulator converts a positive input voltage into a negative

output voltage which is higher in magnitude.
The Switched Capacitor Filter

Basic Representation:

The simplest switched capacitor (SC) circuit is the switched capacitor resistor,
made of one capacitor C and two switches S1 and S2 which connect the capacitor
with a given frequency alternately to the input and output of the SC. Each
switching cycle transfers a charge q from the input to the output at the switching
frequency f. Recall that the charge q on a capacitor C with a voltage V between the
plates is given by:

q=CV

where V is the voltage across the capacitor. Therefore, when S1 is closed while S2
is open, the charge transferred from the source to CS is:

qIN=CSVIN

And when S2 is closed while S1 is open, the charge transferred from CS to the load
is:

qOUT = CSVOUT

Thus, the charge transferred in each cycle is:

Q=qOUT-qIN=Cs(VOUT-VIN)

Since a charge q is transferred at a rate f, the rate of transfer of charge per unit time
is:

I=qf

Note that we use I, the symbol for electric current, for this quantity. This is to
demonstrate that a continuous transfer of charge from one node to another is
equivalent to a current. Substituting for q in the above, we have:

I=Cs(VOUT-VIN)f

Let us define V, the voltage across the SC from input to output, thus:

V=VOUT-VIN

We now have a relationship between I and V, which we can rearrange to give an

equivalent resistance R:

R=V/I=1/Csf

Thus, the SC behaves like a resistor whose value depends on CS and f.

The SC resistor is used as a replacement for simple resistors in integrated circuits

because it is easier to fabricate reliably with a wide range of values. It also has the
benefit that its value can be adjusted by changing the switching frequency. See
also: operational amplifier applications.

This same circuit can be used in discrete time systems (such as analog to digital
converters) as a track and hold circuit. During the appropriate clock phase, the
capacitor samples the analog voltage through switch one and in the second phase
presents this held sampled value to an electronic circuit for processing.

Switched Capacitor Circuits:

The switched capacitor filter allows for very sophisticated, accurate, and tuneable
analog circuits to be manufactured without using resistors.

Advantages: resistors are hard to build on integrated circuits (they take up a lot
of room), and the circuits can be made to depend on ratios of capacitor values
(which can be set accurately), and not absolute values (which vary between
manufacturing runs).

The Switched Capacitor Resistor:

Consider the circuit shown with a capacitor connected to two switches and two
different voltages.

If S2 closes with S1 open, then S1 closes with switch S2 open, a charge (q is

transferred from V2 to V1 with

∆q=C1(v2-v1)
If this switching process is repeated N times in a time (t, the amount of charge
transferred per unit time is given by

∆q/∆t=C1(v2-v1) N/∆t

the number of cycles per unit time is the switching frequency (or clock frequency,
fCLK)

i= C1(v2-v1) fCLK

Rearranging we get

(v2-v1) / I = [ 1/ C1 fCLK ] -R

Which states that the switched capacitor is equivalent to a resistor? The value of
this resistor decreases with increasing switching frequency or increasing
capacitance, as either will increase the amount of charge transferred from V 2 to
V1 in a given time.

The Switched Capacitor Integrator:

Now consider the integrator circuit. You have shown (in a previous lab) that the
input-output relationship for this circuit is given by (neglecting initial conditions):

We can also write this with the "s" notation (assuming a sinusoidal input, Ae st,
s=jω)

If you replaced the input resistor with a switched capacitor resistor, you would get
Thus, you can change the equivalent ω' of the circuit by changing the clock
frequency. The value of ω' can be set very precisely because it depends only on the
ratio of C1 and C2, and not their absolute value.

Switched Capacitor Filter ICs:

Some of the Switched capacitor filter ICs is MF 5, MF10 and MF100

MF10:

The MF10 contains two of the second-order universal filter sections found in the
MF5. Therefore with MF10, two second order filters or one fourth-order filter can
be built. As the MF5 and MF10 have similar filter sections, the design procedure
for them is same.
Frequency to Voltage (F-V) and voltage to frequency convertors (V-
F)

Frequency to Voltage convertors (F-V)

 F-V convertors applications: Tachometer in motor speed control Rotational

speed measurement.

 Two types of it: Pulse integrating Phase locked loop

 F-V convertor produces an output voltage whose amplitude is a function of

input signal frequency.

 V0=kf fi kf is sensitivity of F-V convertor

 It is basically a FM discriminator.
Input frequency is applied to comparator A.

Resistor R acts as feedback element.

Capacitor Ci enables charge-balancing,

High pass network conditions input signal

For negative spike of V 01, comparator COMP triggers one shot multivibrator with
threshold 7.5V The output of multivibrator closes the switch SW, for a time TH,
this causes voltage Vo to build up and inject thru R and this continues until current
out of summing input of opamp is equal to that injected by Vo through R
continuously.

Vo=10-3 *TH *R*fi as TH =7.5 C /1X10-3

Ripple Voltage, Vr(max) =7.5 C /Ci

Voltage to frequency convertor

Principle: Charge balancing technique-the process of charging and discharging

results in frequency proportional to input signal F0= k Vi

Operation: Op-amp A converts input Vi to current Ii = Vi/R into summing junction.

When switch SW is open the current flows into capacitor Ci and charges it, and
node voltage Vo1 produce ramp down.

When V01 =0 CMP triggers and sends a triggering signal to one shot multivibrator
that closes the switch SW and turns transistor Q ON for time TH.

The threshold of mono shot = 7.5 V and TH= 7.5 C/10-3

During TH , V01 ramps upward by amount ∆V01=(1mA-Ii) TH /Ci

Time duration TL for vo1 to return to 0 is TL = C∆V01/Ii

TL+TH = 1mA TH /Ii = T

F0=Vi/7.5 RC
Power Audio Amplifier IC LM 380:

Introduction:

Small signal amplifiers are essentially voltage amplifier that supplies their loads
with larger amplifier signal voltage.

On the other hand, large signal or power amplifier supply a large signal current to
current operated loads such as speakers & motors.

In audio applications, however, the amplifier called upon to deliver much higher
current than that supplied by general purpose op-amps. This means that loads such
as speakers & motors requiring substantial currents cannot be driven directly by
the output of general purpose op-amps. To handle it following is done

 To use discrete or monolithic power transistors called power boosters at the

output of the op-amp
 To use specialized ICs designed as power amplifiers like LM 380.

Features of LM380:

1. Internally fixed gain of 50 (34dB)

2. Output is automatically self centering to one half of the supply voltage.

3. Output is short circuit proof with internal thermal limiting.

4. Input stage allows the input to be ground referenced or ac

5. Wide supply voltage range (5 to 22V).

6. High peak current capability.

7. High impedance.
LM380 circuit description:
It is connected of 4 stages,

(i) PNP emitter follower

(ii) Different amplifier

(iii) Common emitter

(iv) Emitter follower

(i) PNP Emitter follower:

 The input stage is emitter follower composed of PNP transistors Q1 & Q2

which drives the PNP Q3-Q4 differential pair.

 The choice of PNP input transistors Q1 & Q2 allows the input to be referenced
to ground i.e., the input can be direct coupled to either the inverting & non-
inverting terminals of the amplifier.

(ii) Differential Amplifier:

 The current in the PNP differential pair Q3-Q4 is established by Q7, R3 & +V.

 The current mirror formed by transistor Q7, Q8 & associated resistors then
establishes the collector current of Q9.

 Transistor Q5 & Q6 constitute of collector loads for the PNP differential pair.

 The output of the differential amplifier is taken at the junction of Q4 & Q6

transistors & is applied as an input to the common emitter voltage gain.

(iii) Common Emitter amplifier stage:

 Common Emitter amplifier stage is formed by transistor Q9 with D1, D2 &

Q8 as a current source load.

 The capacitor C between the base & collector of Q9 provides internal

compensation & helps to establish the upper cutoff frequency of 100 KHz.
 Since Q7 & Q8 form a current mirror, the current through D1 & D2 is
approximately the same as the current through R3.

 D1 & D2 are temperature compensating diodes for transistors Q10 & Q11 in
that D1 & D2 have the same characteristics as the base-emitter junctions of Q11.
Therefore the current through Q10 & (Q11-Q12) is approximately equal to the
current through diodes D1 & D2.

(iv) (Output stage) - Emitter follower:

 Emitter follower formed by NPN transistor Q10 & Q11. The combination of
PNP transistor Q11 & NPN transistor Q12 has the power capability of NPN
transistors but the characteristics of a PNP transistor.

 The negative dc feedback applied through R5 balances the differential

amplifier so that the dc output voltage is stabilized at +V/2;

 To decouple the input stage from the supply voltage +V, by pass capacitor in
order of micro farad should be connected between the bypass terminal (pin 1) &
ground (pin 7).

 The overall internal gain of the amplifier is fixed at 50. However gain can be
increased by using positive feedback.

Applications:

(i) Audio Power Amplifier:

 Amplifier requires very few external components because of the internal
biasing, compensation & fixed gain.

 When the power amplifier is used in the non inverting configuration, the
inverting terminal may be either shorted to ground, connected to ground through
resistors & capacitors.

 Similarly when the power amplifier is used in the inverting mode, the non
inverting terminal may be either shorted to ground or returned to ground through
resistor or capacitor.

 Usually a capacitor is connected between the inverting terminal & ground if

the input has a high internal impedance.

 As a precautionary measure, an RC combination should be used at the output

terminal (pin 8) to eliminate 5-to-10 MHz oscillation.

 C1 is coupling capacitor which couples the output of the amplifier to the 8

ohms loud speaker which acts as a load. The amplifier will amplify the Vin applied
at the non-inverting terminal.

(ii) LM 380 as a High gain amplifier:

 The gain of LM380 is internally fixed at 50. But it can be increased by using
the external components.

 The increase in gain is possible due to the use of positive feedback, this setup
to obtain a gain 200.

(iii) LM 380 as a variable Gain:

 Instead of getting a fixed gain of 50, it is possible to obtain a variable gain up

to 50 by connecting a potentiometer between the input terminals.
(iv) LM 380 as a Bridge Audio Power Amplifier:

 If a certain application requires more power than what is provided by a single

LM380 amplifier, then 2 LM380 chips can be used in the bridge configuration.

 With this arrangement we get an output voltage swing which is twice that of a
single LM380 amplifier.

 As the voltage is doubled, power output will increase by four times that of a
single LM380 amplifier. The pot R4 is used to balance the output offset voltages of
the two chips.
(v) Intercom system using LM 380:

 When the switch is in Talk mode position, the master speaker acts as a
microphone.

 When the switch is in Listen position, the remote speaker acts as a

microphone.

 In either phone the overall gain of the circuit is the same depends on the turns
of transformer T.

Opto couplers/Opto Isolators and fibre optic IC

 Opto couplers or Opt isolators is a combination of light source & light detector
in the same package.

 They are used to couple signal from one point to other optically, by providing
a complete electric isolation between them. This kind of isolation is provided
between a low power control circuit & high power output circuit, to protect the
control circuit.

Characteristics of opto coupler:

(i) Current Transfer Ratio:

It is defined as the ratio of output collector current (Ic) to the input forward current
(If)

CTR = Ic/If * 100%. Its value depends on the devices used as source & detector.

(ii) Isolation voltage between input & output:

It is the maximum voltage which can exist differentially between the input &
output without affecting the electrical isolation voltage is specified in K Vrms with
a relative humidity of 40 to 60%.

(iii) Response Time:

Response time indicates how fast an opto coupler can change its output state.
Response time largely depends on the detector transistor, input current & load
resistance.

(iv) Common mode Rejection:

Even though the opto couplers are electrically isolated for dc & low frequency
signals, an impulsive input signal (the signal which changes suddenly) can give
rise to a displacement current Ic= Cf*dv/dt. This current can flow between input &
output due to the capacitance Cf existing between input & output. This allows the
noise to appear in the output. Depending on the type of light source & detector
used we can get a variety of opto couplers.

They are as follows,

(i) LED – Photodiode opto coupler:

 LED photodiode shown in figure, here the infrared LED acts as a light source
& photodiode is used as a detector.

 The advantage of using the photodiode is its high linearity. When the pulse at
the input goes high, the LED turns ON. It emits light. This light is focused on the
photodiode.

 In response to this light the photocurrent will start flowing though the
photodiode. As soon as the input pulse reduces to zero, the LED turns OFF & the
photocurrent through the photodiode reduces to zero. Thus the pulse at the input is
coupled to the output side.
(ii) LED – Phototransistor Opto coupler:

 The LED phototransistor opto coupler shown in figure. An infrared LED acts
as a light source and the phototransistor acts as a photo detector.

 This is the most popularly used opto coupler, because it does not need any
additional amplification.

 When the pulse at the input goes high, the LED turns ON. The light emitted by
the LED is focused on the CB junction of the phototransistor.

 In response to this light photocurrent starts flowing which acts as a base

current for the phototransistor.

 The collector current of phototransistor starts flowing. As soon as the input

pulse reduces to zero, the LED turns OFF & the collector current of phototransistor
reduces to zero. Thus the pulse at the input is optically coupled to the output side.

 The input & output waveforms are 180º out of phase as the output is taken at
the collector of the phototransistor

Advantages of Opto coupler:

 Control circuits are well protected due to electrical isolation.

 Wideband signal transmission is possible.

 Due to unidirectional signal transfer, noise from the output side does not get
coupled to the input side.

 Interfacing with logic circuits is easily possible.

 It is small size & light weight device.

Disadvantages:

 Slow speed.

 Possibility of signal coupling for high power signals.

Applications:

Opto couplers are used basically to isolate low power circuits from high power
circuits.

 At the same time the control signals are coupled from the control circuits to
the high power circuits.

 Some of such applications are,

(i) AC to DC converters used for DC motor speed control

(ii) High power choppers

(iii) High power inverters

 One of the most important applications of an opto coupler is to couple the base
driving signals to a power transistor connected in a DC-DC chopper.
Opto coupler IC:

The optocouplers are available in the IC form MCT2E is the standard optocoupler
IC which is used popularly in many electronic application.

 This input is applied between pin 1& pin 2. An infrared light emitting diode is
connected between these pins.

 The infrared radiation from the LED gets focused on the internal
phototransistor.

 The base of the phototransistor is generally left open. But sometimes a high
value pull down resistance is connected from the Base to ground to improve the
sensitivity.

 The block diagram shows the opto-electronic-integrated circuit (OEIC) and the
major components of a fiber-optic communication facility.

 The block diagram shows the opto-electronic-integrated circuit (OEIC) and the
major components of a fiber-optic communication facility.